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Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
6670a5a5 | 34 | |
26b1ff35 BW |
35 | /* PPGTT stuff */ |
36 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 37 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
38 | |
39 | #define GEN6_PDE_VALID (1 << 0) | |
40 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
41 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
42 | ||
43 | #define GEN6_PTE_VALID (1 << 0) | |
44 | #define GEN6_PTE_UNCACHED (1 << 1) | |
45 | #define HSW_PTE_UNCACHED (0) | |
46 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 47 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
49 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
50 | ||
51 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
52 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
53 | */ | |
54 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
55 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 56 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 57 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 58 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 59 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 60 | |
350ec881 | 61 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
62 | enum i915_cache_level level, |
63 | bool valid) | |
54d12527 | 64 | { |
b35b380e | 65 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 66 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
67 | |
68 | switch (level) { | |
350ec881 CW |
69 | case I915_CACHE_L3_LLC: |
70 | case I915_CACHE_LLC: | |
71 | pte |= GEN6_PTE_CACHE_LLC; | |
72 | break; | |
73 | case I915_CACHE_NONE: | |
74 | pte |= GEN6_PTE_UNCACHED; | |
75 | break; | |
76 | default: | |
77 | WARN_ON(1); | |
78 | } | |
79 | ||
80 | return pte; | |
81 | } | |
82 | ||
83 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
84 | enum i915_cache_level level, |
85 | bool valid) | |
350ec881 | 86 | { |
b35b380e | 87 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
88 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
89 | ||
90 | switch (level) { | |
91 | case I915_CACHE_L3_LLC: | |
92 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
93 | break; |
94 | case I915_CACHE_LLC: | |
95 | pte |= GEN6_PTE_CACHE_LLC; | |
96 | break; | |
97 | case I915_CACHE_NONE: | |
9119708c | 98 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
99 | break; |
100 | default: | |
350ec881 | 101 | WARN_ON(1); |
e7210c3c BW |
102 | } |
103 | ||
54d12527 BW |
104 | return pte; |
105 | } | |
106 | ||
93c34e70 KG |
107 | #define BYT_PTE_WRITEABLE (1 << 1) |
108 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
109 | ||
80a74f7f | 110 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
111 | enum i915_cache_level level, |
112 | bool valid) | |
93c34e70 | 113 | { |
b35b380e | 114 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
115 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
116 | ||
117 | /* Mark the page as writeable. Other platforms don't have a | |
118 | * setting for read-only/writable, so this matches that behavior. | |
119 | */ | |
120 | pte |= BYT_PTE_WRITEABLE; | |
121 | ||
122 | if (level != I915_CACHE_NONE) | |
123 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
124 | ||
125 | return pte; | |
126 | } | |
127 | ||
80a74f7f | 128 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
129 | enum i915_cache_level level, |
130 | bool valid) | |
9119708c | 131 | { |
b35b380e | 132 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 133 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
134 | |
135 | if (level != I915_CACHE_NONE) | |
87a6b688 | 136 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
137 | |
138 | return pte; | |
139 | } | |
140 | ||
4d15c145 | 141 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
142 | enum i915_cache_level level, |
143 | bool valid) | |
4d15c145 | 144 | { |
b35b380e | 145 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
146 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
147 | ||
651d794f CW |
148 | switch (level) { |
149 | case I915_CACHE_NONE: | |
150 | break; | |
151 | case I915_CACHE_WT: | |
152 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
153 | break; | |
154 | default: | |
4d15c145 | 155 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
156 | break; |
157 | } | |
4d15c145 BW |
158 | |
159 | return pte; | |
160 | } | |
161 | ||
3e302542 | 162 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 163 | { |
853ba5d2 | 164 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
165 | gen6_gtt_pte_t __iomem *pd_addr; |
166 | uint32_t pd_entry; | |
167 | int i; | |
168 | ||
0a732870 | 169 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
170 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
171 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
172 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
173 | dma_addr_t pt_addr; | |
174 | ||
175 | pt_addr = ppgtt->pt_dma_addr[i]; | |
176 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
177 | pd_entry |= GEN6_PDE_VALID; | |
178 | ||
179 | writel(pd_entry, pd_addr + i); | |
180 | } | |
181 | readl(pd_addr); | |
3e302542 BW |
182 | } |
183 | ||
184 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
185 | { | |
186 | drm_i915_private_t *dev_priv = dev->dev_private; | |
187 | uint32_t pd_offset; | |
188 | struct intel_ring_buffer *ring; | |
189 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
190 | int i; | |
191 | ||
192 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
193 | ||
194 | gen6_write_pdes(ppgtt); | |
6197349b BW |
195 | |
196 | pd_offset = ppgtt->pd_offset; | |
197 | pd_offset /= 64; /* in cachelines, */ | |
198 | pd_offset <<= 16; | |
199 | ||
200 | if (INTEL_INFO(dev)->gen == 6) { | |
201 | uint32_t ecochk, gab_ctl, ecobits; | |
202 | ||
203 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
204 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
205 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
206 | |
207 | gab_ctl = I915_READ(GAB_CTL); | |
208 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
209 | ||
210 | ecochk = I915_READ(GAM_ECOCHK); | |
211 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
212 | ECOCHK_PPGTT_CACHE64B); | |
213 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
214 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 215 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
216 | |
217 | ecobits = I915_READ(GAC_ECO_BITS); | |
218 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
219 | ||
a6f429a5 VS |
220 | ecochk = I915_READ(GAM_ECOCHK); |
221 | if (IS_HASWELL(dev)) { | |
222 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
223 | } else { | |
224 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
225 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
226 | } | |
227 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
228 | /* GFX_MODE is per-ring on gen7+ */ |
229 | } | |
230 | ||
231 | for_each_ring(ring, dev_priv, i) { | |
232 | if (INTEL_INFO(dev)->gen >= 7) | |
233 | I915_WRITE(RING_MODE_GEN7(ring), | |
234 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
235 | ||
236 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
237 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
238 | } | |
b7c36d25 | 239 | return 0; |
6197349b BW |
240 | } |
241 | ||
1d2a314c | 242 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 243 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 244 | unsigned first_entry, |
828c7908 BW |
245 | unsigned num_entries, |
246 | bool use_scratch) | |
1d2a314c | 247 | { |
853ba5d2 BW |
248 | struct i915_hw_ppgtt *ppgtt = |
249 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 250 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 251 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
252 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
253 | unsigned last_pte, i; | |
1d2a314c | 254 | |
b35b380e | 255 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 256 | |
7bddb01f DV |
257 | while (num_entries) { |
258 | last_pte = first_pte + num_entries; | |
259 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
260 | last_pte = I915_PPGTT_PT_ENTRIES; | |
261 | ||
a15326a5 | 262 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 263 | |
7bddb01f DV |
264 | for (i = first_pte; i < last_pte; i++) |
265 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
266 | |
267 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 268 | |
7bddb01f DV |
269 | num_entries -= last_pte - first_pte; |
270 | first_pte = 0; | |
a15326a5 | 271 | act_pt++; |
7bddb01f | 272 | } |
1d2a314c DV |
273 | } |
274 | ||
853ba5d2 | 275 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
276 | struct sg_table *pages, |
277 | unsigned first_entry, | |
278 | enum i915_cache_level cache_level) | |
279 | { | |
853ba5d2 BW |
280 | struct i915_hw_ppgtt *ppgtt = |
281 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 282 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 283 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
284 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
285 | struct sg_page_iter sg_iter; | |
286 | ||
a15326a5 | 287 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
288 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
289 | dma_addr_t page_addr; | |
290 | ||
2db76d7c | 291 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 292 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
293 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
294 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
295 | act_pt++; |
296 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 297 | act_pte = 0; |
def886c3 | 298 | |
def886c3 | 299 | } |
def886c3 | 300 | } |
6e995e23 | 301 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
302 | } |
303 | ||
853ba5d2 | 304 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 305 | { |
853ba5d2 BW |
306 | struct i915_hw_ppgtt *ppgtt = |
307 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
308 | int i; |
309 | ||
93bd8649 BW |
310 | drm_mm_takedown(&ppgtt->base.mm); |
311 | ||
3440d265 DV |
312 | if (ppgtt->pt_dma_addr) { |
313 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 314 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
315 | ppgtt->pt_dma_addr[i], |
316 | 4096, PCI_DMA_BIDIRECTIONAL); | |
317 | } | |
318 | ||
319 | kfree(ppgtt->pt_dma_addr); | |
320 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
321 | __free_page(ppgtt->pt_pages[i]); | |
322 | kfree(ppgtt->pt_pages); | |
323 | kfree(ppgtt); | |
324 | } | |
325 | ||
326 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
327 | { | |
853ba5d2 | 328 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 329 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 330 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
331 | int i; |
332 | int ret = -ENOMEM; | |
333 | ||
334 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
335 | * entries. For aliasing ppgtt support we just steal them at the end for | |
336 | * now. */ | |
e1b73cba | 337 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 338 | |
08c45263 | 339 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 340 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 341 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
342 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
343 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
344 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
345 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
a1e22653 | 346 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
347 | GFP_KERNEL); |
348 | if (!ppgtt->pt_pages) | |
3440d265 | 349 | return -ENOMEM; |
1d2a314c DV |
350 | |
351 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
352 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
353 | if (!ppgtt->pt_pages[i]) | |
354 | goto err_pt_alloc; | |
355 | } | |
356 | ||
a1e22653 | 357 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
358 | GFP_KERNEL); |
359 | if (!ppgtt->pt_dma_addr) | |
360 | goto err_pt_alloc; | |
1d2a314c | 361 | |
8d2e6308 BW |
362 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
363 | dma_addr_t pt_addr; | |
211c568b | 364 | |
8d2e6308 BW |
365 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
366 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 367 | |
8d2e6308 BW |
368 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
369 | ret = -EIO; | |
370 | goto err_pd_pin; | |
1d2a314c | 371 | |
211c568b | 372 | } |
8d2e6308 | 373 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 374 | } |
1d2a314c | 375 | |
853ba5d2 | 376 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 377 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 378 | |
e7c2b58b | 379 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 380 | |
1d2a314c DV |
381 | return 0; |
382 | ||
383 | err_pd_pin: | |
384 | if (ppgtt->pt_dma_addr) { | |
385 | for (i--; i >= 0; i--) | |
386 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
387 | 4096, PCI_DMA_BIDIRECTIONAL); | |
388 | } | |
389 | err_pt_alloc: | |
390 | kfree(ppgtt->pt_dma_addr); | |
391 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
392 | if (ppgtt->pt_pages[i]) | |
393 | __free_page(ppgtt->pt_pages[i]); | |
394 | } | |
395 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
396 | |
397 | return ret; | |
398 | } | |
399 | ||
400 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
401 | { | |
402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403 | struct i915_hw_ppgtt *ppgtt; | |
404 | int ret; | |
405 | ||
406 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
407 | if (!ppgtt) | |
408 | return -ENOMEM; | |
409 | ||
853ba5d2 | 410 | ppgtt->base.dev = dev; |
3440d265 | 411 | |
3ed124b2 BW |
412 | if (INTEL_INFO(dev)->gen < 8) |
413 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 DV |
414 | else if (IS_GEN8(dev)) |
415 | ret = -ENOSYS; | |
3ed124b2 BW |
416 | else |
417 | BUG(); | |
418 | ||
3440d265 DV |
419 | if (ret) |
420 | kfree(ppgtt); | |
93bd8649 | 421 | else { |
3440d265 | 422 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
423 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
424 | ppgtt->base.total); | |
425 | } | |
1d2a314c DV |
426 | |
427 | return ret; | |
428 | } | |
429 | ||
430 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
431 | { | |
432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
433 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
434 | |
435 | if (!ppgtt) | |
436 | return; | |
437 | ||
853ba5d2 | 438 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 439 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
440 | } |
441 | ||
7bddb01f DV |
442 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
443 | struct drm_i915_gem_object *obj, | |
444 | enum i915_cache_level cache_level) | |
445 | { | |
853ba5d2 BW |
446 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
447 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
448 | cache_level); | |
7bddb01f DV |
449 | } |
450 | ||
451 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
452 | struct drm_i915_gem_object *obj) | |
453 | { | |
853ba5d2 BW |
454 | ppgtt->base.clear_range(&ppgtt->base, |
455 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
456 | obj->base.size >> PAGE_SHIFT, |
457 | true); | |
7bddb01f DV |
458 | } |
459 | ||
a81cc00c BW |
460 | extern int intel_iommu_gfx_mapped; |
461 | /* Certain Gen5 chipsets require require idling the GPU before | |
462 | * unmapping anything from the GTT when VT-d is enabled. | |
463 | */ | |
464 | static inline bool needs_idle_maps(struct drm_device *dev) | |
465 | { | |
466 | #ifdef CONFIG_INTEL_IOMMU | |
467 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
468 | * was loaded first. | |
469 | */ | |
470 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
471 | return true; | |
472 | #endif | |
473 | return false; | |
474 | } | |
475 | ||
5c042287 BW |
476 | static bool do_idling(struct drm_i915_private *dev_priv) |
477 | { | |
478 | bool ret = dev_priv->mm.interruptible; | |
479 | ||
a81cc00c | 480 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 481 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 482 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
483 | DRM_ERROR("Couldn't idle GPU\n"); |
484 | /* Wait a bit, in hopes it avoids the hang */ | |
485 | udelay(10); | |
486 | } | |
487 | } | |
488 | ||
489 | return ret; | |
490 | } | |
491 | ||
492 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
493 | { | |
a81cc00c | 494 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
495 | dev_priv->mm.interruptible = interruptible; |
496 | } | |
497 | ||
828c7908 BW |
498 | void i915_check_and_clear_faults(struct drm_device *dev) |
499 | { | |
500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
501 | struct intel_ring_buffer *ring; | |
502 | int i; | |
503 | ||
504 | if (INTEL_INFO(dev)->gen < 6) | |
505 | return; | |
506 | ||
507 | for_each_ring(ring, dev_priv, i) { | |
508 | u32 fault_reg; | |
509 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
510 | if (fault_reg & RING_FAULT_VALID) { | |
511 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
512 | "\tAddr: 0x%08lx\\n" | |
513 | "\tAddress space: %s\n" | |
514 | "\tSource ID: %d\n" | |
515 | "\tType: %d\n", | |
516 | fault_reg & PAGE_MASK, | |
517 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
518 | RING_FAULT_SRCID(fault_reg), | |
519 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
520 | I915_WRITE(RING_FAULT_REG(ring), | |
521 | fault_reg & ~RING_FAULT_VALID); | |
522 | } | |
523 | } | |
524 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
525 | } | |
526 | ||
527 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
528 | { | |
529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
530 | ||
531 | /* Don't bother messing with faults pre GEN6 as we have little | |
532 | * documentation supporting that it's a good idea. | |
533 | */ | |
534 | if (INTEL_INFO(dev)->gen < 6) | |
535 | return; | |
536 | ||
537 | i915_check_and_clear_faults(dev); | |
538 | ||
539 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
540 | dev_priv->gtt.base.start / PAGE_SIZE, | |
541 | dev_priv->gtt.base.total / PAGE_SIZE, | |
542 | false); | |
543 | } | |
544 | ||
76aaf220 DV |
545 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
546 | { | |
547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 548 | struct drm_i915_gem_object *obj; |
76aaf220 | 549 | |
828c7908 BW |
550 | i915_check_and_clear_faults(dev); |
551 | ||
bee4a186 | 552 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
553 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
554 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
555 | dev_priv->gtt.base.total / PAGE_SIZE, |
556 | true); | |
bee4a186 | 557 | |
35c20a60 | 558 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 559 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 560 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
561 | } |
562 | ||
e76e9aeb | 563 | i915_gem_chipset_flush(dev); |
76aaf220 | 564 | } |
7c2e6fdf | 565 | |
74163907 | 566 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 567 | { |
9da3da66 | 568 | if (obj->has_dma_mapping) |
74163907 | 569 | return 0; |
9da3da66 CW |
570 | |
571 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
572 | obj->pages->sgl, obj->pages->nents, | |
573 | PCI_DMA_BIDIRECTIONAL)) | |
574 | return -ENOSPC; | |
575 | ||
576 | return 0; | |
7c2e6fdf DV |
577 | } |
578 | ||
e76e9aeb BW |
579 | /* |
580 | * Binds an object into the global gtt with the specified cache level. The object | |
581 | * will be accessible to the GPU via commands whose operands reference offsets | |
582 | * within the global GTT as well as accessible by the GPU through the GMADR | |
583 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
584 | */ | |
853ba5d2 | 585 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
586 | struct sg_table *st, |
587 | unsigned int first_entry, | |
588 | enum i915_cache_level level) | |
e76e9aeb | 589 | { |
853ba5d2 | 590 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
591 | gen6_gtt_pte_t __iomem *gtt_entries = |
592 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
593 | int i = 0; |
594 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
595 | dma_addr_t addr; |
596 | ||
6e995e23 | 597 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 598 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 599 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 600 | i++; |
e76e9aeb BW |
601 | } |
602 | ||
e76e9aeb BW |
603 | /* XXX: This serves as a posting read to make sure that the PTE has |
604 | * actually been updated. There is some concern that even though | |
605 | * registers and PTEs are within the same BAR that they are potentially | |
606 | * of NUMA access patterns. Therefore, even with the way we assume | |
607 | * hardware should work, we must keep this posting read for paranoia. | |
608 | */ | |
609 | if (i != 0) | |
853ba5d2 | 610 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 611 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
612 | |
613 | /* This next bit makes the above posting read even more important. We | |
614 | * want to flush the TLBs only after we're certain all the PTE updates | |
615 | * have finished. | |
616 | */ | |
617 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
618 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
619 | } |
620 | ||
853ba5d2 | 621 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 622 | unsigned int first_entry, |
828c7908 BW |
623 | unsigned int num_entries, |
624 | bool use_scratch) | |
7faf1ab2 | 625 | { |
853ba5d2 | 626 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
627 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
628 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 629 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
630 | int i; |
631 | ||
632 | if (WARN(num_entries > max_entries, | |
633 | "First entry = %d; Num entries = %d (max=%d)\n", | |
634 | first_entry, num_entries, max_entries)) | |
635 | num_entries = max_entries; | |
636 | ||
828c7908 BW |
637 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
638 | ||
7faf1ab2 DV |
639 | for (i = 0; i < num_entries; i++) |
640 | iowrite32(scratch_pte, >t_base[i]); | |
641 | readl(gtt_base); | |
642 | } | |
643 | ||
644 | ||
853ba5d2 | 645 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
646 | struct sg_table *st, |
647 | unsigned int pg_start, | |
648 | enum i915_cache_level cache_level) | |
649 | { | |
650 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
651 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
652 | ||
653 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
654 | ||
655 | } | |
656 | ||
853ba5d2 | 657 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 658 | unsigned int first_entry, |
828c7908 BW |
659 | unsigned int num_entries, |
660 | bool unused) | |
7faf1ab2 DV |
661 | { |
662 | intel_gtt_clear_range(first_entry, num_entries); | |
663 | } | |
664 | ||
665 | ||
74163907 DV |
666 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
667 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
668 | { |
669 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 670 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 671 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 672 | |
853ba5d2 BW |
673 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
674 | entry, | |
675 | cache_level); | |
d5bd1449 | 676 | |
74898d7e | 677 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
678 | } |
679 | ||
05394f39 | 680 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 681 | { |
7faf1ab2 DV |
682 | struct drm_device *dev = obj->base.dev; |
683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 684 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 685 | |
853ba5d2 BW |
686 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
687 | entry, | |
828c7908 BW |
688 | obj->base.size >> PAGE_SHIFT, |
689 | true); | |
74898d7e DV |
690 | |
691 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
692 | } |
693 | ||
694 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 695 | { |
5c042287 BW |
696 | struct drm_device *dev = obj->base.dev; |
697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
698 | bool interruptible; | |
699 | ||
700 | interruptible = do_idling(dev_priv); | |
701 | ||
9da3da66 CW |
702 | if (!obj->has_dma_mapping) |
703 | dma_unmap_sg(&dev->pdev->dev, | |
704 | obj->pages->sgl, obj->pages->nents, | |
705 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
706 | |
707 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 708 | } |
644ec02b | 709 | |
42d6ab48 CW |
710 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
711 | unsigned long color, | |
712 | unsigned long *start, | |
713 | unsigned long *end) | |
714 | { | |
715 | if (node->color != color) | |
716 | *start += 4096; | |
717 | ||
718 | if (!list_empty(&node->node_list)) { | |
719 | node = list_entry(node->node_list.next, | |
720 | struct drm_mm_node, | |
721 | node_list); | |
722 | if (node->allocated && node->color != color) | |
723 | *end -= 4096; | |
724 | } | |
725 | } | |
d7e5008f BW |
726 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
727 | unsigned long start, | |
728 | unsigned long mappable_end, | |
729 | unsigned long end) | |
644ec02b | 730 | { |
e78891ca BW |
731 | /* Let GEM Manage all of the aperture. |
732 | * | |
733 | * However, leave one page at the end still bound to the scratch page. | |
734 | * There are a number of places where the hardware apparently prefetches | |
735 | * past the end of the object, and we've seen multiple hangs with the | |
736 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
737 | * aperture. One page should be enough to keep any prefetching inside | |
738 | * of the aperture. | |
739 | */ | |
40d74980 BW |
740 | struct drm_i915_private *dev_priv = dev->dev_private; |
741 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
742 | struct drm_mm_node *entry; |
743 | struct drm_i915_gem_object *obj; | |
744 | unsigned long hole_start, hole_end; | |
644ec02b | 745 | |
35451cb6 BW |
746 | BUG_ON(mappable_end > end); |
747 | ||
ed2f3452 | 748 | /* Subtract the guard page ... */ |
40d74980 | 749 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 750 | if (!HAS_LLC(dev)) |
93bd8649 | 751 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 752 | |
ed2f3452 | 753 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 754 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 755 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 756 | int ret; |
edd41a87 | 757 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
758 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
759 | ||
760 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 761 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 762 | if (ret) |
b3a070cc | 763 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 764 | obj->has_global_gtt_mapping = 1; |
2f633156 | 765 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
766 | } |
767 | ||
853ba5d2 BW |
768 | dev_priv->gtt.base.start = start; |
769 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 770 | |
ed2f3452 | 771 | /* Clear any non-preallocated blocks */ |
40d74980 | 772 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 773 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
774 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
775 | hole_start, hole_end); | |
828c7908 | 776 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
777 | } |
778 | ||
779 | /* And finally clear the reserved guard page */ | |
828c7908 | 780 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
781 | } |
782 | ||
d7e5008f BW |
783 | static bool |
784 | intel_enable_ppgtt(struct drm_device *dev) | |
785 | { | |
786 | if (i915_enable_ppgtt >= 0) | |
787 | return i915_enable_ppgtt; | |
788 | ||
789 | #ifdef CONFIG_INTEL_IOMMU | |
790 | /* Disable ppgtt on SNB if VT-d is on. */ | |
791 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
792 | return false; | |
793 | #endif | |
794 | ||
795 | return true; | |
796 | } | |
797 | ||
798 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
799 | { | |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 802 | |
853ba5d2 | 803 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 804 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
805 | |
806 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 807 | int ret; |
3eb1c005 BW |
808 | |
809 | if (INTEL_INFO(dev)->gen <= 7) { | |
810 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
811 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 812 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 813 | } |
d7e5008f BW |
814 | |
815 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
816 | ||
817 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 818 | if (!ret) |
d7e5008f | 819 | return; |
e78891ca BW |
820 | |
821 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 822 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 823 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 824 | } |
e78891ca | 825 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
826 | } |
827 | ||
828 | static int setup_scratch_page(struct drm_device *dev) | |
829 | { | |
830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
831 | struct page *page; | |
832 | dma_addr_t dma_addr; | |
833 | ||
834 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
835 | if (page == NULL) | |
836 | return -ENOMEM; | |
837 | get_page(page); | |
838 | set_pages_uc(page, 1); | |
839 | ||
840 | #ifdef CONFIG_INTEL_IOMMU | |
841 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
842 | PCI_DMA_BIDIRECTIONAL); | |
843 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
844 | return -EINVAL; | |
845 | #else | |
846 | dma_addr = page_to_phys(page); | |
847 | #endif | |
853ba5d2 BW |
848 | dev_priv->gtt.base.scratch.page = page; |
849 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static void teardown_scratch_page(struct drm_device *dev) | |
855 | { | |
856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
857 | struct page *page = dev_priv->gtt.base.scratch.page; |
858 | ||
859 | set_pages_wb(page, 1); | |
860 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 861 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
862 | put_page(page); |
863 | __free_page(page); | |
e76e9aeb BW |
864 | } |
865 | ||
866 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
867 | { | |
868 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
869 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
870 | return snb_gmch_ctl << 20; | |
871 | } | |
872 | ||
9459d252 BW |
873 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
874 | { | |
875 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
876 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
877 | if (bdw_gmch_ctl) | |
878 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
879 | return bdw_gmch_ctl << 20; | |
880 | } | |
881 | ||
baa09f5f | 882 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
883 | { |
884 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
885 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
886 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
887 | } | |
888 | ||
9459d252 BW |
889 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
890 | { | |
891 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
892 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
893 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
894 | } | |
895 | ||
63340133 BW |
896 | static int ggtt_probe_common(struct drm_device *dev, |
897 | size_t gtt_size) | |
898 | { | |
899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
900 | phys_addr_t gtt_bus_addr; | |
901 | int ret; | |
902 | ||
903 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
904 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
905 | (pci_resource_len(dev->pdev, 0) / 2); | |
906 | ||
907 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
908 | if (!dev_priv->gtt.gsm) { | |
909 | DRM_ERROR("Failed to map the gtt page table\n"); | |
910 | return -ENOMEM; | |
911 | } | |
912 | ||
913 | ret = setup_scratch_page(dev); | |
914 | if (ret) { | |
915 | DRM_ERROR("Scratch setup failed\n"); | |
916 | /* iounmap will also get called at remove, but meh */ | |
917 | iounmap(dev_priv->gtt.gsm); | |
918 | } | |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
923 | static int gen8_gmch_probe(struct drm_device *dev, | |
924 | size_t *gtt_total, | |
925 | size_t *stolen, | |
926 | phys_addr_t *mappable_base, | |
927 | unsigned long *mappable_end) | |
928 | { | |
929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
930 | unsigned int gtt_size; | |
931 | u16 snb_gmch_ctl; | |
932 | int ret; | |
933 | ||
934 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
935 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
936 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
937 | ||
938 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
939 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
940 | ||
941 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
942 | ||
943 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
944 | ||
945 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 946 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 BW |
947 | |
948 | ret = ggtt_probe_common(dev, gtt_size); | |
949 | ||
950 | dev_priv->gtt.base.clear_range = NULL; | |
951 | dev_priv->gtt.base.insert_entries = NULL; | |
952 | ||
953 | return ret; | |
954 | } | |
955 | ||
baa09f5f BW |
956 | static int gen6_gmch_probe(struct drm_device *dev, |
957 | size_t *gtt_total, | |
41907ddc BW |
958 | size_t *stolen, |
959 | phys_addr_t *mappable_base, | |
960 | unsigned long *mappable_end) | |
e76e9aeb BW |
961 | { |
962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 963 | unsigned int gtt_size; |
e76e9aeb | 964 | u16 snb_gmch_ctl; |
e76e9aeb BW |
965 | int ret; |
966 | ||
41907ddc BW |
967 | *mappable_base = pci_resource_start(dev->pdev, 2); |
968 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
969 | ||
baa09f5f BW |
970 | /* 64/512MB is the current min/max we actually know of, but this is just |
971 | * a coarse sanity check. | |
e76e9aeb | 972 | */ |
41907ddc | 973 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
974 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
975 | dev_priv->gtt.mappable_end); | |
976 | return -ENXIO; | |
e76e9aeb BW |
977 | } |
978 | ||
e76e9aeb BW |
979 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
980 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 981 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 982 | |
63340133 | 983 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 984 | |
63340133 BW |
985 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
986 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
a93e4161 | 987 | |
63340133 | 988 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 989 | |
853ba5d2 BW |
990 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
991 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 992 | |
e76e9aeb BW |
993 | return ret; |
994 | } | |
995 | ||
853ba5d2 | 996 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 997 | { |
853ba5d2 BW |
998 | |
999 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
1000 | iounmap(gtt->gsm); | |
1001 | teardown_scratch_page(vm->dev); | |
644ec02b | 1002 | } |
baa09f5f BW |
1003 | |
1004 | static int i915_gmch_probe(struct drm_device *dev, | |
1005 | size_t *gtt_total, | |
41907ddc BW |
1006 | size_t *stolen, |
1007 | phys_addr_t *mappable_base, | |
1008 | unsigned long *mappable_end) | |
baa09f5f BW |
1009 | { |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011 | int ret; | |
1012 | ||
baa09f5f BW |
1013 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1014 | if (!ret) { | |
1015 | DRM_ERROR("failed to set up gmch\n"); | |
1016 | return -EIO; | |
1017 | } | |
1018 | ||
41907ddc | 1019 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1020 | |
1021 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
1022 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
1023 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
1024 | |
1025 | return 0; | |
1026 | } | |
1027 | ||
853ba5d2 | 1028 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1029 | { |
1030 | intel_gmch_remove(); | |
1031 | } | |
1032 | ||
1033 | int i915_gem_gtt_init(struct drm_device *dev) | |
1034 | { | |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1037 | int ret; |
1038 | ||
baa09f5f | 1039 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1040 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1041 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1042 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1043 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1044 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1045 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1046 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1047 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1048 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1049 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1050 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1051 | else if (INTEL_INFO(dev)->gen >= 7) |
1052 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1053 | else |
350ec881 | 1054 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1055 | } else { |
1056 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1057 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1058 | } |
1059 | ||
853ba5d2 | 1060 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1061 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1062 | if (ret) |
baa09f5f | 1063 | return ret; |
baa09f5f | 1064 | |
853ba5d2 BW |
1065 | gtt->base.dev = dev; |
1066 | ||
baa09f5f | 1067 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1068 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1069 | gtt->base.total >> 20); | |
b2f21b4d BW |
1070 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1071 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1072 | |
1073 | return 0; | |
1074 | } |