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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
cfa7c862 DV |
36 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
37 | { | |
38 | if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
39 | return 0; | |
40 | ||
41 | if (enable_ppgtt == 1) | |
42 | return 1; | |
43 | ||
44 | if (enable_ppgtt == 2 && HAS_PPGTT(dev)) | |
45 | return 2; | |
46 | ||
93a25a9e DV |
47 | #ifdef CONFIG_INTEL_IOMMU |
48 | /* Disable ppgtt on SNB if VT-d is on. */ | |
49 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
50 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 51 | return 0; |
93a25a9e DV |
52 | } |
53 | #endif | |
54 | ||
62942ed7 | 55 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
56 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
57 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
58 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
59 | return 0; | |
60 | } | |
61 | ||
cfa7c862 | 62 | return HAS_ALIASING_PPGTT(dev) ? 1 : 0; |
93a25a9e DV |
63 | } |
64 | ||
fbe5d36e | 65 | |
6f65e29a BW |
66 | static void ppgtt_bind_vma(struct i915_vma *vma, |
67 | enum i915_cache_level cache_level, | |
68 | u32 flags); | |
69 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 70 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 71 | |
94ec8f61 BW |
72 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
73 | enum i915_cache_level level, | |
74 | bool valid) | |
75 | { | |
76 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
77 | pte |= addr; | |
63c42e56 BW |
78 | |
79 | switch (level) { | |
80 | case I915_CACHE_NONE: | |
fbe5d36e | 81 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
82 | break; |
83 | case I915_CACHE_WT: | |
84 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
85 | break; | |
86 | default: | |
87 | pte |= PPAT_CACHED_INDEX; | |
88 | break; | |
89 | } | |
90 | ||
94ec8f61 BW |
91 | return pte; |
92 | } | |
93 | ||
b1fe6673 BW |
94 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
95 | dma_addr_t addr, | |
96 | enum i915_cache_level level) | |
97 | { | |
98 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
99 | pde |= addr; | |
100 | if (level != I915_CACHE_NONE) | |
101 | pde |= PPAT_CACHED_PDE_INDEX; | |
102 | else | |
103 | pde |= PPAT_UNCACHED_INDEX; | |
104 | return pde; | |
105 | } | |
106 | ||
350ec881 | 107 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 108 | enum i915_cache_level level, |
24f3a8cf | 109 | bool valid, u32 unused) |
54d12527 | 110 | { |
b35b380e | 111 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 112 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
113 | |
114 | switch (level) { | |
350ec881 CW |
115 | case I915_CACHE_L3_LLC: |
116 | case I915_CACHE_LLC: | |
117 | pte |= GEN6_PTE_CACHE_LLC; | |
118 | break; | |
119 | case I915_CACHE_NONE: | |
120 | pte |= GEN6_PTE_UNCACHED; | |
121 | break; | |
122 | default: | |
123 | WARN_ON(1); | |
124 | } | |
125 | ||
126 | return pte; | |
127 | } | |
128 | ||
129 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 130 | enum i915_cache_level level, |
24f3a8cf | 131 | bool valid, u32 unused) |
350ec881 | 132 | { |
b35b380e | 133 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
134 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
135 | ||
136 | switch (level) { | |
137 | case I915_CACHE_L3_LLC: | |
138 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
139 | break; |
140 | case I915_CACHE_LLC: | |
141 | pte |= GEN6_PTE_CACHE_LLC; | |
142 | break; | |
143 | case I915_CACHE_NONE: | |
9119708c | 144 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
145 | break; |
146 | default: | |
350ec881 | 147 | WARN_ON(1); |
e7210c3c BW |
148 | } |
149 | ||
54d12527 BW |
150 | return pte; |
151 | } | |
152 | ||
80a74f7f | 153 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 154 | enum i915_cache_level level, |
24f3a8cf | 155 | bool valid, u32 flags) |
93c34e70 | 156 | { |
b35b380e | 157 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
158 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
159 | ||
160 | /* Mark the page as writeable. Other platforms don't have a | |
161 | * setting for read-only/writable, so this matches that behavior. | |
162 | */ | |
24f3a8cf AG |
163 | if (!(flags & PTE_READ_ONLY)) |
164 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
165 | |
166 | if (level != I915_CACHE_NONE) | |
167 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
168 | ||
169 | return pte; | |
170 | } | |
171 | ||
80a74f7f | 172 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 173 | enum i915_cache_level level, |
24f3a8cf | 174 | bool valid, u32 unused) |
9119708c | 175 | { |
b35b380e | 176 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 177 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
178 | |
179 | if (level != I915_CACHE_NONE) | |
87a6b688 | 180 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
181 | |
182 | return pte; | |
183 | } | |
184 | ||
4d15c145 | 185 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 186 | enum i915_cache_level level, |
24f3a8cf | 187 | bool valid, u32 unused) |
4d15c145 | 188 | { |
b35b380e | 189 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
190 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
191 | ||
651d794f CW |
192 | switch (level) { |
193 | case I915_CACHE_NONE: | |
194 | break; | |
195 | case I915_CACHE_WT: | |
c51e9701 | 196 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
197 | break; |
198 | default: | |
c51e9701 | 199 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
200 | break; |
201 | } | |
4d15c145 BW |
202 | |
203 | return pte; | |
204 | } | |
205 | ||
94e409c1 | 206 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 207 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
e178f705 | 208 | uint64_t val, bool synchronous) |
94e409c1 | 209 | { |
e178f705 | 210 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
211 | int ret; |
212 | ||
213 | BUG_ON(entry >= 4); | |
214 | ||
e178f705 BW |
215 | if (synchronous) { |
216 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
217 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
218 | return 0; | |
219 | } | |
220 | ||
94e409c1 BW |
221 | ret = intel_ring_begin(ring, 6); |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
226 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
227 | intel_ring_emit(ring, (u32)(val >> 32)); | |
228 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
229 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
230 | intel_ring_emit(ring, (u32)(val)); | |
231 | intel_ring_advance(ring); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
eeb9488e | 236 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 237 | struct intel_engine_cs *ring, |
eeb9488e | 238 | bool synchronous) |
94e409c1 | 239 | { |
eeb9488e | 240 | int i, ret; |
94e409c1 BW |
241 | |
242 | /* bit of a hack to find the actual last used pd */ | |
243 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
244 | ||
94e409c1 BW |
245 | for (i = used_pd - 1; i >= 0; i--) { |
246 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
247 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
248 | if (ret) | |
249 | return ret; | |
94e409c1 | 250 | } |
d595bd4b | 251 | |
eeb9488e | 252 | return 0; |
94e409c1 BW |
253 | } |
254 | ||
459108b8 | 255 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
256 | uint64_t start, |
257 | uint64_t length, | |
459108b8 BW |
258 | bool use_scratch) |
259 | { | |
260 | struct i915_hw_ppgtt *ppgtt = | |
261 | container_of(vm, struct i915_hw_ppgtt, base); | |
262 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
263 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
264 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
265 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 266 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
267 | unsigned last_pte, i; |
268 | ||
269 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
270 | I915_CACHE_LLC, use_scratch); | |
271 | ||
272 | while (num_entries) { | |
7ad47cf2 | 273 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 274 | |
7ad47cf2 | 275 | last_pte = pte + num_entries; |
459108b8 BW |
276 | if (last_pte > GEN8_PTES_PER_PAGE) |
277 | last_pte = GEN8_PTES_PER_PAGE; | |
278 | ||
279 | pt_vaddr = kmap_atomic(page_table); | |
280 | ||
7ad47cf2 | 281 | for (i = pte; i < last_pte; i++) { |
459108b8 | 282 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
283 | num_entries--; |
284 | } | |
459108b8 | 285 | |
fd1ab8f4 RB |
286 | if (!HAS_LLC(ppgtt->base.dev)) |
287 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
288 | kunmap_atomic(pt_vaddr); |
289 | ||
7ad47cf2 BW |
290 | pte = 0; |
291 | if (++pde == GEN8_PDES_PER_PAGE) { | |
292 | pdpe++; | |
293 | pde = 0; | |
294 | } | |
459108b8 BW |
295 | } |
296 | } | |
297 | ||
9df15b49 BW |
298 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
299 | struct sg_table *pages, | |
782f1495 | 300 | uint64_t start, |
24f3a8cf | 301 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
302 | { |
303 | struct i915_hw_ppgtt *ppgtt = | |
304 | container_of(vm, struct i915_hw_ppgtt, base); | |
305 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
306 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
307 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
308 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
309 | struct sg_page_iter sg_iter; |
310 | ||
6f1cc993 | 311 | pt_vaddr = NULL; |
7ad47cf2 | 312 | |
9df15b49 | 313 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
314 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
315 | break; | |
316 | ||
6f1cc993 | 317 | if (pt_vaddr == NULL) |
7ad47cf2 | 318 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 319 | |
7ad47cf2 | 320 | pt_vaddr[pte] = |
6f1cc993 CW |
321 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
322 | cache_level, true); | |
7ad47cf2 | 323 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
324 | if (!HAS_LLC(ppgtt->base.dev)) |
325 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 326 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 327 | pt_vaddr = NULL; |
7ad47cf2 BW |
328 | if (++pde == GEN8_PDES_PER_PAGE) { |
329 | pdpe++; | |
330 | pde = 0; | |
331 | } | |
332 | pte = 0; | |
9df15b49 BW |
333 | } |
334 | } | |
fd1ab8f4 RB |
335 | if (pt_vaddr) { |
336 | if (!HAS_LLC(ppgtt->base.dev)) | |
337 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 338 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 339 | } |
9df15b49 BW |
340 | } |
341 | ||
7ad47cf2 BW |
342 | static void gen8_free_page_tables(struct page **pt_pages) |
343 | { | |
344 | int i; | |
345 | ||
346 | if (pt_pages == NULL) | |
347 | return; | |
348 | ||
349 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
350 | if (pt_pages[i]) | |
351 | __free_pages(pt_pages[i], 0); | |
352 | } | |
353 | ||
354 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
355 | { |
356 | int i; | |
357 | ||
7ad47cf2 BW |
358 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
359 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
360 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 361 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 362 | } |
b45a6715 | 363 | |
b45a6715 BW |
364 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
365 | } | |
366 | ||
367 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
368 | { | |
f3a964b9 | 369 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
370 | int i, j; |
371 | ||
372 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
373 | /* TODO: In the future we'll support sparse mappings, so this | |
374 | * will have to change. */ | |
375 | if (!ppgtt->pd_dma_addr[i]) | |
376 | continue; | |
377 | ||
f3a964b9 BW |
378 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
379 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
380 | |
381 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
382 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
383 | if (addr) | |
f3a964b9 BW |
384 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
385 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
386 | } |
387 | } | |
388 | } | |
389 | ||
37aca44a BW |
390 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
391 | { | |
392 | struct i915_hw_ppgtt *ppgtt = | |
393 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 394 | |
7e0d96bc | 395 | list_del(&vm->global_link); |
686e1f6f BW |
396 | drm_mm_takedown(&vm->mm); |
397 | ||
b45a6715 BW |
398 | gen8_ppgtt_unmap_pages(ppgtt); |
399 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
400 | } |
401 | ||
7ad47cf2 BW |
402 | static struct page **__gen8_alloc_page_tables(void) |
403 | { | |
404 | struct page **pt_pages; | |
405 | int i; | |
406 | ||
407 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
408 | if (!pt_pages) | |
409 | return ERR_PTR(-ENOMEM); | |
410 | ||
411 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
412 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
413 | if (!pt_pages[i]) | |
414 | goto bail; | |
415 | } | |
416 | ||
417 | return pt_pages; | |
418 | ||
419 | bail: | |
420 | gen8_free_page_tables(pt_pages); | |
421 | kfree(pt_pages); | |
422 | return ERR_PTR(-ENOMEM); | |
423 | } | |
424 | ||
bf2b4ed2 BW |
425 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
426 | const int max_pdp) | |
427 | { | |
7ad47cf2 | 428 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 429 | int i, ret; |
bf2b4ed2 | 430 | |
7ad47cf2 BW |
431 | for (i = 0; i < max_pdp; i++) { |
432 | pt_pages[i] = __gen8_alloc_page_tables(); | |
433 | if (IS_ERR(pt_pages[i])) { | |
434 | ret = PTR_ERR(pt_pages[i]); | |
435 | goto unwind_out; | |
436 | } | |
437 | } | |
438 | ||
439 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
440 | * "atomic" - for cleanup purposes. | |
441 | */ | |
442 | for (i = 0; i < max_pdp; i++) | |
443 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 444 | |
bf2b4ed2 | 445 | return 0; |
7ad47cf2 BW |
446 | |
447 | unwind_out: | |
448 | while (i--) { | |
449 | gen8_free_page_tables(pt_pages[i]); | |
450 | kfree(pt_pages[i]); | |
451 | } | |
452 | ||
453 | return ret; | |
bf2b4ed2 BW |
454 | } |
455 | ||
456 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
457 | { | |
458 | int i; | |
459 | ||
460 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
461 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
462 | sizeof(dma_addr_t), | |
463 | GFP_KERNEL); | |
464 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
465 | return -ENOMEM; | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
472 | const int max_pdp) | |
473 | { | |
474 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
475 | if (!ppgtt->pd_pages) | |
476 | return -ENOMEM; | |
477 | ||
478 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
479 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
485 | const int max_pdp) | |
486 | { | |
487 | int ret; | |
488 | ||
489 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
494 | if (ret) { | |
495 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
496 | return ret; | |
497 | } | |
498 | ||
499 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
500 | ||
501 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
502 | if (ret) | |
503 | gen8_ppgtt_free(ppgtt); | |
504 | ||
505 | return ret; | |
506 | } | |
507 | ||
508 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
509 | const int pd) | |
510 | { | |
511 | dma_addr_t pd_addr; | |
512 | int ret; | |
513 | ||
514 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
515 | &ppgtt->pd_pages[pd], 0, | |
516 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
517 | ||
518 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
528 | const int pd, | |
529 | const int pt) | |
530 | { | |
531 | dma_addr_t pt_addr; | |
532 | struct page *p; | |
533 | int ret; | |
534 | ||
7ad47cf2 | 535 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
536 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
537 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
538 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
539 | if (ret) | |
540 | return ret; | |
541 | ||
542 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
37aca44a | 547 | /** |
f3a964b9 BW |
548 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
549 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
550 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
551 | * space. | |
37aca44a | 552 | * |
f3a964b9 BW |
553 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
554 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 555 | * TODO: Do something with the size parameter |
f3a964b9 | 556 | */ |
37aca44a BW |
557 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
558 | { | |
37aca44a | 559 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 560 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 561 | int i, j, ret; |
37aca44a BW |
562 | |
563 | if (size % (1<<30)) | |
564 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
565 | ||
bf2b4ed2 BW |
566 | /* 1. Do all our allocations for page directories and page tables. */ |
567 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
568 | if (ret) | |
569 | return ret; | |
f3a964b9 | 570 | |
37aca44a | 571 | /* |
bf2b4ed2 | 572 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
573 | */ |
574 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 575 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
576 | if (ret) |
577 | goto bail; | |
37aca44a | 578 | |
37aca44a | 579 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 580 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
581 | if (ret) |
582 | goto bail; | |
37aca44a BW |
583 | } |
584 | } | |
585 | ||
f3a964b9 BW |
586 | /* |
587 | * 3. Map all the page directory entires to point to the page tables | |
588 | * we've allocated. | |
589 | * | |
590 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 591 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
592 | * will never need to touch the PDEs again. |
593 | */ | |
b1fe6673 BW |
594 | for (i = 0; i < max_pdp; i++) { |
595 | gen8_ppgtt_pde_t *pd_vaddr; | |
596 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
597 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
598 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
599 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
600 | I915_CACHE_LLC); | |
601 | } | |
fd1ab8f4 RB |
602 | if (!HAS_LLC(ppgtt->base.dev)) |
603 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
604 | kunmap_atomic(pd_vaddr); |
605 | } | |
606 | ||
f3a964b9 BW |
607 | ppgtt->enable = gen8_ppgtt_enable; |
608 | ppgtt->switch_mm = gen8_mm_switch; | |
609 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
610 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
611 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
612 | ppgtt->base.start = 0; | |
5abbcca3 | 613 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 614 | |
5abbcca3 | 615 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 616 | |
37aca44a BW |
617 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
618 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
619 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
620 | ppgtt->num_pd_entries, |
621 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 622 | return 0; |
37aca44a | 623 | |
f3a964b9 BW |
624 | bail: |
625 | gen8_ppgtt_unmap_pages(ppgtt); | |
626 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
627 | return ret; |
628 | } | |
629 | ||
87d60b63 BW |
630 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
631 | { | |
632 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
633 | struct i915_address_space *vm = &ppgtt->base; | |
634 | gen6_gtt_pte_t __iomem *pd_addr; | |
635 | gen6_gtt_pte_t scratch_pte; | |
636 | uint32_t pd_entry; | |
637 | int pte, pde; | |
638 | ||
24f3a8cf | 639 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
640 | |
641 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
642 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
643 | ||
644 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
645 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
646 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
647 | u32 expected; | |
648 | gen6_gtt_pte_t *pt_vaddr; | |
649 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
650 | pd_entry = readl(pd_addr + pde); | |
651 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
652 | ||
653 | if (pd_entry != expected) | |
654 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
655 | pde, | |
656 | pd_entry, | |
657 | expected); | |
658 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
659 | ||
660 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
661 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
662 | unsigned long va = | |
663 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
664 | (pte * PAGE_SIZE); | |
665 | int i; | |
666 | bool found = false; | |
667 | for (i = 0; i < 4; i++) | |
668 | if (pt_vaddr[pte + i] != scratch_pte) | |
669 | found = true; | |
670 | if (!found) | |
671 | continue; | |
672 | ||
673 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
674 | for (i = 0; i < 4; i++) { | |
675 | if (pt_vaddr[pte + i] != scratch_pte) | |
676 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
677 | else | |
678 | seq_puts(m, " SCRATCH "); | |
679 | } | |
680 | seq_puts(m, "\n"); | |
681 | } | |
682 | kunmap_atomic(pt_vaddr); | |
683 | } | |
684 | } | |
685 | ||
3e302542 | 686 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 687 | { |
853ba5d2 | 688 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
689 | gen6_gtt_pte_t __iomem *pd_addr; |
690 | uint32_t pd_entry; | |
691 | int i; | |
692 | ||
0a732870 | 693 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
694 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
695 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
696 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
697 | dma_addr_t pt_addr; | |
698 | ||
699 | pt_addr = ppgtt->pt_dma_addr[i]; | |
700 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
701 | pd_entry |= GEN6_PDE_VALID; | |
702 | ||
703 | writel(pd_entry, pd_addr + i); | |
704 | } | |
705 | readl(pd_addr); | |
3e302542 BW |
706 | } |
707 | ||
b4a74e3a | 708 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 709 | { |
b4a74e3a BW |
710 | BUG_ON(ppgtt->pd_offset & 0x3f); |
711 | ||
712 | return (ppgtt->pd_offset / 64) << 16; | |
713 | } | |
714 | ||
90252e5c | 715 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 716 | struct intel_engine_cs *ring, |
90252e5c BW |
717 | bool synchronous) |
718 | { | |
719 | struct drm_device *dev = ppgtt->base.dev; | |
720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
721 | int ret; | |
722 | ||
723 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
724 | * manually frob these bits. Ideally we could use the ring functions, | |
725 | * except our error handling makes it quite difficult (can't use | |
726 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
727 | * | |
728 | * FIXME: We should try not to special case reset | |
729 | */ | |
730 | if (synchronous || | |
731 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
732 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
733 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
734 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
735 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
736 | return 0; | |
737 | } | |
738 | ||
739 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
740 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
741 | if (ret) | |
742 | return ret; | |
743 | ||
744 | ret = intel_ring_begin(ring, 6); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
749 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
750 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
751 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
752 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
753 | intel_ring_emit(ring, MI_NOOP); | |
754 | intel_ring_advance(ring); | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
48a10389 | 759 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 760 | struct intel_engine_cs *ring, |
48a10389 BW |
761 | bool synchronous) |
762 | { | |
763 | struct drm_device *dev = ppgtt->base.dev; | |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
765 | int ret; | |
766 | ||
767 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
768 | * manually frob these bits. Ideally we could use the ring functions, | |
769 | * except our error handling makes it quite difficult (can't use | |
770 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
771 | * | |
772 | * FIXME: We should try not to special case reset | |
773 | */ | |
774 | if (synchronous || | |
775 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
776 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
777 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
778 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
779 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
780 | return 0; | |
781 | } | |
782 | ||
783 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
784 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
785 | if (ret) | |
786 | return ret; | |
787 | ||
788 | ret = intel_ring_begin(ring, 6); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
792 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
793 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
794 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
795 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
796 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
797 | intel_ring_emit(ring, MI_NOOP); | |
798 | intel_ring_advance(ring); | |
799 | ||
90252e5c BW |
800 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
801 | if (ring->id != RCS) { | |
802 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
803 | if (ret) | |
804 | return ret; | |
805 | } | |
806 | ||
48a10389 BW |
807 | return 0; |
808 | } | |
809 | ||
eeb9488e | 810 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 811 | struct intel_engine_cs *ring, |
eeb9488e BW |
812 | bool synchronous) |
813 | { | |
814 | struct drm_device *dev = ppgtt->base.dev; | |
815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
816 | ||
48a10389 BW |
817 | if (!synchronous) |
818 | return 0; | |
819 | ||
eeb9488e BW |
820 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
821 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
822 | ||
823 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
828 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
829 | { | |
830 | struct drm_device *dev = ppgtt->base.dev; | |
831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 832 | struct intel_engine_cs *ring; |
eeb9488e | 833 | int j, ret; |
3e302542 | 834 | |
eeb9488e BW |
835 | for_each_ring(ring, dev_priv, j) { |
836 | I915_WRITE(RING_MODE_GEN7(ring), | |
837 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 838 | |
d2ff7192 BW |
839 | /* We promise to do a switch later with FULL PPGTT. If this is |
840 | * aliasing, this is the one and only switch we'll do */ | |
841 | if (USES_FULL_PPGTT(dev)) | |
842 | continue; | |
6197349b | 843 | |
eeb9488e BW |
844 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
845 | if (ret) | |
846 | goto err_out; | |
847 | } | |
6197349b | 848 | |
eeb9488e | 849 | return 0; |
6197349b | 850 | |
eeb9488e BW |
851 | err_out: |
852 | for_each_ring(ring, dev_priv, j) | |
853 | I915_WRITE(RING_MODE_GEN7(ring), | |
854 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
855 | return ret; | |
856 | } | |
6197349b | 857 | |
b4a74e3a | 858 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 859 | { |
a3d67d23 | 860 | struct drm_device *dev = ppgtt->base.dev; |
50227e1c | 861 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 862 | struct intel_engine_cs *ring; |
b4a74e3a | 863 | uint32_t ecochk, ecobits; |
3e302542 | 864 | int i; |
6197349b | 865 | |
b4a74e3a BW |
866 | ecobits = I915_READ(GAC_ECO_BITS); |
867 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 868 | |
b4a74e3a BW |
869 | ecochk = I915_READ(GAM_ECOCHK); |
870 | if (IS_HASWELL(dev)) { | |
871 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
872 | } else { | |
873 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
874 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
875 | } | |
876 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 877 | |
b4a74e3a | 878 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 879 | int ret; |
6197349b | 880 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
881 | I915_WRITE(RING_MODE_GEN7(ring), |
882 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
883 | |
884 | /* We promise to do a switch later with FULL PPGTT. If this is | |
885 | * aliasing, this is the one and only switch we'll do */ | |
886 | if (USES_FULL_PPGTT(dev)) | |
887 | continue; | |
888 | ||
eeb9488e BW |
889 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
890 | if (ret) | |
891 | return ret; | |
6197349b BW |
892 | } |
893 | ||
b4a74e3a BW |
894 | return 0; |
895 | } | |
6197349b | 896 | |
b4a74e3a BW |
897 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
898 | { | |
899 | struct drm_device *dev = ppgtt->base.dev; | |
50227e1c | 900 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 901 | struct intel_engine_cs *ring; |
b4a74e3a BW |
902 | uint32_t ecochk, gab_ctl, ecobits; |
903 | int i; | |
a65c2fcd | 904 | |
b4a74e3a BW |
905 | ecobits = I915_READ(GAC_ECO_BITS); |
906 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
907 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 908 | |
b4a74e3a BW |
909 | gab_ctl = I915_READ(GAB_CTL); |
910 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
911 | ||
912 | ecochk = I915_READ(GAM_ECOCHK); | |
913 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
914 | ||
915 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 916 | |
b4a74e3a | 917 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
918 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
919 | if (ret) | |
920 | return ret; | |
6197349b | 921 | } |
b4a74e3a | 922 | |
b7c36d25 | 923 | return 0; |
6197349b BW |
924 | } |
925 | ||
1d2a314c | 926 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 927 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
928 | uint64_t start, |
929 | uint64_t length, | |
828c7908 | 930 | bool use_scratch) |
1d2a314c | 931 | { |
853ba5d2 BW |
932 | struct i915_hw_ppgtt *ppgtt = |
933 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 934 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
935 | unsigned first_entry = start >> PAGE_SHIFT; |
936 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 937 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
938 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
939 | unsigned last_pte, i; | |
1d2a314c | 940 | |
24f3a8cf | 941 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 942 | |
7bddb01f DV |
943 | while (num_entries) { |
944 | last_pte = first_pte + num_entries; | |
945 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
946 | last_pte = I915_PPGTT_PT_ENTRIES; | |
947 | ||
a15326a5 | 948 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 949 | |
7bddb01f DV |
950 | for (i = first_pte; i < last_pte; i++) |
951 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
952 | |
953 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 954 | |
7bddb01f DV |
955 | num_entries -= last_pte - first_pte; |
956 | first_pte = 0; | |
a15326a5 | 957 | act_pt++; |
7bddb01f | 958 | } |
1d2a314c DV |
959 | } |
960 | ||
853ba5d2 | 961 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 962 | struct sg_table *pages, |
782f1495 | 963 | uint64_t start, |
24f3a8cf | 964 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 965 | { |
853ba5d2 BW |
966 | struct i915_hw_ppgtt *ppgtt = |
967 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 968 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 969 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 970 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
971 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
972 | struct sg_page_iter sg_iter; | |
973 | ||
cc79714f | 974 | pt_vaddr = NULL; |
6e995e23 | 975 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
976 | if (pt_vaddr == NULL) |
977 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 978 | |
cc79714f CW |
979 | pt_vaddr[act_pte] = |
980 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
981 | cache_level, true, flags); |
982 | ||
6e995e23 ID |
983 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
984 | kunmap_atomic(pt_vaddr); | |
cc79714f | 985 | pt_vaddr = NULL; |
a15326a5 | 986 | act_pt++; |
6e995e23 | 987 | act_pte = 0; |
def886c3 | 988 | } |
def886c3 | 989 | } |
cc79714f CW |
990 | if (pt_vaddr) |
991 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
992 | } |
993 | ||
a00d825d | 994 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 995 | { |
3440d265 DV |
996 | int i; |
997 | ||
998 | if (ppgtt->pt_dma_addr) { | |
999 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 1000 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
1001 | ppgtt->pt_dma_addr[i], |
1002 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1003 | } | |
a00d825d BW |
1004 | } |
1005 | ||
1006 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
1007 | { | |
1008 | int i; | |
3440d265 DV |
1009 | |
1010 | kfree(ppgtt->pt_dma_addr); | |
1011 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1012 | __free_page(ppgtt->pt_pages[i]); | |
1013 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1014 | } |
1015 | ||
a00d825d BW |
1016 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1017 | { | |
1018 | struct i915_hw_ppgtt *ppgtt = | |
1019 | container_of(vm, struct i915_hw_ppgtt, base); | |
1020 | ||
1021 | list_del(&vm->global_link); | |
1022 | drm_mm_takedown(&ppgtt->base.mm); | |
1023 | drm_mm_remove_node(&ppgtt->node); | |
1024 | ||
1025 | gen6_ppgtt_unmap_pages(ppgtt); | |
1026 | gen6_ppgtt_free(ppgtt); | |
1027 | } | |
1028 | ||
b146520f | 1029 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1030 | { |
853ba5d2 | 1031 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1032 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1033 | bool retried = false; |
b146520f | 1034 | int ret; |
1d2a314c | 1035 | |
c8d4c0d6 BW |
1036 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1037 | * allocator works in address space sizes, so it's multiplied by page | |
1038 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1039 | */ | |
1040 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1041 | alloc: |
c8d4c0d6 BW |
1042 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1043 | &ppgtt->node, GEN6_PD_SIZE, | |
1044 | GEN6_PD_ALIGN, 0, | |
1045 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1046 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1047 | if (ret == -ENOSPC && !retried) { |
1048 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1049 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1050 | I915_CACHE_NONE, |
1051 | 0, dev_priv->gtt.base.total, | |
1052 | 0); | |
e3cc1995 BW |
1053 | if (ret) |
1054 | return ret; | |
1055 | ||
1056 | retried = true; | |
1057 | goto alloc; | |
1058 | } | |
c8d4c0d6 BW |
1059 | |
1060 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1061 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1062 | |
6670a5a5 | 1063 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1064 | return ret; |
1065 | } | |
1066 | ||
1067 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1068 | { | |
1069 | int i; | |
1070 | ||
a1e22653 | 1071 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1072 | GFP_KERNEL); |
b146520f BW |
1073 | |
1074 | if (!ppgtt->pt_pages) | |
3440d265 | 1075 | return -ENOMEM; |
1d2a314c DV |
1076 | |
1077 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1078 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1079 | if (!ppgtt->pt_pages[i]) { |
1080 | gen6_ppgtt_free(ppgtt); | |
1081 | return -ENOMEM; | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1089 | { | |
1090 | int ret; | |
1091 | ||
1092 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | ||
1096 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1097 | if (ret) { | |
1098 | drm_mm_remove_node(&ppgtt->node); | |
1099 | return ret; | |
1d2a314c DV |
1100 | } |
1101 | ||
a1e22653 | 1102 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1103 | GFP_KERNEL); |
b146520f BW |
1104 | if (!ppgtt->pt_dma_addr) { |
1105 | drm_mm_remove_node(&ppgtt->node); | |
1106 | gen6_ppgtt_free(ppgtt); | |
1107 | return -ENOMEM; | |
1108 | } | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1114 | { | |
1115 | struct drm_device *dev = ppgtt->base.dev; | |
1116 | int i; | |
1d2a314c | 1117 | |
8d2e6308 BW |
1118 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1119 | dma_addr_t pt_addr; | |
211c568b | 1120 | |
8d2e6308 BW |
1121 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1122 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1123 | |
8d2e6308 | 1124 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1125 | gen6_ppgtt_unmap_pages(ppgtt); |
1126 | return -EIO; | |
211c568b | 1127 | } |
b146520f | 1128 | |
8d2e6308 | 1129 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1130 | } |
1d2a314c | 1131 | |
b146520f BW |
1132 | return 0; |
1133 | } | |
1134 | ||
1135 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1136 | { | |
1137 | struct drm_device *dev = ppgtt->base.dev; | |
1138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1139 | int ret; | |
1140 | ||
1141 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1142 | if (IS_GEN6(dev)) { | |
1143 | ppgtt->enable = gen6_ppgtt_enable; | |
1144 | ppgtt->switch_mm = gen6_mm_switch; | |
1145 | } else if (IS_HASWELL(dev)) { | |
1146 | ppgtt->enable = gen7_ppgtt_enable; | |
1147 | ppgtt->switch_mm = hsw_mm_switch; | |
1148 | } else if (IS_GEN7(dev)) { | |
1149 | ppgtt->enable = gen7_ppgtt_enable; | |
1150 | ppgtt->switch_mm = gen7_mm_switch; | |
1151 | } else | |
1152 | BUG(); | |
1153 | ||
1154 | ret = gen6_ppgtt_alloc(ppgtt); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
1158 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1159 | if (ret) { | |
1160 | gen6_ppgtt_free(ppgtt); | |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1165 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1166 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1167 | ppgtt->base.start = 0; |
5a6c93fe | 1168 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1169 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1170 | |
c8d4c0d6 BW |
1171 | ppgtt->pd_offset = |
1172 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1173 | |
b146520f | 1174 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1175 | |
b146520f BW |
1176 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1177 | ppgtt->node.size >> 20, | |
1178 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1179 | |
b146520f | 1180 | return 0; |
3440d265 DV |
1181 | } |
1182 | ||
ee960be7 | 1183 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1184 | { |
1185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1186 | int ret = 0; |
3440d265 | 1187 | |
853ba5d2 | 1188 | ppgtt->base.dev = dev; |
8407bb91 | 1189 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1190 | |
3ed124b2 BW |
1191 | if (INTEL_INFO(dev)->gen < 8) |
1192 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1193 | else if (IS_GEN8(dev)) |
37aca44a | 1194 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1195 | else |
1196 | BUG(); | |
1197 | ||
c7c48dfd | 1198 | if (!ret) { |
7e0d96bc | 1199 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1200 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1201 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1202 | ppgtt->base.total); | |
7e0d96bc BW |
1203 | i915_init_vm(dev_priv, &ppgtt->base); |
1204 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1205 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1206 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1207 | ppgtt->pd_offset << 10); | |
1208 | } | |
93bd8649 | 1209 | } |
1d2a314c DV |
1210 | |
1211 | return ret; | |
1212 | } | |
1213 | ||
ee960be7 DV |
1214 | void i915_ppgtt_release(struct kref *kref) |
1215 | { | |
1216 | struct i915_hw_ppgtt *ppgtt = | |
1217 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1218 | ||
1219 | /* vmas should already be unbound */ | |
1220 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1221 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1222 | ||
1223 | ppgtt->base.cleanup(&ppgtt->base); | |
1224 | kfree(ppgtt); | |
1225 | } | |
1226 | ||
7e0d96bc | 1227 | static void |
6f65e29a BW |
1228 | ppgtt_bind_vma(struct i915_vma *vma, |
1229 | enum i915_cache_level cache_level, | |
1230 | u32 flags) | |
1d2a314c | 1231 | { |
24f3a8cf AG |
1232 | /* Currently applicable only to VLV */ |
1233 | if (vma->obj->gt_ro) | |
1234 | flags |= PTE_READ_ONLY; | |
1235 | ||
782f1495 | 1236 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1237 | cache_level, flags); |
1d2a314c DV |
1238 | } |
1239 | ||
7e0d96bc | 1240 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1241 | { |
6f65e29a | 1242 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1243 | vma->node.start, |
1244 | vma->obj->base.size, | |
6f65e29a | 1245 | true); |
7bddb01f DV |
1246 | } |
1247 | ||
a81cc00c BW |
1248 | extern int intel_iommu_gfx_mapped; |
1249 | /* Certain Gen5 chipsets require require idling the GPU before | |
1250 | * unmapping anything from the GTT when VT-d is enabled. | |
1251 | */ | |
1252 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1253 | { | |
1254 | #ifdef CONFIG_INTEL_IOMMU | |
1255 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1256 | * was loaded first. | |
1257 | */ | |
1258 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1259 | return true; | |
1260 | #endif | |
1261 | return false; | |
1262 | } | |
1263 | ||
5c042287 BW |
1264 | static bool do_idling(struct drm_i915_private *dev_priv) |
1265 | { | |
1266 | bool ret = dev_priv->mm.interruptible; | |
1267 | ||
a81cc00c | 1268 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1269 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1270 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1271 | DRM_ERROR("Couldn't idle GPU\n"); |
1272 | /* Wait a bit, in hopes it avoids the hang */ | |
1273 | udelay(10); | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | return ret; | |
1278 | } | |
1279 | ||
1280 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1281 | { | |
a81cc00c | 1282 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1283 | dev_priv->mm.interruptible = interruptible; |
1284 | } | |
1285 | ||
828c7908 BW |
1286 | void i915_check_and_clear_faults(struct drm_device *dev) |
1287 | { | |
1288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1289 | struct intel_engine_cs *ring; |
828c7908 BW |
1290 | int i; |
1291 | ||
1292 | if (INTEL_INFO(dev)->gen < 6) | |
1293 | return; | |
1294 | ||
1295 | for_each_ring(ring, dev_priv, i) { | |
1296 | u32 fault_reg; | |
1297 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1298 | if (fault_reg & RING_FAULT_VALID) { | |
1299 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1300 | "\tAddr: 0x%08lx\\n" | |
1301 | "\tAddress space: %s\n" | |
1302 | "\tSource ID: %d\n" | |
1303 | "\tType: %d\n", | |
1304 | fault_reg & PAGE_MASK, | |
1305 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1306 | RING_FAULT_SRCID(fault_reg), | |
1307 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1308 | I915_WRITE(RING_FAULT_REG(ring), | |
1309 | fault_reg & ~RING_FAULT_VALID); | |
1310 | } | |
1311 | } | |
1312 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1313 | } | |
1314 | ||
1315 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1316 | { | |
1317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1318 | ||
1319 | /* Don't bother messing with faults pre GEN6 as we have little | |
1320 | * documentation supporting that it's a good idea. | |
1321 | */ | |
1322 | if (INTEL_INFO(dev)->gen < 6) | |
1323 | return; | |
1324 | ||
1325 | i915_check_and_clear_faults(dev); | |
1326 | ||
1327 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1328 | dev_priv->gtt.base.start, |
1329 | dev_priv->gtt.base.total, | |
e568af1c | 1330 | true); |
828c7908 BW |
1331 | } |
1332 | ||
76aaf220 DV |
1333 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1334 | { | |
1335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1336 | struct drm_i915_gem_object *obj; |
80da2161 | 1337 | struct i915_address_space *vm; |
76aaf220 | 1338 | |
828c7908 BW |
1339 | i915_check_and_clear_faults(dev); |
1340 | ||
bee4a186 | 1341 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1342 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1343 | dev_priv->gtt.base.start, |
1344 | dev_priv->gtt.base.total, | |
828c7908 | 1345 | true); |
bee4a186 | 1346 | |
35c20a60 | 1347 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1348 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1349 | &dev_priv->gtt.base); | |
1350 | if (!vma) | |
1351 | continue; | |
1352 | ||
2c22569b | 1353 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1354 | /* The bind_vma code tries to be smart about tracking mappings. |
1355 | * Unfortunately above, we've just wiped out the mappings | |
1356 | * without telling our object about it. So we need to fake it. | |
1357 | */ | |
1358 | obj->has_global_gtt_mapping = 0; | |
1359 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1360 | } |
1361 | ||
80da2161 | 1362 | |
a2319c08 | 1363 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1364 | if (IS_CHERRYVIEW(dev)) |
1365 | chv_setup_private_ppat(dev_priv); | |
1366 | else | |
1367 | bdw_setup_private_ppat(dev_priv); | |
1368 | ||
80da2161 | 1369 | return; |
a2319c08 | 1370 | } |
80da2161 BW |
1371 | |
1372 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1373 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1374 | if (i915_is_ggtt(vm)) { | |
1375 | if (dev_priv->mm.aliasing_ppgtt) | |
1376 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1377 | continue; | |
1378 | } | |
1379 | ||
1380 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1381 | } |
1382 | ||
e76e9aeb | 1383 | i915_gem_chipset_flush(dev); |
76aaf220 | 1384 | } |
7c2e6fdf | 1385 | |
74163907 | 1386 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1387 | { |
9da3da66 | 1388 | if (obj->has_dma_mapping) |
74163907 | 1389 | return 0; |
9da3da66 CW |
1390 | |
1391 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1392 | obj->pages->sgl, obj->pages->nents, | |
1393 | PCI_DMA_BIDIRECTIONAL)) | |
1394 | return -ENOSPC; | |
1395 | ||
1396 | return 0; | |
7c2e6fdf DV |
1397 | } |
1398 | ||
94ec8f61 BW |
1399 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1400 | { | |
1401 | #ifdef writeq | |
1402 | writeq(pte, addr); | |
1403 | #else | |
1404 | iowrite32((u32)pte, addr); | |
1405 | iowrite32(pte >> 32, addr + 4); | |
1406 | #endif | |
1407 | } | |
1408 | ||
1409 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1410 | struct sg_table *st, | |
782f1495 | 1411 | uint64_t start, |
24f3a8cf | 1412 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1413 | { |
1414 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1415 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1416 | gen8_gtt_pte_t __iomem *gtt_entries = |
1417 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1418 | int i = 0; | |
1419 | struct sg_page_iter sg_iter; | |
57007df7 | 1420 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1421 | |
1422 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1423 | addr = sg_dma_address(sg_iter.sg) + | |
1424 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1425 | gen8_set_pte(>t_entries[i], | |
1426 | gen8_pte_encode(addr, level, true)); | |
1427 | i++; | |
1428 | } | |
1429 | ||
1430 | /* | |
1431 | * XXX: This serves as a posting read to make sure that the PTE has | |
1432 | * actually been updated. There is some concern that even though | |
1433 | * registers and PTEs are within the same BAR that they are potentially | |
1434 | * of NUMA access patterns. Therefore, even with the way we assume | |
1435 | * hardware should work, we must keep this posting read for paranoia. | |
1436 | */ | |
1437 | if (i != 0) | |
1438 | WARN_ON(readq(>t_entries[i-1]) | |
1439 | != gen8_pte_encode(addr, level, true)); | |
1440 | ||
94ec8f61 BW |
1441 | /* This next bit makes the above posting read even more important. We |
1442 | * want to flush the TLBs only after we're certain all the PTE updates | |
1443 | * have finished. | |
1444 | */ | |
1445 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1446 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1447 | } |
1448 | ||
e76e9aeb BW |
1449 | /* |
1450 | * Binds an object into the global gtt with the specified cache level. The object | |
1451 | * will be accessible to the GPU via commands whose operands reference offsets | |
1452 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1453 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1454 | */ | |
853ba5d2 | 1455 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1456 | struct sg_table *st, |
782f1495 | 1457 | uint64_t start, |
24f3a8cf | 1458 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1459 | { |
853ba5d2 | 1460 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1461 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1462 | gen6_gtt_pte_t __iomem *gtt_entries = |
1463 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1464 | int i = 0; |
1465 | struct sg_page_iter sg_iter; | |
57007df7 | 1466 | dma_addr_t addr = 0; |
e76e9aeb | 1467 | |
6e995e23 | 1468 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1469 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1470 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1471 | i++; |
e76e9aeb BW |
1472 | } |
1473 | ||
e76e9aeb BW |
1474 | /* XXX: This serves as a posting read to make sure that the PTE has |
1475 | * actually been updated. There is some concern that even though | |
1476 | * registers and PTEs are within the same BAR that they are potentially | |
1477 | * of NUMA access patterns. Therefore, even with the way we assume | |
1478 | * hardware should work, we must keep this posting read for paranoia. | |
1479 | */ | |
57007df7 PM |
1480 | if (i != 0) { |
1481 | unsigned long gtt = readl(>t_entries[i-1]); | |
1482 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1483 | } | |
0f9b91c7 BW |
1484 | |
1485 | /* This next bit makes the above posting read even more important. We | |
1486 | * want to flush the TLBs only after we're certain all the PTE updates | |
1487 | * have finished. | |
1488 | */ | |
1489 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1490 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1491 | } |
1492 | ||
94ec8f61 | 1493 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1494 | uint64_t start, |
1495 | uint64_t length, | |
94ec8f61 BW |
1496 | bool use_scratch) |
1497 | { | |
1498 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1499 | unsigned first_entry = start >> PAGE_SHIFT; |
1500 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1501 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1502 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1503 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1504 | int i; | |
1505 | ||
1506 | if (WARN(num_entries > max_entries, | |
1507 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1508 | first_entry, num_entries, max_entries)) | |
1509 | num_entries = max_entries; | |
1510 | ||
1511 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1512 | I915_CACHE_LLC, | |
1513 | use_scratch); | |
1514 | for (i = 0; i < num_entries; i++) | |
1515 | gen8_set_pte(>t_base[i], scratch_pte); | |
1516 | readl(gtt_base); | |
1517 | } | |
1518 | ||
853ba5d2 | 1519 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1520 | uint64_t start, |
1521 | uint64_t length, | |
828c7908 | 1522 | bool use_scratch) |
7faf1ab2 | 1523 | { |
853ba5d2 | 1524 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1525 | unsigned first_entry = start >> PAGE_SHIFT; |
1526 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1527 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1528 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1529 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1530 | int i; |
1531 | ||
1532 | if (WARN(num_entries > max_entries, | |
1533 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1534 | first_entry, num_entries, max_entries)) | |
1535 | num_entries = max_entries; | |
1536 | ||
24f3a8cf | 1537 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1538 | |
7faf1ab2 DV |
1539 | for (i = 0; i < num_entries; i++) |
1540 | iowrite32(scratch_pte, >t_base[i]); | |
1541 | readl(gtt_base); | |
1542 | } | |
1543 | ||
6f65e29a BW |
1544 | |
1545 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1546 | enum i915_cache_level cache_level, | |
1547 | u32 unused) | |
7faf1ab2 | 1548 | { |
6f65e29a | 1549 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1550 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1551 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1552 | ||
6f65e29a BW |
1553 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1554 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1555 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1556 | } |
1557 | ||
853ba5d2 | 1558 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1559 | uint64_t start, |
1560 | uint64_t length, | |
828c7908 | 1561 | bool unused) |
7faf1ab2 | 1562 | { |
782f1495 BW |
1563 | unsigned first_entry = start >> PAGE_SHIFT; |
1564 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1565 | intel_gtt_clear_range(first_entry, num_entries); |
1566 | } | |
1567 | ||
6f65e29a BW |
1568 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1569 | { | |
1570 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1571 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1572 | |
6f65e29a BW |
1573 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1574 | vma->obj->has_global_gtt_mapping = 0; | |
1575 | intel_gtt_clear_range(first, size); | |
1576 | } | |
7faf1ab2 | 1577 | |
6f65e29a BW |
1578 | static void ggtt_bind_vma(struct i915_vma *vma, |
1579 | enum i915_cache_level cache_level, | |
1580 | u32 flags) | |
d5bd1449 | 1581 | { |
6f65e29a | 1582 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1583 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1584 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1585 | |
24f3a8cf AG |
1586 | /* Currently applicable only to VLV */ |
1587 | if (obj->gt_ro) | |
1588 | flags |= PTE_READ_ONLY; | |
1589 | ||
6f65e29a BW |
1590 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1591 | * or we have a global mapping already but the cacheability flags have | |
1592 | * changed, set the global PTEs. | |
1593 | * | |
1594 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1595 | * instead if none of the above hold true. | |
1596 | * | |
1597 | * NB: A global mapping should only be needed for special regions like | |
1598 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1599 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1600 | */ | |
1601 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1602 | if (!obj->has_global_gtt_mapping || | |
1603 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1604 | vma->vm->insert_entries(vma->vm, obj->pages, |
1605 | vma->node.start, | |
24f3a8cf | 1606 | cache_level, flags); |
6f65e29a BW |
1607 | obj->has_global_gtt_mapping = 1; |
1608 | } | |
1609 | } | |
d5bd1449 | 1610 | |
6f65e29a BW |
1611 | if (dev_priv->mm.aliasing_ppgtt && |
1612 | (!obj->has_aliasing_ppgtt_mapping || | |
1613 | (cache_level != obj->cache_level))) { | |
1614 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1615 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1616 | vma->obj->pages, |
1617 | vma->node.start, | |
24f3a8cf | 1618 | cache_level, flags); |
6f65e29a BW |
1619 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1620 | } | |
d5bd1449 CW |
1621 | } |
1622 | ||
6f65e29a | 1623 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1624 | { |
6f65e29a | 1625 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1626 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1627 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1628 | |
1629 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1630 | vma->vm->clear_range(vma->vm, |
1631 | vma->node.start, | |
1632 | obj->base.size, | |
6f65e29a BW |
1633 | true); |
1634 | obj->has_global_gtt_mapping = 0; | |
1635 | } | |
74898d7e | 1636 | |
6f65e29a BW |
1637 | if (obj->has_aliasing_ppgtt_mapping) { |
1638 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1639 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1640 | vma->node.start, |
1641 | obj->base.size, | |
6f65e29a BW |
1642 | true); |
1643 | obj->has_aliasing_ppgtt_mapping = 0; | |
1644 | } | |
74163907 DV |
1645 | } |
1646 | ||
1647 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1648 | { |
5c042287 BW |
1649 | struct drm_device *dev = obj->base.dev; |
1650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1651 | bool interruptible; | |
1652 | ||
1653 | interruptible = do_idling(dev_priv); | |
1654 | ||
9da3da66 CW |
1655 | if (!obj->has_dma_mapping) |
1656 | dma_unmap_sg(&dev->pdev->dev, | |
1657 | obj->pages->sgl, obj->pages->nents, | |
1658 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1659 | |
1660 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1661 | } |
644ec02b | 1662 | |
42d6ab48 CW |
1663 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1664 | unsigned long color, | |
1665 | unsigned long *start, | |
1666 | unsigned long *end) | |
1667 | { | |
1668 | if (node->color != color) | |
1669 | *start += 4096; | |
1670 | ||
1671 | if (!list_empty(&node->node_list)) { | |
1672 | node = list_entry(node->node_list.next, | |
1673 | struct drm_mm_node, | |
1674 | node_list); | |
1675 | if (node->allocated && node->color != color) | |
1676 | *end -= 4096; | |
1677 | } | |
1678 | } | |
fbe5d36e | 1679 | |
d7e5008f BW |
1680 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1681 | unsigned long start, | |
1682 | unsigned long mappable_end, | |
1683 | unsigned long end) | |
644ec02b | 1684 | { |
e78891ca BW |
1685 | /* Let GEM Manage all of the aperture. |
1686 | * | |
1687 | * However, leave one page at the end still bound to the scratch page. | |
1688 | * There are a number of places where the hardware apparently prefetches | |
1689 | * past the end of the object, and we've seen multiple hangs with the | |
1690 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1691 | * aperture. One page should be enough to keep any prefetching inside | |
1692 | * of the aperture. | |
1693 | */ | |
40d74980 BW |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; |
1695 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1696 | struct drm_mm_node *entry; |
1697 | struct drm_i915_gem_object *obj; | |
1698 | unsigned long hole_start, hole_end; | |
644ec02b | 1699 | |
35451cb6 BW |
1700 | BUG_ON(mappable_end > end); |
1701 | ||
ed2f3452 | 1702 | /* Subtract the guard page ... */ |
40d74980 | 1703 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1704 | if (!HAS_LLC(dev)) |
93bd8649 | 1705 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1706 | |
ed2f3452 | 1707 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1708 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1709 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1710 | int ret; |
edd41a87 | 1711 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1712 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1713 | ||
1714 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1715 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1716 | if (ret) |
b3a070cc | 1717 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1718 | obj->has_global_gtt_mapping = 1; |
1719 | } | |
1720 | ||
853ba5d2 BW |
1721 | dev_priv->gtt.base.start = start; |
1722 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1723 | |
ed2f3452 | 1724 | /* Clear any non-preallocated blocks */ |
40d74980 | 1725 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1726 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1727 | hole_start, hole_end); | |
782f1495 BW |
1728 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1729 | hole_end - hole_start, true); | |
ed2f3452 CW |
1730 | } |
1731 | ||
1732 | /* And finally clear the reserved guard page */ | |
782f1495 | 1733 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1734 | } |
1735 | ||
d7e5008f BW |
1736 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1737 | { | |
1738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1739 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1740 | |
853ba5d2 | 1741 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1742 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1743 | |
e78891ca | 1744 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1745 | } |
1746 | ||
1747 | static int setup_scratch_page(struct drm_device *dev) | |
1748 | { | |
1749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1750 | struct page *page; | |
1751 | dma_addr_t dma_addr; | |
1752 | ||
1753 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1754 | if (page == NULL) | |
1755 | return -ENOMEM; | |
1756 | get_page(page); | |
1757 | set_pages_uc(page, 1); | |
1758 | ||
1759 | #ifdef CONFIG_INTEL_IOMMU | |
1760 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1761 | PCI_DMA_BIDIRECTIONAL); | |
1762 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1763 | return -EINVAL; | |
1764 | #else | |
1765 | dma_addr = page_to_phys(page); | |
1766 | #endif | |
853ba5d2 BW |
1767 | dev_priv->gtt.base.scratch.page = page; |
1768 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1769 | |
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | static void teardown_scratch_page(struct drm_device *dev) | |
1774 | { | |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1776 | struct page *page = dev_priv->gtt.base.scratch.page; |
1777 | ||
1778 | set_pages_wb(page, 1); | |
1779 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1780 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1781 | put_page(page); |
1782 | __free_page(page); | |
e76e9aeb BW |
1783 | } |
1784 | ||
1785 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1786 | { | |
1787 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1788 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1789 | return snb_gmch_ctl << 20; | |
1790 | } | |
1791 | ||
9459d252 BW |
1792 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1793 | { | |
1794 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1795 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1796 | if (bdw_gmch_ctl) | |
1797 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1798 | |
1799 | #ifdef CONFIG_X86_32 | |
1800 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1801 | if (bdw_gmch_ctl > 4) | |
1802 | bdw_gmch_ctl = 4; | |
1803 | #endif | |
1804 | ||
9459d252 BW |
1805 | return bdw_gmch_ctl << 20; |
1806 | } | |
1807 | ||
d7f25f23 DL |
1808 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1809 | { | |
1810 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1811 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1812 | ||
1813 | if (gmch_ctrl) | |
1814 | return 1 << (20 + gmch_ctrl); | |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
baa09f5f | 1819 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1820 | { |
1821 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1822 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1823 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1824 | } | |
1825 | ||
9459d252 BW |
1826 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1827 | { | |
1828 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1829 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1830 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1831 | } | |
1832 | ||
d7f25f23 DL |
1833 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1834 | { | |
1835 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1836 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1837 | ||
1838 | /* | |
1839 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1840 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1841 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1842 | */ | |
1843 | if (gmch_ctrl < 0x11) | |
1844 | return gmch_ctrl << 25; | |
1845 | else if (gmch_ctrl < 0x17) | |
1846 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1847 | else | |
1848 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1849 | } | |
1850 | ||
63340133 BW |
1851 | static int ggtt_probe_common(struct drm_device *dev, |
1852 | size_t gtt_size) | |
1853 | { | |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1855 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1856 | int ret; |
1857 | ||
1858 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1859 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1860 | (pci_resource_len(dev->pdev, 0) / 2); |
1861 | ||
21c34607 | 1862 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1863 | if (!dev_priv->gtt.gsm) { |
1864 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1865 | return -ENOMEM; | |
1866 | } | |
1867 | ||
1868 | ret = setup_scratch_page(dev); | |
1869 | if (ret) { | |
1870 | DRM_ERROR("Scratch setup failed\n"); | |
1871 | /* iounmap will also get called at remove, but meh */ | |
1872 | iounmap(dev_priv->gtt.gsm); | |
1873 | } | |
1874 | ||
1875 | return ret; | |
1876 | } | |
1877 | ||
fbe5d36e BW |
1878 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1879 | * bits. When using advanced contexts each context stores its own PAT, but | |
1880 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1881 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1882 | { |
fbe5d36e BW |
1883 | uint64_t pat; |
1884 | ||
1885 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1886 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1887 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1888 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1889 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1890 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1891 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1892 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1893 | ||
1894 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1895 | * write would work. */ | |
1896 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1897 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1898 | } | |
1899 | ||
ee0ce478 VS |
1900 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1901 | { | |
1902 | uint64_t pat; | |
1903 | ||
1904 | /* | |
1905 | * Map WB on BDW to snooped on CHV. | |
1906 | * | |
1907 | * Only the snoop bit has meaning for CHV, the rest is | |
1908 | * ignored. | |
1909 | * | |
1910 | * Note that the harware enforces snooping for all page | |
1911 | * table accesses. The snoop bit is actually ignored for | |
1912 | * PDEs. | |
1913 | */ | |
1914 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1915 | GEN8_PPAT(1, 0) | | |
1916 | GEN8_PPAT(2, 0) | | |
1917 | GEN8_PPAT(3, 0) | | |
1918 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1919 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1920 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1921 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1922 | ||
1923 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1924 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1925 | } | |
1926 | ||
63340133 BW |
1927 | static int gen8_gmch_probe(struct drm_device *dev, |
1928 | size_t *gtt_total, | |
1929 | size_t *stolen, | |
1930 | phys_addr_t *mappable_base, | |
1931 | unsigned long *mappable_end) | |
1932 | { | |
1933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1934 | unsigned int gtt_size; | |
1935 | u16 snb_gmch_ctl; | |
1936 | int ret; | |
1937 | ||
1938 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1939 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1940 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1941 | ||
1942 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1943 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1944 | ||
1945 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1946 | ||
d7f25f23 DL |
1947 | if (IS_CHERRYVIEW(dev)) { |
1948 | *stolen = chv_get_stolen_size(snb_gmch_ctl); | |
1949 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
1950 | } else { | |
1951 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1952 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
1953 | } | |
63340133 | 1954 | |
d31eb10e | 1955 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1956 | |
ee0ce478 VS |
1957 | if (IS_CHERRYVIEW(dev)) |
1958 | chv_setup_private_ppat(dev_priv); | |
1959 | else | |
1960 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 1961 | |
63340133 BW |
1962 | ret = ggtt_probe_common(dev, gtt_size); |
1963 | ||
94ec8f61 BW |
1964 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1965 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1966 | |
1967 | return ret; | |
1968 | } | |
1969 | ||
baa09f5f BW |
1970 | static int gen6_gmch_probe(struct drm_device *dev, |
1971 | size_t *gtt_total, | |
41907ddc BW |
1972 | size_t *stolen, |
1973 | phys_addr_t *mappable_base, | |
1974 | unsigned long *mappable_end) | |
e76e9aeb BW |
1975 | { |
1976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1977 | unsigned int gtt_size; |
e76e9aeb | 1978 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1979 | int ret; |
1980 | ||
41907ddc BW |
1981 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1982 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1983 | ||
baa09f5f BW |
1984 | /* 64/512MB is the current min/max we actually know of, but this is just |
1985 | * a coarse sanity check. | |
e76e9aeb | 1986 | */ |
41907ddc | 1987 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1988 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1989 | dev_priv->gtt.mappable_end); | |
1990 | return -ENXIO; | |
e76e9aeb BW |
1991 | } |
1992 | ||
e76e9aeb BW |
1993 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1994 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1995 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1996 | |
c4ae25ec | 1997 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1998 | |
63340133 BW |
1999 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2000 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2001 | |
63340133 | 2002 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2003 | |
853ba5d2 BW |
2004 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2005 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2006 | |
e76e9aeb BW |
2007 | return ret; |
2008 | } | |
2009 | ||
853ba5d2 | 2010 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2011 | { |
853ba5d2 BW |
2012 | |
2013 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2014 | |
4c2e0990 DV |
2015 | if (drm_mm_initialized(&vm->mm)) { |
2016 | drm_mm_takedown(&vm->mm); | |
2017 | list_del(&vm->global_link); | |
2018 | } | |
853ba5d2 BW |
2019 | iounmap(gtt->gsm); |
2020 | teardown_scratch_page(vm->dev); | |
644ec02b | 2021 | } |
baa09f5f BW |
2022 | |
2023 | static int i915_gmch_probe(struct drm_device *dev, | |
2024 | size_t *gtt_total, | |
41907ddc BW |
2025 | size_t *stolen, |
2026 | phys_addr_t *mappable_base, | |
2027 | unsigned long *mappable_end) | |
baa09f5f BW |
2028 | { |
2029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2030 | int ret; | |
2031 | ||
baa09f5f BW |
2032 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2033 | if (!ret) { | |
2034 | DRM_ERROR("failed to set up gmch\n"); | |
2035 | return -EIO; | |
2036 | } | |
2037 | ||
41907ddc | 2038 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2039 | |
2040 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2041 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2042 | |
c0a7f818 CW |
2043 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2044 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2045 | ||
baa09f5f BW |
2046 | return 0; |
2047 | } | |
2048 | ||
853ba5d2 | 2049 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f | 2050 | { |
4c2e0990 DV |
2051 | if (drm_mm_initialized(&vm->mm)) { |
2052 | drm_mm_takedown(&vm->mm); | |
2053 | list_del(&vm->global_link); | |
2054 | } | |
baa09f5f BW |
2055 | intel_gmch_remove(); |
2056 | } | |
2057 | ||
2058 | int i915_gem_gtt_init(struct drm_device *dev) | |
2059 | { | |
2060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2061 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2062 | int ret; |
2063 | ||
baa09f5f | 2064 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2065 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2066 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2067 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2068 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2069 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2070 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2071 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2072 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2073 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2074 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2075 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2076 | else if (INTEL_INFO(dev)->gen >= 7) |
2077 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2078 | else |
350ec881 | 2079 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2080 | } else { |
2081 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2082 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2083 | } |
2084 | ||
853ba5d2 | 2085 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2086 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2087 | if (ret) |
baa09f5f | 2088 | return ret; |
baa09f5f | 2089 | |
853ba5d2 BW |
2090 | gtt->base.dev = dev; |
2091 | ||
baa09f5f | 2092 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2093 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2094 | gtt->base.total >> 20); | |
b2f21b4d BW |
2095 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2096 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2097 | #ifdef CONFIG_INTEL_IOMMU |
2098 | if (intel_iommu_gfx_mapped) | |
2099 | DRM_INFO("VT-d active for gfx access\n"); | |
2100 | #endif | |
cfa7c862 DV |
2101 | /* |
2102 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2103 | * user's requested state against the hardware/driver capabilities. We | |
2104 | * do this now so that we can print out any log messages once rather | |
2105 | * than every time we check intel_enable_ppgtt(). | |
2106 | */ | |
2107 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2108 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2109 | |
2110 | return 0; | |
2111 | } | |
6f65e29a BW |
2112 | |
2113 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2114 | struct i915_address_space *vm) | |
2115 | { | |
2116 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2117 | if (vma == NULL) | |
2118 | return ERR_PTR(-ENOMEM); | |
2119 | ||
2120 | INIT_LIST_HEAD(&vma->vma_link); | |
2121 | INIT_LIST_HEAD(&vma->mm_list); | |
2122 | INIT_LIST_HEAD(&vma->exec_list); | |
2123 | vma->vm = vm; | |
2124 | vma->obj = obj; | |
2125 | ||
2126 | switch (INTEL_INFO(vm->dev)->gen) { | |
2127 | case 8: | |
2128 | case 7: | |
2129 | case 6: | |
7e0d96bc BW |
2130 | if (i915_is_ggtt(vm)) { |
2131 | vma->unbind_vma = ggtt_unbind_vma; | |
2132 | vma->bind_vma = ggtt_bind_vma; | |
2133 | } else { | |
2134 | vma->unbind_vma = ppgtt_unbind_vma; | |
2135 | vma->bind_vma = ppgtt_bind_vma; | |
2136 | } | |
6f65e29a BW |
2137 | break; |
2138 | case 5: | |
2139 | case 4: | |
2140 | case 3: | |
2141 | case 2: | |
2142 | BUG_ON(!i915_is_ggtt(vm)); | |
2143 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2144 | vma->bind_vma = i915_ggtt_bind_vma; | |
2145 | break; | |
2146 | default: | |
2147 | BUG(); | |
2148 | } | |
2149 | ||
2150 | /* Keep GGTT vmas first to make debug easier */ | |
2151 | if (i915_is_ggtt(vm)) | |
2152 | list_add(&vma->vma_link, &obj->vma_list); | |
2153 | else | |
2154 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2155 | ||
2156 | return vma; | |
2157 | } | |
2158 | ||
2159 | struct i915_vma * | |
2160 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2161 | struct i915_address_space *vm) | |
2162 | { | |
2163 | struct i915_vma *vma; | |
2164 | ||
2165 | vma = i915_gem_obj_to_vma(obj, vm); | |
2166 | if (!vma) | |
2167 | vma = __i915_gem_vma_create(obj, vm); | |
2168 | ||
ee960be7 | 2169 | i915_ppgtt_get(vm_to_ppgtt(vm)); |
b9d06dd9 | 2170 | |
6f65e29a BW |
2171 | return vma; |
2172 | } |