[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / i915_gem_object.h

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef __I915_GEM_OBJECT_H__
#define __I915_GEM_OBJECT_H__

#include <linux/reservation.h>

#include <drm/drm_vma_manager.h>
#include <drm/drm_gem.h>
#include <drm/drm_file.h>
#include <drm/drm_device.h>

#include <drm/i915_drm.h>

#include "i915_request.h"
#include "i915_selftest.h"

struct drm_i915_gem_object;

/*
 * struct i915_lut_handle tracks the fast lookups from handle to vma used
 * for execbuf. Although we use a radixtree for that mapping, in order to
 * remove them as the object or context is closed, we need a secondary list
 * and a translation entry (i915_lut_handle).
 */
struct i915_lut_handle {
	struct list_head obj_link;
	struct list_head ctx_link;
	struct i915_gem_context *ctx;
	u32 handle;
};

struct drm_i915_gem_object_ops {
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE	BIT(0)
#define I915_GEM_OBJECT_IS_SHRINKABLE	BIT(1)
#define I915_GEM_OBJECT_IS_PROXY	BIT(2)
#define I915_GEM_OBJECT_ASYNC_CANCEL	BIT(3)

	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);

	int (*pwrite)(struct drm_i915_gem_object *,
		      const struct drm_i915_gem_pwrite *);

	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
};

struct drm_i915_gem_object {
	struct drm_gem_object base;

	const struct drm_i915_gem_object_ops *ops;

	struct {
		/**
		 * @vma.lock: protect the list/tree of vmas
		 */
		spinlock_t lock;

		/**
		 * @vma.list: List of VMAs backed by this object
		 *
		 * The VMA on this list are ordered by type, all GGTT vma are
		 * placed at the head and all ppGTT vma are placed at the tail.
		 * The different types of GGTT vma are unordered between
		 * themselves, use the @vma.tree (which has a defined order
		 * between all VMA) to quickly find an exact match.
		 */
		struct list_head list;

		/**
		 * @vma.tree: Ordered tree of VMAs backed by this object
		 *
		 * All VMA created for this object are placed in the @vma.tree
		 * for fast retrieval via a binary search in
		 * i915_vma_instance(). They are also added to @vma.list for
		 * easy iteration.
		 */
		struct rb_root tree;
	} vma;

	/**
	 * @lut_list: List of vma lookup entries in use for this object.
	 *
	 * If this object is closed, we need to remove all of its VMA from
	 * the fast lookup index in associated contexts; @lut_list provides
	 * this translation from object to context->handles_vma.
	 */
	struct list_head lut_list;

	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
	union {
		struct rcu_head rcu;
		struct llist_node freed;
	};

	/**
	 * Whether the object is currently in the GGTT mmap.
	 */
	unsigned int userfault_count;
	struct list_head userfault_link;

	struct list_head batch_pool_link;
	I915_SELFTEST_DECLARE(struct list_head st_link);

	unsigned long flags;

	/**
	 * Have we taken a reference for the object for incomplete GPU
	 * activity?
	 */
#define I915_BO_ACTIVE_REF 0

	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned int cache_level:3;
	unsigned int cache_coherent:2;
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
	unsigned int cache_dirty:1;

	/**
	 * @read_domains: Read memory domains.
	 *
	 * These monitor which caches contain read/write data related to the
	 * object. When transitioning from one set of domains to another,
	 * the driver is called to ensure that caches are suitably flushed and
	 * invalidated.
	 */
	u16 read_domains;

	/**
	 * @write_domain: Corresponding unique write memory domain.
	 */
	u16 write_domain;

	atomic_t frontbuffer_bits;
	unsigned int frontbuffer_ggtt_origin; /* write once */
	struct i915_active_request frontbuffer_write;

	/** Current tiling stride for the object, if it's tiled. */
	unsigned int tiling_and_stride;
#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
#define STRIDE_MASK (~TILING_MASK)

	/** Count of VMA actually bound by this object */
	unsigned int bind_count;
	unsigned int active_count;
	/** Count of how many global VMA are currently pinned for use by HW */
	unsigned int pin_global;

	struct {
		struct mutex lock; /* protects the pages and their use */
		atomic_t pages_pin_count;

		struct sg_table *pages;
		void *mapping;

		/* TODO: whack some of this into the error state */
		struct i915_page_sizes {
			/**
			 * The sg mask of the pages sg_table. i.e the mask of
			 * of the lengths for each sg entry.
			 */
			unsigned int phys;

			/**
			 * The gtt page sizes we are allowed to use given the
			 * sg mask and the supported page sizes. This will
			 * express the smallest unit we can use for the whole
			 * object, as well as the larger sizes we may be able
			 * to use opportunistically.
			 */
			unsigned int sg;

			/**
			 * The actual gtt page size usage. Since we can have
			 * multiple vma associated with this object we need to
			 * prevent any trampling of state, hence a copy of this
			 * struct also lives in each vma, therefore the gtt
			 * value here should only be read/write through the vma.
			 */
			unsigned int gtt;
		} page_sizes;

		I915_SELFTEST_DECLARE(unsigned int page_mask);

		struct i915_gem_object_page_iter {
			struct scatterlist *sg_pos;
			unsigned int sg_idx; /* in pages, but 32bit eek! */

			struct radix_tree_root radix;
			struct mutex lock; /* protects this cache */
		} get_page;

		/**
		 * Element within i915->mm.unbound_list or i915->mm.bound_list,
		 * locked by i915->mm.obj_lock.
		 */
		struct list_head link;

		/**
		 * Advice: are the backing pages purgeable?
		 */
		unsigned int madv:2;

		/**
		 * This is set if the object has been written to since the
		 * pages were last acquired.
		 */
		bool dirty:1;

		/**
		 * This is set if the object has been pinned due to unknown
		 * swizzling.
		 */
		bool quirked:1;
	} mm;

	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
	 */
	struct reservation_object *resv;

	/** References from framebuffers, locks out tiling changes. */
	unsigned int framebuffer_references;

	/** Record of address bit 17 of each page at last unbind. */
	unsigned long *bit_17;

	union {
		struct i915_gem_userptr {
			uintptr_t ptr;

			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
			struct work_struct *work;
		} userptr;

		unsigned long scratch;

		void *gvt_info;
	};

	/** for phys allocated objects */
	struct drm_dma_handle *phys_handle;

	struct reservation_object __builtin_resv;
};

static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object *gem)
{
	/* Assert that to_intel_bo(NULL) == NULL */
	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));

	return container_of(gem, struct drm_i915_gem_object, base);
}

/**
 * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
 * @filp: DRM file private date
 * @handle: userspace handle
 *
 * Returns:
 *
 * A pointer to the object named by the handle if such exists on @filp, NULL
 * otherwise. This object is only valid whilst under the RCU read lock, and
 * note carefully the object may be in the process of being destroyed.
 */
static inline struct drm_i915_gem_object *
i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)
{
#ifdef CONFIG_LOCKDEP
	WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map));
#endif
	return idr_find(&file->object_idr, handle);
}

static inline struct drm_i915_gem_object *
i915_gem_object_lookup(struct drm_file *file, u32 handle)
{
	struct drm_i915_gem_object *obj;

	rcu_read_lock();
	obj = i915_gem_object_lookup_rcu(file, handle);
	if (obj && !kref_get_unless_zero(&obj->base.refcount))
		obj = NULL;
	rcu_read_unlock();

	return obj;
}

__deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);

__attribute__((nonnull))
static inline struct drm_i915_gem_object *
i915_gem_object_get(struct drm_i915_gem_object *obj)
{
	drm_gem_object_get(&obj->base);
	return obj;
}

__attribute__((nonnull))
static inline void
i915_gem_object_put(struct drm_i915_gem_object *obj)
{
	__drm_gem_object_put(&obj->base);
}

static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj)
{
	reservation_object_lock(obj->resv, NULL);
}

static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj)
{
	reservation_object_unlock(obj->resv);
}

static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
	obj->base.vma_node.readonly = true;
}

static inline bool
i915_gem_object_is_readonly(const struct drm_i915_gem_object *obj)
{
	return obj->base.vma_node.readonly;
}

static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
}

static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE;
}

static inline bool
i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
}

static inline bool
i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
}

static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
	return obj->active_count;
}

static inline bool
i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj)
{
	return test_bit(I915_BO_ACTIVE_REF, &obj->flags);
}

static inline void
i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	__set_bit(I915_BO_ACTIVE_REF, &obj->flags);
}

static inline void
i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	__clear_bit(I915_BO_ACTIVE_REF, &obj->flags);
}

void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj);

static inline bool
i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
{
	return READ_ONCE(obj->framebuffer_references);
}

static inline unsigned int
i915_gem_object_get_tiling(const struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & TILING_MASK;
}

static inline bool
i915_gem_object_is_tiled(const struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
}

static inline unsigned int
i915_gem_object_get_stride(const struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & STRIDE_MASK;
}

static inline unsigned int
i915_gem_tile_height(unsigned int tiling)
{
	GEM_BUG_ON(!tiling);
	return tiling == I915_TILING_Y ? 32 : 8;
}

static inline unsigned int
i915_gem_object_get_tile_height(const struct drm_i915_gem_object *obj)
{
	return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
}

static inline unsigned int
i915_gem_object_get_tile_row_size(const struct drm_i915_gem_object *obj)
{
	return (i915_gem_object_get_stride(obj) *
		i915_gem_object_get_tile_height(obj));
}

int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
			       unsigned int tiling, unsigned int stride);

static inline struct intel_engine_cs *
i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
{
	struct intel_engine_cs *engine = NULL;
	struct dma_fence *fence;

	rcu_read_lock();
	fence = reservation_object_get_excl_rcu(obj->resv);
	rcu_read_unlock();

	if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence))
		engine = to_request(fence)->engine;
	dma_fence_put(fence);

	return engine;
}

void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
					 unsigned int cache_level);
void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);

#endif
Commit	Line	Data
b42fe9ca JL	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef __I915_GEM_OBJECT_H__
	26	#define __I915_GEM_OBJECT_H__
	27
	28	#include <linux/reservation.h>
	29
	30	#include <drm/drm_vma_manager.h>
	31	#include <drm/drm_gem.h>
2f80d7bd JN	32	#include <drm/drm_file.h>
2f80d7bd JN	33	#include <drm/drm_device.h>
b42fe9ca JL	34
	35	#include <drm/i915_drm.h>
	36
e61e0f51	37	#include "i915_request.h"
8d28ba45 CW	38	#include "i915_selftest.h"
8d28ba45 CW	39
b8f55be6 CW	40	struct drm_i915_gem_object;
b8f55be6 CW	41
d1b48c1e CW	42	/*
	43	* struct i915_lut_handle tracks the fast lookups from handle to vma used
	44	* for execbuf. Although we use a radixtree for that mapping, in order to
	45	* remove them as the object or context is closed, we need a secondary list
	46	* and a translation entry (i915_lut_handle).
	47	*/
	48	struct i915_lut_handle {
	49	struct list_head obj_link;
	50	struct list_head ctx_link;
	51	struct i915_gem_context *ctx;
	52	u32 handle;
	53	};
	54
b42fe9ca JL	55	struct drm_i915_gem_object_ops {
b42fe9ca JL	56	unsigned int flags;
a03f395a TZ	57	#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
	58	#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
	59	#define I915_GEM_OBJECT_IS_PROXY BIT(2)
484d9a84	60	#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
b42fe9ca JL	61
	62	/* Interface between the GEM object and its backing storage.
	63	* get_pages() is called once prior to the use of the associated set
	64	* of pages before to binding them into the GTT, and put_pages() is
	65	* called after we no longer need them. As we expect there to be
	66	* associated cost with migrating pages between the backing storage
	67	* and making them available for the GPU (e.g. clflush), we may hold
	68	* onto the pages after they are no longer referenced by the GPU
	69	* in case they may be used again shortly (for example migrating the
	70	* pages to a different memory domain within the GTT). put_pages()
	71	* will therefore most likely be called when the object itself is
	72	* being released or under memory pressure (where we attempt to
	73	* reap pages for the shrinker).
	74	*/
b91b09ee	75	int (get_pages)(struct drm_i915_gem_object );
b42fe9ca JL	76	void (put_pages)(struct drm_i915_gem_object , struct sg_table *);
b42fe9ca JL	77
7c55e2c5 CW	78	int (pwrite)(struct drm_i915_gem_object ,
	79	const struct drm_i915_gem_pwrite *);
	80
b42fe9ca JL	81	int (dmabuf_export)(struct drm_i915_gem_object );
	82	void (release)(struct drm_i915_gem_object );
	83	};
	84
	85	struct drm_i915_gem_object {
	86	struct drm_gem_object base;
	87
	88	const struct drm_i915_gem_object_ops *ops;
	89
528cbd17 CW	90	struct {
	91	/**
	92	* @vma.lock: protect the list/tree of vmas
	93	*/
	94	spinlock_t lock;
	95
	96	/**
	97	* @vma.list: List of VMAs backed by this object
	98	*
	99	* The VMA on this list are ordered by type, all GGTT vma are
	100	* placed at the head and all ppGTT vma are placed at the tail.
	101	* The different types of GGTT vma are unordered between
	102	* themselves, use the @vma.tree (which has a defined order
	103	* between all VMA) to quickly find an exact match.
	104	*/
	105	struct list_head list;
	106
	107	/**
	108	* @vma.tree: Ordered tree of VMAs backed by this object
	109	*
	110	* All VMA created for this object are placed in the @vma.tree
	111	* for fast retrieval via a binary search in
	112	* i915_vma_instance(). They are also added to @vma.list for
	113	* easy iteration.
	114	*/
	115	struct rb_root tree;
	116	} vma;
d1b48c1e CW	117
	118	/**
	119	* @lut_list: List of vma lookup entries in use for this object.
	120	*
	121	* If this object is closed, we need to remove all of its VMA from
	122	* the fast lookup index in associated contexts; @lut_list provides
	123	* this translation from object to context->handles_vma.
	124	*/
	125	struct list_head lut_list;
b42fe9ca JL	126
	127	/** Stolen memory for this object, instead of being backed by shmem. */
	128	struct drm_mm_node *stolen;
b42fe9ca JL	129	union {
	130	struct rcu_head rcu;
	131	struct llist_node freed;
	132	};
	133
	134	/**
	135	* Whether the object is currently in the GGTT mmap.
	136	*/
a65adaf8	137	unsigned int userfault_count;
b42fe9ca JL	138	struct list_head userfault_link;
b42fe9ca JL	139
b42fe9ca	140	struct list_head batch_pool_link;
8d28ba45	141	I915_SELFTEST_DECLARE(struct list_head st_link);
b42fe9ca JL	142
	143	unsigned long flags;
	144
	145	/**
	146	* Have we taken a reference for the object for incomplete GPU
	147	* activity?
	148	*/
	149	#define I915_BO_ACTIVE_REF 0
	150
	151	/*
	152	* Is the object to be mapped as read-only to the GPU
	153	* Only honoured if hardware has relevant pte bit
	154	*/
b42fe9ca	155	unsigned int cache_level:3;
b8f55be6 CW	156	unsigned int cache_coherent:2;
	157	#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
	158	#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
b42fe9ca JL	159	unsigned int cache_dirty:1;
b42fe9ca JL	160
c0a51fd0 CK	161	/**
	162	* @read_domains: Read memory domains.
	163	*
	164	* These monitor which caches contain read/write data related to the
	165	* object. When transitioning from one set of domains to another,
	166	* the driver is called to ensure that caches are suitably flushed and
	167	* invalidated.
	168	*/
	169	u16 read_domains;
	170
	171	/**
	172	* @write_domain: Corresponding unique write memory domain.
	173	*/
	174	u16 write_domain;
	175
b42fe9ca JL	176	atomic_t frontbuffer_bits;
b42fe9ca JL	177	unsigned int frontbuffer_ggtt_origin; /* write once */
21950ee7	178	struct i915_active_request frontbuffer_write;
b42fe9ca JL	179
	180	/** Current tiling stride for the object, if it's tiled. */
	181	unsigned int tiling_and_stride;
	182	#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
	183	#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
	184	#define STRIDE_MASK (~TILING_MASK)
	185
	186	/** Count of VMA actually bound by this object */
	187	unsigned int bind_count;
	188	unsigned int active_count;
bd3d2252 CW	189	/** Count of how many global VMA are currently pinned for use by HW */
bd3d2252 CW	190	unsigned int pin_global;
b42fe9ca JL	191
	192	struct {
	193	struct mutex lock; /* protects the pages and their use */
	194	atomic_t pages_pin_count;
	195
	196	struct sg_table *pages;
	197	void *mapping;
	198
d9ec12f8	199	/* TODO: whack some of this into the error state */
a5c08166 MA	200	struct i915_page_sizes {
	201	/**
	202	* The sg mask of the pages sg_table. i.e the mask of
	203	* of the lengths for each sg entry.
	204	*/
	205	unsigned int phys;
	206
	207	/**
	208	* The gtt page sizes we are allowed to use given the
	209	* sg mask and the supported page sizes. This will
	210	* express the smallest unit we can use for the whole
	211	* object, as well as the larger sizes we may be able
	212	* to use opportunistically.
	213	*/
	214	unsigned int sg;
d9ec12f8 MA	215
	216	/**
	217	* The actual gtt page size usage. Since we can have
	218	* multiple vma associated with this object we need to
	219	* prevent any trampling of state, hence a copy of this
	220	* struct also lives in each vma, therefore the gtt
	221	* value here should only be read/write through the vma.
	222	*/
	223	unsigned int gtt;
a5c08166 MA	224	} page_sizes;
a5c08166 MA	225
4049866f MA	226	I915_SELFTEST_DECLARE(unsigned int page_mask);
4049866f MA	227
b42fe9ca JL	228	struct i915_gem_object_page_iter {
	229	struct scatterlist *sg_pos;
	230	unsigned int sg_idx; /* in pages, but 32bit eek! */
	231
	232	struct radix_tree_root radix;
	233	struct mutex lock; /* protects this cache */
	234	} get_page;
	235
f2123818 CW	236	/**
	237	* Element within i915->mm.unbound_list or i915->mm.bound_list,
	238	* locked by i915->mm.obj_lock.
	239	*/
	240	struct list_head link;
	241
b42fe9ca JL	242	/**
	243	* Advice: are the backing pages purgeable?
	244	*/
	245	unsigned int madv:2;
	246
	247	/**
	248	* This is set if the object has been written to since the
	249	* pages were last acquired.
	250	*/
	251	bool dirty:1;
	252
	253	/**
	254	* This is set if the object has been pinned due to unknown
	255	* swizzling.
	256	*/
	257	bool quirked:1;
	258	} mm;
	259
	260	/** Breadcrumb of last rendering to the buffer.
	261	* There can only be one writer, but we allow for multiple readers.
	262	* If there is a writer that necessarily implies that all other
	263	* read requests are complete - but we may only be lazily clearing
	264	* the read requests. A read request is naturally the most recent
	265	* request on a ring, so we may have two different write and read
	266	* requests on one ring where the write request is older than the
	267	* read request. This allows for the CPU to read from an active
	268	* buffer by only waiting for the write to complete.
	269	*/
	270	struct reservation_object *resv;
	271
	272	/** References from framebuffers, locks out tiling changes. */
dd689287	273	unsigned int framebuffer_references;
b42fe9ca JL	274
	275	/** Record of address bit 17 of each page at last unbind. */
	276	unsigned long *bit_17;
	277
44653988 CW	278	union {
	279	struct i915_gem_userptr {
	280	uintptr_t ptr;
44653988 CW	281
	282	struct i915_mm_struct *mm;
	283	struct i915_mmu_object *mmu_object;
	284	struct work_struct *work;
	285	} userptr;
	286
	287	unsigned long scratch;
e546e281 TZ	288
e546e281 TZ	289	void *gvt_info;
44653988	290	};
b42fe9ca JL	291
	292	/** for phys allocated objects */
	293	struct drm_dma_handle *phys_handle;
	294
	295	struct reservation_object __builtin_resv;
	296	};
	297
	298	static inline struct drm_i915_gem_object *
	299	to_intel_bo(struct drm_gem_object *gem)
	300	{
	301	/* Assert that to_intel_bo(NULL) == NULL */
	302	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
	303
	304	return container_of(gem, struct drm_i915_gem_object, base);
	305	}
	306
	307	/**
	308	* i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
	309	* @filp: DRM file private date
	310	* @handle: userspace handle
	311	*
	312	* Returns:
	313	*
	314	* A pointer to the object named by the handle if such exists on @filp, NULL
	315	* otherwise. This object is only valid whilst under the RCU read lock, and
	316	* note carefully the object may be in the process of being destroyed.
	317	*/
	318	static inline struct drm_i915_gem_object *
	319	i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)
	320	{
	321	#ifdef CONFIG_LOCKDEP
	322	WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map));
	323	#endif
	324	return idr_find(&file->object_idr, handle);
	325	}
	326
	327	static inline struct drm_i915_gem_object *
	328	i915_gem_object_lookup(struct drm_file *file, u32 handle)
	329	{
	330	struct drm_i915_gem_object *obj;
	331
	332	rcu_read_lock();
	333	obj = i915_gem_object_lookup_rcu(file, handle);
	334	if (obj && !kref_get_unless_zero(&obj->base.refcount))
	335	obj = NULL;
	336	rcu_read_unlock();
	337
	338	return obj;
	339	}
	340
	341	__deprecated
	342	extern struct drm_gem_object *
	343	drm_gem_object_lookup(struct drm_file *file, u32 handle);
	344
	345	__attribute__((nonnull))
	346	static inline struct drm_i915_gem_object *
	347	i915_gem_object_get(struct drm_i915_gem_object *obj)
	348	{
0f67706e	349	drm_gem_object_get(&obj->base);
b42fe9ca JL	350	return obj;
	351	}
	352
b42fe9ca JL	353	__attribute__((nonnull))
	354	static inline void
	355	i915_gem_object_put(struct drm_i915_gem_object *obj)
	356	{
55f95c27	357	__drm_gem_object_put(&obj->base);
b42fe9ca JL	358	}
b42fe9ca JL	359
dd689287 CW	360	static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj)
	361	{
	362	reservation_object_lock(obj->resv, NULL);
	363	}
	364
	365	static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj)
	366	{
	367	reservation_object_unlock(obj->resv);
	368	}
	369
3e977ac6 CW	370	static inline void
	371	i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
	372	{
	373	obj->base.vma_node.readonly = true;
	374	}
	375
	376	static inline bool
	377	i915_gem_object_is_readonly(const struct drm_i915_gem_object *obj)
	378	{
	379	return obj->base.vma_node.readonly;
	380	}
	381
b42fe9ca JL	382	static inline bool
	383	i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
	384	{
	385	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
	386	}
	387
	388	static inline bool
	389	i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
	390	{
	391	return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE;
	392	}
	393
a03f395a TZ	394	static inline bool
	395	i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
	396	{
	397	return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
	398	}
	399
484d9a84 CW	400	static inline bool
	401	i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
	402	{
	403	return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
	404	}
	405
b42fe9ca JL	406	static inline bool
	407	i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
	408	{
	409	return obj->active_count;
	410	}
	411
	412	static inline bool
	413	i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj)
	414	{
	415	return test_bit(I915_BO_ACTIVE_REF, &obj->flags);
	416	}
	417
	418	static inline void
	419	i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj)
	420	{
	421	lockdep_assert_held(&obj->base.dev->struct_mutex);
	422	__set_bit(I915_BO_ACTIVE_REF, &obj->flags);
	423	}
	424
	425	static inline void
	426	i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj)
	427	{
	428	lockdep_assert_held(&obj->base.dev->struct_mutex);
	429	__clear_bit(I915_BO_ACTIVE_REF, &obj->flags);
	430	}
	431
	432	void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj);
	433
dd689287 CW	434	static inline bool
	435	i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
	436	{
	437	return READ_ONCE(obj->framebuffer_references);
	438	}
	439
b42fe9ca	440	static inline unsigned int
d899aceb	441	i915_gem_object_get_tiling(const struct drm_i915_gem_object *obj)
b42fe9ca JL	442	{
	443	return obj->tiling_and_stride & TILING_MASK;
	444	}
	445
	446	static inline bool
d899aceb	447	i915_gem_object_is_tiled(const struct drm_i915_gem_object *obj)
b42fe9ca JL	448	{
	449	return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
	450	}
	451
	452	static inline unsigned int
d899aceb	453	i915_gem_object_get_stride(const struct drm_i915_gem_object *obj)
b42fe9ca JL	454	{
	455	return obj->tiling_and_stride & STRIDE_MASK;
	456	}
	457
6649a0b6 CW	458	static inline unsigned int
	459	i915_gem_tile_height(unsigned int tiling)
	460	{
	461	GEM_BUG_ON(!tiling);
	462	return tiling == I915_TILING_Y ? 32 : 8;
	463	}
	464
	465	static inline unsigned int
d899aceb	466	i915_gem_object_get_tile_height(const struct drm_i915_gem_object *obj)
6649a0b6 CW	467	{
	468	return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
	469	}
	470
	471	static inline unsigned int
d899aceb	472	i915_gem_object_get_tile_row_size(const struct drm_i915_gem_object *obj)
6649a0b6 CW	473	{
	474	return (i915_gem_object_get_stride(obj) *
	475	i915_gem_object_get_tile_height(obj));
	476	}
	477
957870f9 CW	478	int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
	479	unsigned int tiling, unsigned int stride);
	480
b42fe9ca JL	481	static inline struct intel_engine_cs *
	482	i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
	483	{
	484	struct intel_engine_cs *engine = NULL;
	485	struct dma_fence *fence;
	486
	487	rcu_read_lock();
	488	fence = reservation_object_get_excl_rcu(obj->resv);
	489	rcu_read_unlock();
	490
	491	if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence))
	492	engine = to_request(fence)->engine;
	493	dma_fence_put(fence);
	494
	495	return engine;
	496	}
	497
b8f55be6 CW	498	void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
b8f55be6 CW	499	unsigned int cache_level);
5a97bcc6 CW	500	void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
5a97bcc6 CW	501
b42fe9ca JL	502	#endif
b42fe9ca JL	503