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84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
0e39037b CW |
30 | #include <linux/ascii85.h> |
31 | #include <linux/nmi.h> | |
3bdd4f84 | 32 | #include <linux/pagevec.h> |
0e39037b | 33 | #include <linux/scatterlist.h> |
0e39037b | 34 | #include <linux/utsname.h> |
0a97015d | 35 | #include <linux/zlib.h> |
0e39037b | 36 | |
7d41ef34 MW |
37 | #include <drm/drm_print.h> |
38 | ||
df0566a6 | 39 | #include "display/intel_atomic.h" |
06d3ff6e | 40 | #include "display/intel_csr.h" |
df0566a6 JN |
41 | #include "display/intel_overlay.h" |
42 | ||
10be98a7 | 43 | #include "gem/i915_gem_context.h" |
895d8ebe | 44 | #include "gem/i915_gem_lmem.h" |
742379c0 | 45 | #include "gt/intel_gt_pm.h" |
10be98a7 | 46 | |
84734a04 | 47 | #include "i915_drv.h" |
05ca9306 | 48 | #include "i915_gpu_error.h" |
9c9082b9 | 49 | #include "i915_memcpy.h" |
37d63f8f | 50 | #include "i915_scatterlist.h" |
84734a04 | 51 | |
3bdd4f84 CW |
52 | #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) |
53 | #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) | |
54 | ||
0e39037b CW |
55 | static void __sg_set_buf(struct scatterlist *sg, |
56 | void *addr, unsigned int len, loff_t it) | |
84734a04 | 57 | { |
0e39037b CW |
58 | sg->page_link = (unsigned long)virt_to_page(addr); |
59 | sg->offset = offset_in_page(addr); | |
60 | sg->length = len; | |
61 | sg->dma_address = it; | |
84734a04 MK |
62 | } |
63 | ||
0e39037b | 64 | static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) |
84734a04 | 65 | { |
0e39037b | 66 | if (!len) |
84734a04 | 67 | return false; |
84734a04 | 68 | |
0e39037b CW |
69 | if (e->bytes + len + 1 <= e->size) |
70 | return true; | |
71 | ||
72 | if (e->bytes) { | |
73 | __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); | |
74 | e->iter += e->bytes; | |
75 | e->buf = NULL; | |
76 | e->bytes = 0; | |
84734a04 MK |
77 | } |
78 | ||
0e39037b CW |
79 | if (e->cur == e->end) { |
80 | struct scatterlist *sgl; | |
84734a04 | 81 | |
3bdd4f84 | 82 | sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); |
0e39037b CW |
83 | if (!sgl) { |
84 | e->err = -ENOMEM; | |
85 | return false; | |
86 | } | |
84734a04 | 87 | |
0e39037b CW |
88 | if (e->cur) { |
89 | e->cur->offset = 0; | |
90 | e->cur->length = 0; | |
91 | e->cur->page_link = | |
92 | (unsigned long)sgl | SG_CHAIN; | |
93 | } else { | |
94 | e->sgl = sgl; | |
84734a04 MK |
95 | } |
96 | ||
0e39037b CW |
97 | e->cur = sgl; |
98 | e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; | |
84734a04 MK |
99 | } |
100 | ||
0e39037b | 101 | e->size = ALIGN(len + 1, SZ_64K); |
3bdd4f84 | 102 | e->buf = kmalloc(e->size, ALLOW_FAIL); |
0e39037b CW |
103 | if (!e->buf) { |
104 | e->size = PAGE_ALIGN(len + 1); | |
105 | e->buf = kmalloc(e->size, GFP_KERNEL); | |
106 | } | |
107 | if (!e->buf) { | |
108 | e->err = -ENOMEM; | |
109 | return false; | |
110 | } | |
111 | ||
112 | return true; | |
84734a04 MK |
113 | } |
114 | ||
dda35931 | 115 | __printf(2, 0) |
84734a04 | 116 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, |
0e39037b | 117 | const char *fmt, va_list args) |
84734a04 | 118 | { |
0e39037b CW |
119 | va_list ap; |
120 | int len; | |
84734a04 | 121 | |
0e39037b | 122 | if (e->err) |
84734a04 MK |
123 | return; |
124 | ||
0e39037b CW |
125 | va_copy(ap, args); |
126 | len = vsnprintf(NULL, 0, fmt, ap); | |
127 | va_end(ap); | |
128 | if (len <= 0) { | |
129 | e->err = len; | |
130 | return; | |
84734a04 MK |
131 | } |
132 | ||
0e39037b CW |
133 | if (!__i915_error_grow(e, len)) |
134 | return; | |
84734a04 | 135 | |
0e39037b CW |
136 | GEM_BUG_ON(e->bytes >= e->size); |
137 | len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); | |
138 | if (len < 0) { | |
139 | e->err = len; | |
140 | return; | |
141 | } | |
142 | e->bytes += len; | |
84734a04 MK |
143 | } |
144 | ||
0e39037b | 145 | static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) |
84734a04 MK |
146 | { |
147 | unsigned len; | |
148 | ||
0e39037b | 149 | if (e->err || !str) |
84734a04 MK |
150 | return; |
151 | ||
152 | len = strlen(str); | |
0e39037b CW |
153 | if (!__i915_error_grow(e, len)) |
154 | return; | |
84734a04 | 155 | |
0e39037b | 156 | GEM_BUG_ON(e->bytes + len > e->size); |
84734a04 | 157 | memcpy(e->buf + e->bytes, str, len); |
0e39037b | 158 | e->bytes += len; |
84734a04 MK |
159 | } |
160 | ||
161 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
162 | #define err_puts(e, s) i915_error_puts(e, s) | |
163 | ||
7d41ef34 MW |
164 | static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) |
165 | { | |
166 | i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); | |
167 | } | |
168 | ||
169 | static inline struct drm_printer | |
170 | i915_error_printer(struct drm_i915_error_state_buf *e) | |
171 | { | |
172 | struct drm_printer p = { | |
173 | .printfn = __i915_printfn_error, | |
174 | .arg = e, | |
175 | }; | |
176 | return p; | |
177 | } | |
178 | ||
3bdd4f84 CW |
179 | /* single threaded page allocator with a reserved stash for emergencies */ |
180 | static void pool_fini(struct pagevec *pv) | |
181 | { | |
182 | pagevec_release(pv); | |
183 | } | |
184 | ||
185 | static int pool_refill(struct pagevec *pv, gfp_t gfp) | |
186 | { | |
187 | while (pagevec_space(pv)) { | |
188 | struct page *p; | |
189 | ||
190 | p = alloc_page(gfp); | |
191 | if (!p) | |
192 | return -ENOMEM; | |
193 | ||
194 | pagevec_add(pv, p); | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static int pool_init(struct pagevec *pv, gfp_t gfp) | |
201 | { | |
202 | int err; | |
203 | ||
204 | pagevec_init(pv); | |
205 | ||
206 | err = pool_refill(pv, gfp); | |
207 | if (err) | |
208 | pool_fini(pv); | |
209 | ||
210 | return err; | |
211 | } | |
212 | ||
213 | static void *pool_alloc(struct pagevec *pv, gfp_t gfp) | |
214 | { | |
215 | struct page *p; | |
216 | ||
217 | p = alloc_page(gfp); | |
218 | if (!p && pagevec_count(pv)) | |
219 | p = pv->pages[--pv->nr]; | |
220 | ||
221 | return p ? page_address(p) : NULL; | |
222 | } | |
223 | ||
224 | static void pool_free(struct pagevec *pv, void *addr) | |
225 | { | |
226 | struct page *p = virt_to_page(addr); | |
227 | ||
228 | if (pagevec_space(pv)) | |
229 | pagevec_add(pv, p); | |
230 | else | |
231 | __free_page(p); | |
232 | } | |
233 | ||
0a97015d CW |
234 | #ifdef CONFIG_DRM_I915_COMPRESS_ERROR |
235 | ||
742379c0 | 236 | struct i915_vma_compress { |
3bdd4f84 | 237 | struct pagevec pool; |
d637c178 CW |
238 | struct z_stream_s zstream; |
239 | void *tmp; | |
240 | }; | |
241 | ||
742379c0 | 242 | static bool compress_init(struct i915_vma_compress *c) |
0a97015d | 243 | { |
3bdd4f84 | 244 | struct z_stream_s *zstream = &c->zstream; |
0a97015d | 245 | |
3bdd4f84 | 246 | if (pool_init(&c->pool, ALLOW_FAIL)) |
0a97015d CW |
247 | return false; |
248 | ||
3bdd4f84 CW |
249 | zstream->workspace = |
250 | kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), | |
251 | ALLOW_FAIL); | |
252 | if (!zstream->workspace) { | |
253 | pool_fini(&c->pool); | |
0a97015d CW |
254 | return false; |
255 | } | |
256 | ||
d637c178 | 257 | c->tmp = NULL; |
c4d3ae68 | 258 | if (i915_has_memcpy_from_wc()) |
3bdd4f84 | 259 | c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); |
d637c178 | 260 | |
0a97015d CW |
261 | return true; |
262 | } | |
263 | ||
742379c0 | 264 | static bool compress_start(struct i915_vma_compress *c) |
83bc0f5b | 265 | { |
3bdd4f84 CW |
266 | struct z_stream_s *zstream = &c->zstream; |
267 | void *workspace = zstream->workspace; | |
268 | ||
269 | memset(zstream, 0, sizeof(*zstream)); | |
270 | zstream->workspace = workspace; | |
271 | ||
272 | return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; | |
273 | } | |
274 | ||
742379c0 CW |
275 | static void *compress_next_page(struct i915_vma_compress *c, |
276 | struct i915_vma_coredump *dst) | |
3bdd4f84 CW |
277 | { |
278 | void *page; | |
83bc0f5b CW |
279 | |
280 | if (dst->page_count >= dst->num_pages) | |
281 | return ERR_PTR(-ENOSPC); | |
282 | ||
79c7a28e | 283 | page = pool_alloc(&c->pool, ALLOW_FAIL); |
83bc0f5b CW |
284 | if (!page) |
285 | return ERR_PTR(-ENOMEM); | |
286 | ||
3bdd4f84 | 287 | return dst->pages[dst->page_count++] = page; |
83bc0f5b CW |
288 | } |
289 | ||
742379c0 | 290 | static int compress_page(struct i915_vma_compress *c, |
0a97015d | 291 | void *src, |
742379c0 CW |
292 | struct i915_vma_coredump *dst, |
293 | bool wc) | |
0a97015d | 294 | { |
d637c178 CW |
295 | struct z_stream_s *zstream = &c->zstream; |
296 | ||
0a97015d | 297 | zstream->next_in = src; |
742379c0 | 298 | if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) |
d637c178 | 299 | zstream->next_in = c->tmp; |
0a97015d CW |
300 | zstream->avail_in = PAGE_SIZE; |
301 | ||
302 | do { | |
303 | if (zstream->avail_out == 0) { | |
3bdd4f84 | 304 | zstream->next_out = compress_next_page(c, dst); |
83bc0f5b CW |
305 | if (IS_ERR(zstream->next_out)) |
306 | return PTR_ERR(zstream->next_out); | |
0a97015d | 307 | |
0a97015d CW |
308 | zstream->avail_out = PAGE_SIZE; |
309 | } | |
310 | ||
83bc0f5b | 311 | if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) |
0a97015d CW |
312 | return -EIO; |
313 | } while (zstream->avail_in); | |
314 | ||
315 | /* Fallback to uncompressed if we increase size? */ | |
316 | if (0 && zstream->total_out > zstream->total_in) | |
317 | return -E2BIG; | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
742379c0 CW |
322 | static int compress_flush(struct i915_vma_compress *c, |
323 | struct i915_vma_coredump *dst) | |
0a97015d | 324 | { |
d637c178 CW |
325 | struct z_stream_s *zstream = &c->zstream; |
326 | ||
83bc0f5b CW |
327 | do { |
328 | switch (zlib_deflate(zstream, Z_FINISH)) { | |
329 | case Z_OK: /* more space requested */ | |
3bdd4f84 | 330 | zstream->next_out = compress_next_page(c, dst); |
83bc0f5b CW |
331 | if (IS_ERR(zstream->next_out)) |
332 | return PTR_ERR(zstream->next_out); | |
333 | ||
334 | zstream->avail_out = PAGE_SIZE; | |
335 | break; | |
336 | ||
337 | case Z_STREAM_END: | |
338 | goto end; | |
339 | ||
340 | default: /* any error */ | |
341 | return -EIO; | |
342 | } | |
343 | } while (1); | |
344 | ||
345 | end: | |
346 | memset(zstream->next_out, 0, zstream->avail_out); | |
347 | dst->unused = zstream->avail_out; | |
348 | return 0; | |
349 | } | |
350 | ||
742379c0 | 351 | static void compress_finish(struct i915_vma_compress *c) |
83bc0f5b | 352 | { |
3bdd4f84 CW |
353 | zlib_deflateEnd(&c->zstream); |
354 | } | |
0a97015d | 355 | |
742379c0 | 356 | static void compress_fini(struct i915_vma_compress *c) |
3bdd4f84 CW |
357 | { |
358 | kfree(c->zstream.workspace); | |
d637c178 | 359 | if (c->tmp) |
3bdd4f84 CW |
360 | pool_free(&c->pool, c->tmp); |
361 | pool_fini(&c->pool); | |
0a97015d CW |
362 | } |
363 | ||
364 | static void err_compression_marker(struct drm_i915_error_state_buf *m) | |
365 | { | |
366 | err_puts(m, ":"); | |
367 | } | |
368 | ||
369 | #else | |
370 | ||
742379c0 | 371 | struct i915_vma_compress { |
3bdd4f84 | 372 | struct pagevec pool; |
d637c178 CW |
373 | }; |
374 | ||
742379c0 | 375 | static bool compress_init(struct i915_vma_compress *c) |
3bdd4f84 CW |
376 | { |
377 | return pool_init(&c->pool, ALLOW_FAIL) == 0; | |
378 | } | |
379 | ||
742379c0 | 380 | static bool compress_start(struct i915_vma_compress *c) |
0a97015d CW |
381 | { |
382 | return true; | |
383 | } | |
384 | ||
742379c0 | 385 | static int compress_page(struct i915_vma_compress *c, |
0a97015d | 386 | void *src, |
742379c0 CW |
387 | struct i915_vma_coredump *dst, |
388 | bool wc) | |
0a97015d | 389 | { |
d637c178 | 390 | void *ptr; |
0a97015d | 391 | |
79c7a28e | 392 | ptr = pool_alloc(&c->pool, ALLOW_FAIL); |
3bdd4f84 | 393 | if (!ptr) |
0a97015d CW |
394 | return -ENOMEM; |
395 | ||
742379c0 | 396 | if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) |
d637c178 CW |
397 | memcpy(ptr, src, PAGE_SIZE); |
398 | dst->pages[dst->page_count++] = ptr; | |
0a97015d CW |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
742379c0 CW |
403 | static int compress_flush(struct i915_vma_compress *c, |
404 | struct i915_vma_coredump *dst) | |
83bc0f5b CW |
405 | { |
406 | return 0; | |
407 | } | |
408 | ||
742379c0 | 409 | static void compress_finish(struct i915_vma_compress *c) |
0a97015d CW |
410 | { |
411 | } | |
412 | ||
742379c0 | 413 | static void compress_fini(struct i915_vma_compress *c) |
3bdd4f84 CW |
414 | { |
415 | pool_fini(&c->pool); | |
416 | } | |
417 | ||
0a97015d CW |
418 | static void err_compression_marker(struct drm_i915_error_state_buf *m) |
419 | { | |
420 | err_puts(m, "~"); | |
421 | } | |
422 | ||
423 | #endif | |
424 | ||
d636951e | 425 | static void error_print_instdone(struct drm_i915_error_state_buf *m, |
742379c0 | 426 | const struct intel_engine_coredump *ee) |
d636951e | 427 | { |
eaef5b3c | 428 | const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; |
f9e61372 BW |
429 | int slice; |
430 | int subslice; | |
431 | ||
d636951e BW |
432 | err_printf(m, " INSTDONE: 0x%08x\n", |
433 | ee->instdone.instdone); | |
434 | ||
c990b4c3 | 435 | if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) |
d636951e BW |
436 | return; |
437 | ||
438 | err_printf(m, " SC_INSTDONE: 0x%08x\n", | |
439 | ee->instdone.slice_common); | |
440 | ||
441 | if (INTEL_GEN(m->i915) <= 6) | |
442 | return; | |
443 | ||
eaef5b3c | 444 | for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) |
f9e61372 BW |
445 | err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", |
446 | slice, subslice, | |
447 | ee->instdone.sampler[slice][subslice]); | |
448 | ||
eaef5b3c | 449 | for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) |
f9e61372 BW |
450 | err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", |
451 | slice, subslice, | |
452 | ee->instdone.row[slice][subslice]); | |
f7043102 LL |
453 | |
454 | if (INTEL_GEN(m->i915) < 12) | |
455 | return; | |
456 | ||
457 | err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", | |
458 | ee->instdone.slice_common_extra[0]); | |
459 | err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", | |
460 | ee->instdone.slice_common_extra[1]); | |
d636951e BW |
461 | } |
462 | ||
35ca039e CW |
463 | static void error_print_request(struct drm_i915_error_state_buf *m, |
464 | const char *prefix, | |
742379c0 | 465 | const struct i915_request_coredump *erq) |
35ca039e CW |
466 | { |
467 | if (!erq->seqno) | |
468 | return; | |
469 | ||
742379c0 | 470 | err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n", |
7f4127c4 | 471 | prefix, erq->pid, erq->context, erq->seqno, |
52c0fdb2 CW |
472 | test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
473 | &erq->flags) ? "!" : "", | |
474 | test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, | |
475 | &erq->flags) ? "+" : "", | |
476 | erq->sched_attr.priority, | |
3a068721 | 477 | erq->start, erq->head, erq->tail); |
35ca039e CW |
478 | } |
479 | ||
4fa6053e CW |
480 | static void error_print_context(struct drm_i915_error_state_buf *m, |
481 | const char *header, | |
742379c0 | 482 | const struct i915_gem_context_coredump *ctx) |
4fa6053e | 483 | { |
1883a0a4 TU |
484 | const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; |
485 | ||
486 | err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", | |
2935ed53 | 487 | header, ctx->comm, ctx->pid, ctx->sched_attr.priority, |
1883a0a4 TU |
488 | ctx->guilty, ctx->active, |
489 | ctx->total_runtime * period, | |
490 | mul_u32_u32(ctx->avg_runtime, period)); | |
4fa6053e CW |
491 | } |
492 | ||
742379c0 CW |
493 | static struct i915_vma_coredump * |
494 | __find_vma(struct i915_vma_coredump *vma, const char *name) | |
495 | { | |
496 | while (vma) { | |
497 | if (strcmp(vma->name, name) == 0) | |
498 | return vma; | |
499 | vma = vma->next; | |
500 | } | |
501 | ||
502 | return NULL; | |
503 | } | |
504 | ||
505 | static struct i915_vma_coredump * | |
506 | find_batch(const struct intel_engine_coredump *ee) | |
507 | { | |
508 | return __find_vma(ee->vma, "batch"); | |
509 | } | |
510 | ||
6361f4ba | 511 | static void error_print_engine(struct drm_i915_error_state_buf *m, |
742379c0 | 512 | const struct intel_engine_coredump *ee) |
84734a04 | 513 | { |
742379c0 | 514 | struct i915_vma_coredump *batch; |
76e70087 MK |
515 | int n; |
516 | ||
c990b4c3 | 517 | err_printf(m, "%s command stream:\n", ee->engine->name); |
742379c0 | 518 | err_printf(m, " CCID: 0x%08x\n", ee->ccid); |
6361f4ba | 519 | err_printf(m, " START: 0x%08x\n", ee->start); |
06392e3b | 520 | err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); |
cdb324bd CW |
521 | err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", |
522 | ee->tail, ee->rq_post, ee->rq_tail); | |
6361f4ba | 523 | err_printf(m, " CTL: 0x%08x\n", ee->ctl); |
21a2c58a | 524 | err_printf(m, " MODE: 0x%08x\n", ee->mode); |
6361f4ba CW |
525 | err_printf(m, " HWS: 0x%08x\n", ee->hws); |
526 | err_printf(m, " ACTHD: 0x%08x %08x\n", | |
527 | (u32)(ee->acthd>>32), (u32)ee->acthd); | |
528 | err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); | |
529 | err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); | |
70a76a9b | 530 | err_printf(m, " ESR: 0x%08x\n", ee->esr); |
d636951e BW |
531 | |
532 | error_print_instdone(m, ee); | |
533 | ||
742379c0 CW |
534 | batch = find_batch(ee); |
535 | if (batch) { | |
536 | u64 start = batch->gtt_offset; | |
537 | u64 end = start + batch->gtt_size; | |
03382dfb CW |
538 | |
539 | err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", | |
540 | upper_32_bits(start), lower_32_bits(start), | |
541 | upper_32_bits(end), lower_32_bits(end)); | |
542 | } | |
6361f4ba | 543 | if (INTEL_GEN(m->i915) >= 4) { |
03382dfb | 544 | err_printf(m, " BBADDR: 0x%08x_%08x\n", |
6361f4ba CW |
545 | (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); |
546 | err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); | |
547 | err_printf(m, " INSTPS: 0x%08x\n", ee->instps); | |
3dda20a9 | 548 | } |
6361f4ba CW |
549 | err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); |
550 | err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), | |
551 | lower_32_bits(ee->faddr)); | |
552 | if (INTEL_GEN(m->i915) >= 6) { | |
553 | err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); | |
554 | err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); | |
84734a04 | 555 | } |
4bdafb9d | 556 | if (HAS_PPGTT(m->i915)) { |
6361f4ba | 557 | err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); |
6c7a01ec | 558 | |
6361f4ba | 559 | if (INTEL_GEN(m->i915) >= 8) { |
6c7a01ec BW |
560 | int i; |
561 | for (i = 0; i < 4; i++) | |
562 | err_printf(m, " PDP%d: 0x%016llx\n", | |
6361f4ba | 563 | i, ee->vm_info.pdp[i]); |
6c7a01ec BW |
564 | } else { |
565 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
6361f4ba | 566 | ee->vm_info.pp_dir_base); |
6c7a01ec BW |
567 | } |
568 | } | |
702c8f8e | 569 | err_printf(m, " engine reset count: %u\n", ee->reset_count); |
3fe3b030 | 570 | |
76e70087 MK |
571 | for (n = 0; n < ee->num_ports; n++) { |
572 | err_printf(m, " ELSP[%d]:", n); | |
742379c0 | 573 | error_print_request(m, " ", &ee->execlist[n]); |
76e70087 MK |
574 | } |
575 | ||
4fa6053e | 576 | error_print_context(m, " Active context: ", &ee->context); |
84734a04 MK |
577 | } |
578 | ||
579 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
580 | { | |
581 | va_list args; | |
582 | ||
583 | va_start(args, f); | |
584 | i915_error_vprintf(e, f, args); | |
585 | va_end(args); | |
586 | } | |
587 | ||
742379c0 | 588 | static void print_error_vma(struct drm_i915_error_state_buf *m, |
c990b4c3 | 589 | const struct intel_engine_cs *engine, |
742379c0 | 590 | const struct i915_vma_coredump *vma) |
ab0e7ff9 | 591 | { |
489cae63 | 592 | char out[ASCII85_BUFSZ]; |
0a97015d | 593 | int page; |
ab0e7ff9 | 594 | |
742379c0 | 595 | if (!vma) |
fc4c79c3 CW |
596 | return; |
597 | ||
742379c0 CW |
598 | err_printf(m, "%s --- %s = 0x%08x %08x\n", |
599 | engine ? engine->name : "global", vma->name, | |
600 | upper_32_bits(vma->gtt_offset), | |
601 | lower_32_bits(vma->gtt_offset)); | |
fc4c79c3 | 602 | |
742379c0 CW |
603 | if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) |
604 | err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); | |
fd521d3b | 605 | |
0a97015d | 606 | err_compression_marker(m); |
742379c0 | 607 | for (page = 0; page < vma->page_count; page++) { |
0a97015d CW |
608 | int i, len; |
609 | ||
610 | len = PAGE_SIZE; | |
742379c0 CW |
611 | if (page == vma->page_count - 1) |
612 | len -= vma->unused; | |
0a97015d CW |
613 | len = ascii85_encode_len(len); |
614 | ||
489cae63 | 615 | for (i = 0; i < len; i++) |
742379c0 | 616 | err_puts(m, ascii85_encode(vma->pages[page][i], out)); |
ab0e7ff9 | 617 | } |
0a97015d | 618 | err_puts(m, "\n"); |
ab0e7ff9 CW |
619 | } |
620 | ||
2bd160a1 | 621 | static void err_print_capabilities(struct drm_i915_error_state_buf *m, |
3fed1808 | 622 | const struct intel_device_info *info, |
0258404f | 623 | const struct intel_runtime_info *runtime, |
3fed1808 | 624 | const struct intel_driver_caps *caps) |
2bd160a1 | 625 | { |
a8c9b849 MW |
626 | struct drm_printer p = i915_error_printer(m); |
627 | ||
72404978 CW |
628 | intel_device_info_print_static(info, &p); |
629 | intel_device_info_print_runtime(runtime, &p); | |
630 | intel_device_info_print_topology(&runtime->sseu, &p); | |
3fed1808 | 631 | intel_driver_caps_print(caps, &p); |
2bd160a1 CW |
632 | } |
633 | ||
642c8a72 | 634 | static void err_print_params(struct drm_i915_error_state_buf *m, |
acfb9973 | 635 | const struct i915_params *params) |
642c8a72 | 636 | { |
acfb9973 MW |
637 | struct drm_printer p = i915_error_printer(m); |
638 | ||
639 | i915_params_dump(params, &p); | |
642c8a72 CW |
640 | } |
641 | ||
5a4c6f1b CW |
642 | static void err_print_pciid(struct drm_i915_error_state_buf *m, |
643 | struct drm_i915_private *i915) | |
644 | { | |
645 | struct pci_dev *pdev = i915->drm.pdev; | |
646 | ||
647 | err_printf(m, "PCI ID: 0x%04x\n", pdev->device); | |
648 | err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); | |
649 | err_printf(m, "PCI Subsystem: %04x:%04x\n", | |
650 | pdev->subsystem_vendor, | |
651 | pdev->subsystem_device); | |
652 | } | |
653 | ||
7d41ef34 | 654 | static void err_print_uc(struct drm_i915_error_state_buf *m, |
742379c0 | 655 | const struct intel_uc_coredump *error_uc) |
7d41ef34 MW |
656 | { |
657 | struct drm_printer p = i915_error_printer(m); | |
7d41ef34 MW |
658 | |
659 | intel_uc_fw_dump(&error_uc->guc_fw, &p); | |
660 | intel_uc_fw_dump(&error_uc->huc_fw, &p); | |
742379c0 | 661 | print_error_vma(m, NULL, error_uc->guc_log); |
7d41ef34 MW |
662 | } |
663 | ||
0e39037b | 664 | static void err_free_sgl(struct scatterlist *sgl) |
84734a04 | 665 | { |
0e39037b CW |
666 | while (sgl) { |
667 | struct scatterlist *sg; | |
84734a04 | 668 | |
0e39037b CW |
669 | for (sg = sgl; !sg_is_chain(sg); sg++) { |
670 | kfree(sg_virt(sg)); | |
671 | if (sg_is_last(sg)) | |
672 | break; | |
673 | } | |
674 | ||
675 | sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); | |
676 | free_page((unsigned long)sgl); | |
677 | sgl = sg; | |
84734a04 | 678 | } |
0e39037b | 679 | } |
84734a04 | 680 | |
742379c0 CW |
681 | static void err_print_gt(struct drm_i915_error_state_buf *m, |
682 | struct intel_gt_coredump *gt) | |
683 | { | |
684 | const struct intel_engine_coredump *ee; | |
1a8585bd | 685 | int i; |
742379c0 CW |
686 | |
687 | err_printf(m, "GT awake: %s\n", yesno(gt->awake)); | |
688 | err_printf(m, "EIR: 0x%08x\n", gt->eir); | |
689 | err_printf(m, "IER: 0x%08x\n", gt->ier); | |
690 | for (i = 0; i < gt->ngtier; i++) | |
691 | err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); | |
692 | err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); | |
693 | err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); | |
694 | err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); | |
695 | ||
696 | for (i = 0; i < gt->nfence; i++) | |
697 | err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); | |
698 | ||
699 | if (IS_GEN_RANGE(m->i915, 6, 11)) { | |
700 | err_printf(m, "ERROR: 0x%08x\n", gt->error); | |
701 | err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); | |
702 | } | |
703 | ||
704 | if (INTEL_GEN(m->i915) >= 8) | |
705 | err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", | |
706 | gt->fault_data1, gt->fault_data0); | |
707 | ||
708 | if (IS_GEN(m->i915, 7)) | |
709 | err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); | |
710 | ||
711 | if (IS_GEN_RANGE(m->i915, 8, 11)) | |
712 | err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); | |
713 | ||
714 | if (IS_GEN(m->i915, 12)) | |
715 | err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); | |
716 | ||
717 | if (INTEL_GEN(m->i915) >= 12) { | |
718 | int i; | |
719 | ||
720 | for (i = 0; i < GEN12_SFC_DONE_MAX; i++) | |
721 | err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, | |
722 | gt->sfc_done[i]); | |
723 | ||
724 | err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); | |
725 | } | |
726 | ||
727 | for (ee = gt->engine; ee; ee = ee->next) { | |
728 | const struct i915_vma_coredump *vma; | |
729 | ||
730 | error_print_engine(m, ee); | |
742379c0 CW |
731 | for (vma = ee->vma; vma; vma = vma->next) |
732 | print_error_vma(m, ee->engine, vma); | |
742379c0 CW |
733 | } |
734 | ||
735 | if (gt->uc) | |
736 | err_print_uc(m, gt->uc); | |
737 | } | |
738 | ||
0e39037b | 739 | static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, |
742379c0 | 740 | struct i915_gpu_coredump *error) |
0e39037b | 741 | { |
742379c0 | 742 | const struct intel_engine_coredump *ee; |
0e39037b | 743 | struct timespec64 ts; |
fb6f0b64 | 744 | |
5a4c6f1b CW |
745 | if (*error->error_msg) |
746 | err_printf(m, "%s\n", error->error_msg); | |
57428bcc CW |
747 | err_printf(m, "Kernel: %s %s\n", |
748 | init_utsname()->release, | |
749 | init_utsname()->machine); | |
d71c4b03 | 750 | err_printf(m, "Driver: %s\n", DRIVER_DATE); |
c6270dbc AB |
751 | ts = ktime_to_timespec64(error->time); |
752 | err_printf(m, "Time: %lld s %ld us\n", | |
753 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
754 | ts = ktime_to_timespec64(error->boottime); | |
755 | err_printf(m, "Boottime: %lld s %ld us\n", | |
756 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
757 | ts = ktime_to_timespec64(error->uptime); | |
758 | err_printf(m, "Uptime: %lld s %ld us\n", | |
759 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
058179e7 CW |
760 | err_printf(m, "Capture: %lu jiffies; %d ms ago\n", |
761 | error->capture, jiffies_to_msecs(jiffies - error->capture)); | |
3fe3b030 | 762 | |
742379c0 | 763 | for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) |
7f4127c4 | 764 | err_printf(m, "Active process (on ring %s): %s [%d]\n", |
c990b4c3 CW |
765 | ee->engine->name, |
766 | ee->context.comm, | |
767 | ee->context.pid); | |
768 | ||
48b031e3 | 769 | err_printf(m, "Reset count: %u\n", error->reset_count); |
62d5d69b | 770 | err_printf(m, "Suspend count: %u\n", error->suspend_count); |
2e0d26f8 | 771 | err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); |
805446c8 TU |
772 | err_printf(m, "Subplatform: 0x%x\n", |
773 | intel_subplatform(&error->runtime_info, | |
774 | error->device_info.platform)); | |
0e39037b | 775 | err_print_pciid(m, m->i915); |
642c8a72 | 776 | |
eb5be9d0 | 777 | err_printf(m, "IOMMU enabled?: %d\n", error->iommu); |
0ac7655c | 778 | |
0e39037b CW |
779 | if (HAS_CSR(m->i915)) { |
780 | struct intel_csr *csr = &m->i915->csr; | |
0ac7655c MK |
781 | |
782 | err_printf(m, "DMC loaded: %s\n", | |
783 | yesno(csr->dmc_payload != NULL)); | |
784 | err_printf(m, "DMC fw version: %d.%d\n", | |
785 | CSR_VERSION_MAJOR(csr->version), | |
786 | CSR_VERSION_MINOR(csr->version)); | |
787 | } | |
788 | ||
e5aac87e CW |
789 | err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); |
790 | err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); | |
84734a04 | 791 | |
742379c0 CW |
792 | if (error->gt) |
793 | err_print_gt(m, error->gt); | |
84734a04 MK |
794 | |
795 | if (error->overlay) | |
796 | intel_overlay_print_error_state(m, error->overlay); | |
797 | ||
798 | if (error->display) | |
5a4c6f1b | 799 | intel_display_print_error_state(m, error->display); |
84734a04 | 800 | |
0258404f JN |
801 | err_print_capabilities(m, &error->device_info, &error->runtime_info, |
802 | &error->driver_caps); | |
642c8a72 | 803 | err_print_params(m, &error->params); |
0e39037b CW |
804 | } |
805 | ||
742379c0 | 806 | static int err_print_to_sgl(struct i915_gpu_coredump *error) |
0e39037b CW |
807 | { |
808 | struct drm_i915_error_state_buf m; | |
809 | ||
810 | if (IS_ERR(error)) | |
811 | return PTR_ERR(error); | |
812 | ||
813 | if (READ_ONCE(error->sgl)) | |
814 | return 0; | |
815 | ||
816 | memset(&m, 0, sizeof(m)); | |
817 | m.i915 = error->i915; | |
818 | ||
819 | __err_print_to_sgl(&m, error); | |
820 | ||
821 | if (m.buf) { | |
822 | __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); | |
823 | m.bytes = 0; | |
824 | m.buf = NULL; | |
825 | } | |
826 | if (m.cur) { | |
827 | GEM_BUG_ON(m.end < m.cur); | |
828 | sg_mark_end(m.cur - 1); | |
829 | } | |
830 | GEM_BUG_ON(m.sgl && !m.cur); | |
831 | ||
832 | if (m.err) { | |
833 | err_free_sgl(m.sgl); | |
834 | return m.err; | |
835 | } | |
642c8a72 | 836 | |
0e39037b CW |
837 | if (cmpxchg(&error->sgl, NULL, m.sgl)) |
838 | err_free_sgl(m.sgl); | |
84734a04 MK |
839 | |
840 | return 0; | |
841 | } | |
842 | ||
742379c0 CW |
843 | ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, |
844 | char *buf, loff_t off, size_t rem) | |
84734a04 | 845 | { |
0e39037b CW |
846 | struct scatterlist *sg; |
847 | size_t count; | |
848 | loff_t pos; | |
849 | int err; | |
84734a04 | 850 | |
0e39037b CW |
851 | if (!error || !rem) |
852 | return 0; | |
84734a04 | 853 | |
0e39037b CW |
854 | err = err_print_to_sgl(error); |
855 | if (err) | |
856 | return err; | |
84734a04 | 857 | |
0e39037b CW |
858 | sg = READ_ONCE(error->fit); |
859 | if (!sg || off < sg->dma_address) | |
860 | sg = error->sgl; | |
861 | if (!sg) | |
862 | return 0; | |
84734a04 | 863 | |
0e39037b CW |
864 | pos = sg->dma_address; |
865 | count = 0; | |
866 | do { | |
867 | size_t len, start; | |
868 | ||
869 | if (sg_is_chain(sg)) { | |
870 | sg = sg_chain_ptr(sg); | |
871 | GEM_BUG_ON(sg_is_chain(sg)); | |
872 | } | |
84734a04 | 873 | |
0e39037b CW |
874 | len = sg->length; |
875 | if (pos + len <= off) { | |
876 | pos += len; | |
877 | continue; | |
878 | } | |
84734a04 | 879 | |
0e39037b CW |
880 | start = sg->offset; |
881 | if (pos < off) { | |
882 | GEM_BUG_ON(off - pos > len); | |
883 | len -= off - pos; | |
884 | start += off - pos; | |
885 | pos = off; | |
886 | } | |
887 | ||
888 | len = min(len, rem); | |
889 | GEM_BUG_ON(!len || len > sg->length); | |
890 | ||
891 | memcpy(buf, page_address(sg_page(sg)) + start, len); | |
892 | ||
893 | count += len; | |
894 | pos += len; | |
895 | ||
896 | buf += len; | |
897 | rem -= len; | |
898 | if (!rem) { | |
899 | WRITE_ONCE(error->fit, sg); | |
900 | break; | |
901 | } | |
902 | } while (!sg_is_last(sg++)); | |
903 | ||
904 | return count; | |
84734a04 MK |
905 | } |
906 | ||
742379c0 | 907 | static void i915_vma_coredump_free(struct i915_vma_coredump *vma) |
84734a04 | 908 | { |
742379c0 CW |
909 | while (vma) { |
910 | struct i915_vma_coredump *next = vma->next; | |
911 | int page; | |
84734a04 | 912 | |
742379c0 CW |
913 | for (page = 0; page < vma->page_count; page++) |
914 | free_page((unsigned long)vma->pages[page]); | |
84734a04 | 915 | |
742379c0 CW |
916 | kfree(vma); |
917 | vma = next; | |
918 | } | |
84734a04 MK |
919 | } |
920 | ||
742379c0 | 921 | static void cleanup_params(struct i915_gpu_coredump *error) |
84a20a8a | 922 | { |
16cabb12 | 923 | i915_params_free(&error->params); |
84a20a8a MW |
924 | } |
925 | ||
742379c0 | 926 | static void cleanup_uc(struct intel_uc_coredump *uc) |
7d41ef34 | 927 | { |
742379c0 CW |
928 | kfree(uc->guc_fw.path); |
929 | kfree(uc->huc_fw.path); | |
930 | i915_vma_coredump_free(uc->guc_log); | |
7d41ef34 | 931 | |
742379c0 | 932 | kfree(uc); |
7d41ef34 MW |
933 | } |
934 | ||
742379c0 | 935 | static void cleanup_gt(struct intel_gt_coredump *gt) |
84734a04 | 936 | { |
742379c0 CW |
937 | while (gt->engine) { |
938 | struct intel_engine_coredump *ee = gt->engine; | |
939 | ||
940 | gt->engine = ee->next; | |
84734a04 | 941 | |
742379c0 | 942 | i915_vma_coredump_free(ee->vma); |
742379c0 CW |
943 | kfree(ee); |
944 | } | |
6361f4ba | 945 | |
742379c0 CW |
946 | if (gt->uc) |
947 | cleanup_uc(gt->uc); | |
c990b4c3 | 948 | |
742379c0 CW |
949 | kfree(gt); |
950 | } | |
b0fd47ad | 951 | |
742379c0 CW |
952 | void __i915_gpu_coredump_free(struct kref *error_ref) |
953 | { | |
954 | struct i915_gpu_coredump *error = | |
955 | container_of(error_ref, typeof(*error), ref); | |
6361f4ba | 956 | |
742379c0 CW |
957 | while (error->gt) { |
958 | struct intel_gt_coredump *gt = error->gt; | |
959 | ||
960 | error->gt = gt->next; | |
961 | cleanup_gt(gt); | |
84734a04 MK |
962 | } |
963 | ||
84734a04 MK |
964 | kfree(error->overlay); |
965 | kfree(error->display); | |
1d6aa7a3 | 966 | |
84a20a8a | 967 | cleanup_params(error); |
7d41ef34 | 968 | |
0e39037b | 969 | err_free_sgl(error->sgl); |
84734a04 MK |
970 | kfree(error); |
971 | } | |
972 | ||
742379c0 CW |
973 | static struct i915_vma_coredump * |
974 | i915_vma_coredump_create(const struct intel_gt *gt, | |
975 | const struct i915_vma *vma, | |
976 | const char *name, | |
977 | struct i915_vma_compress *compress) | |
84734a04 | 978 | { |
742379c0 | 979 | struct i915_ggtt *ggtt = gt->ggtt; |
95374d75 | 980 | const u64 slot = ggtt->error_capture.start; |
742379c0 | 981 | struct i915_vma_coredump *dst; |
95374d75 CW |
982 | unsigned long num_pages; |
983 | struct sgt_iter iter; | |
83bc0f5b | 984 | int ret; |
84734a04 | 985 | |
79c7a28e CW |
986 | might_sleep(); |
987 | ||
742379c0 | 988 | if (!vma || !vma->pages || !compress) |
058d88c4 CW |
989 | return NULL; |
990 | ||
95374d75 | 991 | num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; |
0a97015d | 992 | num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ |
79c7a28e | 993 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); |
058d88c4 | 994 | if (!dst) |
84734a04 MK |
995 | return NULL; |
996 | ||
3bdd4f84 CW |
997 | if (!compress_start(compress)) { |
998 | kfree(dst); | |
999 | return NULL; | |
1000 | } | |
1001 | ||
742379c0 CW |
1002 | strcpy(dst->name, name); |
1003 | dst->next = NULL; | |
1004 | ||
03382dfb CW |
1005 | dst->gtt_offset = vma->node.start; |
1006 | dst->gtt_size = vma->node.size; | |
fd521d3b | 1007 | dst->gtt_page_sizes = vma->page_sizes.gtt; |
83bc0f5b | 1008 | dst->num_pages = num_pages; |
95374d75 | 1009 | dst->page_count = 0; |
0a97015d CW |
1010 | dst->unused = 0; |
1011 | ||
83bc0f5b | 1012 | ret = -EINVAL; |
895d8ebe | 1013 | if (drm_mm_node_allocated(&ggtt->error_capture)) { |
95374d75 | 1014 | void __iomem *s; |
895d8ebe | 1015 | dma_addr_t dma; |
b3c3f5e6 | 1016 | |
895d8ebe DCS |
1017 | for_each_sgt_daddr(dma, iter, vma->pages) { |
1018 | ggtt->vm.insert_page(&ggtt->vm, dma, slot, | |
1019 | I915_CACHE_NONE, 0); | |
742379c0 | 1020 | mb(); |
b3c3f5e6 | 1021 | |
895d8ebe | 1022 | s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); |
742379c0 CW |
1023 | ret = compress_page(compress, |
1024 | (void __force *)s, dst, | |
1025 | true); | |
895d8ebe DCS |
1026 | io_mapping_unmap(s); |
1027 | if (ret) | |
1028 | break; | |
1029 | } | |
1030 | } else if (i915_gem_object_is_lmem(vma->obj)) { | |
1031 | struct intel_memory_region *mem = vma->obj->mm.region; | |
1032 | dma_addr_t dma; | |
1033 | ||
1034 | for_each_sgt_daddr(dma, iter, vma->pages) { | |
1035 | void __iomem *s; | |
1036 | ||
48715f70 | 1037 | s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); |
742379c0 CW |
1038 | ret = compress_page(compress, |
1039 | (void __force *)s, dst, | |
1040 | true); | |
48715f70 | 1041 | io_mapping_unmap(s); |
895d8ebe DCS |
1042 | if (ret) |
1043 | break; | |
1044 | } | |
1045 | } else { | |
1046 | struct page *page; | |
1047 | ||
1048 | for_each_sgt_page(page, iter, vma->pages) { | |
1049 | void *s; | |
1050 | ||
1051 | drm_clflush_pages(&page, 1); | |
1052 | ||
48715f70 | 1053 | s = kmap(page); |
742379c0 | 1054 | ret = compress_page(compress, s, dst, false); |
bae21dac | 1055 | kunmap(page); |
895d8ebe DCS |
1056 | |
1057 | drm_clflush_pages(&page, 1); | |
1058 | ||
1059 | if (ret) | |
1060 | break; | |
1061 | } | |
84734a04 | 1062 | } |
84734a04 | 1063 | |
3bdd4f84 | 1064 | if (ret || compress_flush(compress, dst)) { |
83bc0f5b | 1065 | while (dst->page_count--) |
3bdd4f84 | 1066 | pool_free(&compress->pool, dst->pages[dst->page_count]); |
83bc0f5b CW |
1067 | kfree(dst); |
1068 | dst = NULL; | |
1069 | } | |
3bdd4f84 | 1070 | compress_finish(compress); |
95374d75 | 1071 | |
95374d75 | 1072 | return dst; |
84734a04 | 1073 | } |
84734a04 | 1074 | |
742379c0 | 1075 | static void gt_record_fences(struct intel_gt_coredump *gt) |
011cf577 | 1076 | { |
742379c0 CW |
1077 | struct i915_ggtt *ggtt = gt->_gt->ggtt; |
1078 | struct intel_uncore *uncore = gt->_gt->uncore; | |
84734a04 MK |
1079 | int i; |
1080 | ||
742379c0 CW |
1081 | if (INTEL_GEN(uncore->i915) >= 6) { |
1082 | for (i = 0; i < ggtt->num_fences; i++) | |
1083 | gt->fence[i] = | |
7f1502d9 TU |
1084 | intel_uncore_read64(uncore, |
1085 | FENCE_REG_GEN6_LO(i)); | |
742379c0 CW |
1086 | } else if (INTEL_GEN(uncore->i915) >= 4) { |
1087 | for (i = 0; i < ggtt->num_fences; i++) | |
1088 | gt->fence[i] = | |
7f1502d9 TU |
1089 | intel_uncore_read64(uncore, |
1090 | FENCE_REG_965_LO(i)); | |
5a4c6f1b | 1091 | } else { |
742379c0 CW |
1092 | for (i = 0; i < ggtt->num_fences; i++) |
1093 | gt->fence[i] = | |
7f1502d9 | 1094 | intel_uncore_read(uncore, FENCE_REG(i)); |
eecf613a | 1095 | } |
742379c0 | 1096 | gt->nfence = i; |
84734a04 MK |
1097 | } |
1098 | ||
742379c0 | 1099 | static void engine_record_registers(struct intel_engine_coredump *ee) |
84734a04 | 1100 | { |
742379c0 CW |
1101 | const struct intel_engine_cs *engine = ee->engine; |
1102 | struct drm_i915_private *i915 = engine->i915; | |
6361f4ba | 1103 | |
742379c0 | 1104 | if (INTEL_GEN(i915) >= 6) { |
baba6e57 | 1105 | ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); |
91b59cd9 | 1106 | |
742379c0 CW |
1107 | if (INTEL_GEN(i915) >= 12) |
1108 | ee->fault_reg = intel_uncore_read(engine->uncore, | |
1109 | GEN12_RING_FAULT_REG); | |
1110 | else if (INTEL_GEN(i915) >= 8) | |
1111 | ee->fault_reg = intel_uncore_read(engine->uncore, | |
1112 | GEN8_RING_FAULT_REG); | |
62acc7e8 | 1113 | else |
77a302e0 | 1114 | ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); |
4e5aabfd BW |
1115 | } |
1116 | ||
742379c0 | 1117 | if (INTEL_GEN(i915) >= 4) { |
70a76a9b | 1118 | ee->esr = ENGINE_READ(engine, RING_ESR); |
baba6e57 DCS |
1119 | ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); |
1120 | ee->ipeir = ENGINE_READ(engine, RING_IPEIR); | |
1121 | ee->ipehr = ENGINE_READ(engine, RING_IPEHR); | |
1122 | ee->instps = ENGINE_READ(engine, RING_INSTPS); | |
1123 | ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); | |
742379c0 CW |
1124 | ee->ccid = ENGINE_READ(engine, CCID); |
1125 | if (INTEL_GEN(i915) >= 8) { | |
baba6e57 DCS |
1126 | ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; |
1127 | ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; | |
13ffadd1 | 1128 | } |
baba6e57 | 1129 | ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); |
84734a04 | 1130 | } else { |
baba6e57 DCS |
1131 | ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); |
1132 | ee->ipeir = ENGINE_READ(engine, IPEIR); | |
1133 | ee->ipehr = ENGINE_READ(engine, IPEHR); | |
84734a04 MK |
1134 | } |
1135 | ||
0e704476 | 1136 | intel_engine_get_instdone(engine, &ee->instdone); |
d636951e | 1137 | |
baba6e57 | 1138 | ee->instpm = ENGINE_READ(engine, RING_INSTPM); |
7e37f889 | 1139 | ee->acthd = intel_engine_get_active_head(engine); |
baba6e57 DCS |
1140 | ee->start = ENGINE_READ(engine, RING_START); |
1141 | ee->head = ENGINE_READ(engine, RING_HEAD); | |
1142 | ee->tail = ENGINE_READ(engine, RING_TAIL); | |
1143 | ee->ctl = ENGINE_READ(engine, RING_CTL); | |
742379c0 | 1144 | if (INTEL_GEN(i915) > 2) |
baba6e57 | 1145 | ee->mode = ENGINE_READ(engine, RING_MI_MODE); |
84734a04 | 1146 | |
742379c0 | 1147 | if (!HWS_NEEDS_PHYSICAL(i915)) { |
f0f59a00 | 1148 | i915_reg_t mmio; |
f3ce3821 | 1149 | |
742379c0 | 1150 | if (IS_GEN(i915, 7)) { |
0bc40be8 | 1151 | switch (engine->id) { |
f3ce3821 | 1152 | default: |
8a68d464 | 1153 | MISSING_CASE(engine->id); |
2defb94e | 1154 | /* fall through */ |
8a68d464 | 1155 | case RCS0: |
f3ce3821 CW |
1156 | mmio = RENDER_HWS_PGA_GEN7; |
1157 | break; | |
8a68d464 | 1158 | case BCS0: |
f3ce3821 CW |
1159 | mmio = BLT_HWS_PGA_GEN7; |
1160 | break; | |
8a68d464 | 1161 | case VCS0: |
f3ce3821 CW |
1162 | mmio = BSD_HWS_PGA_GEN7; |
1163 | break; | |
8a68d464 | 1164 | case VECS0: |
f3ce3821 CW |
1165 | mmio = VEBOX_HWS_PGA_GEN7; |
1166 | break; | |
1167 | } | |
cf819eff | 1168 | } else if (IS_GEN(engine->i915, 6)) { |
0bc40be8 | 1169 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
f3ce3821 CW |
1170 | } else { |
1171 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 1172 | mmio = RING_HWS_PGA(engine->mmio_base); |
f3ce3821 CW |
1173 | } |
1174 | ||
742379c0 | 1175 | ee->hws = intel_uncore_read(engine->uncore, mmio); |
f3ce3821 CW |
1176 | } |
1177 | ||
742379c0 | 1178 | ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); |
6c7a01ec | 1179 | |
742379c0 | 1180 | if (HAS_PPGTT(i915)) { |
6c7a01ec BW |
1181 | int i; |
1182 | ||
dbc65183 | 1183 | ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); |
6c7a01ec | 1184 | |
742379c0 | 1185 | if (IS_GEN(i915, 6)) { |
6361f4ba | 1186 | ee->vm_info.pp_dir_base = |
baba6e57 | 1187 | ENGINE_READ(engine, RING_PP_DIR_BASE_READ); |
742379c0 | 1188 | } else if (IS_GEN(i915, 7)) { |
6361f4ba | 1189 | ee->vm_info.pp_dir_base = |
6d425728 | 1190 | ENGINE_READ(engine, RING_PP_DIR_BASE); |
742379c0 | 1191 | } else if (INTEL_GEN(i915) >= 8) { |
6d425728 CW |
1192 | u32 base = engine->mmio_base; |
1193 | ||
6c7a01ec | 1194 | for (i = 0; i < 4; i++) { |
6361f4ba | 1195 | ee->vm_info.pdp[i] = |
742379c0 CW |
1196 | intel_uncore_read(engine->uncore, |
1197 | GEN8_RING_PDP_UDW(base, i)); | |
6361f4ba CW |
1198 | ee->vm_info.pdp[i] <<= 32; |
1199 | ee->vm_info.pdp[i] |= | |
742379c0 CW |
1200 | intel_uncore_read(engine->uncore, |
1201 | GEN8_RING_PDP_LDW(base, i)); | |
6c7a01ec | 1202 | } |
6d425728 | 1203 | } |
6c7a01ec | 1204 | } |
84734a04 MK |
1205 | } |
1206 | ||
22b7a426 | 1207 | static void record_request(const struct i915_request *request, |
742379c0 | 1208 | struct i915_request_coredump *erq) |
35ca039e | 1209 | { |
52c0fdb2 | 1210 | erq->flags = request->fence.flags; |
b300fde8 CW |
1211 | erq->context = request->fence.context; |
1212 | erq->seqno = request->fence.seqno; | |
b7268c5e | 1213 | erq->sched_attr = request->sched.attr; |
3a068721 | 1214 | erq->start = i915_ggtt_offset(request->ring->vma); |
35ca039e CW |
1215 | erq->head = request->head; |
1216 | erq->tail = request->tail; | |
6a8679c0 CW |
1217 | |
1218 | erq->pid = 0; | |
1219 | rcu_read_lock(); | |
30523408 CW |
1220 | if (!intel_context_is_closed(request->context)) { |
1221 | const struct i915_gem_context *ctx; | |
1222 | ||
1223 | ctx = rcu_dereference(request->context->gem_context); | |
1224 | if (ctx) | |
1225 | erq->pid = pid_nr(ctx->pid); | |
1226 | } | |
6a8679c0 | 1227 | rcu_read_unlock(); |
35ca039e CW |
1228 | } |
1229 | ||
742379c0 | 1230 | static void engine_record_execlists(struct intel_engine_coredump *ee) |
35ca039e | 1231 | { |
742379c0 CW |
1232 | const struct intel_engine_execlists * const el = &ee->engine->execlists; |
1233 | struct i915_request * const *port = el->active; | |
22b7a426 | 1234 | unsigned int n = 0; |
35ca039e | 1235 | |
22b7a426 CW |
1236 | while (*port) |
1237 | record_request(*port++, &ee->execlist[n++]); | |
76e70087 MK |
1238 | |
1239 | ee->num_ports = n; | |
35ca039e CW |
1240 | } |
1241 | ||
742379c0 | 1242 | static bool record_context(struct i915_gem_context_coredump *e, |
c990b4c3 | 1243 | const struct i915_request *rq) |
4fa6053e | 1244 | { |
6a8679c0 CW |
1245 | struct i915_gem_context *ctx; |
1246 | struct task_struct *task; | |
03d0ed8a | 1247 | bool simulated; |
6a8679c0 CW |
1248 | |
1249 | rcu_read_lock(); | |
1250 | ctx = rcu_dereference(rq->context->gem_context); | |
1251 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
1252 | ctx = NULL; | |
1253 | rcu_read_unlock(); | |
9f3ccd40 | 1254 | if (!ctx) |
03d0ed8a | 1255 | return true; |
c990b4c3 | 1256 | |
6a8679c0 CW |
1257 | rcu_read_lock(); |
1258 | task = pid_task(ctx->pid, PIDTYPE_PID); | |
1259 | if (task) { | |
1260 | strcpy(e->comm, task->comm); | |
1261 | e->pid = task->pid; | |
4fa6053e | 1262 | } |
6a8679c0 | 1263 | rcu_read_unlock(); |
4fa6053e | 1264 | |
b7268c5e | 1265 | e->sched_attr = ctx->sched; |
77b25a97 CW |
1266 | e->guilty = atomic_read(&ctx->guilty_count); |
1267 | e->active = atomic_read(&ctx->active_count); | |
c990b4c3 | 1268 | |
1883a0a4 TU |
1269 | e->total_runtime = rq->context->runtime.total; |
1270 | e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); | |
1271 | ||
03d0ed8a | 1272 | simulated = i915_gem_context_no_error_capture(ctx); |
6a8679c0 CW |
1273 | |
1274 | i915_gem_context_put(ctx); | |
03d0ed8a | 1275 | return simulated; |
4fa6053e CW |
1276 | } |
1277 | ||
742379c0 CW |
1278 | struct intel_engine_capture_vma { |
1279 | struct intel_engine_capture_vma *next; | |
1280 | struct i915_vma *vma; | |
1281 | char name[16]; | |
79c7a28e CW |
1282 | }; |
1283 | ||
742379c0 CW |
1284 | static struct intel_engine_capture_vma * |
1285 | capture_vma(struct intel_engine_capture_vma *next, | |
79c7a28e | 1286 | struct i915_vma *vma, |
742379c0 CW |
1287 | const char *name, |
1288 | gfp_t gfp) | |
79c7a28e | 1289 | { |
742379c0 | 1290 | struct intel_engine_capture_vma *c; |
79c7a28e | 1291 | |
79c7a28e CW |
1292 | if (!vma) |
1293 | return next; | |
1294 | ||
742379c0 | 1295 | c = kmalloc(sizeof(*c), gfp); |
79c7a28e CW |
1296 | if (!c) |
1297 | return next; | |
1298 | ||
b1e3177b | 1299 | if (!i915_active_acquire_if_busy(&vma->active)) { |
79c7a28e CW |
1300 | kfree(c); |
1301 | return next; | |
1302 | } | |
1303 | ||
742379c0 CW |
1304 | strcpy(c->name, name); |
1305 | c->vma = i915_vma_get(vma); | |
79c7a28e CW |
1306 | |
1307 | c->next = next; | |
1308 | return c; | |
1309 | } | |
1310 | ||
742379c0 CW |
1311 | static struct intel_engine_capture_vma * |
1312 | capture_user(struct intel_engine_capture_vma *capture, | |
1313 | const struct i915_request *rq, | |
1314 | gfp_t gfp) | |
b0fd47ad | 1315 | { |
e61e0f51 | 1316 | struct i915_capture_list *c; |
b0fd47ad | 1317 | |
742379c0 CW |
1318 | for (c = rq->capture_list; c; c = c->next) |
1319 | capture = capture_vma(capture, c->vma, "user", gfp); | |
79c7a28e CW |
1320 | |
1321 | return capture; | |
b0fd47ad CW |
1322 | } |
1323 | ||
742379c0 CW |
1324 | static struct i915_vma_coredump * |
1325 | capture_object(const struct intel_gt *gt, | |
3bdd4f84 | 1326 | struct drm_i915_gem_object *obj, |
742379c0 CW |
1327 | const char *name, |
1328 | struct i915_vma_compress *compress) | |
4e90a6e2 CW |
1329 | { |
1330 | if (obj && i915_gem_object_has_pages(obj)) { | |
1331 | struct i915_vma fake = { | |
1332 | .node = { .start = U64_MAX, .size = obj->base.size }, | |
b5e0a941 | 1333 | .size = obj->base.size, |
4e90a6e2 CW |
1334 | .pages = obj->mm.pages, |
1335 | .obj = obj, | |
1336 | }; | |
1337 | ||
742379c0 | 1338 | return i915_vma_coredump_create(gt, &fake, name, compress); |
4e90a6e2 CW |
1339 | } else { |
1340 | return NULL; | |
1341 | } | |
1342 | } | |
1343 | ||
742379c0 CW |
1344 | static void add_vma(struct intel_engine_coredump *ee, |
1345 | struct i915_vma_coredump *vma) | |
84734a04 | 1346 | { |
742379c0 CW |
1347 | if (vma) { |
1348 | vma->next = ee->vma; | |
1349 | ee->vma = vma; | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | struct intel_engine_coredump * | |
1354 | intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) | |
1355 | { | |
1356 | struct intel_engine_coredump *ee; | |
c990b4c3 | 1357 | |
742379c0 | 1358 | ee = kzalloc(sizeof(*ee), gfp); |
c990b4c3 | 1359 | if (!ee) |
742379c0 | 1360 | return NULL; |
84734a04 | 1361 | |
742379c0 | 1362 | ee->engine = engine; |
372fbb8e | 1363 | |
742379c0 CW |
1364 | engine_record_registers(ee); |
1365 | engine_record_execlists(ee); | |
3bdd4f84 | 1366 | |
742379c0 CW |
1367 | return ee; |
1368 | } | |
ab0e7ff9 | 1369 | |
742379c0 CW |
1370 | struct intel_engine_capture_vma * |
1371 | intel_engine_coredump_add_request(struct intel_engine_coredump *ee, | |
1372 | struct i915_request *rq, | |
1373 | gfp_t gfp) | |
1374 | { | |
1375 | struct intel_engine_capture_vma *vma = NULL; | |
79c7a28e | 1376 | |
742379c0 CW |
1377 | ee->simulated |= record_context(&ee->context, rq); |
1378 | if (ee->simulated) | |
1379 | return NULL; | |
ab0e7ff9 | 1380 | |
742379c0 CW |
1381 | /* |
1382 | * We need to copy these to an anonymous buffer | |
1383 | * as the simplest method to avoid being overwritten | |
1384 | * by userspace. | |
1385 | */ | |
1386 | vma = capture_vma(vma, rq->batch, "batch", gfp); | |
1387 | vma = capture_user(vma, rq, gfp); | |
1388 | vma = capture_vma(vma, rq->ring->vma, "ring", gfp); | |
1389 | vma = capture_vma(vma, rq->context->state, "HW context", gfp); | |
79c7a28e | 1390 | |
742379c0 CW |
1391 | ee->rq_head = rq->head; |
1392 | ee->rq_post = rq->postfix; | |
1393 | ee->rq_tail = rq->tail; | |
bc3d6744 | 1394 | |
742379c0 CW |
1395 | return vma; |
1396 | } | |
cdb324bd | 1397 | |
742379c0 CW |
1398 | void |
1399 | intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, | |
1400 | struct intel_engine_capture_vma *capture, | |
1401 | struct i915_vma_compress *compress) | |
1402 | { | |
1403 | const struct intel_engine_cs *engine = ee->engine; | |
57bc699d | 1404 | |
742379c0 CW |
1405 | while (capture) { |
1406 | struct intel_engine_capture_vma *this = capture; | |
1407 | struct i915_vma *vma = this->vma; | |
c990b4c3 | 1408 | |
742379c0 CW |
1409 | add_vma(ee, |
1410 | i915_vma_coredump_create(engine->gt, | |
1411 | vma, this->name, | |
1412 | compress)); | |
84734a04 | 1413 | |
742379c0 CW |
1414 | i915_active_release(&vma->active); |
1415 | i915_vma_put(vma); | |
c990b4c3 | 1416 | |
742379c0 CW |
1417 | capture = this->next; |
1418 | kfree(this); | |
1419 | } | |
79c7a28e | 1420 | |
742379c0 CW |
1421 | add_vma(ee, |
1422 | i915_vma_coredump_create(engine->gt, | |
1423 | engine->status_page.vma, | |
1424 | "HW Status", | |
1425 | compress)); | |
79c7a28e | 1426 | |
742379c0 CW |
1427 | add_vma(ee, |
1428 | i915_vma_coredump_create(engine->gt, | |
1429 | engine->wa_ctx.vma, | |
1430 | "WA context", | |
1431 | compress)); | |
79c7a28e | 1432 | |
742379c0 CW |
1433 | add_vma(ee, |
1434 | capture_object(engine->gt, | |
1435 | engine->default_state, | |
1436 | "NULL context", | |
1437 | compress)); | |
1438 | } | |
1439 | ||
1440 | static struct intel_engine_coredump * | |
1441 | capture_engine(struct intel_engine_cs *engine, | |
1442 | struct i915_vma_compress *compress) | |
1443 | { | |
1a8585bd | 1444 | struct intel_engine_capture_vma *capture = NULL; |
742379c0 CW |
1445 | struct intel_engine_coredump *ee; |
1446 | struct i915_request *rq; | |
1447 | unsigned long flags; | |
79c7a28e | 1448 | |
742379c0 CW |
1449 | ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); |
1450 | if (!ee) | |
1451 | return NULL; | |
c0ce4663 | 1452 | |
742379c0 | 1453 | spin_lock_irqsave(&engine->active.lock, flags); |
742379c0 | 1454 | rq = intel_engine_find_active_request(engine); |
1a8585bd CW |
1455 | if (rq) |
1456 | capture = intel_engine_coredump_add_request(ee, rq, | |
1457 | ATOMIC_MAYFAIL); | |
1458 | spin_unlock_irqrestore(&engine->active.lock, flags); | |
1459 | if (!capture) { | |
742379c0 CW |
1460 | kfree(ee); |
1461 | return NULL; | |
1462 | } | |
c990b4c3 | 1463 | |
742379c0 | 1464 | intel_engine_coredump_add_vma(ee, capture, compress); |
c990b4c3 | 1465 | |
742379c0 | 1466 | return ee; |
84734a04 MK |
1467 | } |
1468 | ||
3bdd4f84 | 1469 | static void |
742379c0 CW |
1470 | gt_record_engines(struct intel_gt_coredump *gt, |
1471 | struct i915_vma_compress *compress) | |
7d41ef34 | 1472 | { |
742379c0 CW |
1473 | struct intel_engine_cs *engine; |
1474 | enum intel_engine_id id; | |
7d41ef34 | 1475 | |
742379c0 CW |
1476 | for_each_engine(engine, gt->_gt, id) { |
1477 | struct intel_engine_coredump *ee; | |
1478 | ||
1479 | /* Refill our page pool before entering atomic section */ | |
1480 | pool_refill(&compress->pool, ALLOW_FAIL); | |
1481 | ||
1482 | ee = capture_engine(engine, compress); | |
1483 | if (!ee) | |
1484 | continue; | |
1485 | ||
1486 | gt->simulated |= ee->simulated; | |
1487 | if (ee->simulated) { | |
1488 | kfree(ee); | |
1489 | continue; | |
1490 | } | |
1491 | ||
1492 | ee->next = gt->engine; | |
1493 | gt->engine = ee; | |
1494 | } | |
1495 | } | |
1496 | ||
1497 | static struct intel_uc_coredump * | |
1498 | gt_record_uc(struct intel_gt_coredump *gt, | |
1499 | struct i915_vma_compress *compress) | |
1500 | { | |
1501 | const struct intel_uc *uc = >->_gt->uc; | |
1502 | struct intel_uc_coredump *error_uc; | |
1503 | ||
1504 | error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); | |
1505 | if (!error_uc) | |
1506 | return NULL; | |
7d41ef34 | 1507 | |
abb042f3 MW |
1508 | memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); |
1509 | memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); | |
7d41ef34 MW |
1510 | |
1511 | /* Non-default firmware paths will be specified by the modparam. | |
1512 | * As modparams are generally accesible from the userspace make | |
1513 | * explicit copies of the firmware paths. | |
1514 | */ | |
3bdd4f84 CW |
1515 | error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); |
1516 | error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); | |
742379c0 CW |
1517 | error_uc->guc_log = |
1518 | i915_vma_coredump_create(gt->_gt, | |
1519 | uc->guc.log.vma, "GuC log buffer", | |
1520 | compress); | |
1521 | ||
1522 | return error_uc; | |
1523 | } | |
1524 | ||
1525 | static void gt_capture_prepare(struct intel_gt_coredump *gt) | |
1526 | { | |
1527 | struct i915_ggtt *ggtt = gt->_gt->ggtt; | |
1528 | ||
1529 | mutex_lock(&ggtt->error_mutex); | |
1530 | } | |
1531 | ||
1532 | static void gt_capture_finish(struct intel_gt_coredump *gt) | |
1533 | { | |
1534 | struct i915_ggtt *ggtt = gt->_gt->ggtt; | |
1535 | ||
1536 | if (drm_mm_node_allocated(&ggtt->error_capture)) | |
1537 | ggtt->vm.clear_range(&ggtt->vm, | |
1538 | ggtt->error_capture.start, | |
1539 | PAGE_SIZE); | |
1540 | ||
1541 | mutex_unlock(&ggtt->error_mutex); | |
27b85bea AG |
1542 | } |
1543 | ||
1d762aad | 1544 | /* Capture all registers which don't fit into another category. */ |
742379c0 | 1545 | static void gt_record_regs(struct intel_gt_coredump *gt) |
84734a04 | 1546 | { |
742379c0 CW |
1547 | struct intel_uncore *uncore = gt->_gt->uncore; |
1548 | struct drm_i915_private *i915 = uncore->i915; | |
885ea5a8 | 1549 | int i; |
84734a04 | 1550 | |
742379c0 CW |
1551 | /* |
1552 | * General organization | |
654c90c6 BW |
1553 | * 1. Registers specific to a single generation |
1554 | * 2. Registers which belong to multiple generations | |
1555 | * 3. Feature specific registers. | |
1556 | * 4. Everything else | |
1557 | * Please try to follow the order. | |
1558 | */ | |
84734a04 | 1559 | |
654c90c6 | 1560 | /* 1: Registers specific to a single generation */ |
4f5fd91f | 1561 | if (IS_VALLEYVIEW(i915)) { |
742379c0 CW |
1562 | gt->gtier[0] = intel_uncore_read(uncore, GTIER); |
1563 | gt->ier = intel_uncore_read(uncore, VLV_IER); | |
1564 | gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); | |
654c90c6 | 1565 | } |
84734a04 | 1566 | |
4f5fd91f | 1567 | if (IS_GEN(i915, 7)) |
742379c0 | 1568 | gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); |
84734a04 | 1569 | |
91b59cd9 | 1570 | if (INTEL_GEN(i915) >= 12) { |
742379c0 CW |
1571 | gt->fault_data0 = intel_uncore_read(uncore, |
1572 | GEN12_FAULT_TLB_DATA0); | |
1573 | gt->fault_data1 = intel_uncore_read(uncore, | |
1574 | GEN12_FAULT_TLB_DATA1); | |
91b59cd9 | 1575 | } else if (INTEL_GEN(i915) >= 8) { |
742379c0 CW |
1576 | gt->fault_data0 = intel_uncore_read(uncore, |
1577 | GEN8_FAULT_TLB_DATA0); | |
1578 | gt->fault_data1 = intel_uncore_read(uncore, | |
1579 | GEN8_FAULT_TLB_DATA1); | |
6c826f34 MK |
1580 | } |
1581 | ||
4f5fd91f | 1582 | if (IS_GEN(i915, 6)) { |
742379c0 CW |
1583 | gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); |
1584 | gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); | |
1585 | gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); | |
91ec5d11 | 1586 | } |
84734a04 | 1587 | |
654c90c6 | 1588 | /* 2: Registers which belong to multiple generations */ |
4f5fd91f | 1589 | if (INTEL_GEN(i915) >= 7) |
742379c0 | 1590 | gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); |
84734a04 | 1591 | |
4f5fd91f | 1592 | if (INTEL_GEN(i915) >= 6) { |
742379c0 | 1593 | gt->derrmr = intel_uncore_read(uncore, DERRMR); |
23dea051 | 1594 | if (INTEL_GEN(i915) < 12) { |
742379c0 CW |
1595 | gt->error = intel_uncore_read(uncore, ERROR_GEN6); |
1596 | gt->done_reg = intel_uncore_read(uncore, DONE_REG); | |
23dea051 | 1597 | } |
84734a04 MK |
1598 | } |
1599 | ||
654c90c6 | 1600 | /* 3: Feature specific registers */ |
4f5fd91f | 1601 | if (IS_GEN_RANGE(i915, 6, 7)) { |
742379c0 CW |
1602 | gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); |
1603 | gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); | |
91ec5d11 BW |
1604 | } |
1605 | ||
fd521d3b | 1606 | if (IS_GEN_RANGE(i915, 8, 11)) |
742379c0 | 1607 | gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); |
fd521d3b | 1608 | |
ba1d18e3 | 1609 | if (IS_GEN(i915, 12)) |
742379c0 | 1610 | gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); |
ba1d18e3 | 1611 | |
e50dbdbf MK |
1612 | if (INTEL_GEN(i915) >= 12) { |
1613 | for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { | |
742379c0 | 1614 | gt->sfc_done[i] = |
e50dbdbf MK |
1615 | intel_uncore_read(uncore, GEN12_SFC_DONE(i)); |
1616 | } | |
811bb3db | 1617 | |
742379c0 | 1618 | gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); |
e50dbdbf MK |
1619 | } |
1620 | ||
91ec5d11 | 1621 | /* 4: Everything else */ |
4f5fd91f | 1622 | if (INTEL_GEN(i915) >= 11) { |
742379c0 CW |
1623 | gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); |
1624 | gt->gtier[0] = | |
4f5fd91f TU |
1625 | intel_uncore_read(uncore, |
1626 | GEN11_RENDER_COPY_INTR_ENABLE); | |
742379c0 | 1627 | gt->gtier[1] = |
4f5fd91f | 1628 | intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); |
742379c0 | 1629 | gt->gtier[2] = |
4f5fd91f | 1630 | intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); |
742379c0 | 1631 | gt->gtier[3] = |
4f5fd91f TU |
1632 | intel_uncore_read(uncore, |
1633 | GEN11_GPM_WGBOXPERF_INTR_ENABLE); | |
742379c0 | 1634 | gt->gtier[4] = |
4f5fd91f TU |
1635 | intel_uncore_read(uncore, |
1636 | GEN11_CRYPTO_RSVD_INTR_ENABLE); | |
742379c0 | 1637 | gt->gtier[5] = |
4f5fd91f TU |
1638 | intel_uncore_read(uncore, |
1639 | GEN11_GUNIT_CSME_INTR_ENABLE); | |
742379c0 | 1640 | gt->ngtier = 6; |
4f5fd91f | 1641 | } else if (INTEL_GEN(i915) >= 8) { |
742379c0 | 1642 | gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); |
885ea5a8 | 1643 | for (i = 0; i < 4; i++) |
742379c0 CW |
1644 | gt->gtier[i] = |
1645 | intel_uncore_read(uncore, GEN8_GT_IER(i)); | |
1646 | gt->ngtier = 4; | |
4f5fd91f | 1647 | } else if (HAS_PCH_SPLIT(i915)) { |
742379c0 CW |
1648 | gt->ier = intel_uncore_read(uncore, DEIER); |
1649 | gt->gtier[0] = intel_uncore_read(uncore, GTIER); | |
1650 | gt->ngtier = 1; | |
4f5fd91f | 1651 | } else if (IS_GEN(i915, 2)) { |
742379c0 | 1652 | gt->ier = intel_uncore_read16(uncore, GEN2_IER); |
4f5fd91f | 1653 | } else if (!IS_VALLEYVIEW(i915)) { |
742379c0 | 1654 | gt->ier = intel_uncore_read(uncore, GEN2_IER); |
654c90c6 | 1655 | } |
742379c0 CW |
1656 | gt->eir = intel_uncore_read(uncore, EIR); |
1657 | gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); | |
1658 | } | |
1659 | ||
1660 | /* | |
1661 | * Generate a semi-unique error code. The code is not meant to have meaning, The | |
1662 | * code's only purpose is to try to prevent false duplicated bug reports by | |
1663 | * grossly estimating a GPU error state. | |
1664 | * | |
1665 | * TODO Ideally, hashing the batchbuffer would be a very nice way to determine | |
1666 | * the hang if we could strip the GTT offset information from it. | |
1667 | * | |
1668 | * It's only a small step better than a random number in its current form. | |
1669 | */ | |
1670 | static u32 generate_ecode(const struct intel_engine_coredump *ee) | |
1671 | { | |
1672 | /* | |
1673 | * IPEHR would be an ideal way to detect errors, as it's the gross | |
1674 | * measure of "the command that hung." However, has some very common | |
1675 | * synchronization commands which almost always appear in the case | |
1676 | * strictly a client bug. Use instdone to differentiate those some. | |
1677 | */ | |
1678 | return ee ? ee->ipehr ^ ee->instdone.instdone : 0; | |
1d762aad BW |
1679 | } |
1680 | ||
742379c0 | 1681 | static const char *error_msg(struct i915_gpu_coredump *error) |
cb383002 | 1682 | { |
742379c0 CW |
1683 | struct intel_engine_coredump *first = NULL; |
1684 | struct intel_gt_coredump *gt; | |
1685 | intel_engine_mask_t engines; | |
eb8d0f5a | 1686 | int len; |
cb383002 | 1687 | |
742379c0 CW |
1688 | engines = 0; |
1689 | for (gt = error->gt; gt; gt = gt->next) { | |
1690 | struct intel_engine_coredump *cs; | |
1691 | ||
1692 | if (gt->engine && !first) | |
1693 | first = gt->engine; | |
1694 | ||
1695 | for (cs = gt->engine; cs; cs = cs->next) | |
1696 | engines |= cs->engine->mask; | |
1697 | } | |
1698 | ||
58174462 | 1699 | len = scnprintf(error->error_msg, sizeof(error->error_msg), |
742379c0 | 1700 | "GPU HANG: ecode %d:%x:%08x", |
eb8d0f5a | 1701 | INTEL_GEN(error->i915), engines, |
742379c0 | 1702 | generate_ecode(first)); |
29baf3ae | 1703 | if (first && first->context.pid) { |
eb8d0f5a | 1704 | /* Just show the first executing process, more is confusing */ |
58174462 MK |
1705 | len += scnprintf(error->error_msg + len, |
1706 | sizeof(error->error_msg) - len, | |
1707 | ", in %s [%d]", | |
742379c0 | 1708 | first->context.comm, first->context.pid); |
eb8d0f5a | 1709 | } |
58174462 | 1710 | |
eb8d0f5a | 1711 | return error->error_msg; |
cb383002 MK |
1712 | } |
1713 | ||
742379c0 | 1714 | static void capture_gen(struct i915_gpu_coredump *error) |
48b031e3 | 1715 | { |
53b725c7 DCS |
1716 | struct drm_i915_private *i915 = error->i915; |
1717 | ||
53b725c7 DCS |
1718 | error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); |
1719 | error->suspended = i915->runtime_pm.suspended; | |
f73b5674 | 1720 | |
eb5be9d0 CW |
1721 | error->iommu = -1; |
1722 | #ifdef CONFIG_INTEL_IOMMU | |
1723 | error->iommu = intel_iommu_gfx_mapped; | |
1724 | #endif | |
53b725c7 DCS |
1725 | error->reset_count = i915_reset_count(&i915->gpu_error); |
1726 | error->suspend_count = i915->suspend_count; | |
2bd160a1 | 1727 | |
742379c0 | 1728 | i915_params_copy(&error->params, &i915_modparams); |
2bd160a1 | 1729 | memcpy(&error->device_info, |
53b725c7 | 1730 | INTEL_INFO(i915), |
2bd160a1 | 1731 | sizeof(error->device_info)); |
0258404f JN |
1732 | memcpy(&error->runtime_info, |
1733 | RUNTIME_INFO(i915), | |
1734 | sizeof(error->runtime_info)); | |
53b725c7 | 1735 | error->driver_caps = i915->caps; |
48b031e3 MK |
1736 | } |
1737 | ||
742379c0 CW |
1738 | struct i915_gpu_coredump * |
1739 | i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) | |
84a20a8a | 1740 | { |
742379c0 CW |
1741 | struct i915_gpu_coredump *error; |
1742 | ||
1743 | if (!i915_modparams.error_capture) | |
1744 | return NULL; | |
1745 | ||
1746 | error = kzalloc(sizeof(*error), gfp); | |
1747 | if (!error) | |
1748 | return NULL; | |
1749 | ||
1750 | kref_init(&error->ref); | |
1751 | error->i915 = i915; | |
1752 | ||
1753 | error->time = ktime_get_real(); | |
1754 | error->boottime = ktime_get_boottime(); | |
1755 | error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); | |
1756 | error->capture = jiffies; | |
1757 | ||
1758 | capture_gen(error); | |
1759 | ||
1760 | return error; | |
84a20a8a MW |
1761 | } |
1762 | ||
742379c0 CW |
1763 | #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) |
1764 | ||
1765 | struct intel_gt_coredump * | |
1766 | intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) | |
8f5c6fe4 | 1767 | { |
742379c0 | 1768 | struct intel_gt_coredump *gc; |
8f5c6fe4 | 1769 | |
742379c0 CW |
1770 | gc = kzalloc(sizeof(*gc), gfp); |
1771 | if (!gc) | |
1772 | return NULL; | |
1773 | ||
1774 | gc->_gt = gt; | |
1775 | gc->awake = intel_gt_pm_is_awake(gt); | |
1776 | ||
1777 | gt_record_regs(gc); | |
1778 | gt_record_fences(gc); | |
1779 | ||
1780 | return gc; | |
1781 | } | |
895d8ebe | 1782 | |
742379c0 CW |
1783 | struct i915_vma_compress * |
1784 | i915_vma_capture_prepare(struct intel_gt_coredump *gt) | |
1785 | { | |
1786 | struct i915_vma_compress *compress; | |
1787 | ||
1788 | compress = kmalloc(sizeof(*compress), ALLOW_FAIL); | |
1789 | if (!compress) | |
1790 | return NULL; | |
1791 | ||
1792 | if (!compress_init(compress)) { | |
1793 | kfree(compress); | |
1794 | return NULL; | |
895d8ebe | 1795 | } |
742379c0 CW |
1796 | |
1797 | gt_capture_prepare(gt); | |
1798 | ||
1799 | return compress; | |
8f5c6fe4 CW |
1800 | } |
1801 | ||
742379c0 CW |
1802 | void i915_vma_capture_finish(struct intel_gt_coredump *gt, |
1803 | struct i915_vma_compress *compress) | |
1804 | { | |
1805 | if (!compress) | |
1806 | return; | |
eafc4894 | 1807 | |
742379c0 CW |
1808 | gt_capture_finish(gt); |
1809 | ||
1810 | compress_fini(compress); | |
1811 | kfree(compress); | |
1812 | } | |
1813 | ||
1814 | struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) | |
5a4c6f1b | 1815 | { |
742379c0 | 1816 | struct i915_gpu_coredump *error; |
5a4c6f1b | 1817 | |
e6154e4c CW |
1818 | /* Check if GPU capture has been disabled */ |
1819 | error = READ_ONCE(i915->gpu_error.first_error); | |
1820 | if (IS_ERR(error)) | |
1821 | return error; | |
1822 | ||
742379c0 CW |
1823 | error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); |
1824 | if (!error) | |
e6154e4c | 1825 | return ERR_PTR(-ENOMEM); |
5a4c6f1b | 1826 | |
742379c0 CW |
1827 | error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); |
1828 | if (error->gt) { | |
1829 | struct i915_vma_compress *compress; | |
3bdd4f84 | 1830 | |
742379c0 CW |
1831 | compress = i915_vma_capture_prepare(error->gt); |
1832 | if (!compress) { | |
1833 | kfree(error->gt); | |
1834 | kfree(error); | |
1835 | return ERR_PTR(-ENOMEM); | |
1836 | } | |
5a4c6f1b | 1837 | |
742379c0 CW |
1838 | gt_record_engines(error->gt, compress); |
1839 | ||
1840 | if (INTEL_INFO(i915)->has_gt_uc) | |
1841 | error->gt->uc = gt_record_uc(error->gt, compress); | |
3bdd4f84 | 1842 | |
742379c0 CW |
1843 | i915_vma_capture_finish(error->gt, compress); |
1844 | ||
1845 | error->simulated |= error->gt->simulated; | |
1846 | } | |
3bdd4f84 CW |
1847 | |
1848 | error->overlay = intel_overlay_capture_error_state(i915); | |
1849 | error->display = intel_display_capture_error_state(i915); | |
1850 | ||
5a4c6f1b CW |
1851 | return error; |
1852 | } | |
1853 | ||
742379c0 | 1854 | void i915_error_state_store(struct i915_gpu_coredump *error) |
1d762aad | 1855 | { |
742379c0 | 1856 | struct drm_i915_private *i915; |
53a4c6b2 | 1857 | static bool warned; |
1d762aad | 1858 | |
742379c0 | 1859 | if (IS_ERR_OR_NULL(error)) |
98a2f411 CW |
1860 | return; |
1861 | ||
742379c0 CW |
1862 | i915 = error->i915; |
1863 | dev_info(i915->drm.dev, "%s\n", error_msg(error)); | |
9777cca0 | 1864 | |
742379c0 CW |
1865 | if (error->simulated || |
1866 | cmpxchg(&i915->gpu_error.first_error, NULL, error)) | |
1d762aad | 1867 | return; |
1d762aad | 1868 | |
742379c0 | 1869 | i915_gpu_coredump_get(error); |
cb383002 | 1870 | |
a1e37b02 | 1871 | if (!xchg(&warned, true) && |
eafc4894 | 1872 | ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { |
88f8065c | 1873 | pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); |
ddae4d7a JN |
1874 | pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); |
1875 | pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); | |
88f8065c CW |
1876 | pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); |
1877 | pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); | |
1878 | pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", | |
1879 | i915->drm.primary->index); | |
cb383002 | 1880 | } |
84734a04 MK |
1881 | } |
1882 | ||
742379c0 CW |
1883 | /** |
1884 | * i915_capture_error_state - capture an error record for later analysis | |
1885 | * @i915: i915 device | |
1886 | * | |
1887 | * Should be called when an error is detected (either a hang or an error | |
1888 | * interrupt) to capture error state from the time of the error. Fills | |
1889 | * out a structure which becomes available in debugfs for user level tools | |
1890 | * to pick up. | |
1891 | */ | |
1892 | void i915_capture_error_state(struct drm_i915_private *i915) | |
1893 | { | |
1894 | struct i915_gpu_coredump *error; | |
1895 | ||
1896 | error = i915_gpu_coredump(i915); | |
1897 | if (IS_ERR(error)) { | |
1898 | cmpxchg(&i915->gpu_error.first_error, NULL, error); | |
1899 | return; | |
1900 | } | |
1901 | ||
1902 | i915_error_state_store(error); | |
1903 | i915_gpu_coredump_put(error); | |
1904 | } | |
1905 | ||
1906 | struct i915_gpu_coredump * | |
5a4c6f1b | 1907 | i915_first_error_state(struct drm_i915_private *i915) |
84734a04 | 1908 | { |
742379c0 | 1909 | struct i915_gpu_coredump *error; |
84734a04 | 1910 | |
5a4c6f1b CW |
1911 | spin_lock_irq(&i915->gpu_error.lock); |
1912 | error = i915->gpu_error.first_error; | |
e6154e4c | 1913 | if (!IS_ERR_OR_NULL(error)) |
742379c0 | 1914 | i915_gpu_coredump_get(error); |
5a4c6f1b | 1915 | spin_unlock_irq(&i915->gpu_error.lock); |
84734a04 | 1916 | |
5a4c6f1b | 1917 | return error; |
84734a04 MK |
1918 | } |
1919 | ||
5a4c6f1b | 1920 | void i915_reset_error_state(struct drm_i915_private *i915) |
84734a04 | 1921 | { |
742379c0 | 1922 | struct i915_gpu_coredump *error; |
84734a04 | 1923 | |
5a4c6f1b CW |
1924 | spin_lock_irq(&i915->gpu_error.lock); |
1925 | error = i915->gpu_error.first_error; | |
e6154e4c CW |
1926 | if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ |
1927 | i915->gpu_error.first_error = NULL; | |
5a4c6f1b | 1928 | spin_unlock_irq(&i915->gpu_error.lock); |
84734a04 | 1929 | |
e6154e4c | 1930 | if (!IS_ERR_OR_NULL(error)) |
742379c0 | 1931 | i915_gpu_coredump_put(error); |
fb6f0b64 CW |
1932 | } |
1933 | ||
1934 | void i915_disable_error_state(struct drm_i915_private *i915, int err) | |
1935 | { | |
1936 | spin_lock_irq(&i915->gpu_error.lock); | |
1937 | if (!i915->gpu_error.first_error) | |
1938 | i915->gpu_error.first_error = ERR_PTR(err); | |
1939 | spin_unlock_irq(&i915->gpu_error.lock); | |
84734a04 | 1940 | } |