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Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
e8861964 CW |
26 | #include <linux/irq_work.h> |
27 | #include <linux/prefetch.h> | |
e6017571 IM |
28 | #include <linux/sched.h> |
29 | #include <linux/sched/clock.h> | |
f361bf4a | 30 | #include <linux/sched/signal.h> |
fa545cbf | 31 | |
10be98a7 CW |
32 | #include "gem/i915_gem_context.h" |
33 | #include "gt/intel_context.h" | |
2871ea85 | 34 | #include "gt/intel_ring.h" |
3e7abf81 | 35 | #include "gt/intel_rps.h" |
10be98a7 | 36 | |
21950ee7 | 37 | #include "i915_active.h" |
696173b0 | 38 | #include "i915_drv.h" |
103b76ee | 39 | #include "i915_globals.h" |
a09d9a80 | 40 | #include "i915_trace.h" |
696173b0 | 41 | #include "intel_pm.h" |
05235c53 | 42 | |
e8861964 CW |
43 | struct execute_cb { |
44 | struct list_head link; | |
45 | struct irq_work work; | |
46 | struct i915_sw_fence *fence; | |
f71e01a7 CW |
47 | void (*hook)(struct i915_request *rq, struct dma_fence *signal); |
48 | struct i915_request *signal; | |
e8861964 CW |
49 | }; |
50 | ||
32eb6bcf | 51 | static struct i915_global_request { |
103b76ee | 52 | struct i915_global base; |
32eb6bcf | 53 | struct kmem_cache *slab_requests; |
e8861964 | 54 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
55 | } global; |
56 | ||
f54d1867 | 57 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 | 58 | { |
65c29dbb | 59 | return dev_name(to_request(fence)->i915->drm.dev); |
04769652 CW |
60 | } |
61 | ||
f54d1867 | 62 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 63 | { |
9f3ccd40 CW |
64 | const struct i915_gem_context *ctx; |
65 | ||
e61e0f51 CW |
66 | /* |
67 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
68 | * may be freed when the request is no longer in use by the GPU. |
69 | * We could extend the life of a context to beyond that of all | |
70 | * fences, possibly keeping the hw resource around indefinitely, | |
71 | * or we just give them a false name. Since | |
72 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
73 | * lie seems justifiable. | |
74 | */ | |
75 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
76 | return "signaled"; | |
77 | ||
6a8679c0 | 78 | ctx = i915_request_gem_context(to_request(fence)); |
9f3ccd40 CW |
79 | if (!ctx) |
80 | return "[" DRIVER_NAME "]"; | |
81 | ||
82 | return ctx->name; | |
04769652 CW |
83 | } |
84 | ||
f54d1867 | 85 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 86 | { |
e61e0f51 | 87 | return i915_request_completed(to_request(fence)); |
04769652 CW |
88 | } |
89 | ||
f54d1867 | 90 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 91 | { |
52c0fdb2 | 92 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
93 | } |
94 | ||
f54d1867 | 95 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 96 | bool interruptible, |
e95433c7 | 97 | signed long timeout) |
04769652 | 98 | { |
62eb3c24 CW |
99 | return i915_request_wait(to_request(fence), |
100 | interruptible | I915_WAIT_PRIORITY, | |
101 | timeout); | |
04769652 CW |
102 | } |
103 | ||
f54d1867 | 104 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 105 | { |
e61e0f51 | 106 | struct i915_request *rq = to_request(fence); |
04769652 | 107 | |
e61e0f51 CW |
108 | /* |
109 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
110 | * is immediately reused), mark the fences as being freed now. |
111 | * Otherwise the debugobjects for the fences are only marked as | |
112 | * freed when the slab cache itself is freed, and so we would get | |
113 | * caught trying to reuse dead objects. | |
114 | */ | |
e61e0f51 | 115 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 116 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 117 | |
32eb6bcf | 118 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
119 | } |
120 | ||
f54d1867 | 121 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
122 | .get_driver_name = i915_fence_get_driver_name, |
123 | .get_timeline_name = i915_fence_get_timeline_name, | |
124 | .enable_signaling = i915_fence_enable_signaling, | |
125 | .signaled = i915_fence_signaled, | |
126 | .wait = i915_fence_wait, | |
127 | .release = i915_fence_release, | |
04769652 CW |
128 | }; |
129 | ||
b87b6c0d CW |
130 | static void irq_execute_cb(struct irq_work *wrk) |
131 | { | |
132 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
133 | ||
134 | i915_sw_fence_complete(cb->fence); | |
135 | kmem_cache_free(global.slab_execute_cbs, cb); | |
136 | } | |
137 | ||
138 | static void irq_execute_cb_hook(struct irq_work *wrk) | |
139 | { | |
140 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
141 | ||
142 | cb->hook(container_of(cb->fence, struct i915_request, submit), | |
143 | &cb->signal->fence); | |
144 | i915_request_put(cb->signal); | |
145 | ||
146 | irq_execute_cb(wrk); | |
147 | } | |
148 | ||
149 | static void __notify_execute_cb(struct i915_request *rq) | |
150 | { | |
151 | struct execute_cb *cb; | |
152 | ||
153 | lockdep_assert_held(&rq->lock); | |
154 | ||
155 | if (list_empty(&rq->execute_cb)) | |
156 | return; | |
157 | ||
158 | list_for_each_entry(cb, &rq->execute_cb, link) | |
159 | irq_work_queue(&cb->work); | |
160 | ||
161 | /* | |
162 | * XXX Rollback on __i915_request_unsubmit() | |
163 | * | |
164 | * In the future, perhaps when we have an active time-slicing scheduler, | |
165 | * it will be interesting to unsubmit parallel execution and remove | |
166 | * busywaits from the GPU until their master is restarted. This is | |
167 | * quite hairy, we have to carefully rollback the fence and do a | |
168 | * preempt-to-idle cycle on the target engine, all the while the | |
169 | * master execute_cb may refire. | |
170 | */ | |
171 | INIT_LIST_HEAD(&rq->execute_cb); | |
172 | } | |
173 | ||
05235c53 | 174 | static inline void |
44c22f3f | 175 | remove_from_client(struct i915_request *request) |
05235c53 | 176 | { |
c8659efa | 177 | struct drm_i915_file_private *file_priv; |
05235c53 | 178 | |
77715906 | 179 | if (!READ_ONCE(request->file_priv)) |
05235c53 CW |
180 | return; |
181 | ||
77715906 CW |
182 | rcu_read_lock(); |
183 | file_priv = xchg(&request->file_priv, NULL); | |
184 | if (file_priv) { | |
185 | spin_lock(&file_priv->mm.lock); | |
c8659efa | 186 | list_del(&request->client_link); |
77715906 | 187 | spin_unlock(&file_priv->mm.lock); |
c8659efa | 188 | } |
77715906 | 189 | rcu_read_unlock(); |
05235c53 CW |
190 | } |
191 | ||
e61e0f51 | 192 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 193 | { |
e61e0f51 | 194 | struct i915_capture_list *capture; |
b0fd47ad | 195 | |
67a3acaa | 196 | capture = fetch_and_zero(&request->capture_list); |
b0fd47ad | 197 | while (capture) { |
e61e0f51 | 198 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
199 | |
200 | kfree(capture); | |
201 | capture = next; | |
202 | } | |
203 | } | |
204 | ||
89dd019a CW |
205 | static void __i915_request_fill(struct i915_request *rq, u8 val) |
206 | { | |
207 | void *vaddr = rq->ring->vaddr; | |
208 | u32 head; | |
209 | ||
210 | head = rq->infix; | |
211 | if (rq->postfix < head) { | |
212 | memset(vaddr + head, val, rq->ring->size - head); | |
213 | head = 0; | |
214 | } | |
215 | memset(vaddr + head, val, rq->postfix - head); | |
216 | } | |
217 | ||
37fa0de3 CW |
218 | static void remove_from_engine(struct i915_request *rq) |
219 | { | |
220 | struct intel_engine_cs *engine, *locked; | |
221 | ||
222 | /* | |
223 | * Virtual engines complicate acquiring the engine timeline lock, | |
224 | * as their rq->engine pointer is not stable until under that | |
225 | * engine lock. The simple ploy we use is to take the lock then | |
226 | * check that the rq still belongs to the newly locked engine. | |
227 | */ | |
228 | locked = READ_ONCE(rq->engine); | |
1dfffa00 | 229 | spin_lock_irq(&locked->active.lock); |
37fa0de3 CW |
230 | while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) { |
231 | spin_unlock(&locked->active.lock); | |
232 | spin_lock(&engine->active.lock); | |
233 | locked = engine; | |
234 | } | |
67a3acaa | 235 | list_del_init(&rq->sched.link); |
b4a9a149 CW |
236 | clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); |
237 | clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags); | |
1dfffa00 | 238 | spin_unlock_irq(&locked->active.lock); |
37fa0de3 CW |
239 | } |
240 | ||
66101975 | 241 | bool i915_request_retire(struct i915_request *rq) |
05235c53 | 242 | { |
9db0c5ca CW |
243 | if (!i915_request_completed(rq)) |
244 | return false; | |
d9b13c4d | 245 | |
639f2f24 | 246 | RQ_TRACE(rq, "\n"); |
4c7d62c6 | 247 | |
9db0c5ca CW |
248 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
249 | trace_i915_request_retire(rq); | |
80b204bc | 250 | |
e5dadff4 CW |
251 | /* |
252 | * We know the GPU must have read the request to have | |
253 | * sent us the seqno + interrupt, so use the position | |
254 | * of tail of the request to update the last known position | |
255 | * of the GPU head. | |
256 | * | |
257 | * Note this requires that we are always called in request | |
258 | * completion order. | |
259 | */ | |
d19d71fc CW |
260 | GEM_BUG_ON(!list_is_first(&rq->link, |
261 | &i915_request_timeline(rq)->requests)); | |
89dd019a CW |
262 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
263 | /* Poison before we release our space in the ring */ | |
264 | __i915_request_fill(rq, POISON_FREE); | |
e5dadff4 | 265 | rq->ring->head = rq->postfix; |
b0fd47ad | 266 | |
22b7a426 CW |
267 | /* |
268 | * We only loosely track inflight requests across preemption, | |
269 | * and so we may find ourselves attempting to retire a _completed_ | |
270 | * request that we have removed from the HW and put back on a run | |
271 | * queue. | |
272 | */ | |
37fa0de3 | 273 | remove_from_engine(rq); |
52e54209 | 274 | |
1dfffa00 | 275 | spin_lock_irq(&rq->lock); |
9db0c5ca CW |
276 | i915_request_mark_complete(rq); |
277 | if (!i915_request_signaled(rq)) | |
278 | dma_fence_signal_locked(&rq->fence); | |
279 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
280 | i915_request_cancel_breadcrumb(rq); | |
2a98f4e6 | 281 | if (i915_request_has_waitboost(rq)) { |
3e7abf81 AS |
282 | GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters)); |
283 | atomic_dec(&rq->engine->gt->rps.num_waiters); | |
9db0c5ca | 284 | } |
b87b6c0d CW |
285 | if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) { |
286 | set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); | |
287 | __notify_execute_cb(rq); | |
288 | } | |
289 | GEM_BUG_ON(!list_empty(&rq->execute_cb)); | |
1dfffa00 | 290 | spin_unlock_irq(&rq->lock); |
52d7f16e | 291 | |
44c22f3f | 292 | remove_from_client(rq); |
dff2a11b | 293 | __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */ |
9db0c5ca | 294 | |
9f3ccd40 CW |
295 | intel_context_exit(rq->context); |
296 | intel_context_unpin(rq->context); | |
75d0a7f3 | 297 | |
9db0c5ca CW |
298 | free_capture_list(rq); |
299 | i915_sched_node_fini(&rq->sched); | |
300 | i915_request_put(rq); | |
301 | ||
302 | return true; | |
05235c53 CW |
303 | } |
304 | ||
e61e0f51 | 305 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 306 | { |
d19d71fc | 307 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e61e0f51 | 308 | struct i915_request *tmp; |
05235c53 | 309 | |
639f2f24 | 310 | RQ_TRACE(rq, "\n"); |
b887d615 | 311 | |
e61e0f51 | 312 | GEM_BUG_ON(!i915_request_completed(rq)); |
4ffd6e0c | 313 | |
05235c53 | 314 | do { |
e5dadff4 | 315 | tmp = list_first_entry(&tl->requests, typeof(*tmp), link); |
9db0c5ca | 316 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
317 | } |
318 | ||
e8861964 | 319 | static int |
c81471f5 CW |
320 | __await_execution(struct i915_request *rq, |
321 | struct i915_request *signal, | |
322 | void (*hook)(struct i915_request *rq, | |
323 | struct dma_fence *signal), | |
324 | gfp_t gfp) | |
e8861964 CW |
325 | { |
326 | struct execute_cb *cb; | |
327 | ||
f71e01a7 CW |
328 | if (i915_request_is_active(signal)) { |
329 | if (hook) | |
330 | hook(rq, &signal->fence); | |
e8861964 | 331 | return 0; |
f71e01a7 | 332 | } |
e8861964 CW |
333 | |
334 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
335 | if (!cb) | |
336 | return -ENOMEM; | |
337 | ||
338 | cb->fence = &rq->submit; | |
339 | i915_sw_fence_await(cb->fence); | |
340 | init_irq_work(&cb->work, irq_execute_cb); | |
341 | ||
f71e01a7 CW |
342 | if (hook) { |
343 | cb->hook = hook; | |
344 | cb->signal = i915_request_get(signal); | |
345 | cb->work.func = irq_execute_cb_hook; | |
346 | } | |
347 | ||
e8861964 CW |
348 | spin_lock_irq(&signal->lock); |
349 | if (i915_request_is_active(signal)) { | |
f71e01a7 CW |
350 | if (hook) { |
351 | hook(rq, &signal->fence); | |
352 | i915_request_put(signal); | |
353 | } | |
e8861964 CW |
354 | i915_sw_fence_complete(cb->fence); |
355 | kmem_cache_free(global.slab_execute_cbs, cb); | |
356 | } else { | |
357 | list_add_tail(&cb->link, &signal->execute_cb); | |
358 | } | |
359 | spin_unlock_irq(&signal->lock); | |
360 | ||
c81471f5 CW |
361 | /* Copy across semaphore status as we need the same behaviour */ |
362 | rq->sched.flags |= signal->sched.flags; | |
e8861964 CW |
363 | return 0; |
364 | } | |
365 | ||
36e191f0 CW |
366 | static bool fatal_error(int error) |
367 | { | |
368 | switch (error) { | |
369 | case 0: /* not an error! */ | |
370 | case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ | |
371 | case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ | |
372 | return false; | |
373 | default: | |
374 | return true; | |
375 | } | |
376 | } | |
377 | ||
378 | void __i915_request_skip(struct i915_request *rq) | |
379 | { | |
380 | GEM_BUG_ON(!fatal_error(rq->fence.error)); | |
381 | ||
382 | if (rq->infix == rq->postfix) | |
383 | return; | |
384 | ||
385 | /* | |
386 | * As this request likely depends on state from the lost | |
387 | * context, clear out all the user operations leaving the | |
388 | * breadcrumb at the end (so we get the fence notifications). | |
389 | */ | |
390 | __i915_request_fill(rq, 0); | |
391 | rq->infix = rq->postfix; | |
392 | } | |
393 | ||
394 | void i915_request_set_error_once(struct i915_request *rq, int error) | |
395 | { | |
396 | int old; | |
397 | ||
398 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
399 | ||
400 | if (i915_request_signaled(rq)) | |
401 | return; | |
402 | ||
403 | old = READ_ONCE(rq->fence.error); | |
404 | do { | |
405 | if (fatal_error(old)) | |
406 | return; | |
407 | } while (!try_cmpxchg(&rq->fence.error, &old, error)); | |
408 | } | |
409 | ||
c0bb487d | 410 | bool __i915_request_submit(struct i915_request *request) |
5590af3e | 411 | { |
73cb9701 | 412 | struct intel_engine_cs *engine = request->engine; |
c0bb487d | 413 | bool result = false; |
5590af3e | 414 | |
639f2f24 | 415 | RQ_TRACE(request, "\n"); |
d9b13c4d | 416 | |
e60a870d | 417 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 418 | lockdep_assert_held(&engine->active.lock); |
e60a870d | 419 | |
c0bb487d CW |
420 | /* |
421 | * With the advent of preempt-to-busy, we frequently encounter | |
422 | * requests that we have unsubmitted from HW, but left running | |
423 | * until the next ack and so have completed in the meantime. On | |
424 | * resubmission of that completed request, we can skip | |
425 | * updating the payload, and execlists can even skip submitting | |
426 | * the request. | |
427 | * | |
428 | * We must remove the request from the caller's priority queue, | |
429 | * and the caller must only call us when the request is in their | |
430 | * priority queue, under the active.lock. This ensures that the | |
431 | * request has *not* yet been retired and we can safely move | |
432 | * the request into the engine->active.list where it will be | |
433 | * dropped upon retiring. (Otherwise if resubmit a *retired* | |
434 | * request, this would be a horrible use-after-free.) | |
435 | */ | |
436 | if (i915_request_completed(request)) | |
437 | goto xfer; | |
438 | ||
36e191f0 CW |
439 | if (unlikely(intel_context_is_banned(request->context))) |
440 | i915_request_set_error_once(request, -EIO); | |
441 | if (unlikely(fatal_error(request->fence.error))) | |
442 | __i915_request_skip(request); | |
d9e61b66 | 443 | |
ca6e56f6 CW |
444 | /* |
445 | * Are we using semaphores when the gpu is already saturated? | |
446 | * | |
447 | * Using semaphores incurs a cost in having the GPU poll a | |
448 | * memory location, busywaiting for it to change. The continual | |
449 | * memory reads can have a noticeable impact on the rest of the | |
450 | * system with the extra bus traffic, stalling the cpu as it too | |
451 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
452 | * | |
453 | * If we installed a semaphore on this request and we only submit | |
454 | * the request after the signaler completed, that indicates the | |
455 | * system is overloaded and using semaphores at this time only | |
456 | * increases the amount of work we are doing. If so, we disable | |
457 | * further use of semaphores until we are idle again, whence we | |
458 | * optimistically try again. | |
459 | */ | |
460 | if (request->sched.semaphores && | |
461 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 462 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 463 | |
c0bb487d CW |
464 | engine->emit_fini_breadcrumb(request, |
465 | request->ring->vaddr + request->postfix); | |
b5773a36 | 466 | |
c0bb487d CW |
467 | trace_i915_request_execute(request); |
468 | engine->serial++; | |
469 | result = true; | |
422d7df4 | 470 | |
c0bb487d CW |
471 | xfer: /* We may be recursing from the signal callback of another i915 fence */ |
472 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
473 | ||
672c368f | 474 | if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) { |
c0bb487d | 475 | list_move_tail(&request->sched.link, &engine->active.requests); |
672c368f CW |
476 | clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags); |
477 | } | |
b5773a36 | 478 | |
52c0fdb2 | 479 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) && |
0152b3b3 | 480 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) && |
52c0fdb2 | 481 | !i915_request_enable_breadcrumb(request)) |
54400257 | 482 | intel_engine_signal_breadcrumbs(engine); |
b5773a36 | 483 | |
e8861964 CW |
484 | __notify_execute_cb(request); |
485 | ||
f2d13290 CW |
486 | spin_unlock(&request->lock); |
487 | ||
c0bb487d | 488 | return result; |
d55ac5bf CW |
489 | } |
490 | ||
e61e0f51 | 491 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
492 | { |
493 | struct intel_engine_cs *engine = request->engine; | |
494 | unsigned long flags; | |
23902e49 | 495 | |
d55ac5bf | 496 | /* Will be called from irq-context when using foreign fences. */ |
422d7df4 | 497 | spin_lock_irqsave(&engine->active.lock, flags); |
d55ac5bf | 498 | |
e61e0f51 | 499 | __i915_request_submit(request); |
d55ac5bf | 500 | |
422d7df4 | 501 | spin_unlock_irqrestore(&engine->active.lock, flags); |
d55ac5bf CW |
502 | } |
503 | ||
e61e0f51 | 504 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 505 | { |
d6a2289d | 506 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 507 | |
639f2f24 | 508 | RQ_TRACE(request, "\n"); |
d9b13c4d | 509 | |
e60a870d | 510 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 511 | lockdep_assert_held(&engine->active.lock); |
48bc2a4a | 512 | |
e61e0f51 CW |
513 | /* |
514 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
515 | * is kept in seqno/ring order. |
516 | */ | |
80b204bc | 517 | |
d6a2289d CW |
518 | /* We may be recursing from the signal callback of another i915 fence */ |
519 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 520 | |
d6a2289d | 521 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 522 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 523 | |
52c0fdb2 CW |
524 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
525 | clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 526 | |
d6a2289d CW |
527 | spin_unlock(&request->lock); |
528 | ||
dba5a7f3 CW |
529 | /* We've already spun, don't charge on resubmitting. */ |
530 | if (request->sched.semaphores && i915_request_started(request)) { | |
531 | request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
532 | request->sched.semaphores = 0; | |
533 | } | |
534 | ||
e61e0f51 CW |
535 | /* |
536 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 537 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 538 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
539 | * should be quite adapt at finding that the request now has a new |
540 | * global_seqno to the one they went to sleep on. | |
541 | */ | |
542 | } | |
543 | ||
e61e0f51 | 544 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
545 | { |
546 | struct intel_engine_cs *engine = request->engine; | |
547 | unsigned long flags; | |
548 | ||
549 | /* Will be called from irq-context when using foreign fences. */ | |
422d7df4 | 550 | spin_lock_irqsave(&engine->active.lock, flags); |
d6a2289d | 551 | |
e61e0f51 | 552 | __i915_request_unsubmit(request); |
d6a2289d | 553 | |
422d7df4 | 554 | spin_unlock_irqrestore(&engine->active.lock, flags); |
5590af3e CW |
555 | } |
556 | ||
23902e49 | 557 | static int __i915_sw_fence_call |
d55ac5bf | 558 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 559 | { |
e61e0f51 | 560 | struct i915_request *request = |
48bc2a4a | 561 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
562 | |
563 | switch (state) { | |
564 | case FENCE_COMPLETE: | |
e61e0f51 | 565 | trace_i915_request_submit(request); |
ef468849 CW |
566 | |
567 | if (unlikely(fence->error)) | |
36e191f0 | 568 | i915_request_set_error_once(request, fence->error); |
ef468849 | 569 | |
af7a8ffa | 570 | /* |
e61e0f51 CW |
571 | * We need to serialize use of the submit_request() callback |
572 | * with its hotplugging performed during an emergency | |
573 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
574 | * critical section in order to force i915_gem_set_wedged() to | |
575 | * wait until the submit_request() is completed before | |
576 | * proceeding. | |
af7a8ffa DV |
577 | */ |
578 | rcu_read_lock(); | |
d55ac5bf | 579 | request->engine->submit_request(request); |
af7a8ffa | 580 | rcu_read_unlock(); |
48bc2a4a CW |
581 | break; |
582 | ||
583 | case FENCE_FREE: | |
e61e0f51 | 584 | i915_request_put(request); |
48bc2a4a CW |
585 | break; |
586 | } | |
587 | ||
23902e49 CW |
588 | return NOTIFY_DONE; |
589 | } | |
590 | ||
209df10b CW |
591 | static void irq_semaphore_cb(struct irq_work *wrk) |
592 | { | |
593 | struct i915_request *rq = | |
594 | container_of(wrk, typeof(*rq), semaphore_work); | |
595 | ||
596 | i915_schedule_bump_priority(rq, I915_PRIORITY_NOSEMAPHORE); | |
597 | i915_request_put(rq); | |
598 | } | |
599 | ||
b7404c7e CW |
600 | static int __i915_sw_fence_call |
601 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
602 | { | |
209df10b | 603 | struct i915_request *rq = container_of(fence, typeof(*rq), semaphore); |
b7404c7e CW |
604 | |
605 | switch (state) { | |
606 | case FENCE_COMPLETE: | |
209df10b CW |
607 | if (!(READ_ONCE(rq->sched.attr.priority) & I915_PRIORITY_NOSEMAPHORE)) { |
608 | i915_request_get(rq); | |
609 | init_irq_work(&rq->semaphore_work, irq_semaphore_cb); | |
610 | irq_work_queue(&rq->semaphore_work); | |
611 | } | |
b7404c7e CW |
612 | break; |
613 | ||
614 | case FENCE_FREE: | |
209df10b | 615 | i915_request_put(rq); |
b7404c7e CW |
616 | break; |
617 | } | |
618 | ||
619 | return NOTIFY_DONE; | |
620 | } | |
621 | ||
e5dadff4 | 622 | static void retire_requests(struct intel_timeline *tl) |
d22ba0cb CW |
623 | { |
624 | struct i915_request *rq, *rn; | |
625 | ||
e5dadff4 | 626 | list_for_each_entry_safe(rq, rn, &tl->requests, link) |
9db0c5ca | 627 | if (!i915_request_retire(rq)) |
d22ba0cb | 628 | break; |
d22ba0cb CW |
629 | } |
630 | ||
631 | static noinline struct i915_request * | |
e5dadff4 | 632 | request_alloc_slow(struct intel_timeline *tl, gfp_t gfp) |
d22ba0cb | 633 | { |
d22ba0cb CW |
634 | struct i915_request *rq; |
635 | ||
e5dadff4 | 636 | if (list_empty(&tl->requests)) |
d22ba0cb CW |
637 | goto out; |
638 | ||
2ccdf6a1 CW |
639 | if (!gfpflags_allow_blocking(gfp)) |
640 | goto out; | |
641 | ||
9db0c5ca | 642 | /* Move our oldest request to the slab-cache (if not in use!) */ |
e5dadff4 | 643 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
9db0c5ca CW |
644 | i915_request_retire(rq); |
645 | ||
646 | rq = kmem_cache_alloc(global.slab_requests, | |
647 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
648 | if (rq) | |
649 | return rq; | |
650 | ||
d22ba0cb | 651 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e5dadff4 | 652 | rq = list_last_entry(&tl->requests, typeof(*rq), link); |
d22ba0cb CW |
653 | cond_synchronize_rcu(rq->rcustate); |
654 | ||
655 | /* Retire our old requests in the hope that we free some */ | |
e5dadff4 | 656 | retire_requests(tl); |
d22ba0cb CW |
657 | |
658 | out: | |
2ccdf6a1 | 659 | return kmem_cache_alloc(global.slab_requests, gfp); |
d22ba0cb CW |
660 | } |
661 | ||
67a3acaa CW |
662 | static void __i915_request_ctor(void *arg) |
663 | { | |
664 | struct i915_request *rq = arg; | |
665 | ||
666 | spin_lock_init(&rq->lock); | |
667 | i915_sched_node_init(&rq->sched); | |
668 | i915_sw_fence_init(&rq->submit, submit_notify); | |
669 | i915_sw_fence_init(&rq->semaphore, semaphore_notify); | |
670 | ||
855e39e6 CW |
671 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0); |
672 | ||
67a3acaa CW |
673 | rq->file_priv = NULL; |
674 | rq->capture_list = NULL; | |
675 | ||
676 | INIT_LIST_HEAD(&rq->execute_cb); | |
677 | } | |
678 | ||
e61e0f51 | 679 | struct i915_request * |
2ccdf6a1 | 680 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 681 | { |
75d0a7f3 | 682 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
683 | struct i915_request *rq; |
684 | u32 seqno; | |
05235c53 CW |
685 | int ret; |
686 | ||
2ccdf6a1 | 687 | might_sleep_if(gfpflags_allow_blocking(gfp)); |
28176ef4 | 688 | |
2ccdf6a1 CW |
689 | /* Check that the caller provided an already pinned context */ |
690 | __intel_context_pin(ce); | |
9b5f4e5e | 691 | |
e61e0f51 CW |
692 | /* |
693 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
694 | * |
695 | * We use RCU to look up requests in flight. The lookups may | |
696 | * race with the request being allocated from the slab freelist. | |
697 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 698 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
699 | * we have to be very careful when overwriting the contents. During |
700 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 701 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
702 | * |
703 | * The reference count is incremented atomically. If it is zero, | |
704 | * the lookup knows the request is unallocated and complete. Otherwise, | |
705 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
706 | * with dma_fence_init(). This increment is safe for release as we |
707 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
708 | * request. |
709 | * | |
710 | * Before we increment the refcount, we chase the request->engine | |
711 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
712 | * that pointer to NULL and cause a crash during the lookup. If | |
713 | * we see the request is completed (based on the value of the | |
714 | * old engine and seqno), the lookup is complete and reports NULL. | |
715 | * If we decide the request is not completed (new engine or seqno), | |
716 | * then we grab a reference and double check that it is still the | |
717 | * active request - which it won't be and restart the lookup. | |
718 | * | |
719 | * Do not use kmem_cache_zalloc() here! | |
720 | */ | |
32eb6bcf | 721 | rq = kmem_cache_alloc(global.slab_requests, |
2ccdf6a1 | 722 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 723 | if (unlikely(!rq)) { |
e5dadff4 | 724 | rq = request_alloc_slow(tl, gfp); |
e61e0f51 | 725 | if (!rq) { |
31c70f97 CW |
726 | ret = -ENOMEM; |
727 | goto err_unreserve; | |
728 | } | |
28176ef4 | 729 | } |
05235c53 | 730 | |
2ccdf6a1 | 731 | rq->i915 = ce->engine->i915; |
9f3ccd40 | 732 | rq->context = ce; |
2ccdf6a1 | 733 | rq->engine = ce->engine; |
1fc44d9b | 734 | rq->ring = ce->ring; |
89b6d183 | 735 | rq->execution_mask = ce->engine->mask; |
d19d71fc | 736 | |
855e39e6 CW |
737 | kref_init(&rq->fence.refcount); |
738 | rq->fence.flags = 0; | |
739 | rq->fence.error = 0; | |
740 | INIT_LIST_HEAD(&rq->fence.cb_list); | |
741 | ||
742 | ret = intel_timeline_get_seqno(tl, rq, &seqno); | |
743 | if (ret) | |
744 | goto err_free; | |
745 | ||
746 | rq->fence.context = tl->fence_context; | |
747 | rq->fence.seqno = seqno; | |
748 | ||
85bedbf1 CW |
749 | RCU_INIT_POINTER(rq->timeline, tl); |
750 | RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline); | |
ebece753 | 751 | rq->hwsp_seqno = tl->hwsp_seqno; |
1eaa251b | 752 | GEM_BUG_ON(i915_request_completed(rq)); |
d19d71fc | 753 | |
ebece753 | 754 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ |
73cb9701 | 755 | |
48bc2a4a | 756 | /* We bump the ref for the fence chain */ |
67a3acaa CW |
757 | i915_sw_fence_reinit(&i915_request_get(rq)->submit); |
758 | i915_sw_fence_reinit(&i915_request_get(rq)->semaphore); | |
5590af3e | 759 | |
67a3acaa | 760 | i915_sched_node_reinit(&rq->sched); |
52e54209 | 761 | |
67a3acaa | 762 | /* No zalloc, everything must be cleared after use */ |
e61e0f51 | 763 | rq->batch = NULL; |
67a3acaa CW |
764 | GEM_BUG_ON(rq->file_priv); |
765 | GEM_BUG_ON(rq->capture_list); | |
766 | GEM_BUG_ON(!list_empty(&rq->execute_cb)); | |
2ccdf6a1 | 767 | |
05235c53 CW |
768 | /* |
769 | * Reserve space in the ring buffer for all the commands required to | |
770 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 771 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
772 | * to be redone if the request is not actually submitted straight |
773 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
774 | * |
775 | * Note that due to how we add reserved_space to intel_ring_begin() | |
776 | * we need to double our request to ensure that if we need to wrap | |
777 | * around inside i915_request_add() there is sufficient space at | |
778 | * the beginning of the ring as well. | |
05235c53 | 779 | */ |
2ccdf6a1 CW |
780 | rq->reserved_space = |
781 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 782 | |
2113184c CW |
783 | /* |
784 | * Record the position of the start of the request so that | |
d045446d CW |
785 | * should we detect the updated seqno part-way through the |
786 | * GPU processing the request, we never over-estimate the | |
787 | * position of the head. | |
788 | */ | |
e61e0f51 | 789 | rq->head = rq->ring->emit; |
d045446d | 790 | |
2ccdf6a1 | 791 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
792 | if (ret) |
793 | goto err_unwind; | |
2113184c | 794 | |
b3ee09a4 CW |
795 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
796 | ||
2ccdf6a1 | 797 | intel_context_mark_active(ce); |
d22d2d07 CW |
798 | list_add_tail_rcu(&rq->link, &tl->requests); |
799 | ||
e61e0f51 | 800 | return rq; |
05235c53 | 801 | |
b1c24a61 | 802 | err_unwind: |
1fc44d9b | 803 | ce->ring->emit = rq->head; |
b1c24a61 | 804 | |
1618bdb8 | 805 | /* Make sure we didn't add ourselves to external state before freeing */ |
0c7112a0 CW |
806 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
807 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 808 | |
ebece753 | 809 | err_free: |
32eb6bcf | 810 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 811 | err_unreserve: |
1fc44d9b | 812 | intel_context_unpin(ce); |
8e637178 | 813 | return ERR_PTR(ret); |
05235c53 CW |
814 | } |
815 | ||
2ccdf6a1 CW |
816 | struct i915_request * |
817 | i915_request_create(struct intel_context *ce) | |
818 | { | |
819 | struct i915_request *rq; | |
e5dadff4 | 820 | struct intel_timeline *tl; |
2ccdf6a1 | 821 | |
e5dadff4 CW |
822 | tl = intel_context_timeline_lock(ce); |
823 | if (IS_ERR(tl)) | |
824 | return ERR_CAST(tl); | |
2ccdf6a1 CW |
825 | |
826 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
e5dadff4 CW |
827 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
828 | if (!list_is_last(&rq->link, &tl->requests)) | |
2ccdf6a1 CW |
829 | i915_request_retire(rq); |
830 | ||
831 | intel_context_enter(ce); | |
832 | rq = __i915_request_create(ce, GFP_KERNEL); | |
833 | intel_context_exit(ce); /* active reference transferred to request */ | |
834 | if (IS_ERR(rq)) | |
835 | goto err_unlock; | |
836 | ||
837 | /* Check that we do not interrupt ourselves with a new request */ | |
e5dadff4 | 838 | rq->cookie = lockdep_pin_lock(&tl->mutex); |
2ccdf6a1 CW |
839 | |
840 | return rq; | |
841 | ||
842 | err_unlock: | |
e5dadff4 | 843 | intel_context_timeline_unlock(tl); |
2ccdf6a1 CW |
844 | return rq; |
845 | } | |
846 | ||
0d90ccb7 CW |
847 | static int |
848 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
849 | { | |
6a79d848 CW |
850 | struct dma_fence *fence; |
851 | int err; | |
0d90ccb7 | 852 | |
ab7a6902 CW |
853 | if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline)) |
854 | return 0; | |
6a79d848 | 855 | |
d22d2d07 CW |
856 | if (i915_request_started(signal)) |
857 | return 0; | |
858 | ||
9ddc8ec0 | 859 | fence = NULL; |
6a79d848 | 860 | rcu_read_lock(); |
9ddc8ec0 | 861 | spin_lock_irq(&signal->lock); |
d22d2d07 CW |
862 | do { |
863 | struct list_head *pos = READ_ONCE(signal->link.prev); | |
864 | struct i915_request *prev; | |
865 | ||
866 | /* Confirm signal has not been retired, the link is valid */ | |
867 | if (unlikely(i915_request_started(signal))) | |
868 | break; | |
869 | ||
870 | /* Is signal the earliest request on its timeline? */ | |
871 | if (pos == &rcu_dereference(signal->timeline)->requests) | |
872 | break; | |
0d90ccb7 | 873 | |
9ddc8ec0 CW |
874 | /* |
875 | * Peek at the request before us in the timeline. That | |
876 | * request will only be valid before it is retired, so | |
877 | * after acquiring a reference to it, confirm that it is | |
878 | * still part of the signaler's timeline. | |
879 | */ | |
d22d2d07 CW |
880 | prev = list_entry(pos, typeof(*prev), link); |
881 | if (!i915_request_get_rcu(prev)) | |
882 | break; | |
883 | ||
884 | /* After the strong barrier, confirm prev is still attached */ | |
885 | if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) { | |
886 | i915_request_put(prev); | |
887 | break; | |
6a79d848 | 888 | } |
d22d2d07 CW |
889 | |
890 | fence = &prev->fence; | |
891 | } while (0); | |
9ddc8ec0 CW |
892 | spin_unlock_irq(&signal->lock); |
893 | rcu_read_unlock(); | |
894 | if (!fence) | |
895 | return 0; | |
6a79d848 CW |
896 | |
897 | err = 0; | |
07e9c59d | 898 | if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence)) |
6a79d848 CW |
899 | err = i915_sw_fence_await_dma_fence(&rq->submit, |
900 | fence, 0, | |
901 | I915_FENCE_GFP); | |
902 | dma_fence_put(fence); | |
903 | ||
904 | return err; | |
0d90ccb7 CW |
905 | } |
906 | ||
ca6e56f6 CW |
907 | static intel_engine_mask_t |
908 | already_busywaiting(struct i915_request *rq) | |
909 | { | |
910 | /* | |
911 | * Polling a semaphore causes bus traffic, delaying other users of | |
912 | * both the GPU and CPU. We want to limit the impact on others, | |
913 | * while taking advantage of early submission to reduce GPU | |
914 | * latency. Therefore we restrict ourselves to not using more | |
915 | * than one semaphore from each source, and not using a semaphore | |
916 | * if we have detected the engine is saturated (i.e. would not be | |
917 | * submitted early and cause bus traffic reading an already passed | |
918 | * semaphore). | |
919 | * | |
920 | * See the are-we-too-late? check in __i915_request_submit(). | |
921 | */ | |
60900add | 922 | return rq->sched.semaphores | READ_ONCE(rq->engine->saturated); |
ca6e56f6 CW |
923 | } |
924 | ||
e8861964 | 925 | static int |
c81471f5 CW |
926 | __emit_semaphore_wait(struct i915_request *to, |
927 | struct i915_request *from, | |
928 | u32 seqno) | |
e8861964 | 929 | { |
c210e85b | 930 | const int has_token = INTEL_GEN(to->i915) >= 12; |
e8861964 | 931 | u32 hwsp_offset; |
c81471f5 | 932 | int len, err; |
e8861964 | 933 | u32 *cs; |
e8861964 | 934 | |
e8861964 CW |
935 | GEM_BUG_ON(INTEL_GEN(to->i915) < 8); |
936 | ||
c8a0e2ae | 937 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
c81471f5 CW |
938 | err = intel_timeline_read_hwsp(from, to, &hwsp_offset); |
939 | if (err) | |
940 | return err; | |
e8861964 | 941 | |
c210e85b CW |
942 | len = 4; |
943 | if (has_token) | |
944 | len += 2; | |
945 | ||
946 | cs = intel_ring_begin(to, len); | |
e8861964 CW |
947 | if (IS_ERR(cs)) |
948 | return PTR_ERR(cs); | |
949 | ||
950 | /* | |
951 | * Using greater-than-or-equal here means we have to worry | |
952 | * about seqno wraparound. To side step that issue, we swap | |
953 | * the timeline HWSP upon wrapping, so that everyone listening | |
954 | * for the old (pre-wrap) values do not see the much smaller | |
955 | * (post-wrap) values than they were expecting (and so wait | |
956 | * forever). | |
957 | */ | |
c210e85b CW |
958 | *cs++ = (MI_SEMAPHORE_WAIT | |
959 | MI_SEMAPHORE_GLOBAL_GTT | | |
960 | MI_SEMAPHORE_POLL | | |
961 | MI_SEMAPHORE_SAD_GTE_SDD) + | |
962 | has_token; | |
c81471f5 | 963 | *cs++ = seqno; |
e8861964 CW |
964 | *cs++ = hwsp_offset; |
965 | *cs++ = 0; | |
c210e85b CW |
966 | if (has_token) { |
967 | *cs++ = 0; | |
968 | *cs++ = MI_NOOP; | |
969 | } | |
e8861964 CW |
970 | |
971 | intel_ring_advance(to, cs); | |
c81471f5 CW |
972 | return 0; |
973 | } | |
974 | ||
975 | static int | |
976 | emit_semaphore_wait(struct i915_request *to, | |
977 | struct i915_request *from, | |
978 | gfp_t gfp) | |
979 | { | |
326611dd CW |
980 | const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask; |
981 | ||
f16ccb64 CW |
982 | if (!intel_context_use_semaphores(to->context)) |
983 | goto await_fence; | |
984 | ||
985 | if (!rcu_access_pointer(from->hwsp_cacheline)) | |
986 | goto await_fence; | |
987 | ||
c81471f5 | 988 | /* Just emit the first semaphore we see as request space is limited. */ |
326611dd | 989 | if (already_busywaiting(to) & mask) |
c81471f5 CW |
990 | goto await_fence; |
991 | ||
992 | if (i915_request_await_start(to, from) < 0) | |
993 | goto await_fence; | |
994 | ||
995 | /* Only submit our spinner after the signaler is running! */ | |
996 | if (__await_execution(to, from, NULL, gfp)) | |
997 | goto await_fence; | |
998 | ||
999 | if (__emit_semaphore_wait(to, from, from->fence.seqno)) | |
1000 | goto await_fence; | |
1001 | ||
326611dd | 1002 | to->sched.semaphores |= mask; |
7881e605 | 1003 | to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN; |
e8861964 | 1004 | return 0; |
6a79d848 CW |
1005 | |
1006 | await_fence: | |
1007 | return i915_sw_fence_await_dma_fence(&to->submit, | |
1008 | &from->fence, 0, | |
1009 | I915_FENCE_GFP); | |
e8861964 CW |
1010 | } |
1011 | ||
a2bc4695 | 1012 | static int |
e61e0f51 | 1013 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 1014 | { |
85e17f59 | 1015 | int ret; |
a2bc4695 CW |
1016 | |
1017 | GEM_BUG_ON(to == from); | |
ceae14bd | 1018 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 1019 | |
bc850943 CW |
1020 | if (i915_request_completed(from)) { |
1021 | i915_sw_fence_set_error_once(&to->submit, from->fence.error); | |
ade0b0c9 | 1022 | return 0; |
bc850943 | 1023 | } |
ade0b0c9 | 1024 | |
52e54209 | 1025 | if (to->engine->schedule) { |
a9d094dc CW |
1026 | ret = i915_sched_node_add_dependency(&to->sched, |
1027 | &from->sched, | |
1028 | I915_DEPENDENCY_EXTERNAL); | |
52e54209 CW |
1029 | if (ret < 0) |
1030 | return ret; | |
1031 | } | |
1032 | ||
0f100b70 | 1033 | if (to->engine == from->engine) |
73cb9701 CW |
1034 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, |
1035 | &from->submit, | |
2abe2f84 | 1036 | I915_FENCE_GFP); |
0f100b70 | 1037 | else |
f16ccb64 | 1038 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); |
17db337f CW |
1039 | if (ret < 0) |
1040 | return ret; | |
1041 | ||
1042 | if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) { | |
1043 | ret = i915_sw_fence_await_dma_fence(&to->semaphore, | |
1044 | &from->fence, 0, | |
1045 | I915_FENCE_GFP); | |
1046 | if (ret < 0) | |
1047 | return ret; | |
1048 | } | |
a2bc4695 | 1049 | |
17db337f | 1050 | return 0; |
a2bc4695 CW |
1051 | } |
1052 | ||
b52992c0 | 1053 | int |
e61e0f51 | 1054 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 1055 | { |
29ef3fa9 CW |
1056 | struct dma_fence **child = &fence; |
1057 | unsigned int nchild = 1; | |
b52992c0 | 1058 | int ret; |
b52992c0 | 1059 | |
e61e0f51 CW |
1060 | /* |
1061 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
1062 | * we should *not* decompose it into its individual fences. However, |
1063 | * we don't currently store which mode the fence-array is operating | |
1064 | * in. Fortunately, the only user of signal-on-any is private to | |
1065 | * amdgpu and we should not see any incoming fence-array from | |
1066 | * sync-file being in signal-on-any mode. | |
1067 | */ | |
29ef3fa9 CW |
1068 | if (dma_fence_is_array(fence)) { |
1069 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1070 | ||
1071 | child = array->fences; | |
1072 | nchild = array->num_fences; | |
1073 | GEM_BUG_ON(!nchild); | |
1074 | } | |
b52992c0 | 1075 | |
29ef3fa9 CW |
1076 | do { |
1077 | fence = *child++; | |
9e31c1fe CW |
1078 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1079 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
29ef3fa9 | 1080 | continue; |
9e31c1fe | 1081 | } |
b52992c0 | 1082 | |
ceae14bd CW |
1083 | /* |
1084 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 1085 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
1086 | * that requests are submitted in-order through each ring. |
1087 | */ | |
e61e0f51 | 1088 | if (fence->context == rq->fence.context) |
ceae14bd CW |
1089 | continue; |
1090 | ||
47979480 | 1091 | /* Squash repeated waits to the same timelines */ |
cc337560 | 1092 | if (fence->context && |
d19d71fc CW |
1093 | intel_timeline_sync_is_later(i915_request_timeline(rq), |
1094 | fence)) | |
47979480 CW |
1095 | continue; |
1096 | ||
29ef3fa9 | 1097 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 1098 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 1099 | else |
e61e0f51 | 1100 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
0f7dc620 | 1101 | fence->context ? I915_FENCE_TIMEOUT : 0, |
2abe2f84 | 1102 | I915_FENCE_GFP); |
b52992c0 CW |
1103 | if (ret < 0) |
1104 | return ret; | |
47979480 CW |
1105 | |
1106 | /* Record the latest fence used against each timeline */ | |
cc337560 | 1107 | if (fence->context) |
d19d71fc CW |
1108 | intel_timeline_sync_set(i915_request_timeline(rq), |
1109 | fence); | |
29ef3fa9 | 1110 | } while (--nchild); |
b52992c0 CW |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
c81471f5 CW |
1115 | static bool intel_timeline_sync_has_start(struct intel_timeline *tl, |
1116 | struct dma_fence *fence) | |
1117 | { | |
1118 | return __intel_timeline_sync_is_later(tl, | |
1119 | fence->context, | |
1120 | fence->seqno - 1); | |
1121 | } | |
1122 | ||
1123 | static int intel_timeline_sync_set_start(struct intel_timeline *tl, | |
1124 | const struct dma_fence *fence) | |
1125 | { | |
1126 | return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1); | |
1127 | } | |
1128 | ||
1129 | static int | |
1130 | __i915_request_await_execution(struct i915_request *to, | |
1131 | struct i915_request *from, | |
1132 | void (*hook)(struct i915_request *rq, | |
1133 | struct dma_fence *signal)) | |
1134 | { | |
1135 | int err; | |
1136 | ||
f16ccb64 CW |
1137 | GEM_BUG_ON(intel_context_is_barrier(from->context)); |
1138 | ||
c81471f5 CW |
1139 | /* Submit both requests at the same time */ |
1140 | err = __await_execution(to, from, hook, I915_FENCE_GFP); | |
1141 | if (err) | |
1142 | return err; | |
1143 | ||
1144 | /* Squash repeated depenendices to the same timelines */ | |
1145 | if (intel_timeline_sync_has_start(i915_request_timeline(to), | |
1146 | &from->fence)) | |
1147 | return 0; | |
1148 | ||
798fa870 CW |
1149 | /* |
1150 | * Wait until the start of this request. | |
1151 | * | |
1152 | * The execution cb fires when we submit the request to HW. But in | |
1153 | * many cases this may be long before the request itself is ready to | |
1154 | * run (consider that we submit 2 requests for the same context, where | |
1155 | * the request of interest is behind an indefinite spinner). So we hook | |
1156 | * up to both to reduce our queues and keep the execution lag minimised | |
1157 | * in the worst case, though we hope that the await_start is elided. | |
1158 | */ | |
1159 | err = i915_request_await_start(to, from); | |
c81471f5 CW |
1160 | if (err < 0) |
1161 | return err; | |
1162 | ||
798fa870 CW |
1163 | /* |
1164 | * Ensure both start together [after all semaphores in signal] | |
1165 | * | |
1166 | * Now that we are queued to the HW at roughly the same time (thanks | |
1167 | * to the execute cb) and are ready to run at roughly the same time | |
1168 | * (thanks to the await start), our signaler may still be indefinitely | |
1169 | * delayed by waiting on a semaphore from a remote engine. If our | |
1170 | * signaler depends on a semaphore, so indirectly do we, and we do not | |
1171 | * want to start our payload until our signaler also starts theirs. | |
1172 | * So we wait. | |
1173 | * | |
1174 | * However, there is also a second condition for which we need to wait | |
1175 | * for the precise start of the signaler. Consider that the signaler | |
1176 | * was submitted in a chain of requests following another context | |
1177 | * (with just an ordinary intra-engine fence dependency between the | |
1178 | * two). In this case the signaler is queued to HW, but not for | |
1179 | * immediate execution, and so we must wait until it reaches the | |
1180 | * active slot. | |
1181 | */ | |
1182 | if (intel_engine_has_semaphores(to->engine)) { | |
1183 | err = __emit_semaphore_wait(to, from, from->fence.seqno - 1); | |
1184 | if (err < 0) | |
1185 | return err; | |
1186 | } | |
1187 | ||
c81471f5 CW |
1188 | /* Couple the dependency tree for PI on this exposed to->fence */ |
1189 | if (to->engine->schedule) { | |
a9d094dc CW |
1190 | err = i915_sched_node_add_dependency(&to->sched, |
1191 | &from->sched, | |
1192 | I915_DEPENDENCY_WEAK); | |
c81471f5 CW |
1193 | if (err < 0) |
1194 | return err; | |
1195 | } | |
1196 | ||
1197 | return intel_timeline_sync_set_start(i915_request_timeline(to), | |
1198 | &from->fence); | |
1199 | } | |
1200 | ||
f71e01a7 CW |
1201 | int |
1202 | i915_request_await_execution(struct i915_request *rq, | |
1203 | struct dma_fence *fence, | |
1204 | void (*hook)(struct i915_request *rq, | |
1205 | struct dma_fence *signal)) | |
1206 | { | |
1207 | struct dma_fence **child = &fence; | |
1208 | unsigned int nchild = 1; | |
1209 | int ret; | |
1210 | ||
1211 | if (dma_fence_is_array(fence)) { | |
1212 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1213 | ||
1214 | /* XXX Error for signal-on-any fence arrays */ | |
1215 | ||
1216 | child = array->fences; | |
1217 | nchild = array->num_fences; | |
1218 | GEM_BUG_ON(!nchild); | |
1219 | } | |
1220 | ||
1221 | do { | |
1222 | fence = *child++; | |
9e31c1fe CW |
1223 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1224 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
f71e01a7 | 1225 | continue; |
9e31c1fe | 1226 | } |
f71e01a7 CW |
1227 | |
1228 | /* | |
1229 | * We don't squash repeated fence dependencies here as we | |
1230 | * want to run our callback in all cases. | |
1231 | */ | |
1232 | ||
1233 | if (dma_fence_is_i915(fence)) | |
1234 | ret = __i915_request_await_execution(rq, | |
1235 | to_request(fence), | |
c81471f5 | 1236 | hook); |
f71e01a7 CW |
1237 | else |
1238 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, | |
1239 | I915_FENCE_TIMEOUT, | |
1240 | GFP_KERNEL); | |
1241 | if (ret < 0) | |
1242 | return ret; | |
1243 | } while (--nchild); | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
a2bc4695 | 1248 | /** |
e61e0f51 | 1249 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1250 | * @to: request we are wishing to use |
1251 | * @obj: object which may be in use on another ring. | |
d8802126 | 1252 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1253 | * |
1254 | * This code is meant to abstract object synchronization with the GPU. | |
1255 | * Conceptually we serialise writes between engines inside the GPU. | |
1256 | * We only allow one engine to write into a buffer at any time, but | |
1257 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1258 | * | |
1259 | * - If there is an outstanding write request to the object, the new | |
1260 | * request must wait for it to complete (either CPU or in hw, requests | |
1261 | * on the same ring will be naturally ordered). | |
1262 | * | |
1263 | * - If we are a write request (pending_write_domain is set), the new | |
1264 | * request must wait for outstanding read requests to complete. | |
1265 | * | |
1266 | * Returns 0 if successful, else propagates up the lower layer error. | |
1267 | */ | |
1268 | int | |
e61e0f51 CW |
1269 | i915_request_await_object(struct i915_request *to, |
1270 | struct drm_i915_gem_object *obj, | |
1271 | bool write) | |
a2bc4695 | 1272 | { |
d07f0e59 CW |
1273 | struct dma_fence *excl; |
1274 | int ret = 0; | |
a2bc4695 CW |
1275 | |
1276 | if (write) { | |
d07f0e59 CW |
1277 | struct dma_fence **shared; |
1278 | unsigned int count, i; | |
1279 | ||
52791eee | 1280 | ret = dma_resv_get_fences_rcu(obj->base.resv, |
d07f0e59 CW |
1281 | &excl, &count, &shared); |
1282 | if (ret) | |
1283 | return ret; | |
1284 | ||
1285 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1286 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1287 | if (ret) |
1288 | break; | |
1289 | ||
1290 | dma_fence_put(shared[i]); | |
1291 | } | |
1292 | ||
1293 | for (; i < count; i++) | |
1294 | dma_fence_put(shared[i]); | |
1295 | kfree(shared); | |
a2bc4695 | 1296 | } else { |
52791eee | 1297 | excl = dma_resv_get_excl_rcu(obj->base.resv); |
a2bc4695 CW |
1298 | } |
1299 | ||
d07f0e59 CW |
1300 | if (excl) { |
1301 | if (ret == 0) | |
e61e0f51 | 1302 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1303 | |
d07f0e59 | 1304 | dma_fence_put(excl); |
a2bc4695 CW |
1305 | } |
1306 | ||
d07f0e59 | 1307 | return ret; |
a2bc4695 CW |
1308 | } |
1309 | ||
ea593dbb CW |
1310 | static struct i915_request * |
1311 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1312 | { | |
d19d71fc | 1313 | struct intel_timeline *timeline = i915_request_timeline(rq); |
ea593dbb CW |
1314 | struct i915_request *prev; |
1315 | ||
1316 | /* | |
1317 | * Dependency tracking and request ordering along the timeline | |
1318 | * is special cased so that we can eliminate redundant ordering | |
1319 | * operations while building the request (we know that the timeline | |
1320 | * itself is ordered, and here we guarantee it). | |
1321 | * | |
1322 | * As we know we will need to emit tracking along the timeline, | |
1323 | * we embed the hooks into our request struct -- at the cost of | |
1324 | * having to have specialised no-allocation interfaces (which will | |
1325 | * be beneficial elsewhere). | |
1326 | * | |
1327 | * A second benefit to open-coding i915_request_await_request is | |
1328 | * that we can apply a slight variant of the rules specialised | |
1329 | * for timelines that jump between engines (such as virtual engines). | |
1330 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1331 | * to prevent scheduling of the second request until the first is | |
1332 | * complete (to maximise our greedy late load balancing) and this | |
1333 | * precludes optimising to use semaphores serialisation of a single | |
1334 | * timeline across engines. | |
1335 | */ | |
b1e3177b CW |
1336 | prev = to_request(__i915_active_fence_set(&timeline->last_request, |
1337 | &rq->fence)); | |
ea593dbb | 1338 | if (prev && !i915_request_completed(prev)) { |
1eaa251b CW |
1339 | /* |
1340 | * The requests are supposed to be kept in order. However, | |
1341 | * we need to be wary in case the timeline->last_request | |
1342 | * is used as a barrier for external modification to this | |
1343 | * context. | |
1344 | */ | |
1345 | GEM_BUG_ON(prev->context == rq->context && | |
1346 | i915_seqno_passed(prev->fence.seqno, | |
1347 | rq->fence.seqno)); | |
1348 | ||
326611dd | 1349 | if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) |
ea593dbb CW |
1350 | i915_sw_fence_await_sw_fence(&rq->submit, |
1351 | &prev->submit, | |
1352 | &rq->submitq); | |
1353 | else | |
1354 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1355 | &prev->fence, | |
1356 | &rq->dmaq); | |
1357 | if (rq->engine->schedule) | |
1358 | __i915_sched_node_add_dependency(&rq->sched, | |
1359 | &prev->sched, | |
1360 | &rq->dep, | |
1361 | 0); | |
1362 | } | |
1363 | ||
2ccdf6a1 CW |
1364 | /* |
1365 | * Make sure that no request gazumped us - if it was allocated after | |
1366 | * our i915_request_alloc() and called __i915_request_add() before | |
1367 | * us, the timeline will hold its seqno which is later than ours. | |
1368 | */ | |
ea593dbb | 1369 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
ea593dbb CW |
1370 | |
1371 | return prev; | |
1372 | } | |
1373 | ||
05235c53 CW |
1374 | /* |
1375 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1376 | * request is not being tracked for completion but the work itself is | |
1377 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1378 | */ | |
2ccdf6a1 | 1379 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1380 | { |
2ccdf6a1 CW |
1381 | struct intel_engine_cs *engine = rq->engine; |
1382 | struct intel_ring *ring = rq->ring; | |
73dec95e | 1383 | u32 *cs; |
05235c53 | 1384 | |
639f2f24 | 1385 | RQ_TRACE(rq, "\n"); |
c781c978 | 1386 | |
05235c53 CW |
1387 | /* |
1388 | * To ensure that this call will not fail, space for its emissions | |
1389 | * should already have been reserved in the ring buffer. Let the ring | |
1390 | * know that it is time to use that space up. | |
1391 | */ | |
2ccdf6a1 CW |
1392 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1393 | rq->reserved_space = 0; | |
e5dadff4 | 1394 | rq->emitted_jiffies = jiffies; |
05235c53 | 1395 | |
8ac71d1d CW |
1396 | /* |
1397 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1398 | * should we detect the updated seqno part-way through the |
1399 | * GPU processing the request, we never over-estimate the | |
d045446d | 1400 | * position of the ring's HEAD. |
05235c53 | 1401 | */ |
2ccdf6a1 | 1402 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1403 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1404 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1405 | |
e5dadff4 | 1406 | return __i915_request_add_to_timeline(rq); |
a79ca656 CW |
1407 | } |
1408 | ||
1409 | void __i915_request_queue(struct i915_request *rq, | |
1410 | const struct i915_sched_attr *attr) | |
1411 | { | |
8ac71d1d CW |
1412 | /* |
1413 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1414 | * to adjust the existing execution schedule due to a high priority |
1415 | * request - i.e. we may want to preempt the current request in order | |
1416 | * to run a high priority dependency chain *before* we can execute this | |
1417 | * request. | |
1418 | * | |
1419 | * This is called before the request is ready to run so that we can | |
1420 | * decide whether to preempt the entire chain so that it is ready to | |
1421 | * run at the earliest possible convenience. | |
1422 | */ | |
a79ca656 CW |
1423 | if (attr && rq->engine->schedule) |
1424 | rq->engine->schedule(rq, attr); | |
209df10b | 1425 | i915_sw_fence_commit(&rq->semaphore); |
2ccdf6a1 | 1426 | i915_sw_fence_commit(&rq->submit); |
2ccdf6a1 CW |
1427 | } |
1428 | ||
1429 | void i915_request_add(struct i915_request *rq) | |
1430 | { | |
d19d71fc | 1431 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e6ba7648 | 1432 | struct i915_sched_attr attr = {}; |
61231f6b | 1433 | struct i915_gem_context *ctx; |
2ccdf6a1 | 1434 | |
e5dadff4 CW |
1435 | lockdep_assert_held(&tl->mutex); |
1436 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2ccdf6a1 CW |
1437 | |
1438 | trace_i915_request_add(rq); | |
61231f6b | 1439 | __i915_request_commit(rq); |
2ccdf6a1 | 1440 | |
61231f6b CW |
1441 | /* XXX placeholder for selftests */ |
1442 | rcu_read_lock(); | |
1443 | ctx = rcu_dereference(rq->context->gem_context); | |
1444 | if (ctx) | |
1445 | attr = ctx->sched; | |
1446 | rcu_read_unlock(); | |
e6ba7648 | 1447 | |
a79ca656 CW |
1448 | if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN)) |
1449 | attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
a79ca656 CW |
1450 | if (list_empty(&rq->sched.signalers_list)) |
1451 | attr.priority |= I915_PRIORITY_WAIT; | |
1452 | ||
62520e33 | 1453 | local_bh_disable(); |
a79ca656 | 1454 | __i915_request_queue(rq, &attr); |
62520e33 | 1455 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ |
a79ca656 | 1456 | |
e5dadff4 | 1457 | mutex_unlock(&tl->mutex); |
05235c53 CW |
1458 | } |
1459 | ||
062444bb | 1460 | static unsigned long local_clock_ns(unsigned int *cpu) |
05235c53 CW |
1461 | { |
1462 | unsigned long t; | |
1463 | ||
e61e0f51 CW |
1464 | /* |
1465 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1466 | * The result and subsequent calculations are also defined in the same |
1467 | * approximate microseconds units. The principal source of timing | |
1468 | * error here is from the simple truncation. | |
1469 | * | |
1470 | * Note that local_clock() is only defined wrt to the current CPU; | |
1471 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1472 | * blocking preemption for the entire busywait, we can detect the CPU | |
1473 | * switch and use that as indicator of system load and a reason to | |
1474 | * stop busywaiting, see busywait_stop(). | |
1475 | */ | |
1476 | *cpu = get_cpu(); | |
062444bb | 1477 | t = local_clock(); |
05235c53 CW |
1478 | put_cpu(); |
1479 | ||
1480 | return t; | |
1481 | } | |
1482 | ||
1483 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1484 | { | |
1485 | unsigned int this_cpu; | |
1486 | ||
062444bb | 1487 | if (time_after(local_clock_ns(&this_cpu), timeout)) |
05235c53 CW |
1488 | return true; |
1489 | ||
1490 | return this_cpu != cpu; | |
1491 | } | |
1492 | ||
062444bb | 1493 | static bool __i915_spin_request(const struct i915_request * const rq, int state) |
05235c53 | 1494 | { |
062444bb | 1495 | unsigned long timeout_ns; |
52c0fdb2 | 1496 | unsigned int cpu; |
b2f2f0fc CW |
1497 | |
1498 | /* | |
1499 | * Only wait for the request if we know it is likely to complete. | |
1500 | * | |
1501 | * We don't track the timestamps around requests, nor the average | |
1502 | * request length, so we do not have a good indicator that this | |
1503 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1504 | * order in which requests are executed by the context and so we can |
1505 | * tell if the request has been started. If the request is not even | |
1506 | * running yet, it is a fair assumption that it will not complete | |
1507 | * within our relatively short timeout. | |
b2f2f0fc | 1508 | */ |
52c0fdb2 | 1509 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1510 | return false; |
1511 | ||
e61e0f51 CW |
1512 | /* |
1513 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1514 | * rendering split between the CPU and GPU, the finite amount of time |
1515 | * required to set up the irq and wait upon it limits the response | |
1516 | * rate. By busywaiting on the request completion for a short while we | |
1517 | * can service the high frequency waits as quick as possible. However, | |
1518 | * if it is a slow request, we want to sleep as quickly as possible. | |
1519 | * The tradeoff between waiting and sleeping is roughly the time it | |
1520 | * takes to sleep on a request, on the order of a microsecond. | |
1521 | */ | |
1522 | ||
062444bb CW |
1523 | timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns); |
1524 | timeout_ns += local_clock_ns(&cpu); | |
05235c53 | 1525 | do { |
52c0fdb2 CW |
1526 | if (i915_request_completed(rq)) |
1527 | return true; | |
c33ed067 | 1528 | |
05235c53 CW |
1529 | if (signal_pending_state(state, current)) |
1530 | break; | |
1531 | ||
062444bb | 1532 | if (busywait_stop(timeout_ns, cpu)) |
05235c53 CW |
1533 | break; |
1534 | ||
f2f09a4c | 1535 | cpu_relax(); |
05235c53 CW |
1536 | } while (!need_resched()); |
1537 | ||
1538 | return false; | |
1539 | } | |
1540 | ||
52c0fdb2 CW |
1541 | struct request_wait { |
1542 | struct dma_fence_cb cb; | |
1543 | struct task_struct *tsk; | |
1544 | }; | |
1545 | ||
1546 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1547 | { | |
1548 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1549 | ||
1550 | wake_up_process(wait->tsk); | |
1551 | } | |
1552 | ||
05235c53 | 1553 | /** |
e532be89 | 1554 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1555 | * @rq: the request to wait upon |
ea746f36 | 1556 | * @flags: how to wait |
e95433c7 CW |
1557 | * @timeout: how long to wait in jiffies |
1558 | * | |
e532be89 | 1559 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1560 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1561 | * unbounded wait). | |
05235c53 | 1562 | * |
e95433c7 CW |
1563 | * Returns the remaining time (in jiffies) if the request completed, which may |
1564 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1565 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1566 | * pending before the request completes. | |
05235c53 | 1567 | */ |
e61e0f51 | 1568 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1569 | unsigned int flags, |
1570 | long timeout) | |
05235c53 | 1571 | { |
ea746f36 CW |
1572 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1573 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1574 | struct request_wait wait; |
05235c53 CW |
1575 | |
1576 | might_sleep(); | |
e95433c7 | 1577 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1578 | |
6e4e9708 | 1579 | if (dma_fence_is_signaled(&rq->fence)) |
e95433c7 | 1580 | return timeout; |
05235c53 | 1581 | |
e95433c7 CW |
1582 | if (!timeout) |
1583 | return -ETIME; | |
05235c53 | 1584 | |
e61e0f51 | 1585 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1586 | |
1587 | /* | |
1588 | * We must never wait on the GPU while holding a lock as we | |
1589 | * may need to perform a GPU reset. So while we don't need to | |
1590 | * serialise wait/reset with an explicit lock, we do want | |
1591 | * lockdep to detect potential dependency cycles. | |
1592 | */ | |
cb823ed9 | 1593 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 1594 | |
7ce99d24 CW |
1595 | /* |
1596 | * Optimistic spin before touching IRQs. | |
1597 | * | |
1598 | * We may use a rather large value here to offset the penalty of | |
1599 | * switching away from the active task. Frequently, the client will | |
1600 | * wait upon an old swapbuffer to throttle itself to remain within a | |
1601 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
1602 | * then it should not be waiting long at all, and a sleep now will incur | |
1603 | * extra scheduler latency in producing the next frame. To try to | |
1604 | * avoid adding the cost of enabling/disabling the interrupt to the | |
1605 | * short wait, we first spin to see if the request would have completed | |
1606 | * in the time taken to setup the interrupt. | |
1607 | * | |
1608 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
1609 | * scheduler latency of a context switch, ignoring the secondary | |
1610 | * impacts from a context switch such as cache eviction. | |
1611 | * | |
1612 | * The scheme used for low-latency IO is called "hybrid interrupt | |
1613 | * polling". The suggestion there is to sleep until just before you | |
1614 | * expect to be woken by the device interrupt and then poll for its | |
1615 | * completion. That requires having a good predictor for the request | |
1616 | * duration, which we currently lack. | |
1617 | */ | |
062444bb CW |
1618 | if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) && |
1619 | __i915_spin_request(rq, state)) { | |
6e4e9708 | 1620 | dma_fence_signal(&rq->fence); |
52c0fdb2 | 1621 | goto out; |
6e4e9708 | 1622 | } |
541ca6ed | 1623 | |
62eb3c24 CW |
1624 | /* |
1625 | * This client is about to stall waiting for the GPU. In many cases | |
1626 | * this is undesirable and limits the throughput of the system, as | |
1627 | * many clients cannot continue processing user input/output whilst | |
1628 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1629 | * to the GPU load and thus incurs additional latency for the client. | |
1630 | * We can circumvent that by promoting the GPU frequency to maximum | |
1631 | * before we sleep. This makes the GPU throttle up much more quickly | |
1632 | * (good for benchmarks and user experience, e.g. window animations), | |
1633 | * but at a cost of spending more power processing the workload | |
1634 | * (bad for battery). | |
1635 | */ | |
1636 | if (flags & I915_WAIT_PRIORITY) { | |
1637 | if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) | |
3e7abf81 | 1638 | intel_rps_boost(rq); |
52c0fdb2 | 1639 | i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT); |
62eb3c24 | 1640 | } |
4680816b | 1641 | |
52c0fdb2 CW |
1642 | wait.tsk = current; |
1643 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1644 | goto out; | |
4680816b | 1645 | |
52c0fdb2 CW |
1646 | for (;;) { |
1647 | set_current_state(state); | |
05235c53 | 1648 | |
ce94bef9 CW |
1649 | if (i915_request_completed(rq)) { |
1650 | dma_fence_signal(&rq->fence); | |
52c0fdb2 | 1651 | break; |
ce94bef9 | 1652 | } |
05235c53 | 1653 | |
602ddb41 CW |
1654 | intel_engine_flush_submission(rq->engine); |
1655 | ||
05235c53 | 1656 | if (signal_pending_state(state, current)) { |
e95433c7 | 1657 | timeout = -ERESTARTSYS; |
05235c53 CW |
1658 | break; |
1659 | } | |
1660 | ||
e95433c7 CW |
1661 | if (!timeout) { |
1662 | timeout = -ETIME; | |
05235c53 CW |
1663 | break; |
1664 | } | |
1665 | ||
e95433c7 | 1666 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1667 | } |
a49625f9 | 1668 | __set_current_state(TASK_RUNNING); |
05235c53 | 1669 | |
52c0fdb2 CW |
1670 | dma_fence_remove_callback(&rq->fence, &wait.cb); |
1671 | ||
1672 | out: | |
5facae4f | 1673 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_); |
52c0fdb2 | 1674 | trace_i915_request_wait_end(rq); |
e95433c7 | 1675 | return timeout; |
05235c53 | 1676 | } |
4b8de8e6 | 1677 | |
c835c550 CW |
1678 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1679 | #include "selftests/mock_request.c" | |
e61e0f51 | 1680 | #include "selftests/i915_request.c" |
c835c550 | 1681 | #endif |
32eb6bcf | 1682 | |
103b76ee CW |
1683 | static void i915_global_request_shrink(void) |
1684 | { | |
103b76ee CW |
1685 | kmem_cache_shrink(global.slab_execute_cbs); |
1686 | kmem_cache_shrink(global.slab_requests); | |
1687 | } | |
1688 | ||
1689 | static void i915_global_request_exit(void) | |
1690 | { | |
103b76ee CW |
1691 | kmem_cache_destroy(global.slab_execute_cbs); |
1692 | kmem_cache_destroy(global.slab_requests); | |
1693 | } | |
1694 | ||
1695 | static struct i915_global_request global = { { | |
1696 | .shrink = i915_global_request_shrink, | |
1697 | .exit = i915_global_request_exit, | |
1698 | } }; | |
1699 | ||
32eb6bcf CW |
1700 | int __init i915_global_request_init(void) |
1701 | { | |
67a3acaa CW |
1702 | global.slab_requests = |
1703 | kmem_cache_create("i915_request", | |
1704 | sizeof(struct i915_request), | |
1705 | __alignof__(struct i915_request), | |
1706 | SLAB_HWCACHE_ALIGN | | |
1707 | SLAB_RECLAIM_ACCOUNT | | |
1708 | SLAB_TYPESAFE_BY_RCU, | |
1709 | __i915_request_ctor); | |
32eb6bcf CW |
1710 | if (!global.slab_requests) |
1711 | return -ENOMEM; | |
1712 | ||
e8861964 CW |
1713 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
1714 | SLAB_HWCACHE_ALIGN | | |
1715 | SLAB_RECLAIM_ACCOUNT | | |
1716 | SLAB_TYPESAFE_BY_RCU); | |
1717 | if (!global.slab_execute_cbs) | |
1718 | goto err_requests; | |
1719 | ||
103b76ee | 1720 | i915_global_register(&global.base); |
32eb6bcf CW |
1721 | return 0; |
1722 | ||
1723 | err_requests: | |
1724 | kmem_cache_destroy(global.slab_requests); | |
1725 | return -ENOMEM; | |
1726 | } |