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fcfe0bdc MC |
1 | /* |
2 | * Copyright © 2018 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Madhav Chauhan <madhav.chauhan@intel.com> | |
25 | * Jani Nikula <jani.nikula@intel.com> | |
26 | */ | |
27 | ||
28 | #include "intel_dsi.h" | |
29 | ||
30 | static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) | |
31 | { | |
32 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
33 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
34 | enum port port; | |
35 | u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); | |
36 | u32 afe_clk_khz; /* 8X Clock */ | |
37 | u32 esc_clk_div_m; | |
38 | ||
39 | afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, | |
40 | intel_dsi->lane_count); | |
41 | ||
42 | esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); | |
43 | ||
44 | for_each_dsi_port(port, intel_dsi->ports) { | |
45 | I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), | |
46 | esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); | |
47 | POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); | |
48 | } | |
49 | ||
50 | for_each_dsi_port(port, intel_dsi->ports) { | |
51 | I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), | |
52 | esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); | |
53 | POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); | |
54 | } | |
55 | } | |
56 | ||
b1cb21a5 MC |
57 | static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) |
58 | { | |
59 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
60 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
61 | enum port port; | |
62 | u32 tmp; | |
63 | ||
64 | for_each_dsi_port(port, intel_dsi->ports) { | |
65 | tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); | |
66 | tmp |= COMBO_PHY_MODE_DSI; | |
67 | I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); | |
68 | } | |
69 | ||
70 | for_each_dsi_port(port, intel_dsi->ports) { | |
71 | intel_display_power_get(dev_priv, port == PORT_A ? | |
72 | POWER_DOMAIN_PORT_DDI_A_IO : | |
73 | POWER_DOMAIN_PORT_DDI_B_IO); | |
74 | } | |
75 | } | |
76 | ||
fcfe0bdc MC |
77 | static void __attribute__((unused)) |
78 | gen11_dsi_pre_enable(struct intel_encoder *encoder, | |
79 | const struct intel_crtc_state *pipe_config, | |
80 | const struct drm_connector_state *conn_state) | |
81 | { | |
b1cb21a5 MC |
82 | /* step2: enable IO power */ |
83 | gen11_dsi_enable_io_power(encoder); | |
84 | ||
fcfe0bdc MC |
85 | /* step3: enable DSI PLL */ |
86 | gen11_dsi_program_esc_clk_div(encoder); | |
87 | } |