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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
c6f95f27 | 30 | #include <drm/drm_atomic_helper.h> |
760285e7 | 31 | #include <drm/drm_crtc.h> |
760285e7 | 32 | #include <drm/drm_edid.h> |
fcd70cd3 | 33 | #include <drm/drm_probe_helper.h> |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
79e53945 JB |
36 | #include "i915_drv.h" |
37 | ||
e7dbb2f2 KP |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
44 | ADPA_CRT_HOTPLUG_ENABLE) | |
45 | ||
c9a1c4cd CW |
46 | struct intel_crt { |
47 | struct intel_encoder base; | |
637f44d2 AJ |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ | |
50 | struct intel_connector *connector; | |
e7dbb2f2 | 51 | bool force_hotplug_required; |
f0f59a00 | 52 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
53 | }; |
54 | ||
eebe6f0b | 55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 56 | { |
eebe6f0b | 57 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
58 | } |
59 | ||
eebe6f0b | 60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 61 | { |
eebe6f0b | 62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 SV |
63 | } |
64 | ||
6102a8ee VS |
65 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
66 | i915_reg_t adpa_reg, enum pipe *pipe) | |
67 | { | |
68 | u32 val; | |
69 | ||
70 | val = I915_READ(adpa_reg); | |
71 | ||
72 | /* asserts want to know the pipe even if the port is disabled */ | |
73 | if (HAS_PCH_CPT(dev_priv)) | |
74 | *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; | |
75 | else | |
76 | *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; | |
77 | ||
78 | return val & ADPA_DAC_ENABLE; | |
79 | } | |
80 | ||
e403fc94 SV |
81 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
82 | enum pipe *pipe) | |
79e53945 | 83 | { |
6102a8ee | 84 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e403fc94 | 85 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
0e6e0be4 | 86 | intel_wakeref_t wakeref; |
1c8fdda1 | 87 | bool ret; |
e403fc94 | 88 | |
0e6e0be4 CW |
89 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
90 | encoder->power_domain); | |
91 | if (!wakeref) | |
6d129bea ID |
92 | return false; |
93 | ||
6102a8ee | 94 | ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); |
e403fc94 | 95 | |
0e6e0be4 | 96 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
1c8fdda1 ID |
97 | |
98 | return ret; | |
e403fc94 SV |
99 | } |
100 | ||
6801c18c | 101 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 102 | { |
fac5e23e | 103 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
104 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
105 | u32 tmp, flags = 0; | |
106 | ||
107 | tmp = I915_READ(crt->adpa_reg); | |
108 | ||
109 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
110 | flags |= DRM_MODE_FLAG_PHSYNC; | |
111 | else | |
112 | flags |= DRM_MODE_FLAG_NHSYNC; | |
113 | ||
114 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
115 | flags |= DRM_MODE_FLAG_PVSYNC; | |
116 | else | |
117 | flags |= DRM_MODE_FLAG_NVSYNC; | |
118 | ||
6801c18c VS |
119 | return flags; |
120 | } | |
121 | ||
122 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 123 | struct intel_crtc_state *pipe_config) |
6801c18c | 124 | { |
e1214b95 VS |
125 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
126 | ||
2d112de7 | 127 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 128 | |
e3b247da | 129 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
130 | } |
131 | ||
6801c18c | 132 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 133 | struct intel_crtc_state *pipe_config) |
6801c18c | 134 | { |
8802e5b6 VS |
135 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
136 | ||
6801c18c VS |
137 | intel_ddi_get_config(encoder, pipe_config); |
138 | ||
2d112de7 | 139 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
140 | DRM_MODE_FLAG_NHSYNC | |
141 | DRM_MODE_FLAG_PVSYNC | | |
142 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 143 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
8802e5b6 VS |
144 | |
145 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); | |
6801c18c VS |
146 | } |
147 | ||
b2cabb0e SV |
148 | /* Note: The caller is required to filter out dpms modes not supported by the |
149 | * platform. */ | |
225cc348 | 150 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
5f88a9c6 | 151 | const struct intel_crtc_state *crtc_state, |
225cc348 | 152 | int mode) |
df0323c4 | 153 | { |
66478475 | 154 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b2cabb0e | 155 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225cc348 ML |
156 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
157 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; | |
894ed1ec SV |
158 | u32 adpa; |
159 | ||
66478475 | 160 | if (INTEL_GEN(dev_priv) >= 5) |
894ed1ec SV |
161 | adpa = ADPA_HOTPLUG_BITS; |
162 | else | |
163 | adpa = 0; | |
df0323c4 | 164 | |
894ed1ec SV |
165 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
166 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
167 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
168 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
169 | ||
170 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
6e266956 | 171 | if (HAS_PCH_LPT(dev_priv)) |
894ed1ec | 172 | ; /* Those bits don't exist here */ |
6e266956 | 173 | else if (HAS_PCH_CPT(dev_priv)) |
6102a8ee | 174 | adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); |
894ed1ec | 175 | else |
6102a8ee | 176 | adpa |= ADPA_PIPE_SEL(crtc->pipe); |
894ed1ec | 177 | |
6e266956 | 178 | if (!HAS_PCH_SPLIT(dev_priv)) |
894ed1ec | 179 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
79e53945 | 180 | |
0206e353 | 181 | switch (mode) { |
79e53945 | 182 | case DRM_MODE_DPMS_ON: |
894ed1ec | 183 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
184 | break; |
185 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 186 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
187 | break; |
188 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 189 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
190 | break; |
191 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 192 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
193 | break; |
194 | } | |
195 | ||
894ed1ec | 196 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 197 | } |
2c07245f | 198 | |
fd6bbda9 | 199 | static void intel_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
200 | const struct intel_crtc_state *old_crtc_state, |
201 | const struct drm_connector_state *old_conn_state) | |
637f44d2 | 202 | { |
225cc348 | 203 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
204 | } |
205 | ||
fd6bbda9 | 206 | static void pch_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
207 | const struct intel_crtc_state *old_crtc_state, |
208 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
209 | { |
210 | } | |
211 | ||
fd6bbda9 | 212 | static void pch_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
213 | const struct intel_crtc_state *old_crtc_state, |
214 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 | 215 | { |
fd6bbda9 | 216 | intel_disable_crt(encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 217 | } |
abfdc1e3 | 218 | |
3daa3cee JN |
219 | static void hsw_disable_crt(struct intel_encoder *encoder, |
220 | const struct intel_crtc_state *old_crtc_state, | |
221 | const struct drm_connector_state *old_conn_state) | |
222 | { | |
c249f1f4 | 223 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3daa3cee | 224 | |
c249f1f4 | 225 | WARN_ON(!old_crtc_state->has_pch_encoder); |
3daa3cee JN |
226 | |
227 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
228 | } | |
229 | ||
b7076546 | 230 | static void hsw_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
231 | const struct intel_crtc_state *old_crtc_state, |
232 | const struct drm_connector_state *old_conn_state) | |
b7076546 ML |
233 | { |
234 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
235 | ||
afb2c443 ID |
236 | intel_ddi_disable_pipe_clock(old_crtc_state); |
237 | ||
b7076546 ML |
238 | pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); |
239 | ||
240 | lpt_disable_pch_transcoder(dev_priv); | |
241 | lpt_disable_iclkip(dev_priv); | |
242 | ||
243 | intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); | |
3daa3cee JN |
244 | |
245 | WARN_ON(!old_crtc_state->has_pch_encoder); | |
246 | ||
247 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
b7076546 ML |
248 | } |
249 | ||
51c4fa69 | 250 | static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 251 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
252 | const struct drm_connector_state *conn_state) |
253 | { | |
c249f1f4 | 254 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51c4fa69 | 255 | |
c249f1f4 | 256 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
257 | |
258 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
259 | } | |
260 | ||
261 | static void hsw_pre_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 262 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
263 | const struct drm_connector_state *conn_state) |
264 | { | |
c249f1f4 VS |
265 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
266 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
267 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 268 | |
c249f1f4 | 269 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
270 | |
271 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
27d81c28 | 272 | |
c249f1f4 | 273 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
afb2c443 ID |
274 | |
275 | intel_ddi_enable_pipe_clock(crtc_state); | |
51c4fa69 JN |
276 | } |
277 | ||
278 | static void hsw_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 279 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
280 | const struct drm_connector_state *conn_state) |
281 | { | |
c249f1f4 VS |
282 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
283 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
284 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 285 | |
c249f1f4 | 286 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 | 287 | |
c249f1f4 | 288 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
51c4fa69 JN |
289 | |
290 | intel_wait_for_vblank(dev_priv, pipe); | |
291 | intel_wait_for_vblank(dev_priv, pipe); | |
292 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
293 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
294 | } | |
295 | ||
fd6bbda9 | 296 | static void intel_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 297 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 298 | const struct drm_connector_state *conn_state) |
637f44d2 | 299 | { |
c249f1f4 | 300 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
301 | } |
302 | ||
c19de8eb DL |
303 | static enum drm_mode_status |
304 | intel_crt_mode_valid(struct drm_connector *connector, | |
305 | struct drm_display_mode *mode) | |
79e53945 | 306 | { |
6bcdcd9e | 307 | struct drm_device *dev = connector->dev; |
6e266956 TU |
308 | struct drm_i915_private *dev_priv = to_i915(dev); |
309 | int max_dotclk = dev_priv->max_dotclk_freq; | |
debded84 | 310 | int max_clock; |
6bcdcd9e | 311 | |
e4dd27aa VS |
312 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
313 | return MODE_NO_DBLESCAN; | |
314 | ||
6bcdcd9e ZY |
315 | if (mode->clock < 25000) |
316 | return MODE_CLOCK_LOW; | |
317 | ||
6e266956 | 318 | if (HAS_PCH_LPT(dev_priv)) |
debded84 | 319 | max_clock = 180000; |
11a914c2 | 320 | else if (IS_VALLEYVIEW(dev_priv)) |
debded84 VS |
321 | /* |
322 | * 270 MHz due to current DPLL limits, | |
323 | * DAC limit supposedly 355 MHz. | |
324 | */ | |
325 | max_clock = 270000; | |
f3ce44a0 | 326 | else if (IS_GEN_RANGE(dev_priv, 3, 4)) |
6bcdcd9e | 327 | max_clock = 400000; |
debded84 VS |
328 | else |
329 | max_clock = 350000; | |
6bcdcd9e ZY |
330 | if (mode->clock > max_clock) |
331 | return MODE_CLOCK_HIGH; | |
79e53945 | 332 | |
f8700b34 MK |
333 | if (mode->clock > max_dotclk) |
334 | return MODE_CLOCK_HIGH; | |
335 | ||
d4b1931c | 336 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
6e266956 | 337 | if (HAS_PCH_LPT(dev_priv) && |
d4b1931c PZ |
338 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
339 | return MODE_CLOCK_HIGH; | |
340 | ||
ad193bc6 VS |
341 | /* HSW/BDW FDI limited to 4k */ |
342 | if (mode->hdisplay > 4096) | |
343 | return MODE_H_ILLEGAL; | |
344 | ||
79e53945 JB |
345 | return MODE_OK; |
346 | } | |
347 | ||
204474a6 LP |
348 | static int intel_crt_compute_config(struct intel_encoder *encoder, |
349 | struct intel_crtc_state *pipe_config, | |
350 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 351 | { |
e4dd27aa VS |
352 | struct drm_display_mode *adjusted_mode = |
353 | &pipe_config->base.adjusted_mode; | |
354 | ||
355 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 356 | return -EINVAL; |
e4dd27aa | 357 | |
d9facae6 | 358 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
204474a6 LP |
359 | |
360 | return 0; | |
2f26cdc0 JN |
361 | } |
362 | ||
204474a6 LP |
363 | static int pch_crt_compute_config(struct intel_encoder *encoder, |
364 | struct intel_crtc_state *pipe_config, | |
365 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 366 | { |
e4dd27aa VS |
367 | struct drm_display_mode *adjusted_mode = |
368 | &pipe_config->base.adjusted_mode; | |
369 | ||
370 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 371 | return -EINVAL; |
e4dd27aa | 372 | |
2f26cdc0 | 373 | pipe_config->has_pch_encoder = true; |
d9facae6 | 374 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
2f26cdc0 | 375 | |
204474a6 | 376 | return 0; |
2f26cdc0 JN |
377 | } |
378 | ||
204474a6 LP |
379 | static int hsw_crt_compute_config(struct intel_encoder *encoder, |
380 | struct intel_crtc_state *pipe_config, | |
381 | struct drm_connector_state *conn_state) | |
79e53945 | 382 | { |
4f8036a2 | 383 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e4dd27aa VS |
384 | struct drm_display_mode *adjusted_mode = |
385 | &pipe_config->base.adjusted_mode; | |
386 | ||
387 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 388 | return -EINVAL; |
5bfe2ac0 | 389 | |
ad193bc6 VS |
390 | /* HSW/BDW FDI limited to 4k */ |
391 | if (adjusted_mode->crtc_hdisplay > 4096 || | |
392 | adjusted_mode->crtc_hblank_start > 4096) | |
204474a6 | 393 | return -EINVAL; |
ad193bc6 | 394 | |
2f26cdc0 | 395 | pipe_config->has_pch_encoder = true; |
d9facae6 | 396 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
5bfe2ac0 | 397 | |
2a7aceec | 398 | /* LPT FDI RX only supports 8bpc. */ |
4f8036a2 | 399 | if (HAS_PCH_LPT(dev_priv)) { |
f58a1acc SV |
400 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
401 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | |
204474a6 | 402 | return -EINVAL; |
f58a1acc SV |
403 | } |
404 | ||
2a7aceec | 405 | pipe_config->pipe_bpp = 24; |
f58a1acc | 406 | } |
2a7aceec | 407 | |
8f7abfd8 | 408 | /* FDI must always be 2.7 GHz */ |
2f26cdc0 | 409 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 410 | |
204474a6 | 411 | return 0; |
79e53945 JB |
412 | } |
413 | ||
f2b115e6 | 414 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
415 | { |
416 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 417 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 418 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 419 | u32 adpa; |
2c07245f ZW |
420 | bool ret; |
421 | ||
e7dbb2f2 KP |
422 | /* The first time through, trigger an explicit detection cycle */ |
423 | if (crt->force_hotplug_required) { | |
6e266956 | 424 | bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); |
e7dbb2f2 | 425 | u32 save_adpa; |
67941da2 | 426 | |
e7dbb2f2 KP |
427 | crt->force_hotplug_required = 0; |
428 | ||
ca54b810 | 429 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
430 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
431 | ||
432 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
433 | if (turn_off_dac) | |
434 | adpa &= ~ADPA_DAC_ENABLE; | |
435 | ||
ca54b810 | 436 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 437 | |
e1672d1c CW |
438 | if (intel_wait_for_register(dev_priv, |
439 | crt->adpa_reg, | |
440 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
441 | 1000)) | |
e7dbb2f2 KP |
442 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
443 | ||
444 | if (turn_off_dac) { | |
ca54b810 VS |
445 | I915_WRITE(crt->adpa_reg, save_adpa); |
446 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 447 | } |
a4a6b901 ZW |
448 | } |
449 | ||
2c07245f | 450 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 451 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 452 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
453 | ret = true; |
454 | else | |
455 | ret = false; | |
e7dbb2f2 | 456 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 457 | |
2c07245f | 458 | return ret; |
79e53945 JB |
459 | } |
460 | ||
7d2c24e8 JB |
461 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
462 | { | |
463 | struct drm_device *dev = connector->dev; | |
ca54b810 | 464 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 465 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 466 | bool reenable_hpd; |
7d2c24e8 JB |
467 | u32 adpa; |
468 | bool ret; | |
469 | u32 save_adpa; | |
470 | ||
b236d7c8 L |
471 | /* |
472 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
473 | * get us stuck in a loop if we're polling: | |
474 | * - We enable power wells and reset the ADPA | |
475 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
476 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
477 | * - output_poll_exec shuts off the ADPA, unlocks | |
478 | * dev->mode_config.mutex | |
479 | * - HPD handler runs, resets ADPA and brings us back to the start | |
480 | * | |
481 | * Just disable HPD interrupts here to prevent this | |
482 | */ | |
483 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
484 | ||
ca54b810 | 485 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
486 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
487 | ||
488 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
489 | ||
ca54b810 | 490 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 491 | |
a522ae4b CW |
492 | if (intel_wait_for_register(dev_priv, |
493 | crt->adpa_reg, | |
494 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
495 | 1000)) { | |
7d2c24e8 | 496 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
ca54b810 | 497 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
498 | } |
499 | ||
500 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 501 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
502 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
503 | ret = true; | |
504 | else | |
505 | ret = false; | |
506 | ||
507 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
508 | ||
b236d7c8 L |
509 | if (reenable_hpd) |
510 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
511 | ||
7d2c24e8 JB |
512 | return ret; |
513 | } | |
514 | ||
79e53945 JB |
515 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
516 | { | |
517 | struct drm_device *dev = connector->dev; | |
fac5e23e | 518 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 519 | u32 stat; |
7a772c49 | 520 | bool ret = false; |
771cb081 | 521 | int i, tries = 0; |
2c07245f | 522 | |
6e266956 | 523 | if (HAS_PCH_SPLIT(dev_priv)) |
f2b115e6 | 524 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 525 | |
11a914c2 | 526 | if (IS_VALLEYVIEW(dev_priv)) |
7d2c24e8 JB |
527 | return valleyview_crt_detect_hotplug(connector); |
528 | ||
771cb081 ZY |
529 | /* |
530 | * On 4 series desktop, CRT detect sequence need to be done twice | |
531 | * to get a reliable result. | |
532 | */ | |
79e53945 | 533 | |
1c0f1b3d | 534 | if (IS_G45(dev_priv)) |
771cb081 ZY |
535 | tries = 2; |
536 | else | |
537 | tries = 1; | |
771cb081 | 538 | |
771cb081 | 539 | for (i = 0; i < tries ; i++) { |
771cb081 | 540 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
541 | i915_hotplug_interrupt_update(dev_priv, |
542 | CRT_HOTPLUG_FORCE_DETECT, | |
543 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 544 | /* wait for FORCE_DETECT to go off */ |
fd3790d4 CW |
545 | if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, |
546 | CRT_HOTPLUG_FORCE_DETECT, 0, | |
547 | 1000)) | |
79077319 | 548 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 549 | } |
79e53945 | 550 | |
7a772c49 AJ |
551 | stat = I915_READ(PORT_HOTPLUG_STAT); |
552 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
553 | ret = true; | |
554 | ||
555 | /* clear the interrupt we just generated, if any */ | |
556 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 557 | |
0706f17c | 558 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
559 | |
560 | return ret; | |
79e53945 JB |
561 | } |
562 | ||
f1a2f5b7 JN |
563 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
564 | struct i2c_adapter *i2c) | |
565 | { | |
566 | struct edid *edid; | |
567 | ||
568 | edid = drm_get_edid(connector, i2c); | |
569 | ||
570 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
571 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
572 | intel_gmbus_force_bit(i2c, true); | |
573 | edid = drm_get_edid(connector, i2c); | |
574 | intel_gmbus_force_bit(i2c, false); | |
575 | } | |
576 | ||
577 | return edid; | |
578 | } | |
579 | ||
580 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
581 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
582 | struct i2c_adapter *adapter) | |
583 | { | |
584 | struct edid *edid; | |
ebda95a9 | 585 | int ret; |
f1a2f5b7 JN |
586 | |
587 | edid = intel_crt_get_edid(connector, adapter); | |
588 | if (!edid) | |
589 | return 0; | |
590 | ||
ebda95a9 JN |
591 | ret = intel_connector_update_modes(connector, edid); |
592 | kfree(edid); | |
593 | ||
594 | return ret; | |
f1a2f5b7 JN |
595 | } |
596 | ||
f5afcd3d | 597 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 598 | { |
f5afcd3d | 599 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 600 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
a2bd1f54 SV |
601 | struct edid *edid; |
602 | struct i2c_adapter *i2c; | |
c96b63a6 | 603 | bool ret = false; |
79e53945 | 604 | |
a2bd1f54 | 605 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 606 | |
41aa3448 | 607 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 608 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 SV |
609 | |
610 | if (edid) { | |
611 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 612 | |
f5afcd3d DM |
613 | /* |
614 | * This may be a DVI-I connector with a shared DDC | |
615 | * link between analog and digital outputs, so we | |
616 | * have to check the EDID input spec of the attached device. | |
617 | */ | |
f5afcd3d DM |
618 | if (!is_digital) { |
619 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
c96b63a6 ACO |
620 | ret = true; |
621 | } else { | |
622 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
f5afcd3d | 623 | } |
a2bd1f54 SV |
624 | } else { |
625 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
626 | } |
627 | ||
a2bd1f54 SV |
628 | kfree(edid); |
629 | ||
c96b63a6 | 630 | return ret; |
79e53945 JB |
631 | } |
632 | ||
e4a5d54f | 633 | static enum drm_connector_status |
c7cc5216 | 634 | intel_crt_load_detect(struct intel_crt *crt, u32 pipe) |
e4a5d54f | 635 | { |
7173188d | 636 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 637 | struct drm_i915_private *dev_priv = to_i915(dev); |
c7cc5216 JN |
638 | u32 save_bclrpat; |
639 | u32 save_vtotal; | |
640 | u32 vtotal, vactive; | |
641 | u32 vsample; | |
642 | u32 vblank, vblank_start, vblank_end; | |
643 | u32 dsl; | |
f0f59a00 VS |
644 | i915_reg_t bclrpat_reg, vtotal_reg, |
645 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
c7cc5216 | 646 | u8 st00; |
e4a5d54f ML |
647 | enum drm_connector_status status; |
648 | ||
6ec3d0c0 CW |
649 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
650 | ||
9db4a9c7 JB |
651 | bclrpat_reg = BCLRPAT(pipe); |
652 | vtotal_reg = VTOTAL(pipe); | |
653 | vblank_reg = VBLANK(pipe); | |
654 | vsync_reg = VSYNC(pipe); | |
655 | pipeconf_reg = PIPECONF(pipe); | |
656 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
657 | |
658 | save_bclrpat = I915_READ(bclrpat_reg); | |
659 | save_vtotal = I915_READ(vtotal_reg); | |
660 | vblank = I915_READ(vblank_reg); | |
661 | ||
662 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
663 | vactive = (save_vtotal & 0x7ff) + 1; | |
664 | ||
665 | vblank_start = (vblank & 0xfff) + 1; | |
666 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
667 | ||
668 | /* Set the border color to purple. */ | |
669 | I915_WRITE(bclrpat_reg, 0x500050); | |
670 | ||
cf819eff | 671 | if (!IS_GEN(dev_priv, 2)) { |
c7cc5216 | 672 | u32 pipeconf = I915_READ(pipeconf_reg); |
e4a5d54f | 673 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
19c55da1 | 674 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
675 | /* Wait for next Vblank to substitue |
676 | * border color for Color info */ | |
0f0f74bc | 677 | intel_wait_for_vblank(dev_priv, pipe); |
f0f59a00 | 678 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
679 | status = ((st00 & (1 << 4)) != 0) ? |
680 | connector_status_connected : | |
681 | connector_status_disconnected; | |
682 | ||
683 | I915_WRITE(pipeconf_reg, pipeconf); | |
684 | } else { | |
685 | bool restore_vblank = false; | |
686 | int count, detect; | |
687 | ||
688 | /* | |
689 | * If there isn't any border, add some. | |
690 | * Yes, this will flicker | |
691 | */ | |
692 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
c7cc5216 JN |
693 | u32 vsync = I915_READ(vsync_reg); |
694 | u32 vsync_start = (vsync & 0xffff) + 1; | |
e4a5d54f ML |
695 | |
696 | vblank_start = vsync_start; | |
697 | I915_WRITE(vblank_reg, | |
698 | (vblank_start - 1) | | |
699 | ((vblank_end - 1) << 16)); | |
700 | restore_vblank = true; | |
701 | } | |
702 | /* sample in the vertical border, selecting the larger one */ | |
703 | if (vblank_start - vactive >= vtotal - vblank_end) | |
704 | vsample = (vblank_start + vactive) >> 1; | |
705 | else | |
706 | vsample = (vtotal + vblank_end) >> 1; | |
707 | ||
708 | /* | |
709 | * Wait for the border to be displayed | |
710 | */ | |
711 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
712 | ; | |
713 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
714 | ; | |
715 | /* | |
716 | * Watch ST00 for an entire scanline | |
717 | */ | |
718 | detect = 0; | |
719 | count = 0; | |
720 | do { | |
721 | count++; | |
722 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 723 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
724 | if (st00 & (1 << 4)) |
725 | detect++; | |
726 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
727 | ||
728 | /* restore vblank if necessary */ | |
729 | if (restore_vblank) | |
730 | I915_WRITE(vblank_reg, vblank); | |
731 | /* | |
732 | * If more than 3/4 of the scanline detected a monitor, | |
733 | * then it is assumed to be present. This works even on i830, | |
734 | * where there isn't any way to force the border color across | |
735 | * the screen | |
736 | */ | |
737 | status = detect * 4 > count * 3 ? | |
738 | connector_status_connected : | |
739 | connector_status_disconnected; | |
740 | } | |
741 | ||
742 | /* Restore previous settings */ | |
743 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
744 | ||
745 | return status; | |
746 | } | |
747 | ||
f0dfb1a8 VS |
748 | static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) |
749 | { | |
750 | DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); | |
751 | return 1; | |
752 | } | |
753 | ||
754 | static const struct dmi_system_id intel_spurious_crt_detect[] = { | |
755 | { | |
756 | .callback = intel_spurious_crt_detect_dmi_callback, | |
757 | .ident = "ACER ZGB", | |
758 | .matches = { | |
759 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
760 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
761 | }, | |
762 | }, | |
69a44b16 VS |
763 | { |
764 | .callback = intel_spurious_crt_detect_dmi_callback, | |
765 | .ident = "Intel DZ77BH-55K", | |
766 | .matches = { | |
767 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), | |
768 | DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), | |
769 | }, | |
770 | }, | |
f0dfb1a8 VS |
771 | { } |
772 | }; | |
773 | ||
6c5ed5ae ML |
774 | static int |
775 | intel_crt_detect(struct drm_connector *connector, | |
776 | struct drm_modeset_acquire_ctx *ctx, | |
777 | bool force) | |
79e53945 | 778 | { |
66478475 | 779 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
c9a1c4cd | 780 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 | 781 | struct intel_encoder *intel_encoder = &crt->base; |
0e6e0be4 | 782 | intel_wakeref_t wakeref; |
6c5ed5ae | 783 | int status, ret; |
e95c8438 | 784 | struct intel_load_detect_pipe tmp; |
79e53945 | 785 | |
164c8598 | 786 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 787 | connector->base.id, connector->name, |
164c8598 CW |
788 | force); |
789 | ||
4165791d | 790 | if (i915_modparams.load_detect_test) { |
0e6e0be4 CW |
791 | wakeref = intel_display_power_get(dev_priv, |
792 | intel_encoder->power_domain); | |
4165791d VS |
793 | goto load_detect; |
794 | } | |
795 | ||
f0dfb1a8 VS |
796 | /* Skip machines without VGA that falsely report hotplug events */ |
797 | if (dmi_check_system(intel_spurious_crt_detect)) | |
798 | return connector_status_disconnected; | |
799 | ||
0e6e0be4 CW |
800 | wakeref = intel_display_power_get(dev_priv, |
801 | intel_encoder->power_domain); | |
671dedd2 | 802 | |
56b857a5 | 803 | if (I915_HAS_HOTPLUG(dev_priv)) { |
aaa37730 SV |
804 | /* We can not rely on the HPD pin always being correctly wired |
805 | * up, for example many KVM do not pass it through, and so | |
806 | * only trust an assertion that the monitor is connected. | |
807 | */ | |
6ec3d0c0 CW |
808 | if (intel_crt_detect_hotplug(connector)) { |
809 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
810 | status = connector_status_connected; |
811 | goto out; | |
aaa37730 | 812 | } else |
e7dbb2f2 | 813 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
814 | } |
815 | ||
c19a0df2 PZ |
816 | if (intel_crt_detect_ddc(connector)) { |
817 | status = connector_status_connected; | |
818 | goto out; | |
819 | } | |
79e53945 | 820 | |
aaa37730 SV |
821 | /* Load detection is broken on HPD capable machines. Whoever wants a |
822 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
823 | * to have the right resistors for HP detection) needs to fix this up. | |
824 | * For now just bail out. */ | |
4165791d | 825 | if (I915_HAS_HOTPLUG(dev_priv)) { |
c19a0df2 PZ |
826 | status = connector_status_disconnected; |
827 | goto out; | |
828 | } | |
aaa37730 | 829 | |
4165791d | 830 | load_detect: |
c19a0df2 PZ |
831 | if (!force) { |
832 | status = connector->status; | |
833 | goto out; | |
834 | } | |
7b334fcb | 835 | |
e4a5d54f | 836 | /* for pre-945g platforms use load detect */ |
6c5ed5ae ML |
837 | ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); |
838 | if (ret > 0) { | |
e95c8438 SV |
839 | if (intel_crt_detect_ddc(connector)) |
840 | status = connector_status_connected; | |
66478475 | 841 | else if (INTEL_GEN(dev_priv) < 4) |
c8ecb2f1 ML |
842 | status = intel_crt_load_detect(crt, |
843 | to_intel_crtc(connector->state->crtc)->pipe); | |
4f044a88 | 844 | else if (i915_modparams.load_detect_test) |
32fff610 | 845 | status = connector_status_disconnected; |
5bedeb2d SV |
846 | else |
847 | status = connector_status_unknown; | |
6c5ed5ae | 848 | intel_release_load_detect_pipe(connector, &tmp, ctx); |
2927e421 | 849 | } else if (ret == 0) { |
e95c8438 | 850 | status = connector_status_unknown; |
2927e421 | 851 | } else { |
6c5ed5ae | 852 | status = ret; |
2927e421 | 853 | } |
208bf9fd | 854 | |
c19a0df2 | 855 | out: |
0e6e0be4 | 856 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
e4a5d54f | 857 | return status; |
79e53945 JB |
858 | } |
859 | ||
79e53945 JB |
860 | static int intel_crt_get_modes(struct drm_connector *connector) |
861 | { | |
8e4d36b9 | 862 | struct drm_device *dev = connector->dev; |
fac5e23e | 863 | struct drm_i915_private *dev_priv = to_i915(dev); |
671dedd2 ID |
864 | struct intel_crt *crt = intel_attached_crt(connector); |
865 | struct intel_encoder *intel_encoder = &crt->base; | |
0e6e0be4 | 866 | intel_wakeref_t wakeref; |
3bd7d909 | 867 | struct i2c_adapter *i2c; |
0e6e0be4 | 868 | int ret; |
8e4d36b9 | 869 | |
0e6e0be4 CW |
870 | wakeref = intel_display_power_get(dev_priv, |
871 | intel_encoder->power_domain); | |
671dedd2 | 872 | |
41aa3448 | 873 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 874 | ret = intel_crt_ddc_get_modes(connector, i2c); |
9beb5fea | 875 | if (ret || !IS_G4X(dev_priv)) |
671dedd2 | 876 | goto out; |
8e4d36b9 | 877 | |
8e4d36b9 | 878 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 879 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
880 | ret = intel_crt_ddc_get_modes(connector, i2c); |
881 | ||
882 | out: | |
0e6e0be4 | 883 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
671dedd2 ID |
884 | |
885 | return ret; | |
79e53945 JB |
886 | } |
887 | ||
9504a892 | 888 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 889 | { |
66478475 | 890 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
28cf71ce | 891 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 892 | |
66478475 | 893 | if (INTEL_GEN(dev_priv) >= 5) { |
2e938892 SV |
894 | u32 adpa; |
895 | ||
ca54b810 | 896 | adpa = I915_READ(crt->adpa_reg); |
2e938892 SV |
897 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
898 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
899 | I915_WRITE(crt->adpa_reg, adpa); |
900 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 901 | |
0039a4b3 | 902 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 903 | crt->force_hotplug_required = 1; |
2e938892 SV |
904 | } |
905 | ||
f3269058 CW |
906 | } |
907 | ||
79e53945 JB |
908 | /* |
909 | * Routines for controlling stuff on the analog port | |
910 | */ | |
911 | ||
79e53945 | 912 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
79e53945 | 913 | .fill_modes = drm_helper_probe_single_connector_modes, |
1ebaa0b9 | 914 | .late_register = intel_connector_register, |
c191eca1 | 915 | .early_unregister = intel_connector_unregister, |
d4b26e4f | 916 | .destroy = intel_connector_destroy, |
c6f95f27 | 917 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 918 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
919 | }; |
920 | ||
921 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
6c5ed5ae | 922 | .detect_ctx = intel_crt_detect, |
79e53945 JB |
923 | .mode_valid = intel_crt_mode_valid, |
924 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
925 | }; |
926 | ||
79e53945 | 927 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 928 | .reset = intel_crt_reset, |
ea5b213a | 929 | .destroy = intel_encoder_destroy, |
79e53945 JB |
930 | }; |
931 | ||
c39055b0 | 932 | void intel_crt_init(struct drm_i915_private *dev_priv) |
79e53945 JB |
933 | { |
934 | struct drm_connector *connector; | |
c9a1c4cd | 935 | struct intel_crt *crt; |
454c1ca8 | 936 | struct intel_connector *intel_connector; |
6c03a6bd VS |
937 | i915_reg_t adpa_reg; |
938 | u32 adpa; | |
79e53945 | 939 | |
6e266956 | 940 | if (HAS_PCH_SPLIT(dev_priv)) |
6c03a6bd | 941 | adpa_reg = PCH_ADPA; |
11a914c2 | 942 | else if (IS_VALLEYVIEW(dev_priv)) |
6c03a6bd VS |
943 | adpa_reg = VLV_ADPA; |
944 | else | |
945 | adpa_reg = ADPA; | |
946 | ||
947 | adpa = I915_READ(adpa_reg); | |
948 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
949 | /* | |
950 | * On some machines (some IVB at least) CRT can be | |
951 | * fused off, but there's no known fuse bit to | |
952 | * indicate that. On these machine the ADPA register | |
953 | * works normally, except the DAC enable bit won't | |
954 | * take. So the only way to tell is attempt to enable | |
955 | * it and see what happens. | |
956 | */ | |
957 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
958 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
959 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
960 | return; | |
961 | I915_WRITE(adpa_reg, adpa); | |
962 | } | |
963 | ||
c9a1c4cd CW |
964 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
965 | if (!crt) | |
79e53945 JB |
966 | return; |
967 | ||
9bdbd0b9 | 968 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 969 | if (!intel_connector) { |
c9a1c4cd | 970 | kfree(crt); |
454c1ca8 ZW |
971 | return; |
972 | } | |
973 | ||
974 | connector = &intel_connector->base; | |
637f44d2 | 975 | crt->connector = intel_connector; |
c39055b0 | 976 | drm_connector_init(&dev_priv->drm, &intel_connector->base, |
79e53945 JB |
977 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
978 | ||
c39055b0 | 979 | drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 980 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 981 | |
c9a1c4cd | 982 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 983 | |
c9a1c4cd | 984 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 985 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
50a0bc90 | 986 | if (IS_I830(dev_priv)) |
59c859d6 ED |
987 | crt->base.crtc_mask = (1 << 0); |
988 | else | |
0826874a | 989 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 990 | |
cf819eff | 991 | if (IS_GEN(dev_priv, 2)) |
dbb02575 SV |
992 | connector->interlace_allowed = 0; |
993 | else | |
994 | connector->interlace_allowed = 1; | |
79e53945 JB |
995 | connector->doublescan_allowed = 0; |
996 | ||
6c03a6bd | 997 | crt->adpa_reg = adpa_reg; |
540a8950 | 998 | |
79f255a0 ACO |
999 | crt->base.power_domain = POWER_DOMAIN_PORT_CRT; |
1000 | ||
56b857a5 | 1001 | if (I915_HAS_HOTPLUG(dev_priv) && |
dba14b27 | 1002 | !dmi_check_system(intel_spurious_crt_detect)) { |
1d843f9d | 1003 | crt->base.hpd_pin = HPD_CRT; |
dba14b27 VS |
1004 | crt->base.hotplug = intel_encoder_hotplug; |
1005 | } | |
c5ce4ef3 | 1006 | |
4f8036a2 | 1007 | if (HAS_DDI(dev_priv)) { |
03cdc1d4 | 1008 | crt->base.port = PORT_E; |
a2985791 | 1009 | crt->base.get_config = hsw_crt_get_config; |
4eda01b2 | 1010 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
2f26cdc0 | 1011 | crt->base.compute_config = hsw_crt_compute_config; |
51c4fa69 JN |
1012 | crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; |
1013 | crt->base.pre_enable = hsw_pre_enable_crt; | |
1014 | crt->base.enable = hsw_enable_crt; | |
3daa3cee | 1015 | crt->base.disable = hsw_disable_crt; |
b7076546 | 1016 | crt->base.post_disable = hsw_post_disable_crt; |
a2985791 | 1017 | } else { |
c5ce4ef3 | 1018 | if (HAS_PCH_SPLIT(dev_priv)) { |
2f26cdc0 | 1019 | crt->base.compute_config = pch_crt_compute_config; |
c5ce4ef3 JN |
1020 | crt->base.disable = pch_disable_crt; |
1021 | crt->base.post_disable = pch_post_disable_crt; | |
1022 | } else { | |
2f26cdc0 | 1023 | crt->base.compute_config = intel_crt_compute_config; |
c5ce4ef3 JN |
1024 | crt->base.disable = intel_disable_crt; |
1025 | } | |
03cdc1d4 | 1026 | crt->base.port = PORT_NONE; |
a2985791 | 1027 | crt->base.get_config = intel_crt_get_config; |
4eda01b2 | 1028 | crt->base.get_hw_state = intel_crt_get_hw_state; |
51c4fa69 | 1029 | crt->base.enable = intel_enable_crt; |
a2985791 | 1030 | } |
e403fc94 | 1031 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 1032 | |
79e53945 JB |
1033 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
1034 | ||
56b857a5 | 1035 | if (!I915_HAS_HOTPLUG(dev_priv)) |
821450c6 | 1036 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
eb1f8e4f | 1037 | |
e7dbb2f2 KP |
1038 | /* |
1039 | * Configure the automatic hotplug detection stuff | |
1040 | */ | |
1041 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 1042 | |
68d18ad7 | 1043 | /* |
3e68320e DL |
1044 | * TODO: find a proper way to discover whether we need to set the the |
1045 | * polarity and link reversal bits or not, instead of relying on the | |
1046 | * BIOS. | |
68d18ad7 | 1047 | */ |
6e266956 | 1048 | if (HAS_PCH_LPT(dev_priv)) { |
3e68320e DL |
1049 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
1050 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
1051 | ||
eede3b53 | 1052 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 1053 | } |
754970ee | 1054 | |
28cf71ce | 1055 | intel_crt_reset(&crt->base.base); |
79e53945 | 1056 | } |