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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
e6017571 | 30 | #include <linux/sched/clock.h> |
0550691d JN |
31 | |
32 | #include <drm/drm_atomic.h> | |
760285e7 | 33 | #include <drm/drm_crtc.h> |
b1ba124d | 34 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 35 | #include <drm/drm_dp_mst_helper.h> |
0550691d JN |
36 | #include <drm/drm_encoder.h> |
37 | #include <drm/drm_fb_helper.h> | |
fcd70cd3 | 38 | #include <drm/drm_probe_helper.h> |
eeca778a | 39 | #include <drm/drm_rect.h> |
fcd70cd3 | 40 | #include <drm/drm_vblank.h> |
0550691d | 41 | #include <drm/i915_drm.h> |
9055aac7 | 42 | #include <drm/i915_mei_hdcp_interface.h> |
9c229127 | 43 | #include <media/cec-notifier.h> |
913d8d11 | 44 | |
0550691d JN |
45 | #include "i915_drv.h" |
46 | ||
bd780f37 CW |
47 | struct drm_printer; |
48 | ||
79e53945 JB |
49 | /* |
50 | * Display related stuff | |
51 | */ | |
52 | ||
79e53945 JB |
53 | /* these are outputs from the chip - integrated only |
54 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
55 | enum intel_output_type { |
56 | INTEL_OUTPUT_UNUSED = 0, | |
57 | INTEL_OUTPUT_ANALOG = 1, | |
58 | INTEL_OUTPUT_DVO = 2, | |
59 | INTEL_OUTPUT_SDVO = 3, | |
60 | INTEL_OUTPUT_LVDS = 4, | |
61 | INTEL_OUTPUT_TVOUT = 5, | |
62 | INTEL_OUTPUT_HDMI = 6, | |
cca0502b | 63 | INTEL_OUTPUT_DP = 7, |
6847d71b PZ |
64 | INTEL_OUTPUT_EDP = 8, |
65 | INTEL_OUTPUT_DSI = 9, | |
7e732cac | 66 | INTEL_OUTPUT_DDI = 10, |
6847d71b PZ |
67 | INTEL_OUTPUT_DP_MST = 11, |
68 | }; | |
79e53945 | 69 | |
79e53945 JB |
70 | struct intel_framebuffer { |
71 | struct drm_framebuffer base; | |
2d7a215f | 72 | struct intel_rotation_info rot_info; |
6687c906 VS |
73 | |
74 | /* for each plane in the normal GTT view */ | |
75 | struct { | |
76 | unsigned int x, y; | |
77 | } normal[2]; | |
78 | /* for each plane in the rotated GTT view */ | |
79 | struct { | |
80 | unsigned int x, y; | |
81 | unsigned int pitch; /* pixels */ | |
82 | } rotated[2]; | |
79e53945 JB |
83 | }; |
84 | ||
37811fcc CW |
85 | struct intel_fbdev { |
86 | struct drm_fb_helper helper; | |
8bcd4553 | 87 | struct intel_framebuffer *fb; |
058d88c4 | 88 | struct i915_vma *vma; |
5935485f | 89 | unsigned long vma_flags; |
43cee314 | 90 | async_cookie_t cookie; |
d978ef14 | 91 | int preferred_bpp; |
fe5ec656 LP |
92 | |
93 | /* Whether or not fbdev hpd processing is temporarily suspended */ | |
94 | bool hpd_suspended : 1; | |
95 | /* Set when a hotplug was received while HPD processing was | |
96 | * suspended | |
97 | */ | |
98 | bool hpd_waiting : 1; | |
99 | ||
100 | /* Protects hpd_suspended */ | |
101 | struct mutex hpd_lock; | |
37811fcc | 102 | }; |
79e53945 | 103 | |
21d40d37 | 104 | struct intel_encoder { |
4ef69c7a | 105 | struct drm_encoder base; |
9a935856 | 106 | |
6847d71b | 107 | enum intel_output_type type; |
03cdc1d4 | 108 | enum port port; |
bc079e8b | 109 | unsigned int cloneable; |
dba14b27 VS |
110 | bool (*hotplug)(struct intel_encoder *encoder, |
111 | struct intel_connector *connector); | |
7e732cac VS |
112 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
113 | struct intel_crtc_state *, | |
114 | struct drm_connector_state *); | |
204474a6 LP |
115 | int (*compute_config)(struct intel_encoder *, |
116 | struct intel_crtc_state *, | |
117 | struct drm_connector_state *); | |
fd6bbda9 | 118 | void (*pre_pll_enable)(struct intel_encoder *, |
5f88a9c6 VS |
119 | const struct intel_crtc_state *, |
120 | const struct drm_connector_state *); | |
fd6bbda9 | 121 | void (*pre_enable)(struct intel_encoder *, |
5f88a9c6 VS |
122 | const struct intel_crtc_state *, |
123 | const struct drm_connector_state *); | |
fd6bbda9 | 124 | void (*enable)(struct intel_encoder *, |
5f88a9c6 VS |
125 | const struct intel_crtc_state *, |
126 | const struct drm_connector_state *); | |
fd6bbda9 | 127 | void (*disable)(struct intel_encoder *, |
5f88a9c6 VS |
128 | const struct intel_crtc_state *, |
129 | const struct drm_connector_state *); | |
fd6bbda9 | 130 | void (*post_disable)(struct intel_encoder *, |
5f88a9c6 VS |
131 | const struct intel_crtc_state *, |
132 | const struct drm_connector_state *); | |
fd6bbda9 | 133 | void (*post_pll_disable)(struct intel_encoder *, |
5f88a9c6 VS |
134 | const struct intel_crtc_state *, |
135 | const struct drm_connector_state *); | |
608ed4ab HG |
136 | void (*update_pipe)(struct intel_encoder *, |
137 | const struct intel_crtc_state *, | |
138 | const struct drm_connector_state *); | |
f0947c37 DV |
139 | /* Read out the current hw state of this connector, returning true if |
140 | * the encoder is active. If the encoder is enabled it also set the pipe | |
141 | * it is connected to in the pipe parameter. */ | |
142 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 143 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 144 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
145 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
146 | * be set correctly before calling this function. */ | |
045ac3b5 | 147 | void (*get_config)(struct intel_encoder *, |
5cec258b | 148 | struct intel_crtc_state *pipe_config); |
3a52fb7e ID |
149 | /* |
150 | * Acquires the power domains needed for an active encoder during | |
151 | * hardware state readout. | |
152 | */ | |
153 | void (*get_power_domains)(struct intel_encoder *encoder, | |
154 | struct intel_crtc_state *crtc_state); | |
07f9cd0b ID |
155 | /* |
156 | * Called during system suspend after all pending requests for the | |
157 | * encoder are flushed (for example for DP AUX transactions) and | |
158 | * device interrupts are disabled. | |
159 | */ | |
160 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 161 | int crtc_mask; |
1d843f9d | 162 | enum hpd_pin hpd_pin; |
79f255a0 | 163 | enum intel_display_power_domain power_domain; |
f1a3acea PD |
164 | /* for communication with audio component; protected by av_mutex */ |
165 | const struct drm_connector *audio_connector; | |
79e53945 JB |
166 | }; |
167 | ||
1d508706 | 168 | struct intel_panel { |
dd06f90e | 169 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 170 | struct drm_display_mode *downclock_mode; |
58c68779 JN |
171 | |
172 | /* backlight */ | |
173 | struct { | |
c91c9f32 | 174 | bool present; |
58c68779 | 175 | u32 level; |
6dda730e | 176 | u32 min; |
7bd688cd | 177 | u32 max; |
58c68779 | 178 | bool enabled; |
636baebf JN |
179 | bool combination_mode; /* gen 2/4 only */ |
180 | bool active_low_pwm; | |
32b421e7 | 181 | bool alternate_pwm_increment; /* lpt+ */ |
b029e66f SK |
182 | |
183 | /* PWM chip */ | |
022e4e52 SK |
184 | bool util_pin_active_low; /* bxt+ */ |
185 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
186 | struct pwm_device *pwm; |
187 | ||
58c68779 | 188 | struct backlight_device *device; |
ab656bb9 | 189 | |
5507faeb JN |
190 | /* Connector and platform specific backlight functions */ |
191 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
d25236a3 JN |
192 | u32 (*get)(struct intel_connector *connector); |
193 | void (*set)(const struct drm_connector_state *conn_state, u32 level); | |
7d025e08 ML |
194 | void (*disable)(const struct drm_connector_state *conn_state); |
195 | void (*enable)(const struct intel_crtc_state *crtc_state, | |
196 | const struct drm_connector_state *conn_state); | |
d25236a3 | 197 | u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); |
5507faeb JN |
198 | void (*power)(struct intel_connector *, bool enable); |
199 | } backlight; | |
1d508706 JN |
200 | }; |
201 | ||
b6ca3eee VS |
202 | struct intel_digital_port; |
203 | ||
22ce2d94 R |
204 | enum check_link_response { |
205 | HDCP_LINK_PROTECTED = 0, | |
206 | HDCP_TOPOLOGY_CHANGE, | |
207 | HDCP_LINK_INTEGRITY_FAILURE, | |
208 | HDCP_REAUTH_REQUEST | |
209 | }; | |
210 | ||
ee5e5e7a SP |
211 | /* |
212 | * This structure serves as a translation layer between the generic HDCP code | |
213 | * and the bus-specific code. What that means is that HDCP over HDMI differs | |
214 | * from HDCP over DP, so to account for these differences, we need to | |
215 | * communicate with the receiver through this shim. | |
216 | * | |
217 | * For completeness, the 2 buses differ in the following ways: | |
218 | * - DP AUX vs. DDC | |
219 | * HDCP registers on the receiver are set via DP AUX for DP, and | |
220 | * they are set via DDC for HDMI. | |
221 | * - Receiver register offsets | |
222 | * The offsets of the registers are different for DP vs. HDMI | |
223 | * - Receiver register masks/offsets | |
224 | * For instance, the ready bit for the KSV fifo is in a different | |
225 | * place on DP vs HDMI | |
226 | * - Receiver register names | |
227 | * Seriously. In the DP spec, the 16-bit register containing | |
228 | * downstream information is called BINFO, on HDMI it's called | |
229 | * BSTATUS. To confuse matters further, DP has a BSTATUS register | |
230 | * with a completely different definition. | |
231 | * - KSV FIFO | |
232 | * On HDMI, the ksv fifo is read all at once, whereas on DP it must | |
233 | * be read 3 keys at a time | |
234 | * - Aksv output | |
235 | * Since Aksv is hidden in hardware, there's different procedures | |
236 | * to send it over DP AUX vs DDC | |
237 | */ | |
238 | struct intel_hdcp_shim { | |
239 | /* Outputs the transmitter's An and Aksv values to the receiver. */ | |
240 | int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); | |
241 | ||
242 | /* Reads the receiver's key selection vector */ | |
243 | int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); | |
244 | ||
245 | /* | |
246 | * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The | |
247 | * definitions are the same in the respective specs, but the names are | |
248 | * different. Call it BSTATUS since that's the name the HDMI spec | |
249 | * uses and it was there first. | |
250 | */ | |
251 | int (*read_bstatus)(struct intel_digital_port *intel_dig_port, | |
252 | u8 *bstatus); | |
253 | ||
254 | /* Determines whether a repeater is present downstream */ | |
255 | int (*repeater_present)(struct intel_digital_port *intel_dig_port, | |
256 | bool *repeater_present); | |
257 | ||
258 | /* Reads the receiver's Ri' value */ | |
259 | int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); | |
260 | ||
261 | /* Determines if the receiver's KSV FIFO is ready for consumption */ | |
262 | int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, | |
263 | bool *ksv_ready); | |
264 | ||
265 | /* Reads the ksv fifo for num_downstream devices */ | |
266 | int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, | |
267 | int num_downstream, u8 *ksv_fifo); | |
268 | ||
269 | /* Reads a 32-bit part of V' from the receiver */ | |
270 | int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, | |
271 | int i, u32 *part); | |
272 | ||
273 | /* Enables HDCP signalling on the port */ | |
274 | int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, | |
275 | bool enable); | |
276 | ||
277 | /* Ensures the link is still protected */ | |
278 | bool (*check_link)(struct intel_digital_port *intel_dig_port); | |
791a98dd R |
279 | |
280 | /* Detects panel's hdcp capability. This is optional for HDMI. */ | |
281 | int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, | |
282 | bool *hdcp_capable); | |
9055aac7 R |
283 | |
284 | /* HDCP adaptation(DP/HDMI) required on the port */ | |
285 | enum hdcp_wired_protocol protocol; | |
49a630b0 R |
286 | |
287 | /* Detects whether sink is HDCP2.2 capable */ | |
288 | int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, | |
289 | bool *capable); | |
bd90d7c7 R |
290 | |
291 | /* Write HDCP2.2 messages */ | |
292 | int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, | |
293 | void *buf, size_t size); | |
294 | ||
295 | /* Read HDCP2.2 messages */ | |
296 | int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, | |
297 | u8 msg_id, void *buf, size_t size); | |
298 | ||
299 | /* | |
300 | * Implementation of DP HDCP2.2 Errata for the communication of stream | |
301 | * type to Receivers. In DP HDCP2.2 Stream type is one of the input to | |
302 | * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. | |
303 | */ | |
304 | int (*config_stream_type)(struct intel_digital_port *intel_dig_port, | |
305 | bool is_repeater, u8 type); | |
22ce2d94 R |
306 | |
307 | /* HDCP2.2 Link Integrity Check */ | |
308 | int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); | |
ee5e5e7a SP |
309 | }; |
310 | ||
d3dacc70 R |
311 | struct intel_hdcp { |
312 | const struct intel_hdcp_shim *shim; | |
313 | /* Mutex for hdcp state of the connector */ | |
314 | struct mutex mutex; | |
315 | u64 value; | |
316 | struct delayed_work check_work; | |
317 | struct work_struct prop_work; | |
04707f97 | 318 | |
09d56393 R |
319 | /* HDCP1.4 Encryption status */ |
320 | bool hdcp_encrypted; | |
321 | ||
04707f97 R |
322 | /* HDCP2.2 related definitions */ |
323 | /* Flag indicates whether this connector supports HDCP2.2 or not. */ | |
324 | bool hdcp2_supported; | |
325 | ||
49a630b0 R |
326 | /* HDCP2.2 Encryption status */ |
327 | bool hdcp2_encrypted; | |
328 | ||
04707f97 R |
329 | /* |
330 | * Content Stream Type defined by content owner. TYPE0(0x0) content can | |
331 | * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) | |
332 | * content can flow only through a link protected by HDCP2.2. | |
333 | */ | |
334 | u8 content_type; | |
9055aac7 | 335 | struct hdcp_port_data port_data; |
bd90d7c7 R |
336 | |
337 | bool is_paired; | |
338 | bool is_repeater; | |
339 | ||
340 | /* | |
341 | * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. | |
342 | * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. | |
343 | * When it rolls over re-auth has to be triggered. | |
344 | */ | |
345 | u32 seq_num_v; | |
346 | ||
347 | /* | |
348 | * Count of RepeaterAuth_Stream_Manage msg propagated. | |
349 | * Initialized to 0 on AKE_INIT. Incremented after every successful | |
350 | * transmission of RepeaterAuth_Stream_Manage message. When it rolls | |
351 | * over re-Auth has to be triggered. | |
352 | */ | |
353 | u32 seq_num_m; | |
cf9cb35f R |
354 | |
355 | /* | |
356 | * Work queue to signal the CP_IRQ. Used for the waiters to read the | |
357 | * available information from HDCP DP sink. | |
358 | */ | |
359 | wait_queue_head_t cp_irq_queue; | |
360 | atomic_t cp_irq_count; | |
361 | int cp_irq_count_cached; | |
d3dacc70 R |
362 | }; |
363 | ||
5daa55eb ZW |
364 | struct intel_connector { |
365 | struct drm_connector base; | |
9a935856 DV |
366 | /* |
367 | * The fixed encoder this connector is connected to. | |
368 | */ | |
df0e9248 | 369 | struct intel_encoder *encoder; |
9a935856 | 370 | |
8e1b56a4 JN |
371 | /* ACPI device id for ACPI and driver cooperation */ |
372 | u32 acpi_device_id; | |
373 | ||
f0947c37 DV |
374 | /* Reads out the current hw, returning true if the connector is enabled |
375 | * and active (i.e. dpms ON state). */ | |
376 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
377 | |
378 | /* Panel info for eDP and LVDS */ | |
379 | struct intel_panel panel; | |
9cd300e0 JN |
380 | |
381 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
382 | struct edid *edid; | |
beb60608 | 383 | struct edid *detect_edid; |
821450c6 EE |
384 | |
385 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
386 | state of connector->polled in case hotplug storm detection changes it */ | |
387 | u8 polled; | |
0e32b39c DA |
388 | |
389 | void *port; /* store this opaque as its illegal to dereference it */ | |
390 | ||
391 | struct intel_dp *mst_port; | |
9301397a MN |
392 | |
393 | /* Work struct to schedule a uevent on link train failure */ | |
394 | struct work_struct modeset_retry_work; | |
ee5e5e7a | 395 | |
d3dacc70 | 396 | struct intel_hdcp hdcp; |
5daa55eb ZW |
397 | }; |
398 | ||
11c1a9ec ML |
399 | struct intel_digital_connector_state { |
400 | struct drm_connector_state base; | |
401 | ||
402 | enum hdmi_force_audio force_audio; | |
403 | int broadcast_rgb; | |
404 | }; | |
405 | ||
406 | #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) | |
407 | ||
9e2c8475 | 408 | struct dpll { |
80ad9206 VS |
409 | /* given values */ |
410 | int n; | |
411 | int m1, m2; | |
412 | int p1, p2; | |
413 | /* derived values */ | |
414 | int dot; | |
415 | int vco; | |
416 | int m; | |
417 | int p; | |
9e2c8475 | 418 | }; |
80ad9206 | 419 | |
de419ab6 ML |
420 | struct intel_atomic_state { |
421 | struct drm_atomic_state base; | |
422 | ||
bb0f4aab VS |
423 | struct { |
424 | /* | |
425 | * Logical state of cdclk (used for all scaling, watermark, | |
426 | * etc. calculations and checks). This is computed as if all | |
427 | * enabled crtcs were active. | |
428 | */ | |
429 | struct intel_cdclk_state logical; | |
430 | ||
431 | /* | |
432 | * Actual state of cdclk, can be different from the logical | |
433 | * state only when all crtc's are DPMS off. | |
434 | */ | |
435 | struct intel_cdclk_state actual; | |
905801fe VS |
436 | |
437 | int force_min_cdclk; | |
438 | bool force_min_cdclk_changed; | |
59f9e9ca VS |
439 | /* pipe to which cd2x update is synchronized */ |
440 | enum pipe pipe; | |
bb0f4aab | 441 | } cdclk; |
1a617b77 | 442 | |
565602d7 ML |
443 | bool dpll_set, modeset; |
444 | ||
8b4a7d05 MR |
445 | /* |
446 | * Does this transaction change the pipes that are active? This mask | |
447 | * tracks which CRTC's have changed their active state at the end of | |
448 | * the transaction (not counting the temporary disable during modesets). | |
449 | * This mask should only be non-zero when intel_state->modeset is true, | |
450 | * but the converse is not necessarily true; simply changing a mode may | |
451 | * not flip the final active status of any CRTC's | |
452 | */ | |
453 | unsigned int active_pipe_changes; | |
454 | ||
565602d7 | 455 | unsigned int active_crtcs; |
d305e061 VS |
456 | /* minimum acceptable cdclk for each pipe */ |
457 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
458 | /* minimum acceptable voltage level for each pipe */ |
459 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 460 | |
2c42e535 | 461 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
ed4a6a7c MR |
462 | |
463 | /* | |
464 | * Current watermarks can't be trusted during hardware readout, so | |
465 | * don't bother calculating intermediate watermarks. | |
466 | */ | |
467 | bool skip_intermediate_wm; | |
98d39494 | 468 | |
60548c55 CW |
469 | bool rps_interactive; |
470 | ||
98d39494 | 471 | /* Gen9+ only */ |
60f8e873 | 472 | struct skl_ddb_values wm_results; |
c004a90b CW |
473 | |
474 | struct i915_sw_fence commit_ready; | |
eb955eee CW |
475 | |
476 | struct llist_node freed; | |
de419ab6 ML |
477 | }; |
478 | ||
eeca778a | 479 | struct intel_plane_state { |
2b875c22 | 480 | struct drm_plane_state base; |
f5929c53 | 481 | struct i915_ggtt_view view; |
be1e3415 | 482 | struct i915_vma *vma; |
5935485f CW |
483 | unsigned long flags; |
484 | #define PLANE_HAS_FENCE BIT(0) | |
32b7eeec | 485 | |
b63a16f6 VS |
486 | struct { |
487 | u32 offset; | |
df79cf44 VS |
488 | /* |
489 | * Plane stride in: | |
490 | * bytes for 0/180 degree rotation | |
491 | * pixels for 90/270 degree rotation | |
492 | */ | |
493 | u32 stride; | |
b63a16f6 | 494 | int x, y; |
c11ada07 | 495 | } color_plane[2]; |
b63a16f6 | 496 | |
a0864d59 VS |
497 | /* plane control register */ |
498 | u32 ctl; | |
499 | ||
4036c78c JA |
500 | /* plane color control register */ |
501 | u32 color_ctl; | |
502 | ||
be41e336 CK |
503 | /* |
504 | * scaler_id | |
505 | * = -1 : not using a scaler | |
506 | * >= 0 : using a scalers | |
507 | * | |
508 | * plane requiring a scaler: | |
509 | * - During check_plane, its bit is set in | |
510 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 511 | * update_scaler_plane. |
be41e336 CK |
512 | * - scaler_id indicates the scaler it got assigned. |
513 | * | |
514 | * plane doesn't require a scaler: | |
515 | * - this can happen when scaling is no more required or plane simply | |
516 | * got disabled. | |
517 | * - During check_plane, corresponding bit is reset in | |
518 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 519 | * update_scaler_plane. |
be41e336 CK |
520 | */ |
521 | int scaler_id; | |
818ed961 | 522 | |
1ab554b0 ML |
523 | /* |
524 | * linked_plane: | |
525 | * | |
526 | * ICL planar formats require 2 planes that are updated as pairs. | |
527 | * This member is used to make sure the other plane is also updated | |
528 | * when required, and for update_slave() to find the correct | |
529 | * plane_state to pass as argument. | |
530 | */ | |
531 | struct intel_plane *linked_plane; | |
532 | ||
533 | /* | |
534 | * slave: | |
535 | * If set don't update use the linked plane's state for updating | |
536 | * this plane during atomic commit with the update_slave() callback. | |
537 | * | |
538 | * It's also used by the watermark code to ignore wm calculations on | |
539 | * this plane. They're calculated by the linked plane's wm code. | |
540 | */ | |
541 | u32 slave; | |
542 | ||
818ed961 | 543 | struct drm_intel_sprite_colorkey ckey; |
eeca778a GP |
544 | }; |
545 | ||
5724dbd1 | 546 | struct intel_initial_plane_config { |
2d14030b | 547 | struct intel_framebuffer *fb; |
49af449b | 548 | unsigned int tiling; |
46f297fb JB |
549 | int size; |
550 | u32 base; | |
f43348a3 | 551 | u8 rotation; |
46f297fb JB |
552 | }; |
553 | ||
be41e336 | 554 | struct intel_scaler { |
be41e336 | 555 | int in_use; |
d25236a3 | 556 | u32 mode; |
be41e336 CK |
557 | }; |
558 | ||
559 | struct intel_crtc_scaler_state { | |
560 | #define SKL_NUM_SCALERS 2 | |
561 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
562 | ||
563 | /* | |
564 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
565 | * | |
566 | * If a bit is set, a user is using a scaler. | |
567 | * Here user can be a plane or crtc as defined below: | |
568 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
569 | * bit 31 - crtc | |
570 | * | |
571 | * Instead of creating a new index to cover planes and crtc, using | |
572 | * existing drm_plane_index for planes which is well less than 31 | |
573 | * planes and bit 31 for crtc. This should be fine to cover all | |
574 | * our platforms. | |
575 | * | |
576 | * intel_atomic_setup_scalers will setup available scalers to users | |
577 | * requesting scalers. It will gracefully fail if request exceeds | |
578 | * avilability. | |
579 | */ | |
580 | #define SKL_CRTC_INDEX 31 | |
581 | unsigned scaler_users; | |
582 | ||
583 | /* scaler used by crtc for panel fitting purpose */ | |
584 | int scaler_id; | |
585 | }; | |
586 | ||
1ed51de9 | 587 | /* drm_mode->private_flags */ |
8a920e24 | 588 | #define I915_MODE_FLAG_INHERITED (1<<0) |
aec0246f US |
589 | /* Flag to get scanline using frame time stamps */ |
590 | #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) | |
8a920e24 VS |
591 | /* Flag to use the scanline counter instead of the pixel counter */ |
592 | #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) | |
1ed51de9 | 593 | |
4e0963c7 MR |
594 | struct intel_pipe_wm { |
595 | struct intel_wm_level wm[5]; | |
d25236a3 | 596 | u32 linetime; |
4e0963c7 MR |
597 | bool fbc_wm_enabled; |
598 | bool pipe_enabled; | |
599 | bool sprites_enabled; | |
600 | bool sprites_scaled; | |
601 | }; | |
602 | ||
a62163e9 | 603 | struct skl_plane_wm { |
4e0963c7 | 604 | struct skl_wm_level wm[8]; |
942aa2d0 | 605 | struct skl_wm_level uv_wm[8]; |
4e0963c7 | 606 | struct skl_wm_level trans_wm; |
b879d58f | 607 | bool is_planar; |
a62163e9 L |
608 | }; |
609 | ||
610 | struct skl_pipe_wm { | |
611 | struct skl_plane_wm planes[I915_MAX_PLANES]; | |
d25236a3 | 612 | u32 linetime; |
4e0963c7 MR |
613 | }; |
614 | ||
855c79f5 VS |
615 | enum vlv_wm_level { |
616 | VLV_WM_LEVEL_PM2, | |
617 | VLV_WM_LEVEL_PM5, | |
618 | VLV_WM_LEVEL_DDR_DVFS, | |
619 | NUM_VLV_WM_LEVELS, | |
620 | }; | |
621 | ||
622 | struct vlv_wm_state { | |
114d7dc0 VS |
623 | struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; |
624 | struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; | |
d25236a3 | 625 | u8 num_levels; |
855c79f5 VS |
626 | bool cxsr; |
627 | }; | |
628 | ||
814e7f0b VS |
629 | struct vlv_fifo_state { |
630 | u16 plane[I915_MAX_PLANES]; | |
631 | }; | |
632 | ||
04548cba VS |
633 | enum g4x_wm_level { |
634 | G4X_WM_LEVEL_NORMAL, | |
635 | G4X_WM_LEVEL_SR, | |
636 | G4X_WM_LEVEL_HPLL, | |
637 | NUM_G4X_WM_LEVELS, | |
638 | }; | |
639 | ||
640 | struct g4x_wm_state { | |
641 | struct g4x_pipe_wm wm; | |
642 | struct g4x_sr_wm sr; | |
643 | struct g4x_sr_wm hpll; | |
644 | bool cxsr; | |
645 | bool hpll_en; | |
646 | bool fbc_en; | |
647 | }; | |
648 | ||
e8f1f02e MR |
649 | struct intel_crtc_wm_state { |
650 | union { | |
651 | struct { | |
652 | /* | |
653 | * Intermediate watermarks; these can be | |
654 | * programmed immediately since they satisfy | |
655 | * both the current configuration we're | |
656 | * switching away from and the new | |
657 | * configuration we're switching to. | |
658 | */ | |
659 | struct intel_pipe_wm intermediate; | |
660 | ||
661 | /* | |
662 | * Optimal watermarks, programmed post-vblank | |
663 | * when this state is committed. | |
664 | */ | |
665 | struct intel_pipe_wm optimal; | |
666 | } ilk; | |
667 | ||
668 | struct { | |
669 | /* gen9+ only needs 1-step wm programming */ | |
670 | struct skl_pipe_wm optimal; | |
ce0ba283 | 671 | struct skl_ddb_entry ddb; |
ff43bc37 VS |
672 | struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; |
673 | struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; | |
e8f1f02e | 674 | } skl; |
855c79f5 VS |
675 | |
676 | struct { | |
5012e604 | 677 | /* "raw" watermarks (not inverted) */ |
114d7dc0 | 678 | struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; |
4841da51 VS |
679 | /* intermediate watermarks (inverted) */ |
680 | struct vlv_wm_state intermediate; | |
855c79f5 VS |
681 | /* optimal watermarks (inverted) */ |
682 | struct vlv_wm_state optimal; | |
814e7f0b VS |
683 | /* display FIFO split */ |
684 | struct vlv_fifo_state fifo_state; | |
855c79f5 | 685 | } vlv; |
04548cba VS |
686 | |
687 | struct { | |
688 | /* "raw" watermarks */ | |
689 | struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; | |
690 | /* intermediate watermarks */ | |
691 | struct g4x_wm_state intermediate; | |
692 | /* optimal watermarks */ | |
693 | struct g4x_wm_state optimal; | |
694 | } g4x; | |
e8f1f02e MR |
695 | }; |
696 | ||
697 | /* | |
698 | * Platforms with two-step watermark programming will need to | |
699 | * update watermark programming post-vblank to switch from the | |
700 | * safe intermediate watermarks to the optimal final | |
701 | * watermarks. | |
702 | */ | |
703 | bool need_postvbl_update; | |
704 | }; | |
705 | ||
d9facae6 SS |
706 | enum intel_output_format { |
707 | INTEL_OUTPUT_FORMAT_INVALID, | |
708 | INTEL_OUTPUT_FORMAT_RGB, | |
33b7f3ee | 709 | INTEL_OUTPUT_FORMAT_YCBCR420, |
8c79f844 | 710 | INTEL_OUTPUT_FORMAT_YCBCR444, |
d9facae6 SS |
711 | }; |
712 | ||
5cec258b | 713 | struct intel_crtc_state { |
2d112de7 ACO |
714 | struct drm_crtc_state base; |
715 | ||
bb760063 DV |
716 | /** |
717 | * quirks - bitfield with hw state readout quirks | |
718 | * | |
719 | * For various reasons the hw state readout code might not be able to | |
720 | * completely faithfully read out the current state. These cases are | |
721 | * tracked with quirk flags so that fastboot and state checker can act | |
722 | * accordingly. | |
723 | */ | |
9953599b | 724 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
725 | unsigned long quirks; |
726 | ||
cd202f69 | 727 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
728 | bool update_pipe; /* can a fast modeset be performed? */ |
729 | bool disable_cxsr; | |
caed361d | 730 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 731 | bool fb_changed; /* fb on any of the planes is changed */ |
236c48e6 | 732 | bool fifo_changed; /* FIFO split is changed */ |
bfd16b2a | 733 | |
37327abd VS |
734 | /* Pipe source size (ie. panel fitter input size) |
735 | * All planes will be positioned inside this space, | |
736 | * and get clipped at the edges. */ | |
737 | int pipe_src_w, pipe_src_h; | |
738 | ||
a7d1b3f4 VS |
739 | /* |
740 | * Pipe pixel rate, adjusted for | |
741 | * panel fitter/pipe scaler downscaling. | |
742 | */ | |
743 | unsigned int pixel_rate; | |
744 | ||
5bfe2ac0 DV |
745 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
746 | * between pch encoders and cpu encoders. */ | |
747 | bool has_pch_encoder; | |
50f3b016 | 748 | |
e43823ec JB |
749 | /* Are we sending infoframes on the attached port */ |
750 | bool has_infoframe; | |
751 | ||
3b117c8f | 752 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
753 | * pipe on Haswell and later (where we have a special eDP transcoder) |
754 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
755 | enum transcoder cpu_transcoder; |
756 | ||
50f3b016 DV |
757 | /* |
758 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
759 | * range fed into the crtcs. | |
760 | */ | |
761 | bool limited_color_range; | |
762 | ||
253c84c8 VS |
763 | /* Bitmask of encoder types (enum intel_output_type) |
764 | * driven by the pipe. | |
765 | */ | |
766 | unsigned int output_types; | |
767 | ||
6897b4b5 DV |
768 | /* Whether we should send NULL infoframes. Required for audio. */ |
769 | bool has_hdmi_sink; | |
770 | ||
9ed109a7 DV |
771 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
772 | * has_dp_encoder is set. */ | |
773 | bool has_audio; | |
774 | ||
d8b32247 DV |
775 | /* |
776 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
777 | * plane bpp. | |
778 | */ | |
965e0c48 | 779 | bool dither; |
f47709a9 | 780 | |
611032bf MN |
781 | /* |
782 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for | |
783 | * compliance video pattern tests. | |
784 | * Disable dither only if it is a compliance test request for | |
785 | * 18bpp. | |
786 | */ | |
787 | bool dither_force_disable; | |
788 | ||
f47709a9 DV |
789 | /* Controls for the clock computation, to override various stages. */ |
790 | bool clock_set; | |
791 | ||
09ede541 DV |
792 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
793 | * work correctly, we need to track this at runtime.*/ | |
794 | bool sdvo_tv_clock; | |
795 | ||
e29c22c0 DV |
796 | /* |
797 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
798 | * required. This is set in the 2nd loop of calling encoder's | |
799 | * ->compute_config if the first pick doesn't work out. | |
800 | */ | |
801 | bool bw_constrained; | |
802 | ||
f47709a9 DV |
803 | /* Settings for the intel dpll used on pretty much everything but |
804 | * haswell. */ | |
80ad9206 | 805 | struct dpll dpll; |
f47709a9 | 806 | |
8106ddbd ACO |
807 | /* Selected dpll when shared or NULL. */ |
808 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 809 | |
66e985c0 DV |
810 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
811 | struct intel_dpll_hw_state dpll_hw_state; | |
812 | ||
47eacbab VS |
813 | /* DSI PLL registers */ |
814 | struct { | |
815 | u32 ctrl, div; | |
816 | } dsi_pll; | |
817 | ||
965e0c48 | 818 | int pipe_bpp; |
6cf86a5e | 819 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 820 | |
439d7ac0 PB |
821 | /* m2_n2 for eDP downclock */ |
822 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 823 | bool has_drrs; |
439d7ac0 | 824 | |
4d90f2d5 VS |
825 | bool has_psr; |
826 | bool has_psr2; | |
827 | ||
ff9a6750 DV |
828 | /* |
829 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
830 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
831 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 832 | */ |
ff9a6750 DV |
833 | int port_clock; |
834 | ||
6cc5f341 DV |
835 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
836 | unsigned pixel_multiplier; | |
2dd24552 | 837 | |
d25236a3 | 838 | u8 lane_count; |
90a6b7b0 | 839 | |
95a7a2ae ID |
840 | /* |
841 | * Used by platforms having DP/HDMI PHY with programmable lane | |
842 | * latency optimization. | |
843 | */ | |
d25236a3 | 844 | u8 lane_lat_optim_mask; |
95a7a2ae | 845 | |
53e9bf5e VS |
846 | /* minimum acceptable voltage level */ |
847 | u8 min_voltage_level; | |
848 | ||
2dd24552 | 849 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
850 | struct { |
851 | u32 control; | |
852 | u32 pgm_ratios; | |
68fc8742 | 853 | u32 lvds_border_bits; |
b074cec8 JB |
854 | } gmch_pfit; |
855 | ||
856 | /* Panel fitter placement and size for Ironlake+ */ | |
857 | struct { | |
858 | u32 pos; | |
859 | u32 size; | |
fd4daa9c | 860 | bool enabled; |
fabf6e51 | 861 | bool force_thru; |
b074cec8 | 862 | } pch_pfit; |
33d29b14 | 863 | |
ca3a0ff8 | 864 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 865 | int fdi_lanes; |
ca3a0ff8 | 866 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
867 | |
868 | bool ips_enabled; | |
a8ebf607 JRS |
869 | |
870 | bool crc_enabled; | |
cf532bb2 | 871 | |
f51be2e0 PZ |
872 | bool enable_fbc; |
873 | ||
cf532bb2 | 874 | bool double_wide; |
0e32b39c | 875 | |
0e32b39c | 876 | int pbn; |
be41e336 CK |
877 | |
878 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
879 | |
880 | /* w/a for waiting 2 vblanks during crtc enable */ | |
881 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
882 | |
883 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
884 | bool disable_lp_wm; | |
4e0963c7 | 885 | |
e8f1f02e | 886 | struct intel_crtc_wm_state wm; |
05dc698c LL |
887 | |
888 | /* Gamma mode programmed on the pipe */ | |
d25236a3 | 889 | u32 gamma_mode; |
e9728bd8 | 890 | |
9fdfb8e7 VS |
891 | union { |
892 | /* CSC mode programmed on the pipe */ | |
893 | u32 csc_mode; | |
894 | ||
895 | /* CHV CGM mode */ | |
896 | u32 cgm_mode; | |
897 | }; | |
a91de580 | 898 | |
e9728bd8 VS |
899 | /* bitmask of visible planes (enum plane_id) */ |
900 | u8 active_planes; | |
8e021151 | 901 | u8 nv12_planes; |
02c52f1e | 902 | u8 c8_planes; |
15953637 | 903 | |
afbd8a72 VS |
904 | /* bitmask of planes that will be updated during the commit */ |
905 | u8 update_planes; | |
906 | ||
e5e70d4a VS |
907 | struct { |
908 | u32 enable; | |
fbf08556 VS |
909 | u32 gcp; |
910 | union hdmi_infoframe avi; | |
911 | union hdmi_infoframe spd; | |
912 | union hdmi_infoframe hdmi; | |
e5e70d4a VS |
913 | } infoframes; |
914 | ||
15953637 SS |
915 | /* HDMI scrambling status */ |
916 | bool hdmi_scrambling; | |
917 | ||
918 | /* HDMI High TMDS char rate ratio */ | |
919 | bool hdmi_high_tmds_clock_ratio; | |
60436fd4 | 920 | |
d9facae6 SS |
921 | /* Output format RGB/YCBCR etc */ |
922 | enum intel_output_format output_format; | |
668b6c17 SS |
923 | |
924 | /* Output down scaling is done in LSPCON device */ | |
925 | bool lspcon_downsampling; | |
7b610f1f | 926 | |
5f29ab23 VS |
927 | /* enable pipe gamma? */ |
928 | bool gamma_enable; | |
929 | ||
8271b2ef VS |
930 | /* enable pipe csc? */ |
931 | bool csc_enable; | |
932 | ||
7b610f1f MN |
933 | /* Display Stream compression state */ |
934 | struct { | |
935 | bool compression_enable; | |
936 | bool dsc_split; | |
937 | u16 compressed_bpp; | |
938 | u8 slice_count; | |
939 | } dsc_params; | |
940 | struct drm_dsc_config dp_dsc_cfg; | |
240999cf AS |
941 | |
942 | /* Forward Error correction State */ | |
943 | bool fec_enable; | |
b8cecdf5 DV |
944 | }; |
945 | ||
79e53945 JB |
946 | struct intel_crtc { |
947 | struct drm_crtc base; | |
80824003 | 948 | enum pipe pipe; |
08a48469 DV |
949 | /* |
950 | * Whether the crtc and the connected output pipeline is active. Implies | |
951 | * that crtc->enabled is set, i.e. the current mode configuration has | |
952 | * some outputs connected to this crtc. | |
08a48469 DV |
953 | */ |
954 | bool active; | |
d97d7b48 | 955 | u8 plane_ids_mask; |
d8fc70b7 | 956 | unsigned long long enabled_power_domains; |
02e792fb | 957 | struct intel_overlay *overlay; |
cda4b7d3 | 958 | |
6e3c9717 | 959 | struct intel_crtc_state *config; |
b8cecdf5 | 960 | |
8664281b PZ |
961 | /* Access to these should be protected by dev_priv->irq_lock. */ |
962 | bool cpu_fifo_underrun_disabled; | |
963 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
964 | |
965 | /* per-pipe watermark state */ | |
966 | struct { | |
967 | /* watermarks currently being used */ | |
4e0963c7 MR |
968 | union { |
969 | struct intel_pipe_wm ilk; | |
7eb4941f | 970 | struct vlv_wm_state vlv; |
04548cba | 971 | struct g4x_wm_state g4x; |
4e0963c7 | 972 | } active; |
0b2ae6d7 | 973 | } wm; |
8d7849db | 974 | |
80715b2f | 975 | int scanline_offset; |
32b7eeec | 976 | |
eb120ef6 JB |
977 | struct { |
978 | unsigned start_vbl_count; | |
979 | ktime_t start_vbl_time; | |
980 | int min_vbl, max_vbl; | |
981 | int scanline_start; | |
982 | } debug; | |
85a62bf9 | 983 | |
be41e336 CK |
984 | /* scalers available on this crtc */ |
985 | int num_scalers; | |
79e53945 JB |
986 | }; |
987 | ||
b840d907 JB |
988 | struct intel_plane { |
989 | struct drm_plane base; | |
ed15030d | 990 | enum i9xx_plane_id i9xx_plane; |
b14e5848 | 991 | enum plane_id id; |
b840d907 | 992 | enum pipe pipe; |
cf1805e6 | 993 | bool has_fbc; |
a38189c5 | 994 | bool has_ccs; |
d25236a3 | 995 | u32 frontbuffer_bit; |
526682e9 | 996 | |
cd5dcbf1 VS |
997 | struct { |
998 | u32 base, cntl, size; | |
999 | } cursor; | |
1000 | ||
8e7d688b MR |
1001 | /* |
1002 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
1003 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 1004 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
1005 | */ |
1006 | ||
ddd5713d VS |
1007 | unsigned int (*max_stride)(struct intel_plane *plane, |
1008 | u32 pixel_format, u64 modifier, | |
1009 | unsigned int rotation); | |
282dbf9b | 1010 | void (*update_plane)(struct intel_plane *plane, |
2fde1391 ML |
1011 | const struct intel_crtc_state *crtc_state, |
1012 | const struct intel_plane_state *plane_state); | |
1ab554b0 ML |
1013 | void (*update_slave)(struct intel_plane *plane, |
1014 | const struct intel_crtc_state *crtc_state, | |
1015 | const struct intel_plane_state *plane_state); | |
282dbf9b | 1016 | void (*disable_plane)(struct intel_plane *plane, |
0dd14be3 | 1017 | const struct intel_crtc_state *crtc_state); |
eade6c89 | 1018 | bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); |
eb0f5044 VS |
1019 | int (*check_plane)(struct intel_crtc_state *crtc_state, |
1020 | struct intel_plane_state *plane_state); | |
b840d907 JB |
1021 | }; |
1022 | ||
b445e3b0 | 1023 | struct intel_watermark_params { |
ae9400ca TU |
1024 | u16 fifo_size; |
1025 | u16 max_wm; | |
1026 | u8 default_wm; | |
1027 | u8 guard_size; | |
1028 | u8 cacheline_size; | |
b445e3b0 ED |
1029 | }; |
1030 | ||
1031 | struct cxsr_latency { | |
c13fb778 TU |
1032 | bool is_desktop : 1; |
1033 | bool is_ddr3 : 1; | |
44a655ca TU |
1034 | u16 fsb_freq; |
1035 | u16 mem_freq; | |
1036 | u16 display_sr; | |
1037 | u16 display_hpll_disable; | |
1038 | u16 cursor_sr; | |
1039 | u16 cursor_hpll_disable; | |
b445e3b0 ED |
1040 | }; |
1041 | ||
de419ab6 | 1042 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 1043 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 1044 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 1045 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 1046 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 1047 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 1048 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 1049 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
a268bcd7 | 1050 | #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) |
79e53945 | 1051 | |
f5bbfca3 | 1052 | struct intel_hdmi { |
f0f59a00 | 1053 | i915_reg_t hdmi_reg; |
f5bbfca3 | 1054 | int ddc_bus; |
b1ba124d VS |
1055 | struct { |
1056 | enum drm_dp_dual_mode_type type; | |
1057 | int max_tmds_clock; | |
1058 | } dp_dual_mode; | |
f5bbfca3 ED |
1059 | bool has_hdmi_sink; |
1060 | bool has_audio; | |
d8b4c43a | 1061 | struct intel_connector *attached_connector; |
9c229127 | 1062 | struct cec_notifier *cec_notifier; |
f5bbfca3 ED |
1063 | }; |
1064 | ||
0e32b39c | 1065 | struct intel_dp_mst_encoder; |
b091cd92 | 1066 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 1067 | |
fe3cd48d R |
1068 | /* |
1069 | * enum link_m_n_set: | |
1070 | * When platform provides two set of M_N registers for dp, we can | |
1071 | * program them and switch between them incase of DRRS. | |
1072 | * But When only one such register is provided, we have to program the | |
1073 | * required divider value on that registers itself based on the DRRS state. | |
1074 | * | |
1075 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
1076 | * dp_m2_n2 on M2_N2 registers (If supported) | |
1077 | * | |
1078 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
1079 | * M2_N2 registers are not supported | |
1080 | */ | |
1081 | ||
1082 | enum link_m_n_set { | |
1083 | /* Sets the m1_n1 and m2_n2 */ | |
1084 | M1_N1 = 0, | |
1085 | M2_N2 | |
1086 | }; | |
1087 | ||
c1617abc MN |
1088 | struct intel_dp_compliance_data { |
1089 | unsigned long edid; | |
d25236a3 JN |
1090 | u8 video_pattern; |
1091 | u16 hdisplay, vdisplay; | |
1092 | u8 bpc; | |
c1617abc MN |
1093 | }; |
1094 | ||
1095 | struct intel_dp_compliance { | |
1096 | unsigned long test_type; | |
1097 | struct intel_dp_compliance_data test_data; | |
1098 | bool test_active; | |
da15f7cb MN |
1099 | int test_link_rate; |
1100 | u8 test_lane_count; | |
c1617abc MN |
1101 | }; |
1102 | ||
54d63ca6 | 1103 | struct intel_dp { |
f0f59a00 | 1104 | i915_reg_t output_reg; |
d25236a3 | 1105 | u32 DP; |
901c2daf | 1106 | int link_rate; |
d25236a3 JN |
1107 | u8 lane_count; |
1108 | u8 sink_count; | |
64ee2fd2 | 1109 | bool link_mst; |
edb2e530 | 1110 | bool link_trained; |
54d63ca6 | 1111 | bool has_audio; |
d7e8ef02 | 1112 | bool reset_link_params; |
d25236a3 JN |
1113 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1114 | u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; | |
1115 | u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; | |
1116 | u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; | |
93ac092f | 1117 | u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; |
08cadae8 | 1118 | u8 fec_capable; |
55cfc580 JN |
1119 | /* source rates */ |
1120 | int num_source_rates; | |
1121 | const int *source_rates; | |
68f357cb JN |
1122 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
1123 | int num_sink_rates; | |
94ca719e | 1124 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
68f357cb | 1125 | bool use_rate_select; |
975ee5fc JN |
1126 | /* intersection of source and sink rates */ |
1127 | int num_common_rates; | |
1128 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
e6c0c64a JN |
1129 | /* Max lane count for the current link */ |
1130 | int max_link_lane_count; | |
1131 | /* Max rate for the current link */ | |
1132 | int max_link_rate; | |
7b3fc170 | 1133 | /* sink or branch descriptor */ |
84c36753 | 1134 | struct drm_dp_desc desc; |
9d1a1031 | 1135 | struct drm_dp_aux aux; |
d25236a3 | 1136 | u8 train_set[4]; |
54d63ca6 SK |
1137 | int panel_power_up_delay; |
1138 | int panel_power_down_delay; | |
1139 | int panel_power_cycle_delay; | |
1140 | int backlight_on_delay; | |
1141 | int backlight_off_delay; | |
54d63ca6 SK |
1142 | struct delayed_work panel_vdd_work; |
1143 | bool want_panel_vdd; | |
dce56b3c PZ |
1144 | unsigned long last_power_on; |
1145 | unsigned long last_backlight_off; | |
d28d4731 | 1146 | ktime_t panel_power_off_time; |
5d42f82a | 1147 | |
01527b31 CT |
1148 | struct notifier_block edp_notifier; |
1149 | ||
a4a5d2f8 VS |
1150 | /* |
1151 | * Pipe whose power sequencer is currently locked into | |
1152 | * this port. Only relevant on VLV/CHV. | |
1153 | */ | |
1154 | enum pipe pps_pipe; | |
9f2bdb00 VS |
1155 | /* |
1156 | * Pipe currently driving the port. Used for preventing | |
1157 | * the use of the PPS for any pipe currentrly driving | |
1158 | * external DP as that will mess things up on VLV. | |
1159 | */ | |
1160 | enum pipe active_pipe; | |
78597996 ID |
1161 | /* |
1162 | * Set if the sequencer may be reset due to a power transition, | |
1163 | * requiring a reinitialization. Only relevant on BXT. | |
1164 | */ | |
1165 | bool pps_reset; | |
36b5f425 | 1166 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 1167 | |
0e32b39c DA |
1168 | bool can_mst; /* this port supports mst */ |
1169 | bool is_mst; | |
19e0b4ca | 1170 | int active_mst_links; |
0e32b39c | 1171 | /* connector directly attached - won't be use for modeset in mst world */ |
dd06f90e | 1172 | struct intel_connector *attached_connector; |
ec5b01dd | 1173 | |
0e32b39c DA |
1174 | /* mst connector list */ |
1175 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
1176 | struct drm_dp_mst_topology_mgr mst_mgr; | |
1177 | ||
d25236a3 | 1178 | u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
1179 | /* |
1180 | * This function returns the value we have to program the AUX_CTL | |
1181 | * register with to kick off an AUX transaction. | |
1182 | */ | |
d25236a3 JN |
1183 | u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, |
1184 | u32 aux_clock_divider); | |
ad64217b | 1185 | |
4904fa66 VS |
1186 | i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); |
1187 | i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); | |
1188 | ||
ad64217b ACO |
1189 | /* This is called before a link training is starterd */ |
1190 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
1191 | ||
c5d5ab7a | 1192 | /* Displayport compliance testing */ |
c1617abc | 1193 | struct intel_dp_compliance compliance; |
e845f099 MN |
1194 | |
1195 | /* Display stream compression testing */ | |
1196 | bool force_dsc_en; | |
54d63ca6 SK |
1197 | }; |
1198 | ||
96e35598 SS |
1199 | enum lspcon_vendor { |
1200 | LSPCON_VENDOR_MCA, | |
1201 | LSPCON_VENDOR_PARADE | |
1202 | }; | |
1203 | ||
dbe9e61b SS |
1204 | struct intel_lspcon { |
1205 | bool active; | |
1206 | enum drm_lspcon_mode mode; | |
96e35598 | 1207 | enum lspcon_vendor vendor; |
dbe9e61b SS |
1208 | }; |
1209 | ||
da63a9f2 PZ |
1210 | struct intel_digital_port { |
1211 | struct intel_encoder base; | |
bcf53de4 | 1212 | u32 saved_port_bits; |
da63a9f2 PZ |
1213 | struct intel_dp dp; |
1214 | struct intel_hdmi hdmi; | |
dbe9e61b | 1215 | struct intel_lspcon lspcon; |
b2c5c181 | 1216 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 1217 | bool release_cl2_override; |
d25236a3 | 1218 | u8 max_lanes; |
563d22a0 ID |
1219 | /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ |
1220 | enum aux_ch aux_ch; | |
62b69566 | 1221 | enum intel_display_power_domain ddi_io_power_domain; |
f6bff60e | 1222 | bool tc_legacy_port:1; |
6075546f | 1223 | enum tc_port_type tc_type; |
f99be1b3 | 1224 | |
790ea70c | 1225 | void (*write_infoframe)(struct intel_encoder *encoder, |
f99be1b3 | 1226 | const struct intel_crtc_state *crtc_state, |
1d776538 | 1227 | unsigned int type, |
f99be1b3 | 1228 | const void *frame, ssize_t len); |
f2a10d61 VS |
1229 | void (*read_infoframe)(struct intel_encoder *encoder, |
1230 | const struct intel_crtc_state *crtc_state, | |
1231 | unsigned int type, | |
1232 | void *frame, ssize_t len); | |
790ea70c | 1233 | void (*set_infoframes)(struct intel_encoder *encoder, |
f99be1b3 VS |
1234 | bool enable, |
1235 | const struct intel_crtc_state *crtc_state, | |
1236 | const struct drm_connector_state *conn_state); | |
509efa2b | 1237 | u32 (*infoframes_enabled)(struct intel_encoder *encoder, |
f99be1b3 | 1238 | const struct intel_crtc_state *pipe_config); |
da63a9f2 PZ |
1239 | }; |
1240 | ||
0e32b39c DA |
1241 | struct intel_dp_mst_encoder { |
1242 | struct intel_encoder base; | |
1243 | enum pipe pipe; | |
1244 | struct intel_digital_port *primary; | |
0552f765 | 1245 | struct intel_connector *connector; |
0e32b39c DA |
1246 | }; |
1247 | ||
65d64cc5 | 1248 | static inline enum dpio_channel |
89b667f8 JB |
1249 | vlv_dport_to_channel(struct intel_digital_port *dport) |
1250 | { | |
8f4f2797 | 1251 | switch (dport->base.port) { |
89b667f8 | 1252 | case PORT_B: |
00fc31b7 | 1253 | case PORT_D: |
e4607fcf | 1254 | return DPIO_CH0; |
89b667f8 | 1255 | case PORT_C: |
e4607fcf | 1256 | return DPIO_CH1; |
89b667f8 JB |
1257 | default: |
1258 | BUG(); | |
1259 | } | |
1260 | } | |
1261 | ||
65d64cc5 VS |
1262 | static inline enum dpio_phy |
1263 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
1264 | { | |
8f4f2797 | 1265 | switch (dport->base.port) { |
65d64cc5 VS |
1266 | case PORT_B: |
1267 | case PORT_C: | |
1268 | return DPIO_PHY0; | |
1269 | case PORT_D: | |
1270 | return DPIO_PHY1; | |
1271 | default: | |
1272 | BUG(); | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | static inline enum dpio_channel | |
eb69b0e5 CML |
1277 | vlv_pipe_to_channel(enum pipe pipe) |
1278 | { | |
1279 | switch (pipe) { | |
1280 | case PIPE_A: | |
1281 | case PIPE_C: | |
1282 | return DPIO_CH0; | |
1283 | case PIPE_B: | |
1284 | return DPIO_CH1; | |
1285 | default: | |
1286 | BUG(); | |
1287 | } | |
1288 | } | |
1289 | ||
e2af48c6 | 1290 | static inline struct intel_crtc * |
b91eb5cc | 1291 | intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
f875c15a | 1292 | { |
f875c15a CW |
1293 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
1294 | } | |
1295 | ||
e2af48c6 | 1296 | static inline struct intel_crtc * |
ed15030d | 1297 | intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) |
417ae147 | 1298 | { |
417ae147 CW |
1299 | return dev_priv->plane_to_crtc_mapping[plane]; |
1300 | } | |
1301 | ||
5f1aae65 | 1302 | struct intel_load_detect_pipe { |
edde3617 | 1303 | struct drm_atomic_state *restore_state; |
5f1aae65 | 1304 | }; |
79e53945 | 1305 | |
5f1aae65 PZ |
1306 | static inline struct intel_encoder * |
1307 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
1308 | { |
1309 | return to_intel_connector(connector)->encoder; | |
1310 | } | |
1311 | ||
4ef03f83 | 1312 | static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) |
da63a9f2 | 1313 | { |
4ef03f83 | 1314 | switch (encoder->type) { |
7e732cac | 1315 | case INTEL_OUTPUT_DDI: |
9a5da00b ACO |
1316 | case INTEL_OUTPUT_DP: |
1317 | case INTEL_OUTPUT_EDP: | |
1318 | case INTEL_OUTPUT_HDMI: | |
4ef03f83 VS |
1319 | return true; |
1320 | default: | |
1321 | return false; | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | static inline struct intel_digital_port * | |
1326 | enc_to_dig_port(struct drm_encoder *encoder) | |
1327 | { | |
1328 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
1329 | ||
1330 | if (intel_encoder_is_dig_port(intel_encoder)) | |
9a5da00b ACO |
1331 | return container_of(encoder, struct intel_digital_port, |
1332 | base.base); | |
4ef03f83 | 1333 | else |
9a5da00b | 1334 | return NULL; |
9ff8c9ba ID |
1335 | } |
1336 | ||
bdc93fe0 R |
1337 | static inline struct intel_digital_port * |
1338 | conn_to_dig_port(struct intel_connector *connector) | |
1339 | { | |
1340 | return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base); | |
1341 | } | |
1342 | ||
0e32b39c DA |
1343 | static inline struct intel_dp_mst_encoder * |
1344 | enc_to_mst(struct drm_encoder *encoder) | |
1345 | { | |
1346 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
1347 | } | |
1348 | ||
9ff8c9ba ID |
1349 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1350 | { | |
1351 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1352 | } |
1353 | ||
14aa521c VS |
1354 | static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) |
1355 | { | |
1356 | switch (encoder->type) { | |
1357 | case INTEL_OUTPUT_DP: | |
1358 | case INTEL_OUTPUT_EDP: | |
1359 | return true; | |
1360 | case INTEL_OUTPUT_DDI: | |
1361 | /* Skip pure HDMI/DVI DDI encoders */ | |
1362 | return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg); | |
1363 | default: | |
1364 | return false; | |
1365 | } | |
1366 | } | |
1367 | ||
06c812d7 SS |
1368 | static inline struct intel_lspcon * |
1369 | enc_to_intel_lspcon(struct drm_encoder *encoder) | |
1370 | { | |
1371 | return &enc_to_dig_port(encoder)->lspcon; | |
1372 | } | |
1373 | ||
da63a9f2 PZ |
1374 | static inline struct intel_digital_port * |
1375 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1376 | { | |
1377 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1378 | } | |
1379 | ||
dd75f6dd ID |
1380 | static inline struct intel_lspcon * |
1381 | dp_to_lspcon(struct intel_dp *intel_dp) | |
1382 | { | |
1383 | return &dp_to_dig_port(intel_dp)->lspcon; | |
1384 | } | |
1385 | ||
de25eb7f RV |
1386 | static inline struct drm_i915_private * |
1387 | dp_to_i915(struct intel_dp *intel_dp) | |
1388 | { | |
1389 | return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
1390 | } | |
1391 | ||
da63a9f2 PZ |
1392 | static inline struct intel_digital_port * |
1393 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1394 | { | |
1395 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1396 | } |
1397 | ||
1ab554b0 ML |
1398 | static inline struct intel_plane_state * |
1399 | intel_atomic_get_plane_state(struct intel_atomic_state *state, | |
1400 | struct intel_plane *plane) | |
1401 | { | |
1402 | struct drm_plane_state *ret = | |
1403 | drm_atomic_get_plane_state(&state->base, &plane->base); | |
1404 | ||
1405 | if (IS_ERR(ret)) | |
1406 | return ERR_CAST(ret); | |
1407 | ||
1408 | return to_intel_plane_state(ret); | |
1409 | } | |
1410 | ||
1411 | static inline struct intel_plane_state * | |
1412 | intel_atomic_get_old_plane_state(struct intel_atomic_state *state, | |
1413 | struct intel_plane *plane) | |
1414 | { | |
1415 | return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, | |
1416 | &plane->base)); | |
1417 | } | |
1418 | ||
b2b55502 VS |
1419 | static inline struct intel_plane_state * |
1420 | intel_atomic_get_new_plane_state(struct intel_atomic_state *state, | |
1421 | struct intel_plane *plane) | |
1422 | { | |
1423 | return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, | |
1424 | &plane->base)); | |
1425 | } | |
1426 | ||
7b510451 VS |
1427 | static inline struct intel_crtc_state * |
1428 | intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, | |
1429 | struct intel_crtc *crtc) | |
1430 | { | |
1431 | return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, | |
1432 | &crtc->base)); | |
1433 | } | |
1434 | ||
d3a8fb32 VS |
1435 | static inline struct intel_crtc_state * |
1436 | intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, | |
1437 | struct intel_crtc *crtc) | |
1438 | { | |
1439 | return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, | |
1440 | &crtc->base)); | |
1441 | } | |
1442 | ||
b680c37a | 1443 | /* intel_display.c */ |
27fec1f9 | 1444 | void intel_plane_destroy(struct drm_plane *plane); |
2ee0da16 VS |
1445 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); |
1446 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
a2196033 | 1447 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); |
49cd97a3 | 1448 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1449 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1450 | const char *name, u32 reg, int ref_freq); | |
7ff89ca2 VS |
1451 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
1452 | const char *name, u32 reg); | |
b7076546 ML |
1453 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); |
1454 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
88212941 | 1455 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
6687c906 | 1456 | unsigned int intel_fb_xy_to_linear(int x, int y, |
2949056c VS |
1457 | const struct intel_plane_state *state, |
1458 | int plane); | |
fdc24cf3 JN |
1459 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, |
1460 | int color_plane, unsigned int height); | |
6687c906 | 1461 | void intel_add_fb_offsets(int *x, int *y, |
2949056c | 1462 | const struct intel_plane_state *state, int plane); |
1663b9d6 | 1463 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
1a74fc0b | 1464 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); |
49d73912 | 1465 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); |
7d993739 TU |
1466 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1467 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
70e0bd74 | 1468 | int intel_display_suspend(struct drm_device *dev); |
8090ba8c | 1469 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); |
87440425 | 1470 | void intel_encoder_destroy(struct drm_encoder *encoder); |
de330815 VS |
1471 | struct drm_display_mode * |
1472 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
176597a1 | 1473 | bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port); |
ac213c1b PZ |
1474 | bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); |
1475 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, | |
1476 | enum port port); | |
6a20fe7b VS |
1477 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
1478 | struct drm_file *file_priv); | |
87440425 PZ |
1479 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1480 | enum pipe pipe); | |
2d84d2b3 VS |
1481 | static inline bool |
1482 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, | |
1483 | enum intel_output_type type) | |
1484 | { | |
1485 | return crtc_state->output_types & (1 << type); | |
1486 | } | |
37a5650b VS |
1487 | static inline bool |
1488 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) | |
1489 | { | |
1490 | return crtc_state->output_types & | |
cca0502b | 1491 | ((1 << INTEL_OUTPUT_DP) | |
37a5650b VS |
1492 | (1 << INTEL_OUTPUT_DP_MST) | |
1493 | (1 << INTEL_OUTPUT_EDP)); | |
1494 | } | |
4f905cf9 | 1495 | static inline void |
0f0f74bc | 1496 | intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) |
4f905cf9 | 1497 | { |
0f0f74bc | 1498 | drm_wait_one_vblank(&dev_priv->drm, pipe); |
4f905cf9 | 1499 | } |
0c241d5b | 1500 | static inline void |
0f0f74bc | 1501 | intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) |
0c241d5b | 1502 | { |
b91eb5cc | 1503 | const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
0c241d5b VS |
1504 | |
1505 | if (crtc->active) | |
0f0f74bc | 1506 | intel_wait_for_vblank(dev_priv, pipe); |
0c241d5b | 1507 | } |
a2991414 ML |
1508 | |
1509 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
1510 | ||
87440425 | 1511 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1512 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1513 | struct intel_digital_port *dport, |
1514 | unsigned int expected_mask); | |
6c5ed5ae | 1515 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 1516 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
1517 | struct intel_load_detect_pipe *old, |
1518 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1519 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1520 | struct intel_load_detect_pipe *old, |
1521 | struct drm_modeset_acquire_ctx *ctx); | |
058d88c4 | 1522 | struct i915_vma * |
5935485f | 1523 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
f5929c53 | 1524 | const struct i915_ggtt_view *view, |
f7a02ad7 | 1525 | bool uses_fence, |
5935485f CW |
1526 | unsigned long *out_flags); |
1527 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); | |
a8bb6818 | 1528 | struct drm_framebuffer * |
24dbf51a CW |
1529 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
1530 | struct drm_mode_fb_cmd2 *mode_cmd); | |
6beb8c23 | 1531 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1832040d | 1532 | struct drm_plane_state *new_state); |
38f3ce3a | 1533 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
1832040d | 1534 | struct drm_plane_state *old_state); |
a98b3431 MR |
1535 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1536 | const struct drm_plane_state *state, | |
1537 | struct drm_property *property, | |
d25236a3 | 1538 | u64 *val); |
a98b3431 MR |
1539 | int intel_plane_atomic_set_property(struct drm_plane *plane, |
1540 | struct drm_plane_state *state, | |
1541 | struct drm_property *property, | |
d25236a3 | 1542 | u64 val); |
b2b55502 VS |
1543 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
1544 | struct drm_crtc_state *crtc_state, | |
1545 | const struct intel_plane_state *old_plane_state, | |
da20eabd | 1546 | struct drm_plane_state *plane_state); |
716c2e55 | 1547 | |
7abd4b35 ACO |
1548 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1549 | enum pipe pipe); | |
1550 | ||
30ad9814 | 1551 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 1552 | const struct dpll *dpll); |
30ad9814 | 1553 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); |
8802e5b6 | 1554 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1555 | |
716c2e55 | 1556 | /* modesetting asserts */ |
b680c37a DV |
1557 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1558 | enum pipe pipe); | |
55607e8a DV |
1559 | void assert_pll(struct drm_i915_private *dev_priv, |
1560 | enum pipe pipe, bool state); | |
1561 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1562 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1563 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1564 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1565 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1566 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1567 | enum pipe pipe, bool state); | |
1568 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1569 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1570 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1571 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1572 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
c033666a CW |
1573 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1574 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
c89e39f3 | 1575 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
87440425 | 1576 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1577 | struct intel_crtc_state *pipe_config); |
4c354754 ML |
1578 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, |
1579 | enum link_m_n_set m_n); | |
3c053a96 GM |
1580 | void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, |
1581 | const struct intel_crtc_state *crtc_state); | |
87440425 | 1582 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
e40396d0 | 1583 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
1584 | struct dpll *best_clock); |
1585 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1586 | |
525b9311 | 1587 | bool intel_crtc_active(struct intel_crtc *crtc); |
24f28450 | 1588 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); |
199ea381 ML |
1589 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state); |
1590 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state); | |
79f255a0 | 1591 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); |
337837ac ID |
1592 | enum intel_display_power_domain |
1593 | intel_aux_power_domain(struct intel_digital_port *dig_port); | |
f6a83288 | 1594 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1595 | struct intel_crtc_state *pipe_config); |
d52ad9cb ML |
1596 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
1597 | struct intel_crtc_state *crtc_state); | |
86adf9d7 | 1598 | |
e7a278a3 | 1599 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); |
e435d6e5 | 1600 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
4e0b83a5 VS |
1601 | int skl_max_scale(const struct intel_crtc_state *crtc_state, |
1602 | u32 pixel_format); | |
8ea30864 | 1603 | |
be1e3415 CW |
1604 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) |
1605 | { | |
1606 | return i915_ggtt_offset(state->vma); | |
1607 | } | |
dedf278c | 1608 | |
4036c78c JA |
1609 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
1610 | const struct intel_plane_state *plane_state); | |
7eb31a0b | 1611 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); |
2e881264 VS |
1612 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
1613 | const struct intel_plane_state *plane_state); | |
7eb31a0b | 1614 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); |
df79cf44 VS |
1615 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
1616 | int plane); | |
73266595 | 1617 | int skl_check_plane_surface(struct intel_plane_state *plane_state); |
f9407ae1 | 1618 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); |
ddf34319 | 1619 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); |
ddd5713d VS |
1620 | unsigned int i9xx_plane_max_stride(struct intel_plane *plane, |
1621 | u32 pixel_format, u64 modifier, | |
1622 | unsigned int rotation); | |
8ae89743 | 1623 | int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); |
121920fa | 1624 | |
9c065a7d | 1625 | /* intel_runtime_pm.c */ |
4547c255 ID |
1626 | #define BITS_PER_WAKEREF \ |
1627 | BITS_PER_TYPE(struct_member(struct i915_runtime_pm, wakeref_count)) | |
1628 | #define INTEL_RPM_WAKELOCK_SHIFT (BITS_PER_WAKEREF / 2) | |
1629 | #define INTEL_RPM_WAKELOCK_BIAS (1 << INTEL_RPM_WAKELOCK_SHIFT) | |
1630 | #define INTEL_RPM_RAW_WAKEREF_MASK (INTEL_RPM_WAKELOCK_BIAS - 1) | |
1631 | ||
1632 | static inline int | |
1633 | intel_rpm_raw_wakeref_count(int wakeref_count) | |
1634 | { | |
1635 | return wakeref_count & INTEL_RPM_RAW_WAKEREF_MASK; | |
1636 | } | |
1637 | ||
1638 | static inline int | |
1639 | intel_rpm_wakelock_count(int wakeref_count) | |
1640 | { | |
1641 | return wakeref_count >> INTEL_RPM_WAKELOCK_SHIFT; | |
1642 | } | |
1643 | ||
da5827c3 | 1644 | static inline void |
eb17af67 | 1645 | assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm) |
da5827c3 | 1646 | { |
eb17af67 | 1647 | WARN_ONCE(rpm->suspended, |
da5827c3 ID |
1648 | "Device suspended during HW access\n"); |
1649 | } | |
1650 | ||
1651 | static inline void | |
4547c255 | 1652 | ____assert_rpm_raw_wakeref_held(struct i915_runtime_pm *rpm, int wakeref_count) |
da5827c3 | 1653 | { |
eb17af67 | 1654 | assert_rpm_device_not_suspended(rpm); |
4547c255 ID |
1655 | WARN_ONCE(!intel_rpm_raw_wakeref_count(wakeref_count), |
1656 | "RPM raw-wakeref not held\n"); | |
1657 | } | |
1658 | ||
1659 | static inline void | |
1660 | ____assert_rpm_wakelock_held(struct i915_runtime_pm *rpm, int wakeref_count) | |
1661 | { | |
1662 | ____assert_rpm_raw_wakeref_held(rpm, wakeref_count); | |
1663 | WARN_ONCE(!intel_rpm_wakelock_count(wakeref_count), | |
1664 | "RPM wakelock ref not held during HW access\n"); | |
1665 | } | |
1666 | ||
1667 | static inline void | |
1668 | assert_rpm_raw_wakeref_held(struct drm_i915_private *i915) | |
1669 | { | |
1670 | struct i915_runtime_pm *rpm = &i915->runtime_pm; | |
1671 | ||
1672 | ____assert_rpm_raw_wakeref_held(rpm, atomic_read(&rpm->wakeref_count)); | |
1673 | } | |
1674 | ||
1675 | static inline void | |
1676 | __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm) | |
1677 | { | |
1678 | ____assert_rpm_wakelock_held(rpm, atomic_read(&rpm->wakeref_count)); | |
da5827c3 ID |
1679 | } |
1680 | ||
eb17af67 DCS |
1681 | static inline void |
1682 | assert_rpm_wakelock_held(struct drm_i915_private *i915) | |
1683 | { | |
1684 | __assert_rpm_wakelock_held(&i915->runtime_pm); | |
1685 | } | |
1686 | ||
1f814dac ID |
1687 | /** |
1688 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
bd780f37 | 1689 | * @i915: i915 device instance |
1f814dac ID |
1690 | * |
1691 | * This function disable asserts that check if we hold an RPM wakelock | |
1692 | * reference, while keeping the device-not-suspended checks still enabled. | |
1693 | * It's meant to be used only in special circumstances where our rule about | |
1694 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
1695 | * to this rule at any point where we access the HW or want to keep the HW in | |
1696 | * an active state we must hold an RPM wakelock reference acquired via one of | |
1697 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
1698 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
1699 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
1700 | * users should avoid using this function. | |
1701 | * | |
1702 | * Any calls to this function must have a symmetric call to | |
1703 | * enable_rpm_wakeref_asserts(). | |
1704 | */ | |
1705 | static inline void | |
bd780f37 | 1706 | disable_rpm_wakeref_asserts(struct drm_i915_private *i915) |
1f814dac | 1707 | { |
4547c255 ID |
1708 | atomic_add(INTEL_RPM_WAKELOCK_BIAS + 1, |
1709 | &i915->runtime_pm.wakeref_count); | |
1f814dac ID |
1710 | } |
1711 | ||
1712 | /** | |
1713 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
bd780f37 | 1714 | * @i915: i915 device instance |
1f814dac ID |
1715 | * |
1716 | * This function re-enables the RPM assert checks after disabling them with | |
1717 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
1718 | * circumstances otherwise its use should be avoided. | |
1719 | * | |
1720 | * Any calls to this function must have a symmetric call to | |
1721 | * disable_rpm_wakeref_asserts(). | |
1722 | */ | |
1723 | static inline void | |
bd780f37 | 1724 | enable_rpm_wakeref_asserts(struct drm_i915_private *i915) |
1f814dac | 1725 | { |
4547c255 ID |
1726 | atomic_sub(INTEL_RPM_WAKELOCK_BIAS + 1, |
1727 | &i915->runtime_pm.wakeref_count); | |
1f814dac ID |
1728 | } |
1729 | ||
79e53945 | 1730 | #endif /* __INTEL_DRV_H__ */ |