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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
e6017571 | 31 | #include <linux/sched/clock.h> |
760285e7 | 32 | #include <drm/i915_drm.h> |
80824003 | 33 | #include "i915_drv.h" |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_crtc_helper.h> | |
9338203c | 36 | #include <drm/drm_encoder.h> |
760285e7 | 37 | #include <drm/drm_fb_helper.h> |
b1ba124d | 38 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 39 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 40 | #include <drm/drm_rect.h> |
10f81c19 | 41 | #include <drm/drm_atomic.h> |
913d8d11 | 42 | |
1d5bfac9 | 43 | /** |
23fdbdd7 | 44 | * __wait_for - magic wait macro |
1d5bfac9 | 45 | * |
23fdbdd7 SP |
46 | * Macro to help avoid open coding check/wait/timeout patterns. Note that it's |
47 | * important that we check the condition again after having timed out, since the | |
48 | * timeout could be due to preemption or similar and we've never had a chance to | |
49 | * check the condition before the timeout. | |
1d5bfac9 | 50 | */ |
23fdbdd7 | 51 | #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ |
3085982c | 52 | const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ |
a54b1873 | 53 | long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ |
b0876afd | 54 | int ret__; \ |
290b20a6 | 55 | might_sleep(); \ |
b0876afd | 56 | for (;;) { \ |
3085982c | 57 | const bool expired__ = ktime_after(ktime_get_raw(), end__); \ |
23fdbdd7 | 58 | OP; \ |
1c3c1dc6 MK |
59 | /* Guarantee COND check prior to timeout */ \ |
60 | barrier(); \ | |
b0876afd DG |
61 | if (COND) { \ |
62 | ret__ = 0; \ | |
63 | break; \ | |
64 | } \ | |
65 | if (expired__) { \ | |
66 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
67 | break; \ |
68 | } \ | |
a54b1873 CW |
69 | usleep_range(wait__, wait__ * 2); \ |
70 | if (wait__ < (Wmax)) \ | |
71 | wait__ <<= 1; \ | |
913d8d11 CW |
72 | } \ |
73 | ret__; \ | |
74 | }) | |
75 | ||
23fdbdd7 SP |
76 | #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ |
77 | (Wmax)) | |
78 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) | |
3f177625 | 79 | |
0351b939 TU |
80 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
81 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
18f4b843 | 82 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic()) |
0351b939 | 83 | #else |
18f4b843 | 84 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0) |
0351b939 TU |
85 | #endif |
86 | ||
18f4b843 TU |
87 | #define _wait_for_atomic(COND, US, ATOMIC) \ |
88 | ({ \ | |
89 | int cpu, ret, timeout = (US) * 1000; \ | |
90 | u64 base; \ | |
91 | _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \ | |
18f4b843 TU |
92 | if (!(ATOMIC)) { \ |
93 | preempt_disable(); \ | |
94 | cpu = smp_processor_id(); \ | |
95 | } \ | |
96 | base = local_clock(); \ | |
97 | for (;;) { \ | |
98 | u64 now = local_clock(); \ | |
99 | if (!(ATOMIC)) \ | |
100 | preempt_enable(); \ | |
1c3c1dc6 MK |
101 | /* Guarantee COND check prior to timeout */ \ |
102 | barrier(); \ | |
18f4b843 TU |
103 | if (COND) { \ |
104 | ret = 0; \ | |
105 | break; \ | |
106 | } \ | |
107 | if (now - base >= timeout) { \ | |
108 | ret = -ETIMEDOUT; \ | |
0351b939 TU |
109 | break; \ |
110 | } \ | |
111 | cpu_relax(); \ | |
18f4b843 TU |
112 | if (!(ATOMIC)) { \ |
113 | preempt_disable(); \ | |
114 | if (unlikely(cpu != smp_processor_id())) { \ | |
115 | timeout -= now - base; \ | |
116 | cpu = smp_processor_id(); \ | |
117 | base = local_clock(); \ | |
118 | } \ | |
119 | } \ | |
0351b939 | 120 | } \ |
18f4b843 TU |
121 | ret; \ |
122 | }) | |
123 | ||
124 | #define wait_for_us(COND, US) \ | |
125 | ({ \ | |
126 | int ret__; \ | |
127 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
128 | if ((US) > 10) \ | |
a54b1873 | 129 | ret__ = _wait_for((COND), (US), 10, 10); \ |
18f4b843 TU |
130 | else \ |
131 | ret__ = _wait_for_atomic((COND), (US), 0); \ | |
0351b939 TU |
132 | ret__; \ |
133 | }) | |
134 | ||
939cf46c TU |
135 | #define wait_for_atomic_us(COND, US) \ |
136 | ({ \ | |
137 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
138 | BUILD_BUG_ON((US) > 50000); \ | |
139 | _wait_for_atomic((COND), (US), 1); \ | |
140 | }) | |
141 | ||
142 | #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000) | |
481b6af3 | 143 | |
49938ac4 JN |
144 | #define KHz(x) (1000 * (x)) |
145 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 146 | |
aa9664ff MK |
147 | #define KBps(x) (1000 * (x)) |
148 | #define MBps(x) KBps(1000 * (x)) | |
149 | #define GBps(x) ((u64)1000 * MBps((x))) | |
150 | ||
79e53945 JB |
151 | /* |
152 | * Display related stuff | |
153 | */ | |
154 | ||
155 | /* store information about an Ixxx DVO */ | |
156 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
157 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
158 | #define MAX_OUTPUTS 6 | |
159 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
160 | |
161 | #define INTEL_I2C_BUS_DVO 1 | |
162 | #define INTEL_I2C_BUS_SDVO 2 | |
163 | ||
164 | /* these are outputs from the chip - integrated only | |
165 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
166 | enum intel_output_type { |
167 | INTEL_OUTPUT_UNUSED = 0, | |
168 | INTEL_OUTPUT_ANALOG = 1, | |
169 | INTEL_OUTPUT_DVO = 2, | |
170 | INTEL_OUTPUT_SDVO = 3, | |
171 | INTEL_OUTPUT_LVDS = 4, | |
172 | INTEL_OUTPUT_TVOUT = 5, | |
173 | INTEL_OUTPUT_HDMI = 6, | |
cca0502b | 174 | INTEL_OUTPUT_DP = 7, |
6847d71b PZ |
175 | INTEL_OUTPUT_EDP = 8, |
176 | INTEL_OUTPUT_DSI = 9, | |
7e732cac | 177 | INTEL_OUTPUT_DDI = 10, |
6847d71b PZ |
178 | INTEL_OUTPUT_DP_MST = 11, |
179 | }; | |
79e53945 JB |
180 | |
181 | #define INTEL_DVO_CHIP_NONE 0 | |
182 | #define INTEL_DVO_CHIP_LVDS 1 | |
183 | #define INTEL_DVO_CHIP_TMDS 2 | |
184 | #define INTEL_DVO_CHIP_TVOUT 4 | |
185 | ||
dfba2e2d SK |
186 | #define INTEL_DSI_VIDEO_MODE 0 |
187 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 188 | |
79e53945 JB |
189 | struct intel_framebuffer { |
190 | struct drm_framebuffer base; | |
2d7a215f | 191 | struct intel_rotation_info rot_info; |
6687c906 VS |
192 | |
193 | /* for each plane in the normal GTT view */ | |
194 | struct { | |
195 | unsigned int x, y; | |
196 | } normal[2]; | |
197 | /* for each plane in the rotated GTT view */ | |
198 | struct { | |
199 | unsigned int x, y; | |
200 | unsigned int pitch; /* pixels */ | |
201 | } rotated[2]; | |
79e53945 JB |
202 | }; |
203 | ||
37811fcc CW |
204 | struct intel_fbdev { |
205 | struct drm_fb_helper helper; | |
8bcd4553 | 206 | struct intel_framebuffer *fb; |
058d88c4 | 207 | struct i915_vma *vma; |
5935485f | 208 | unsigned long vma_flags; |
43cee314 | 209 | async_cookie_t cookie; |
d978ef14 | 210 | int preferred_bpp; |
37811fcc | 211 | }; |
79e53945 | 212 | |
21d40d37 | 213 | struct intel_encoder { |
4ef69c7a | 214 | struct drm_encoder base; |
9a935856 | 215 | |
6847d71b | 216 | enum intel_output_type type; |
03cdc1d4 | 217 | enum port port; |
bc079e8b | 218 | unsigned int cloneable; |
dba14b27 VS |
219 | bool (*hotplug)(struct intel_encoder *encoder, |
220 | struct intel_connector *connector); | |
7e732cac VS |
221 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
222 | struct intel_crtc_state *, | |
223 | struct drm_connector_state *); | |
7ae89233 | 224 | bool (*compute_config)(struct intel_encoder *, |
0a478c27 ML |
225 | struct intel_crtc_state *, |
226 | struct drm_connector_state *); | |
fd6bbda9 | 227 | void (*pre_pll_enable)(struct intel_encoder *, |
5f88a9c6 VS |
228 | const struct intel_crtc_state *, |
229 | const struct drm_connector_state *); | |
fd6bbda9 | 230 | void (*pre_enable)(struct intel_encoder *, |
5f88a9c6 VS |
231 | const struct intel_crtc_state *, |
232 | const struct drm_connector_state *); | |
fd6bbda9 | 233 | void (*enable)(struct intel_encoder *, |
5f88a9c6 VS |
234 | const struct intel_crtc_state *, |
235 | const struct drm_connector_state *); | |
fd6bbda9 | 236 | void (*disable)(struct intel_encoder *, |
5f88a9c6 VS |
237 | const struct intel_crtc_state *, |
238 | const struct drm_connector_state *); | |
fd6bbda9 | 239 | void (*post_disable)(struct intel_encoder *, |
5f88a9c6 VS |
240 | const struct intel_crtc_state *, |
241 | const struct drm_connector_state *); | |
fd6bbda9 | 242 | void (*post_pll_disable)(struct intel_encoder *, |
5f88a9c6 VS |
243 | const struct intel_crtc_state *, |
244 | const struct drm_connector_state *); | |
f0947c37 DV |
245 | /* Read out the current hw state of this connector, returning true if |
246 | * the encoder is active. If the encoder is enabled it also set the pipe | |
247 | * it is connected to in the pipe parameter. */ | |
248 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 249 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 250 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
251 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
252 | * be set correctly before calling this function. */ | |
045ac3b5 | 253 | void (*get_config)(struct intel_encoder *, |
5cec258b | 254 | struct intel_crtc_state *pipe_config); |
62b69566 ACO |
255 | /* Returns a mask of power domains that need to be referenced as part |
256 | * of the hardware state readout code. */ | |
52528055 ID |
257 | u64 (*get_power_domains)(struct intel_encoder *encoder, |
258 | struct intel_crtc_state *crtc_state); | |
07f9cd0b ID |
259 | /* |
260 | * Called during system suspend after all pending requests for the | |
261 | * encoder are flushed (for example for DP AUX transactions) and | |
262 | * device interrupts are disabled. | |
263 | */ | |
264 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 265 | int crtc_mask; |
1d843f9d | 266 | enum hpd_pin hpd_pin; |
79f255a0 | 267 | enum intel_display_power_domain power_domain; |
f1a3acea PD |
268 | /* for communication with audio component; protected by av_mutex */ |
269 | const struct drm_connector *audio_connector; | |
79e53945 JB |
270 | }; |
271 | ||
1d508706 | 272 | struct intel_panel { |
dd06f90e | 273 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 274 | struct drm_display_mode *downclock_mode; |
58c68779 JN |
275 | |
276 | /* backlight */ | |
277 | struct { | |
c91c9f32 | 278 | bool present; |
58c68779 | 279 | u32 level; |
6dda730e | 280 | u32 min; |
7bd688cd | 281 | u32 max; |
58c68779 | 282 | bool enabled; |
636baebf JN |
283 | bool combination_mode; /* gen 2/4 only */ |
284 | bool active_low_pwm; | |
32b421e7 | 285 | bool alternate_pwm_increment; /* lpt+ */ |
b029e66f SK |
286 | |
287 | /* PWM chip */ | |
022e4e52 SK |
288 | bool util_pin_active_low; /* bxt+ */ |
289 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
290 | struct pwm_device *pwm; |
291 | ||
58c68779 | 292 | struct backlight_device *device; |
ab656bb9 | 293 | |
5507faeb JN |
294 | /* Connector and platform specific backlight functions */ |
295 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
296 | uint32_t (*get)(struct intel_connector *connector); | |
7d025e08 ML |
297 | void (*set)(const struct drm_connector_state *conn_state, uint32_t level); |
298 | void (*disable)(const struct drm_connector_state *conn_state); | |
299 | void (*enable)(const struct intel_crtc_state *crtc_state, | |
300 | const struct drm_connector_state *conn_state); | |
5507faeb JN |
301 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, |
302 | uint32_t hz); | |
303 | void (*power)(struct intel_connector *, bool enable); | |
304 | } backlight; | |
1d508706 JN |
305 | }; |
306 | ||
b6ca3eee VS |
307 | struct intel_digital_port; |
308 | ||
ee5e5e7a SP |
309 | /* |
310 | * This structure serves as a translation layer between the generic HDCP code | |
311 | * and the bus-specific code. What that means is that HDCP over HDMI differs | |
312 | * from HDCP over DP, so to account for these differences, we need to | |
313 | * communicate with the receiver through this shim. | |
314 | * | |
315 | * For completeness, the 2 buses differ in the following ways: | |
316 | * - DP AUX vs. DDC | |
317 | * HDCP registers on the receiver are set via DP AUX for DP, and | |
318 | * they are set via DDC for HDMI. | |
319 | * - Receiver register offsets | |
320 | * The offsets of the registers are different for DP vs. HDMI | |
321 | * - Receiver register masks/offsets | |
322 | * For instance, the ready bit for the KSV fifo is in a different | |
323 | * place on DP vs HDMI | |
324 | * - Receiver register names | |
325 | * Seriously. In the DP spec, the 16-bit register containing | |
326 | * downstream information is called BINFO, on HDMI it's called | |
327 | * BSTATUS. To confuse matters further, DP has a BSTATUS register | |
328 | * with a completely different definition. | |
329 | * - KSV FIFO | |
330 | * On HDMI, the ksv fifo is read all at once, whereas on DP it must | |
331 | * be read 3 keys at a time | |
332 | * - Aksv output | |
333 | * Since Aksv is hidden in hardware, there's different procedures | |
334 | * to send it over DP AUX vs DDC | |
335 | */ | |
336 | struct intel_hdcp_shim { | |
337 | /* Outputs the transmitter's An and Aksv values to the receiver. */ | |
338 | int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); | |
339 | ||
340 | /* Reads the receiver's key selection vector */ | |
341 | int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); | |
342 | ||
343 | /* | |
344 | * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The | |
345 | * definitions are the same in the respective specs, but the names are | |
346 | * different. Call it BSTATUS since that's the name the HDMI spec | |
347 | * uses and it was there first. | |
348 | */ | |
349 | int (*read_bstatus)(struct intel_digital_port *intel_dig_port, | |
350 | u8 *bstatus); | |
351 | ||
352 | /* Determines whether a repeater is present downstream */ | |
353 | int (*repeater_present)(struct intel_digital_port *intel_dig_port, | |
354 | bool *repeater_present); | |
355 | ||
356 | /* Reads the receiver's Ri' value */ | |
357 | int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); | |
358 | ||
359 | /* Determines if the receiver's KSV FIFO is ready for consumption */ | |
360 | int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, | |
361 | bool *ksv_ready); | |
362 | ||
363 | /* Reads the ksv fifo for num_downstream devices */ | |
364 | int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, | |
365 | int num_downstream, u8 *ksv_fifo); | |
366 | ||
367 | /* Reads a 32-bit part of V' from the receiver */ | |
368 | int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, | |
369 | int i, u32 *part); | |
370 | ||
371 | /* Enables HDCP signalling on the port */ | |
372 | int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, | |
373 | bool enable); | |
374 | ||
375 | /* Ensures the link is still protected */ | |
376 | bool (*check_link)(struct intel_digital_port *intel_dig_port); | |
791a98dd R |
377 | |
378 | /* Detects panel's hdcp capability. This is optional for HDMI. */ | |
379 | int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, | |
380 | bool *hdcp_capable); | |
ee5e5e7a SP |
381 | }; |
382 | ||
5daa55eb ZW |
383 | struct intel_connector { |
384 | struct drm_connector base; | |
9a935856 DV |
385 | /* |
386 | * The fixed encoder this connector is connected to. | |
387 | */ | |
df0e9248 | 388 | struct intel_encoder *encoder; |
9a935856 | 389 | |
8e1b56a4 JN |
390 | /* ACPI device id for ACPI and driver cooperation */ |
391 | u32 acpi_device_id; | |
392 | ||
f0947c37 DV |
393 | /* Reads out the current hw, returning true if the connector is enabled |
394 | * and active (i.e. dpms ON state). */ | |
395 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
396 | |
397 | /* Panel info for eDP and LVDS */ | |
398 | struct intel_panel panel; | |
9cd300e0 JN |
399 | |
400 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
401 | struct edid *edid; | |
beb60608 | 402 | struct edid *detect_edid; |
821450c6 EE |
403 | |
404 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
405 | state of connector->polled in case hotplug storm detection changes it */ | |
406 | u8 polled; | |
0e32b39c DA |
407 | |
408 | void *port; /* store this opaque as its illegal to dereference it */ | |
409 | ||
410 | struct intel_dp *mst_port; | |
9301397a MN |
411 | |
412 | /* Work struct to schedule a uevent on link train failure */ | |
413 | struct work_struct modeset_retry_work; | |
ee5e5e7a SP |
414 | |
415 | const struct intel_hdcp_shim *hdcp_shim; | |
416 | struct mutex hdcp_mutex; | |
417 | uint64_t hdcp_value; /* protected by hdcp_mutex */ | |
418 | struct delayed_work hdcp_check_work; | |
419 | struct work_struct hdcp_prop_work; | |
5daa55eb ZW |
420 | }; |
421 | ||
11c1a9ec ML |
422 | struct intel_digital_connector_state { |
423 | struct drm_connector_state base; | |
424 | ||
425 | enum hdmi_force_audio force_audio; | |
426 | int broadcast_rgb; | |
427 | }; | |
428 | ||
429 | #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) | |
430 | ||
9e2c8475 | 431 | struct dpll { |
80ad9206 VS |
432 | /* given values */ |
433 | int n; | |
434 | int m1, m2; | |
435 | int p1, p2; | |
436 | /* derived values */ | |
437 | int dot; | |
438 | int vco; | |
439 | int m; | |
440 | int p; | |
9e2c8475 | 441 | }; |
80ad9206 | 442 | |
de419ab6 ML |
443 | struct intel_atomic_state { |
444 | struct drm_atomic_state base; | |
445 | ||
bb0f4aab VS |
446 | struct { |
447 | /* | |
448 | * Logical state of cdclk (used for all scaling, watermark, | |
449 | * etc. calculations and checks). This is computed as if all | |
450 | * enabled crtcs were active. | |
451 | */ | |
452 | struct intel_cdclk_state logical; | |
453 | ||
454 | /* | |
455 | * Actual state of cdclk, can be different from the logical | |
456 | * state only when all crtc's are DPMS off. | |
457 | */ | |
458 | struct intel_cdclk_state actual; | |
459 | } cdclk; | |
1a617b77 | 460 | |
565602d7 ML |
461 | bool dpll_set, modeset; |
462 | ||
8b4a7d05 MR |
463 | /* |
464 | * Does this transaction change the pipes that are active? This mask | |
465 | * tracks which CRTC's have changed their active state at the end of | |
466 | * the transaction (not counting the temporary disable during modesets). | |
467 | * This mask should only be non-zero when intel_state->modeset is true, | |
468 | * but the converse is not necessarily true; simply changing a mode may | |
469 | * not flip the final active status of any CRTC's | |
470 | */ | |
471 | unsigned int active_pipe_changes; | |
472 | ||
565602d7 | 473 | unsigned int active_crtcs; |
d305e061 VS |
474 | /* minimum acceptable cdclk for each pipe */ |
475 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
476 | /* minimum acceptable voltage level for each pipe */ |
477 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 478 | |
2c42e535 | 479 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
ed4a6a7c MR |
480 | |
481 | /* | |
482 | * Current watermarks can't be trusted during hardware readout, so | |
483 | * don't bother calculating intermediate watermarks. | |
484 | */ | |
485 | bool skip_intermediate_wm; | |
98d39494 MR |
486 | |
487 | /* Gen9+ only */ | |
60f8e873 | 488 | struct skl_ddb_values wm_results; |
c004a90b CW |
489 | |
490 | struct i915_sw_fence commit_ready; | |
eb955eee CW |
491 | |
492 | struct llist_node freed; | |
de419ab6 ML |
493 | }; |
494 | ||
eeca778a | 495 | struct intel_plane_state { |
2b875c22 | 496 | struct drm_plane_state base; |
be1e3415 | 497 | struct i915_vma *vma; |
5935485f CW |
498 | unsigned long flags; |
499 | #define PLANE_HAS_FENCE BIT(0) | |
32b7eeec | 500 | |
b63a16f6 VS |
501 | struct { |
502 | u32 offset; | |
503 | int x, y; | |
504 | } main; | |
8d970654 VS |
505 | struct { |
506 | u32 offset; | |
507 | int x, y; | |
508 | } aux; | |
b63a16f6 | 509 | |
a0864d59 VS |
510 | /* plane control register */ |
511 | u32 ctl; | |
512 | ||
4036c78c JA |
513 | /* plane color control register */ |
514 | u32 color_ctl; | |
515 | ||
be41e336 CK |
516 | /* |
517 | * scaler_id | |
518 | * = -1 : not using a scaler | |
519 | * >= 0 : using a scalers | |
520 | * | |
521 | * plane requiring a scaler: | |
522 | * - During check_plane, its bit is set in | |
523 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 524 | * update_scaler_plane. |
be41e336 CK |
525 | * - scaler_id indicates the scaler it got assigned. |
526 | * | |
527 | * plane doesn't require a scaler: | |
528 | * - this can happen when scaling is no more required or plane simply | |
529 | * got disabled. | |
530 | * - During check_plane, corresponding bit is reset in | |
531 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 532 | * update_scaler_plane. |
be41e336 CK |
533 | */ |
534 | int scaler_id; | |
818ed961 ML |
535 | |
536 | struct drm_intel_sprite_colorkey ckey; | |
eeca778a GP |
537 | }; |
538 | ||
5724dbd1 | 539 | struct intel_initial_plane_config { |
2d14030b | 540 | struct intel_framebuffer *fb; |
49af449b | 541 | unsigned int tiling; |
46f297fb JB |
542 | int size; |
543 | u32 base; | |
544 | }; | |
545 | ||
be41e336 CK |
546 | #define SKL_MIN_SRC_W 8 |
547 | #define SKL_MAX_SRC_W 4096 | |
548 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 549 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
550 | #define SKL_MIN_DST_W 8 |
551 | #define SKL_MAX_DST_W 4096 | |
552 | #define SKL_MIN_DST_H 8 | |
6156a456 | 553 | #define SKL_MAX_DST_H 4096 |
323301af NM |
554 | #define ICL_MAX_SRC_W 5120 |
555 | #define ICL_MAX_SRC_H 4096 | |
556 | #define ICL_MAX_DST_W 5120 | |
557 | #define ICL_MAX_DST_H 4096 | |
77224cd5 CK |
558 | #define SKL_MIN_YUV_420_SRC_W 16 |
559 | #define SKL_MIN_YUV_420_SRC_H 16 | |
be41e336 CK |
560 | |
561 | struct intel_scaler { | |
be41e336 CK |
562 | int in_use; |
563 | uint32_t mode; | |
564 | }; | |
565 | ||
566 | struct intel_crtc_scaler_state { | |
567 | #define SKL_NUM_SCALERS 2 | |
568 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
569 | ||
570 | /* | |
571 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
572 | * | |
573 | * If a bit is set, a user is using a scaler. | |
574 | * Here user can be a plane or crtc as defined below: | |
575 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
576 | * bit 31 - crtc | |
577 | * | |
578 | * Instead of creating a new index to cover planes and crtc, using | |
579 | * existing drm_plane_index for planes which is well less than 31 | |
580 | * planes and bit 31 for crtc. This should be fine to cover all | |
581 | * our platforms. | |
582 | * | |
583 | * intel_atomic_setup_scalers will setup available scalers to users | |
584 | * requesting scalers. It will gracefully fail if request exceeds | |
585 | * avilability. | |
586 | */ | |
587 | #define SKL_CRTC_INDEX 31 | |
588 | unsigned scaler_users; | |
589 | ||
590 | /* scaler used by crtc for panel fitting purpose */ | |
591 | int scaler_id; | |
592 | }; | |
593 | ||
1ed51de9 DV |
594 | /* drm_mode->private_flags */ |
595 | #define I915_MODE_FLAG_INHERITED 1 | |
aec0246f US |
596 | /* Flag to get scanline using frame time stamps */ |
597 | #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) | |
1ed51de9 | 598 | |
4e0963c7 MR |
599 | struct intel_pipe_wm { |
600 | struct intel_wm_level wm[5]; | |
601 | uint32_t linetime; | |
602 | bool fbc_wm_enabled; | |
603 | bool pipe_enabled; | |
604 | bool sprites_enabled; | |
605 | bool sprites_scaled; | |
606 | }; | |
607 | ||
a62163e9 | 608 | struct skl_plane_wm { |
4e0963c7 | 609 | struct skl_wm_level wm[8]; |
942aa2d0 | 610 | struct skl_wm_level uv_wm[8]; |
4e0963c7 | 611 | struct skl_wm_level trans_wm; |
b879d58f | 612 | bool is_planar; |
a62163e9 L |
613 | }; |
614 | ||
615 | struct skl_pipe_wm { | |
616 | struct skl_plane_wm planes[I915_MAX_PLANES]; | |
4e0963c7 MR |
617 | uint32_t linetime; |
618 | }; | |
619 | ||
855c79f5 VS |
620 | enum vlv_wm_level { |
621 | VLV_WM_LEVEL_PM2, | |
622 | VLV_WM_LEVEL_PM5, | |
623 | VLV_WM_LEVEL_DDR_DVFS, | |
624 | NUM_VLV_WM_LEVELS, | |
625 | }; | |
626 | ||
627 | struct vlv_wm_state { | |
114d7dc0 VS |
628 | struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; |
629 | struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; | |
855c79f5 | 630 | uint8_t num_levels; |
855c79f5 VS |
631 | bool cxsr; |
632 | }; | |
633 | ||
814e7f0b VS |
634 | struct vlv_fifo_state { |
635 | u16 plane[I915_MAX_PLANES]; | |
636 | }; | |
637 | ||
04548cba VS |
638 | enum g4x_wm_level { |
639 | G4X_WM_LEVEL_NORMAL, | |
640 | G4X_WM_LEVEL_SR, | |
641 | G4X_WM_LEVEL_HPLL, | |
642 | NUM_G4X_WM_LEVELS, | |
643 | }; | |
644 | ||
645 | struct g4x_wm_state { | |
646 | struct g4x_pipe_wm wm; | |
647 | struct g4x_sr_wm sr; | |
648 | struct g4x_sr_wm hpll; | |
649 | bool cxsr; | |
650 | bool hpll_en; | |
651 | bool fbc_en; | |
652 | }; | |
653 | ||
e8f1f02e MR |
654 | struct intel_crtc_wm_state { |
655 | union { | |
656 | struct { | |
657 | /* | |
658 | * Intermediate watermarks; these can be | |
659 | * programmed immediately since they satisfy | |
660 | * both the current configuration we're | |
661 | * switching away from and the new | |
662 | * configuration we're switching to. | |
663 | */ | |
664 | struct intel_pipe_wm intermediate; | |
665 | ||
666 | /* | |
667 | * Optimal watermarks, programmed post-vblank | |
668 | * when this state is committed. | |
669 | */ | |
670 | struct intel_pipe_wm optimal; | |
671 | } ilk; | |
672 | ||
673 | struct { | |
674 | /* gen9+ only needs 1-step wm programming */ | |
675 | struct skl_pipe_wm optimal; | |
ce0ba283 | 676 | struct skl_ddb_entry ddb; |
e8f1f02e | 677 | } skl; |
855c79f5 VS |
678 | |
679 | struct { | |
5012e604 | 680 | /* "raw" watermarks (not inverted) */ |
114d7dc0 | 681 | struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; |
4841da51 VS |
682 | /* intermediate watermarks (inverted) */ |
683 | struct vlv_wm_state intermediate; | |
855c79f5 VS |
684 | /* optimal watermarks (inverted) */ |
685 | struct vlv_wm_state optimal; | |
814e7f0b VS |
686 | /* display FIFO split */ |
687 | struct vlv_fifo_state fifo_state; | |
855c79f5 | 688 | } vlv; |
04548cba VS |
689 | |
690 | struct { | |
691 | /* "raw" watermarks */ | |
692 | struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; | |
693 | /* intermediate watermarks */ | |
694 | struct g4x_wm_state intermediate; | |
695 | /* optimal watermarks */ | |
696 | struct g4x_wm_state optimal; | |
697 | } g4x; | |
e8f1f02e MR |
698 | }; |
699 | ||
700 | /* | |
701 | * Platforms with two-step watermark programming will need to | |
702 | * update watermark programming post-vblank to switch from the | |
703 | * safe intermediate watermarks to the optimal final | |
704 | * watermarks. | |
705 | */ | |
706 | bool need_postvbl_update; | |
707 | }; | |
708 | ||
5cec258b | 709 | struct intel_crtc_state { |
2d112de7 ACO |
710 | struct drm_crtc_state base; |
711 | ||
bb760063 DV |
712 | /** |
713 | * quirks - bitfield with hw state readout quirks | |
714 | * | |
715 | * For various reasons the hw state readout code might not be able to | |
716 | * completely faithfully read out the current state. These cases are | |
717 | * tracked with quirk flags so that fastboot and state checker can act | |
718 | * accordingly. | |
719 | */ | |
9953599b | 720 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
721 | unsigned long quirks; |
722 | ||
cd202f69 | 723 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
724 | bool update_pipe; /* can a fast modeset be performed? */ |
725 | bool disable_cxsr; | |
caed361d | 726 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 727 | bool fb_changed; /* fb on any of the planes is changed */ |
236c48e6 | 728 | bool fifo_changed; /* FIFO split is changed */ |
bfd16b2a | 729 | |
37327abd VS |
730 | /* Pipe source size (ie. panel fitter input size) |
731 | * All planes will be positioned inside this space, | |
732 | * and get clipped at the edges. */ | |
733 | int pipe_src_w, pipe_src_h; | |
734 | ||
a7d1b3f4 VS |
735 | /* |
736 | * Pipe pixel rate, adjusted for | |
737 | * panel fitter/pipe scaler downscaling. | |
738 | */ | |
739 | unsigned int pixel_rate; | |
740 | ||
5bfe2ac0 DV |
741 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
742 | * between pch encoders and cpu encoders. */ | |
743 | bool has_pch_encoder; | |
50f3b016 | 744 | |
e43823ec JB |
745 | /* Are we sending infoframes on the attached port */ |
746 | bool has_infoframe; | |
747 | ||
3b117c8f | 748 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
749 | * pipe on Haswell and later (where we have a special eDP transcoder) |
750 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
751 | enum transcoder cpu_transcoder; |
752 | ||
50f3b016 DV |
753 | /* |
754 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
755 | * range fed into the crtcs. | |
756 | */ | |
757 | bool limited_color_range; | |
758 | ||
253c84c8 VS |
759 | /* Bitmask of encoder types (enum intel_output_type) |
760 | * driven by the pipe. | |
761 | */ | |
762 | unsigned int output_types; | |
763 | ||
6897b4b5 DV |
764 | /* Whether we should send NULL infoframes. Required for audio. */ |
765 | bool has_hdmi_sink; | |
766 | ||
9ed109a7 DV |
767 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
768 | * has_dp_encoder is set. */ | |
769 | bool has_audio; | |
770 | ||
d8b32247 DV |
771 | /* |
772 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
773 | * plane bpp. | |
774 | */ | |
965e0c48 | 775 | bool dither; |
f47709a9 | 776 | |
611032bf MN |
777 | /* |
778 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for | |
779 | * compliance video pattern tests. | |
780 | * Disable dither only if it is a compliance test request for | |
781 | * 18bpp. | |
782 | */ | |
783 | bool dither_force_disable; | |
784 | ||
f47709a9 DV |
785 | /* Controls for the clock computation, to override various stages. */ |
786 | bool clock_set; | |
787 | ||
09ede541 DV |
788 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
789 | * work correctly, we need to track this at runtime.*/ | |
790 | bool sdvo_tv_clock; | |
791 | ||
e29c22c0 DV |
792 | /* |
793 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
794 | * required. This is set in the 2nd loop of calling encoder's | |
795 | * ->compute_config if the first pick doesn't work out. | |
796 | */ | |
797 | bool bw_constrained; | |
798 | ||
f47709a9 DV |
799 | /* Settings for the intel dpll used on pretty much everything but |
800 | * haswell. */ | |
80ad9206 | 801 | struct dpll dpll; |
f47709a9 | 802 | |
8106ddbd ACO |
803 | /* Selected dpll when shared or NULL. */ |
804 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 805 | |
66e985c0 DV |
806 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
807 | struct intel_dpll_hw_state dpll_hw_state; | |
808 | ||
47eacbab VS |
809 | /* DSI PLL registers */ |
810 | struct { | |
811 | u32 ctrl, div; | |
812 | } dsi_pll; | |
813 | ||
965e0c48 | 814 | int pipe_bpp; |
6cf86a5e | 815 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 816 | |
439d7ac0 PB |
817 | /* m2_n2 for eDP downclock */ |
818 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 819 | bool has_drrs; |
439d7ac0 | 820 | |
4d90f2d5 VS |
821 | bool has_psr; |
822 | bool has_psr2; | |
823 | ||
ff9a6750 DV |
824 | /* |
825 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
826 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
827 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 828 | */ |
ff9a6750 DV |
829 | int port_clock; |
830 | ||
6cc5f341 DV |
831 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
832 | unsigned pixel_multiplier; | |
2dd24552 | 833 | |
90a6b7b0 VS |
834 | uint8_t lane_count; |
835 | ||
95a7a2ae ID |
836 | /* |
837 | * Used by platforms having DP/HDMI PHY with programmable lane | |
838 | * latency optimization. | |
839 | */ | |
840 | uint8_t lane_lat_optim_mask; | |
841 | ||
53e9bf5e VS |
842 | /* minimum acceptable voltage level */ |
843 | u8 min_voltage_level; | |
844 | ||
2dd24552 | 845 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
846 | struct { |
847 | u32 control; | |
848 | u32 pgm_ratios; | |
68fc8742 | 849 | u32 lvds_border_bits; |
b074cec8 JB |
850 | } gmch_pfit; |
851 | ||
852 | /* Panel fitter placement and size for Ironlake+ */ | |
853 | struct { | |
854 | u32 pos; | |
855 | u32 size; | |
fd4daa9c | 856 | bool enabled; |
fabf6e51 | 857 | bool force_thru; |
b074cec8 | 858 | } pch_pfit; |
33d29b14 | 859 | |
ca3a0ff8 | 860 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 861 | int fdi_lanes; |
ca3a0ff8 | 862 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
863 | |
864 | bool ips_enabled; | |
6e644626 | 865 | bool ips_force_disable; |
cf532bb2 | 866 | |
f51be2e0 PZ |
867 | bool enable_fbc; |
868 | ||
cf532bb2 | 869 | bool double_wide; |
0e32b39c | 870 | |
0e32b39c | 871 | int pbn; |
be41e336 CK |
872 | |
873 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
874 | |
875 | /* w/a for waiting 2 vblanks during crtc enable */ | |
876 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
877 | |
878 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
879 | bool disable_lp_wm; | |
4e0963c7 | 880 | |
e8f1f02e | 881 | struct intel_crtc_wm_state wm; |
05dc698c LL |
882 | |
883 | /* Gamma mode programmed on the pipe */ | |
884 | uint32_t gamma_mode; | |
e9728bd8 VS |
885 | |
886 | /* bitmask of visible planes (enum plane_id) */ | |
887 | u8 active_planes; | |
8e021151 | 888 | u8 nv12_planes; |
15953637 SS |
889 | |
890 | /* HDMI scrambling status */ | |
891 | bool hdmi_scrambling; | |
892 | ||
893 | /* HDMI High TMDS char rate ratio */ | |
894 | bool hdmi_high_tmds_clock_ratio; | |
60436fd4 SS |
895 | |
896 | /* output format is YCBCR 4:2:0 */ | |
897 | bool ycbcr420; | |
b8cecdf5 DV |
898 | }; |
899 | ||
79e53945 JB |
900 | struct intel_crtc { |
901 | struct drm_crtc base; | |
80824003 | 902 | enum pipe pipe; |
08a48469 DV |
903 | /* |
904 | * Whether the crtc and the connected output pipeline is active. Implies | |
905 | * that crtc->enabled is set, i.e. the current mode configuration has | |
906 | * some outputs connected to this crtc. | |
08a48469 DV |
907 | */ |
908 | bool active; | |
d97d7b48 | 909 | u8 plane_ids_mask; |
d8fc70b7 | 910 | unsigned long long enabled_power_domains; |
02e792fb | 911 | struct intel_overlay *overlay; |
cda4b7d3 | 912 | |
6e3c9717 | 913 | struct intel_crtc_state *config; |
b8cecdf5 | 914 | |
8af29b0c CW |
915 | /* global reset count when the last flip was submitted */ |
916 | unsigned int reset_count; | |
5a21b665 | 917 | |
8664281b PZ |
918 | /* Access to these should be protected by dev_priv->irq_lock. */ |
919 | bool cpu_fifo_underrun_disabled; | |
920 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
921 | |
922 | /* per-pipe watermark state */ | |
923 | struct { | |
924 | /* watermarks currently being used */ | |
4e0963c7 MR |
925 | union { |
926 | struct intel_pipe_wm ilk; | |
7eb4941f | 927 | struct vlv_wm_state vlv; |
04548cba | 928 | struct g4x_wm_state g4x; |
4e0963c7 | 929 | } active; |
0b2ae6d7 | 930 | } wm; |
8d7849db | 931 | |
80715b2f | 932 | int scanline_offset; |
32b7eeec | 933 | |
eb120ef6 JB |
934 | struct { |
935 | unsigned start_vbl_count; | |
936 | ktime_t start_vbl_time; | |
937 | int min_vbl, max_vbl; | |
938 | int scanline_start; | |
939 | } debug; | |
85a62bf9 | 940 | |
be41e336 CK |
941 | /* scalers available on this crtc */ |
942 | int num_scalers; | |
79e53945 JB |
943 | }; |
944 | ||
b840d907 JB |
945 | struct intel_plane { |
946 | struct drm_plane base; | |
ed15030d | 947 | enum i9xx_plane_id i9xx_plane; |
b14e5848 | 948 | enum plane_id id; |
b840d907 | 949 | enum pipe pipe; |
2d354c34 | 950 | bool can_scale; |
cf1805e6 | 951 | bool has_fbc; |
a38189c5 | 952 | bool has_ccs; |
b840d907 | 953 | int max_downscale; |
a9ff8714 | 954 | uint32_t frontbuffer_bit; |
526682e9 | 955 | |
cd5dcbf1 VS |
956 | struct { |
957 | u32 base, cntl, size; | |
958 | } cursor; | |
959 | ||
8e7d688b MR |
960 | /* |
961 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
962 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 963 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
964 | */ |
965 | ||
282dbf9b | 966 | void (*update_plane)(struct intel_plane *plane, |
2fde1391 ML |
967 | const struct intel_crtc_state *crtc_state, |
968 | const struct intel_plane_state *plane_state); | |
282dbf9b VS |
969 | void (*disable_plane)(struct intel_plane *plane, |
970 | struct intel_crtc *crtc); | |
eade6c89 | 971 | bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); |
282dbf9b | 972 | int (*check_plane)(struct intel_plane *plane, |
061e4b8d | 973 | struct intel_crtc_state *crtc_state, |
c59cb179 | 974 | struct intel_plane_state *state); |
b840d907 JB |
975 | }; |
976 | ||
b445e3b0 | 977 | struct intel_watermark_params { |
ae9400ca TU |
978 | u16 fifo_size; |
979 | u16 max_wm; | |
980 | u8 default_wm; | |
981 | u8 guard_size; | |
982 | u8 cacheline_size; | |
b445e3b0 ED |
983 | }; |
984 | ||
985 | struct cxsr_latency { | |
c13fb778 TU |
986 | bool is_desktop : 1; |
987 | bool is_ddr3 : 1; | |
44a655ca TU |
988 | u16 fsb_freq; |
989 | u16 mem_freq; | |
990 | u16 display_sr; | |
991 | u16 display_hpll_disable; | |
992 | u16 cursor_sr; | |
993 | u16 cursor_hpll_disable; | |
b445e3b0 ED |
994 | }; |
995 | ||
de419ab6 | 996 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 997 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 998 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 999 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 1000 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 1001 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 1002 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 1003 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
a268bcd7 | 1004 | #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) |
79e53945 | 1005 | |
f5bbfca3 | 1006 | struct intel_hdmi { |
f0f59a00 | 1007 | i915_reg_t hdmi_reg; |
f5bbfca3 | 1008 | int ddc_bus; |
b1ba124d VS |
1009 | struct { |
1010 | enum drm_dp_dual_mode_type type; | |
1011 | int max_tmds_clock; | |
1012 | } dp_dual_mode; | |
f5bbfca3 ED |
1013 | bool has_hdmi_sink; |
1014 | bool has_audio; | |
abedc077 | 1015 | bool rgb_quant_range_selectable; |
d8b4c43a | 1016 | struct intel_connector *attached_connector; |
f5bbfca3 ED |
1017 | }; |
1018 | ||
0e32b39c | 1019 | struct intel_dp_mst_encoder; |
b091cd92 | 1020 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 1021 | |
fe3cd48d R |
1022 | /* |
1023 | * enum link_m_n_set: | |
1024 | * When platform provides two set of M_N registers for dp, we can | |
1025 | * program them and switch between them incase of DRRS. | |
1026 | * But When only one such register is provided, we have to program the | |
1027 | * required divider value on that registers itself based on the DRRS state. | |
1028 | * | |
1029 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
1030 | * dp_m2_n2 on M2_N2 registers (If supported) | |
1031 | * | |
1032 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
1033 | * M2_N2 registers are not supported | |
1034 | */ | |
1035 | ||
1036 | enum link_m_n_set { | |
1037 | /* Sets the m1_n1 and m2_n2 */ | |
1038 | M1_N1 = 0, | |
1039 | M2_N2 | |
1040 | }; | |
1041 | ||
c1617abc MN |
1042 | struct intel_dp_compliance_data { |
1043 | unsigned long edid; | |
611032bf MN |
1044 | uint8_t video_pattern; |
1045 | uint16_t hdisplay, vdisplay; | |
1046 | uint8_t bpc; | |
c1617abc MN |
1047 | }; |
1048 | ||
1049 | struct intel_dp_compliance { | |
1050 | unsigned long test_type; | |
1051 | struct intel_dp_compliance_data test_data; | |
1052 | bool test_active; | |
da15f7cb MN |
1053 | int test_link_rate; |
1054 | u8 test_lane_count; | |
c1617abc MN |
1055 | }; |
1056 | ||
54d63ca6 | 1057 | struct intel_dp { |
f0f59a00 | 1058 | i915_reg_t output_reg; |
54d63ca6 | 1059 | uint32_t DP; |
901c2daf VS |
1060 | int link_rate; |
1061 | uint8_t lane_count; | |
30d9aa42 | 1062 | uint8_t sink_count; |
64ee2fd2 | 1063 | bool link_mst; |
edb2e530 | 1064 | bool link_trained; |
54d63ca6 | 1065 | bool has_audio; |
7d23e3c3 | 1066 | bool detect_done; |
d7e8ef02 | 1067 | bool reset_link_params; |
bdabdb63 | 1068 | enum aux_ch aux_ch; |
54d63ca6 | 1069 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 1070 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 1071 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
86ee27b5 | 1072 | uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
55cfc580 JN |
1073 | /* source rates */ |
1074 | int num_source_rates; | |
1075 | const int *source_rates; | |
68f357cb JN |
1076 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
1077 | int num_sink_rates; | |
94ca719e | 1078 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
68f357cb | 1079 | bool use_rate_select; |
975ee5fc JN |
1080 | /* intersection of source and sink rates */ |
1081 | int num_common_rates; | |
1082 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
e6c0c64a JN |
1083 | /* Max lane count for the current link */ |
1084 | int max_link_lane_count; | |
1085 | /* Max rate for the current link */ | |
1086 | int max_link_rate; | |
7b3fc170 | 1087 | /* sink or branch descriptor */ |
84c36753 | 1088 | struct drm_dp_desc desc; |
9d1a1031 | 1089 | struct drm_dp_aux aux; |
5432fcaf | 1090 | enum intel_display_power_domain aux_power_domain; |
54d63ca6 SK |
1091 | uint8_t train_set[4]; |
1092 | int panel_power_up_delay; | |
1093 | int panel_power_down_delay; | |
1094 | int panel_power_cycle_delay; | |
1095 | int backlight_on_delay; | |
1096 | int backlight_off_delay; | |
54d63ca6 SK |
1097 | struct delayed_work panel_vdd_work; |
1098 | bool want_panel_vdd; | |
dce56b3c PZ |
1099 | unsigned long last_power_on; |
1100 | unsigned long last_backlight_off; | |
d28d4731 | 1101 | ktime_t panel_power_off_time; |
5d42f82a | 1102 | |
01527b31 CT |
1103 | struct notifier_block edp_notifier; |
1104 | ||
a4a5d2f8 VS |
1105 | /* |
1106 | * Pipe whose power sequencer is currently locked into | |
1107 | * this port. Only relevant on VLV/CHV. | |
1108 | */ | |
1109 | enum pipe pps_pipe; | |
9f2bdb00 VS |
1110 | /* |
1111 | * Pipe currently driving the port. Used for preventing | |
1112 | * the use of the PPS for any pipe currentrly driving | |
1113 | * external DP as that will mess things up on VLV. | |
1114 | */ | |
1115 | enum pipe active_pipe; | |
78597996 ID |
1116 | /* |
1117 | * Set if the sequencer may be reset due to a power transition, | |
1118 | * requiring a reinitialization. Only relevant on BXT. | |
1119 | */ | |
1120 | bool pps_reset; | |
36b5f425 | 1121 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 1122 | |
0e32b39c DA |
1123 | bool can_mst; /* this port supports mst */ |
1124 | bool is_mst; | |
19e0b4ca | 1125 | int active_mst_links; |
0e32b39c | 1126 | /* connector directly attached - won't be use for modeset in mst world */ |
dd06f90e | 1127 | struct intel_connector *attached_connector; |
ec5b01dd | 1128 | |
0e32b39c DA |
1129 | /* mst connector list */ |
1130 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
1131 | struct drm_dp_mst_topology_mgr mst_mgr; | |
1132 | ||
ec5b01dd | 1133 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
1134 | /* |
1135 | * This function returns the value we have to program the AUX_CTL | |
1136 | * register with to kick off an AUX transaction. | |
1137 | */ | |
1138 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
153b1100 DL |
1139 | int send_bytes, |
1140 | uint32_t aux_clock_divider); | |
ad64217b | 1141 | |
4904fa66 VS |
1142 | i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); |
1143 | i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); | |
1144 | ||
ad64217b ACO |
1145 | /* This is called before a link training is starterd */ |
1146 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
1147 | ||
c5d5ab7a | 1148 | /* Displayport compliance testing */ |
c1617abc | 1149 | struct intel_dp_compliance compliance; |
54d63ca6 SK |
1150 | }; |
1151 | ||
dbe9e61b SS |
1152 | struct intel_lspcon { |
1153 | bool active; | |
1154 | enum drm_lspcon_mode mode; | |
dbe9e61b SS |
1155 | }; |
1156 | ||
da63a9f2 PZ |
1157 | struct intel_digital_port { |
1158 | struct intel_encoder base; | |
bcf53de4 | 1159 | u32 saved_port_bits; |
da63a9f2 PZ |
1160 | struct intel_dp dp; |
1161 | struct intel_hdmi hdmi; | |
dbe9e61b | 1162 | struct intel_lspcon lspcon; |
b2c5c181 | 1163 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 1164 | bool release_cl2_override; |
ccb1a831 | 1165 | uint8_t max_lanes; |
62b69566 | 1166 | enum intel_display_power_domain ddi_io_power_domain; |
6075546f | 1167 | enum tc_port_type tc_type; |
f99be1b3 VS |
1168 | |
1169 | void (*write_infoframe)(struct drm_encoder *encoder, | |
1170 | const struct intel_crtc_state *crtc_state, | |
1d776538 | 1171 | unsigned int type, |
f99be1b3 VS |
1172 | const void *frame, ssize_t len); |
1173 | void (*set_infoframes)(struct drm_encoder *encoder, | |
1174 | bool enable, | |
1175 | const struct intel_crtc_state *crtc_state, | |
1176 | const struct drm_connector_state *conn_state); | |
1177 | bool (*infoframe_enabled)(struct drm_encoder *encoder, | |
1178 | const struct intel_crtc_state *pipe_config); | |
da63a9f2 PZ |
1179 | }; |
1180 | ||
0e32b39c DA |
1181 | struct intel_dp_mst_encoder { |
1182 | struct intel_encoder base; | |
1183 | enum pipe pipe; | |
1184 | struct intel_digital_port *primary; | |
0552f765 | 1185 | struct intel_connector *connector; |
0e32b39c DA |
1186 | }; |
1187 | ||
65d64cc5 | 1188 | static inline enum dpio_channel |
89b667f8 JB |
1189 | vlv_dport_to_channel(struct intel_digital_port *dport) |
1190 | { | |
8f4f2797 | 1191 | switch (dport->base.port) { |
89b667f8 | 1192 | case PORT_B: |
00fc31b7 | 1193 | case PORT_D: |
e4607fcf | 1194 | return DPIO_CH0; |
89b667f8 | 1195 | case PORT_C: |
e4607fcf | 1196 | return DPIO_CH1; |
89b667f8 JB |
1197 | default: |
1198 | BUG(); | |
1199 | } | |
1200 | } | |
1201 | ||
65d64cc5 VS |
1202 | static inline enum dpio_phy |
1203 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
1204 | { | |
8f4f2797 | 1205 | switch (dport->base.port) { |
65d64cc5 VS |
1206 | case PORT_B: |
1207 | case PORT_C: | |
1208 | return DPIO_PHY0; | |
1209 | case PORT_D: | |
1210 | return DPIO_PHY1; | |
1211 | default: | |
1212 | BUG(); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | static inline enum dpio_channel | |
eb69b0e5 CML |
1217 | vlv_pipe_to_channel(enum pipe pipe) |
1218 | { | |
1219 | switch (pipe) { | |
1220 | case PIPE_A: | |
1221 | case PIPE_C: | |
1222 | return DPIO_CH0; | |
1223 | case PIPE_B: | |
1224 | return DPIO_CH1; | |
1225 | default: | |
1226 | BUG(); | |
1227 | } | |
1228 | } | |
1229 | ||
e2af48c6 | 1230 | static inline struct intel_crtc * |
b91eb5cc | 1231 | intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
f875c15a | 1232 | { |
f875c15a CW |
1233 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
1234 | } | |
1235 | ||
e2af48c6 | 1236 | static inline struct intel_crtc * |
ed15030d | 1237 | intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) |
417ae147 | 1238 | { |
417ae147 CW |
1239 | return dev_priv->plane_to_crtc_mapping[plane]; |
1240 | } | |
1241 | ||
5f1aae65 | 1242 | struct intel_load_detect_pipe { |
edde3617 | 1243 | struct drm_atomic_state *restore_state; |
5f1aae65 | 1244 | }; |
79e53945 | 1245 | |
5f1aae65 PZ |
1246 | static inline struct intel_encoder * |
1247 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
1248 | { |
1249 | return to_intel_connector(connector)->encoder; | |
1250 | } | |
1251 | ||
4ef03f83 | 1252 | static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) |
da63a9f2 | 1253 | { |
4ef03f83 | 1254 | switch (encoder->type) { |
7e732cac | 1255 | case INTEL_OUTPUT_DDI: |
9a5da00b ACO |
1256 | case INTEL_OUTPUT_DP: |
1257 | case INTEL_OUTPUT_EDP: | |
1258 | case INTEL_OUTPUT_HDMI: | |
4ef03f83 VS |
1259 | return true; |
1260 | default: | |
1261 | return false; | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | static inline struct intel_digital_port * | |
1266 | enc_to_dig_port(struct drm_encoder *encoder) | |
1267 | { | |
1268 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
1269 | ||
1270 | if (intel_encoder_is_dig_port(intel_encoder)) | |
9a5da00b ACO |
1271 | return container_of(encoder, struct intel_digital_port, |
1272 | base.base); | |
4ef03f83 | 1273 | else |
9a5da00b | 1274 | return NULL; |
9ff8c9ba ID |
1275 | } |
1276 | ||
0e32b39c DA |
1277 | static inline struct intel_dp_mst_encoder * |
1278 | enc_to_mst(struct drm_encoder *encoder) | |
1279 | { | |
1280 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
1281 | } | |
1282 | ||
9ff8c9ba ID |
1283 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1284 | { | |
1285 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1286 | } |
1287 | ||
14aa521c VS |
1288 | static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) |
1289 | { | |
1290 | switch (encoder->type) { | |
1291 | case INTEL_OUTPUT_DP: | |
1292 | case INTEL_OUTPUT_EDP: | |
1293 | return true; | |
1294 | case INTEL_OUTPUT_DDI: | |
1295 | /* Skip pure HDMI/DVI DDI encoders */ | |
1296 | return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg); | |
1297 | default: | |
1298 | return false; | |
1299 | } | |
1300 | } | |
1301 | ||
da63a9f2 PZ |
1302 | static inline struct intel_digital_port * |
1303 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1304 | { | |
1305 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1306 | } | |
1307 | ||
dd75f6dd ID |
1308 | static inline struct intel_lspcon * |
1309 | dp_to_lspcon(struct intel_dp *intel_dp) | |
1310 | { | |
1311 | return &dp_to_dig_port(intel_dp)->lspcon; | |
1312 | } | |
1313 | ||
da63a9f2 PZ |
1314 | static inline struct intel_digital_port * |
1315 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1316 | { | |
1317 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1318 | } |
1319 | ||
b2b55502 VS |
1320 | static inline struct intel_plane_state * |
1321 | intel_atomic_get_new_plane_state(struct intel_atomic_state *state, | |
1322 | struct intel_plane *plane) | |
1323 | { | |
1324 | return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, | |
1325 | &plane->base)); | |
1326 | } | |
1327 | ||
7b510451 VS |
1328 | static inline struct intel_crtc_state * |
1329 | intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, | |
1330 | struct intel_crtc *crtc) | |
1331 | { | |
1332 | return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, | |
1333 | &crtc->base)); | |
1334 | } | |
1335 | ||
d3a8fb32 VS |
1336 | static inline struct intel_crtc_state * |
1337 | intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, | |
1338 | struct intel_crtc *crtc) | |
1339 | { | |
1340 | return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, | |
1341 | &crtc->base)); | |
1342 | } | |
1343 | ||
47339cd9 | 1344 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1345 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1346 | enum pipe pipe, bool enable); |
a72e4c9f | 1347 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
a2196033 | 1348 | enum pipe pch_transcoder, |
87440425 | 1349 | bool enable); |
1f7247c0 DV |
1350 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1351 | enum pipe pipe); | |
1352 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
a2196033 | 1353 | enum pipe pch_transcoder); |
aca7b684 VS |
1354 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1355 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
1356 | |
1357 | /* i915_irq.c */ | |
480c8033 DV |
1358 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1359 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
f4e9af4f AG |
1360 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); |
1361 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); | |
d02b98b8 | 1362 | void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
dc97997a | 1363 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
91d14251 TU |
1364 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
1365 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); | |
1300b4f8 CW |
1366 | |
1367 | static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, | |
1368 | u32 mask) | |
1369 | { | |
562d9bae | 1370 | return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; |
1300b4f8 CW |
1371 | } |
1372 | ||
b963291c DV |
1373 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1374 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1375 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1376 | { | |
1377 | /* | |
1378 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1379 | * this is the only thing we need to check. | |
1380 | */ | |
ad1443f0 | 1381 | return dev_priv->runtime_pm.irqs_enabled; |
9df7575f JB |
1382 | } |
1383 | ||
a225f079 | 1384 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be | 1385 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
001bd2cb | 1386 | u8 pipe_mask); |
aae8ba84 | 1387 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
001bd2cb | 1388 | u8 pipe_mask); |
26705e20 SAK |
1389 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); |
1390 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); | |
1391 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); | |
5f1aae65 | 1392 | |
5f1aae65 | 1393 | /* intel_crt.c */ |
6102a8ee VS |
1394 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
1395 | i915_reg_t adpa_reg, enum pipe *pipe); | |
c39055b0 | 1396 | void intel_crt_init(struct drm_i915_private *dev_priv); |
9504a892 | 1397 | void intel_crt_reset(struct drm_encoder *encoder); |
5f1aae65 PZ |
1398 | |
1399 | /* intel_ddi.c */ | |
b7076546 | 1400 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
5f88a9c6 VS |
1401 | const struct intel_crtc_state *old_crtc_state, |
1402 | const struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
1403 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
1404 | const struct intel_crtc_state *crtc_state); | |
c39055b0 | 1405 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); |
87440425 | 1406 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
3dc38eea | 1407 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); |
90c3e219 | 1408 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); |
3dc38eea ACO |
1409 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1410 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); | |
3dc38eea | 1411 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); |
ad64217b | 1412 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 | 1413 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
87440425 | 1414 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1415 | struct intel_crtc_state *pipe_config); |
5f1aae65 | 1416 | |
3dc38eea ACO |
1417 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1418 | bool state); | |
53e9bf5e VS |
1419 | void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, |
1420 | struct intel_crtc_state *crtc_state); | |
d509af6c | 1421 | u32 bxt_signal_levels(struct intel_dp *intel_dp); |
f8896f5d | 1422 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
ffe5111e | 1423 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); |
4718a365 VS |
1424 | u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, |
1425 | u8 voltage_swing); | |
2320175f SP |
1426 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, |
1427 | bool enable); | |
c27e917e PZ |
1428 | void icl_map_plls_to_ports(struct drm_crtc *crtc, |
1429 | struct intel_crtc_state *crtc_state, | |
1430 | struct drm_atomic_state *old_state); | |
1431 | void icl_unmap_plls_to_ports(struct drm_crtc *crtc, | |
1432 | struct intel_crtc_state *crtc_state, | |
1433 | struct drm_atomic_state *old_state); | |
ffe5111e | 1434 | |
d88c4afd VS |
1435 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, |
1436 | int plane, unsigned int height); | |
b680c37a | 1437 | |
7c10a2b5 | 1438 | /* intel_audio.c */ |
88212941 | 1439 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
bbf35e9d ML |
1440 | void intel_audio_codec_enable(struct intel_encoder *encoder, |
1441 | const struct intel_crtc_state *crtc_state, | |
1442 | const struct drm_connector_state *conn_state); | |
8ec47de2 VS |
1443 | void intel_audio_codec_disable(struct intel_encoder *encoder, |
1444 | const struct intel_crtc_state *old_crtc_state, | |
1445 | const struct drm_connector_state *old_conn_state); | |
58fddc28 ID |
1446 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1447 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
eef57324 JA |
1448 | void intel_audio_init(struct drm_i915_private *dev_priv); |
1449 | void intel_audio_deinit(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 1450 | |
7ff89ca2 | 1451 | /* intel_cdclk.c */ |
d305e061 | 1452 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); |
e1cd3325 PZ |
1453 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
1454 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
d8d4a512 VS |
1455 | void cnl_init_cdclk(struct drm_i915_private *dev_priv); |
1456 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
e1cd3325 PZ |
1457 | void bxt_init_cdclk(struct drm_i915_private *dev_priv); |
1458 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); | |
186a277e PZ |
1459 | void icl_init_cdclk(struct drm_i915_private *dev_priv); |
1460 | void icl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
7ff89ca2 VS |
1461 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); |
1462 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv); | |
1463 | void intel_update_cdclk(struct drm_i915_private *dev_priv); | |
1464 | void intel_update_rawclk(struct drm_i915_private *dev_priv); | |
64600bd5 | 1465 | bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, |
49cd97a3 | 1466 | const struct intel_cdclk_state *b); |
64600bd5 VS |
1467 | bool intel_cdclk_changed(const struct intel_cdclk_state *a, |
1468 | const struct intel_cdclk_state *b); | |
b0587e4d VS |
1469 | void intel_set_cdclk(struct drm_i915_private *dev_priv, |
1470 | const struct intel_cdclk_state *cdclk_state); | |
cfddadc9 VS |
1471 | void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, |
1472 | const char *context); | |
7ff89ca2 | 1473 | |
b680c37a | 1474 | /* intel_display.c */ |
2ee0da16 VS |
1475 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); |
1476 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
a2196033 | 1477 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); |
19ab4ed3 | 1478 | void intel_update_rawclk(struct drm_i915_private *dev_priv); |
49cd97a3 | 1479 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1480 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1481 | const char *name, u32 reg, int ref_freq); | |
7ff89ca2 VS |
1482 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
1483 | const char *name, u32 reg); | |
b7076546 ML |
1484 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); |
1485 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
88212941 | 1486 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
6687c906 | 1487 | unsigned int intel_fb_xy_to_linear(int x, int y, |
2949056c VS |
1488 | const struct intel_plane_state *state, |
1489 | int plane); | |
6687c906 | 1490 | void intel_add_fb_offsets(int *x, int *y, |
2949056c | 1491 | const struct intel_plane_state *state, int plane); |
1663b9d6 | 1492 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
49d73912 | 1493 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); |
7d993739 TU |
1494 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1495 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
70e0bd74 | 1496 | int intel_display_suspend(struct drm_device *dev); |
8090ba8c | 1497 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); |
87440425 | 1498 | void intel_encoder_destroy(struct drm_encoder *encoder); |
08d9bc92 ACO |
1499 | int intel_connector_init(struct intel_connector *); |
1500 | struct intel_connector *intel_connector_alloc(void); | |
091a4f91 | 1501 | void intel_connector_free(struct intel_connector *connector); |
87440425 | 1502 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
87440425 PZ |
1503 | void intel_connector_attach_encoder(struct intel_connector *connector, |
1504 | struct intel_encoder *encoder); | |
de330815 VS |
1505 | struct drm_display_mode * |
1506 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
ac213c1b PZ |
1507 | bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); |
1508 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, | |
1509 | enum port port); | |
de330815 | 1510 | |
752aa88a | 1511 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
6a20fe7b VS |
1512 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
1513 | struct drm_file *file_priv); | |
87440425 PZ |
1514 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1515 | enum pipe pipe); | |
2d84d2b3 VS |
1516 | static inline bool |
1517 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, | |
1518 | enum intel_output_type type) | |
1519 | { | |
1520 | return crtc_state->output_types & (1 << type); | |
1521 | } | |
37a5650b VS |
1522 | static inline bool |
1523 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) | |
1524 | { | |
1525 | return crtc_state->output_types & | |
cca0502b | 1526 | ((1 << INTEL_OUTPUT_DP) | |
37a5650b VS |
1527 | (1 << INTEL_OUTPUT_DP_MST) | |
1528 | (1 << INTEL_OUTPUT_EDP)); | |
1529 | } | |
4f905cf9 | 1530 | static inline void |
0f0f74bc | 1531 | intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) |
4f905cf9 | 1532 | { |
0f0f74bc | 1533 | drm_wait_one_vblank(&dev_priv->drm, pipe); |
4f905cf9 | 1534 | } |
0c241d5b | 1535 | static inline void |
0f0f74bc | 1536 | intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) |
0c241d5b | 1537 | { |
b91eb5cc | 1538 | const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
0c241d5b VS |
1539 | |
1540 | if (crtc->active) | |
0f0f74bc | 1541 | intel_wait_for_vblank(dev_priv, pipe); |
0c241d5b | 1542 | } |
a2991414 ML |
1543 | |
1544 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
1545 | ||
87440425 | 1546 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1547 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1548 | struct intel_digital_port *dport, |
1549 | unsigned int expected_mask); | |
6c5ed5ae | 1550 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 1551 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
1552 | struct intel_load_detect_pipe *old, |
1553 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1554 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1555 | struct intel_load_detect_pipe *old, |
1556 | struct drm_modeset_acquire_ctx *ctx); | |
058d88c4 | 1557 | struct i915_vma * |
5935485f CW |
1558 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
1559 | unsigned int rotation, | |
f7a02ad7 | 1560 | bool uses_fence, |
5935485f CW |
1561 | unsigned long *out_flags); |
1562 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); | |
a8bb6818 | 1563 | struct drm_framebuffer * |
24dbf51a CW |
1564 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
1565 | struct drm_mode_fb_cmd2 *mode_cmd); | |
6beb8c23 | 1566 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1832040d | 1567 | struct drm_plane_state *new_state); |
38f3ce3a | 1568 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
1832040d | 1569 | struct drm_plane_state *old_state); |
a98b3431 MR |
1570 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1571 | const struct drm_plane_state *state, | |
1572 | struct drm_property *property, | |
1573 | uint64_t *val); | |
1574 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1575 | struct drm_plane_state *state, | |
1576 | struct drm_property *property, | |
1577 | uint64_t val); | |
b2b55502 VS |
1578 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
1579 | struct drm_crtc_state *crtc_state, | |
1580 | const struct intel_plane_state *old_plane_state, | |
da20eabd | 1581 | struct drm_plane_state *plane_state); |
716c2e55 | 1582 | |
7abd4b35 ACO |
1583 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1584 | enum pipe pipe); | |
1585 | ||
30ad9814 | 1586 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 1587 | const struct dpll *dpll); |
30ad9814 | 1588 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); |
8802e5b6 | 1589 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1590 | |
716c2e55 | 1591 | /* modesetting asserts */ |
b680c37a DV |
1592 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1593 | enum pipe pipe); | |
55607e8a DV |
1594 | void assert_pll(struct drm_i915_private *dev_priv, |
1595 | enum pipe pipe, bool state); | |
1596 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1597 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1598 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1599 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1600 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1601 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1602 | enum pipe pipe, bool state); | |
1603 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1604 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1605 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1606 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1607 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
4f2d9934 | 1608 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c | 1609 | const struct intel_plane_state *state, int plane); |
c033666a CW |
1610 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1611 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
a14cb6fc PZ |
1612 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1613 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
da2f41d1 | 1614 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
664326f8 SK |
1615 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1616 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
f62c79b3 | 1617 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
c89e39f3 | 1618 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
87440425 | 1619 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1620 | struct intel_crtc_state *pipe_config); |
fe3cd48d | 1621 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
87440425 | 1622 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
5ab7b0b7 | 1623 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 ACO |
1624 | struct dpll *best_clock); |
1625 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1626 | |
525b9311 | 1627 | bool intel_crtc_active(struct intel_crtc *crtc); |
24f28450 | 1628 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); |
199ea381 ML |
1629 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state); |
1630 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state); | |
79f255a0 | 1631 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); |
f6a83288 | 1632 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1633 | struct intel_crtc_state *pipe_config); |
d52ad9cb ML |
1634 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
1635 | struct intel_crtc_state *crtc_state); | |
86adf9d7 | 1636 | |
0a59952b | 1637 | u16 skl_scaler_calc_phase(int sub, bool chroma_center); |
e435d6e5 | 1638 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
77224cd5 CK |
1639 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, |
1640 | uint32_t pixel_format); | |
8ea30864 | 1641 | |
be1e3415 CW |
1642 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) |
1643 | { | |
1644 | return i915_ggtt_offset(state->vma); | |
1645 | } | |
dedf278c | 1646 | |
4036c78c JA |
1647 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
1648 | const struct intel_plane_state *plane_state); | |
2e881264 VS |
1649 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
1650 | const struct intel_plane_state *plane_state); | |
38f24f21 | 1651 | u32 glk_color_ctl(const struct intel_plane_state *plane_state); |
d2196774 VS |
1652 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
1653 | unsigned int rotation); | |
c322c649 ID |
1654 | int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, |
1655 | struct intel_plane_state *plane_state); | |
f9407ae1 | 1656 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); |
ddf34319 | 1657 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); |
121920fa | 1658 | |
eb805623 | 1659 | /* intel_csr.c */ |
f4448375 | 1660 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1661 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1662 | void intel_csr_ucode_fini(struct drm_i915_private *); |
f74ed08d ID |
1663 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
1664 | void intel_csr_ucode_resume(struct drm_i915_private *); | |
eb805623 | 1665 | |
5f1aae65 | 1666 | /* intel_dp.c */ |
59b74c49 VS |
1667 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, |
1668 | i915_reg_t dp_reg, enum port port, | |
1669 | enum pipe *pipe); | |
c39055b0 ACO |
1670 | bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, |
1671 | enum port port); | |
87440425 PZ |
1672 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1673 | struct intel_connector *intel_connector); | |
901c2daf | 1674 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1675 | int link_rate, uint8_t lane_count, |
1676 | bool link_mst); | |
fdb14d33 MN |
1677 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
1678 | int link_rate, uint8_t lane_count); | |
87440425 | 1679 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 | 1680 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c85d200e VS |
1681 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
1682 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1683 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
bf93ba67 ID |
1684 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1685 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | |
87440425 | 1686 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
87440425 | 1687 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1688 | struct intel_crtc_state *pipe_config, |
1689 | struct drm_connector_state *conn_state); | |
1853a9da | 1690 | bool intel_dp_is_edp(struct intel_dp *intel_dp); |
7b91bf7f | 1691 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
b2c5c181 DV |
1692 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1693 | bool long_hpd); | |
b037d58f ML |
1694 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
1695 | const struct drm_connector_state *conn_state); | |
1696 | void intel_edp_backlight_off(const struct drm_connector_state *conn_state); | |
24f3e092 | 1697 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1698 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1699 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
1a4313d1 VS |
1700 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); |
1701 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv); | |
50fec21a | 1702 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
3d65a735 | 1703 | int intel_dp_max_lane_count(struct intel_dp *intel_dp); |
ed4e9c1d | 1704 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1705 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
78597996 | 1706 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1707 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1708 | void intel_plane_destroy(struct drm_plane *plane); |
85cb48a1 | 1709 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 1710 | const struct intel_crtc_state *crtc_state); |
85cb48a1 | 1711 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 1712 | const struct intel_crtc_state *crtc_state); |
5748b6a1 CW |
1713 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
1714 | unsigned int frontbuffer_bits); | |
1715 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, | |
1716 | unsigned int frontbuffer_bits); | |
340a44be | 1717 | void icl_program_mg_dp_mode(struct intel_dp *intel_dp); |
bc334d91 PZ |
1718 | void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port); |
1719 | void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port); | |
0bc12bcb | 1720 | |
94223d04 ACO |
1721 | void |
1722 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1723 | uint8_t dp_train_pat); | |
1724 | void | |
1725 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1726 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1727 | uint8_t | |
1728 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1729 | uint8_t | |
1730 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1731 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1732 | uint8_t *link_bw, uint8_t *rate_select); | |
e588fa18 | 1733 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
2edd5327 | 1734 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); |
94223d04 ACO |
1735 | bool |
1736 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
1737 | ||
419b1b7a ACO |
1738 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
1739 | { | |
1740 | return ~((1 << lane_count) - 1) & 0xf; | |
1741 | } | |
1742 | ||
24e807e7 | 1743 | bool intel_dp_read_dpcd(struct intel_dp *intel_dp); |
22a2c8e0 DP |
1744 | int intel_dp_link_required(int pixel_clock, int bpp); |
1745 | int intel_dp_max_data_rate(int max_link_clock, int max_lanes); | |
7533eb4f | 1746 | bool intel_digital_port_connected(struct intel_encoder *encoder); |
24e807e7 | 1747 | |
e7156c83 YA |
1748 | /* intel_dp_aux_backlight.c */ |
1749 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); | |
1750 | ||
0e32b39c DA |
1751 | /* intel_dp_mst.c */ |
1752 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1753 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
ca3589c1 | 1754 | /* vlv_dsi.c */ |
e518634b | 1755 | void vlv_dsi_init(struct drm_i915_private *dev_priv); |
5f1aae65 | 1756 | |
90198355 JN |
1757 | /* intel_dsi_dcs_backlight.c */ |
1758 | int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); | |
5f1aae65 PZ |
1759 | |
1760 | /* intel_dvo.c */ | |
c39055b0 | 1761 | void intel_dvo_init(struct drm_i915_private *dev_priv); |
19625e85 L |
1762 | /* intel_hotplug.c */ |
1763 | void intel_hpd_poll_init(struct drm_i915_private *dev_priv); | |
dba14b27 VS |
1764 | bool intel_encoder_hotplug(struct intel_encoder *encoder, |
1765 | struct intel_connector *connector); | |
5f1aae65 | 1766 | |
0632fef6 | 1767 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 1768 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 1769 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 1770 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4f256d82 DV |
1771 | extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); |
1772 | extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); | |
82e3b8c1 | 1773 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1774 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1775 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1776 | #else |
1777 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1778 | { | |
1779 | return 0; | |
1780 | } | |
5f1aae65 | 1781 | |
e00bf696 | 1782 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a DV |
1783 | { |
1784 | } | |
1785 | ||
4f256d82 DV |
1786 | static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) |
1787 | { | |
1788 | } | |
1789 | ||
1790 | static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) | |
4520f53a DV |
1791 | { |
1792 | } | |
1793 | ||
82e3b8c1 | 1794 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1795 | { |
1796 | } | |
1797 | ||
d9c409d6 JN |
1798 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
1799 | { | |
1800 | } | |
1801 | ||
0632fef6 | 1802 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1803 | { |
1804 | } | |
1805 | #endif | |
5f1aae65 | 1806 | |
7ff0ebcc | 1807 | /* intel_fbc.c */ |
f51be2e0 | 1808 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
dd57602e | 1809 | struct intel_atomic_state *state); |
0e631adc | 1810 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1811 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
1812 | struct intel_crtc_state *crtc_state, | |
1813 | struct intel_plane_state *plane_state); | |
1eb52238 | 1814 | void intel_fbc_post_update(struct intel_crtc *crtc); |
7ff0ebcc | 1815 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 1816 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1817 | void intel_fbc_enable(struct intel_crtc *crtc, |
1818 | struct intel_crtc_state *crtc_state, | |
1819 | struct intel_plane_state *plane_state); | |
c937ab3e PZ |
1820 | void intel_fbc_disable(struct intel_crtc *crtc); |
1821 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
1822 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1823 | unsigned int frontbuffer_bits, | |
1824 | enum fb_op_origin origin); | |
1825 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1826 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 1827 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
61a585d6 | 1828 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); |
d52ad9cb | 1829 | int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1830 | |
5f1aae65 | 1831 | /* intel_hdmi.c */ |
c39055b0 ACO |
1832 | void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, |
1833 | enum port port); | |
87440425 PZ |
1834 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1835 | struct intel_connector *intel_connector); | |
1836 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1837 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
0a478c27 ML |
1838 | struct intel_crtc_state *pipe_config, |
1839 | struct drm_connector_state *conn_state); | |
277ab5ab | 1840 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
1841 | struct drm_connector *connector, |
1842 | bool high_tmds_clock_ratio, | |
1843 | bool scrambling); | |
b2ccb822 | 1844 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
385e4de0 | 1845 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port); |
5f1aae65 PZ |
1846 | |
1847 | ||
1848 | /* intel_lvds.c */ | |
a44628b9 VS |
1849 | bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, |
1850 | i915_reg_t lvds_reg, enum pipe *pipe); | |
c39055b0 | 1851 | void intel_lvds_init(struct drm_i915_private *dev_priv); |
97a824e1 | 1852 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev); |
87440425 | 1853 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
5f1aae65 PZ |
1854 | |
1855 | ||
1856 | /* intel_modes.c */ | |
1857 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1858 | struct edid *edid); |
5f1aae65 | 1859 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1860 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1861 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
7949dd47 | 1862 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
5f1aae65 PZ |
1863 | |
1864 | ||
1865 | /* intel_overlay.c */ | |
1ee8da6d CW |
1866 | void intel_setup_overlay(struct drm_i915_private *dev_priv); |
1867 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv); | |
87440425 | 1868 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
1ee8da6d CW |
1869 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
1870 | struct drm_file *file_priv); | |
1871 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
1872 | struct drm_file *file_priv); | |
1362b776 | 1873 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
1874 | |
1875 | ||
1876 | /* intel_panel.c */ | |
87440425 | 1877 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1878 | struct drm_display_mode *fixed_mode, |
1879 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1880 | void intel_panel_fini(struct intel_panel *panel); |
1881 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1882 | struct drm_display_mode *adjusted_mode); | |
1883 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1884 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
1885 | int fitting_mode); |
1886 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1887 | struct intel_crtc_state *pipe_config, |
87440425 | 1888 | int fitting_mode); |
90d7cd24 | 1889 | void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state, |
6dda730e | 1890 | u32 level, u32 max); |
fda9ee98 CW |
1891 | int intel_panel_setup_backlight(struct drm_connector *connector, |
1892 | enum pipe pipe); | |
b037d58f ML |
1893 | void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, |
1894 | const struct drm_connector_state *conn_state); | |
1895 | void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state); | |
db31af1d | 1896 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
ec9ed197 | 1897 | extern struct drm_display_mode *intel_find_panel_downclock( |
a318b4c4 | 1898 | struct drm_i915_private *dev_priv, |
ec9ed197 VK |
1899 | struct drm_display_mode *fixed_mode, |
1900 | struct drm_connector *connector); | |
e63d87c0 CW |
1901 | |
1902 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) | |
1ebaa0b9 | 1903 | int intel_backlight_device_register(struct intel_connector *connector); |
e63d87c0 CW |
1904 | void intel_backlight_device_unregister(struct intel_connector *connector); |
1905 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
2de2d0b0 | 1906 | static inline int intel_backlight_device_register(struct intel_connector *connector) |
1ebaa0b9 CW |
1907 | { |
1908 | return 0; | |
1909 | } | |
e63d87c0 CW |
1910 | static inline void intel_backlight_device_unregister(struct intel_connector *connector) |
1911 | { | |
1912 | } | |
1913 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
0962c3c9 | 1914 | |
ee5e5e7a SP |
1915 | /* intel_hdcp.c */ |
1916 | void intel_hdcp_atomic_check(struct drm_connector *connector, | |
1917 | struct drm_connector_state *old_state, | |
1918 | struct drm_connector_state *new_state); | |
1919 | int intel_hdcp_init(struct intel_connector *connector, | |
1920 | const struct intel_hdcp_shim *hdcp_shim); | |
1921 | int intel_hdcp_enable(struct intel_connector *connector); | |
1922 | int intel_hdcp_disable(struct intel_connector *connector); | |
1923 | int intel_hdcp_check_link(struct intel_connector *connector); | |
fdddd08c | 1924 | bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); |
5f1aae65 | 1925 | |
0bc12bcb | 1926 | /* intel_psr.c */ |
4371d896 | 1927 | #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) |
77fe36ff | 1928 | void intel_psr_init_dpcd(struct intel_dp *intel_dp); |
d2419ffc VS |
1929 | void intel_psr_enable(struct intel_dp *intel_dp, |
1930 | const struct intel_crtc_state *crtc_state); | |
1931 | void intel_psr_disable(struct intel_dp *intel_dp, | |
1932 | const struct intel_crtc_state *old_crtc_state); | |
5748b6a1 | 1933 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc RV |
1934 | unsigned frontbuffer_bits, |
1935 | enum fb_op_origin origin); | |
5748b6a1 | 1936 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 RV |
1937 | unsigned frontbuffer_bits, |
1938 | enum fb_op_origin origin); | |
c39055b0 | 1939 | void intel_psr_init(struct drm_i915_private *dev_priv); |
4d90f2d5 VS |
1940 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
1941 | struct intel_crtc_state *crtc_state); | |
54fd3149 DP |
1942 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug); |
1943 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); | |
cc3054ff | 1944 | void intel_psr_short_pulse(struct intel_dp *intel_dp); |
c3d43361 | 1945 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state); |
0bc12bcb | 1946 | |
9c065a7d DV |
1947 | /* intel_runtime_pm.c */ |
1948 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1949 | void intel_power_domains_fini(struct drm_i915_private *); |
73dfc227 ID |
1950 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
1951 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); | |
8d8c386c | 1952 | void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); |
d7d7c9ee ID |
1953 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
1954 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); | |
f458ebbc | 1955 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9895ad03 DS |
1956 | const char * |
1957 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 1958 | |
f458ebbc DV |
1959 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1960 | enum intel_display_power_domain domain); | |
1961 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1962 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1963 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1964 | enum intel_display_power_domain domain); | |
09731280 ID |
1965 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
1966 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1967 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1968 | enum intel_display_power_domain domain); | |
aa9664ff MK |
1969 | void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, |
1970 | u8 req_slices); | |
da5827c3 ID |
1971 | |
1972 | static inline void | |
1973 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) | |
1974 | { | |
ad1443f0 | 1975 | WARN_ONCE(dev_priv->runtime_pm.suspended, |
da5827c3 ID |
1976 | "Device suspended during HW access\n"); |
1977 | } | |
1978 | ||
1979 | static inline void | |
1980 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) | |
1981 | { | |
1982 | assert_rpm_device_not_suspended(dev_priv); | |
ad1443f0 | 1983 | WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count), |
1f58c8e7 | 1984 | "RPM wakelock ref not held during HW access"); |
da5827c3 ID |
1985 | } |
1986 | ||
1f814dac ID |
1987 | /** |
1988 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
1989 | * @dev_priv: i915 device instance | |
1990 | * | |
1991 | * This function disable asserts that check if we hold an RPM wakelock | |
1992 | * reference, while keeping the device-not-suspended checks still enabled. | |
1993 | * It's meant to be used only in special circumstances where our rule about | |
1994 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
1995 | * to this rule at any point where we access the HW or want to keep the HW in | |
1996 | * an active state we must hold an RPM wakelock reference acquired via one of | |
1997 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
1998 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
1999 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
2000 | * users should avoid using this function. | |
2001 | * | |
2002 | * Any calls to this function must have a symmetric call to | |
2003 | * enable_rpm_wakeref_asserts(). | |
2004 | */ | |
2005 | static inline void | |
2006 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
2007 | { | |
ad1443f0 | 2008 | atomic_inc(&dev_priv->runtime_pm.wakeref_count); |
1f814dac ID |
2009 | } |
2010 | ||
2011 | /** | |
2012 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
2013 | * @dev_priv: i915 device instance | |
2014 | * | |
2015 | * This function re-enables the RPM assert checks after disabling them with | |
2016 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
2017 | * circumstances otherwise its use should be avoided. | |
2018 | * | |
2019 | * Any calls to this function must have a symmetric call to | |
2020 | * disable_rpm_wakeref_asserts(). | |
2021 | */ | |
2022 | static inline void | |
2023 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
2024 | { | |
ad1443f0 | 2025 | atomic_dec(&dev_priv->runtime_pm.wakeref_count); |
1f814dac ID |
2026 | } |
2027 | ||
9c065a7d | 2028 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
09731280 | 2029 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
9c065a7d DV |
2030 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
2031 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
2032 | ||
d9bc89d9 DV |
2033 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
2034 | ||
e0fce78f VS |
2035 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
2036 | bool override, unsigned int mask); | |
b0b33846 VS |
2037 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
2038 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
2039 | |
2040 | ||
5f1aae65 | 2041 | /* intel_pm.c */ |
46f16e63 | 2042 | void intel_init_clock_gating(struct drm_i915_private *dev_priv); |
712bf364 | 2043 | void intel_suspend_hw(struct drm_i915_private *dev_priv); |
5db94019 | 2044 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv); |
432081bc | 2045 | void intel_update_watermarks(struct intel_crtc *crtc); |
62d75df7 | 2046 | void intel_init_pm(struct drm_i915_private *dev_priv); |
bb400da9 | 2047 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
192aa181 | 2048 | void intel_pm_setup(struct drm_i915_private *dev_priv); |
87440425 PZ |
2049 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
2050 | void intel_gpu_ips_teardown(void); | |
dc97997a | 2051 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f CW |
2052 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); |
2053 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); | |
dc97997a CW |
2054 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); |
2055 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); | |
54b4f68f | 2056 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); |
43cf3bf0 CW |
2057 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
2058 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 2059 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
e61e0f51 | 2060 | void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps); |
04548cba | 2061 | void g4x_wm_get_hw_state(struct drm_device *dev); |
6eb1a681 | 2062 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 2063 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 2064 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
2065 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2066 | struct skl_ddb_allocation *ddb /* out */); | |
bf9d99ad | 2067 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
2068 | struct skl_pipe_wm *out); | |
04548cba | 2069 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv); |
602ae835 | 2070 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv); |
16dcdc4e PZ |
2071 | bool intel_can_enable_sagv(struct drm_atomic_state *state); |
2072 | int intel_enable_sagv(struct drm_i915_private *dev_priv); | |
2073 | int intel_disable_sagv(struct drm_i915_private *dev_priv); | |
45ece230 | 2074 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
2075 | const struct skl_wm_level *l2); | |
2b68504b MK |
2076 | bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv, |
2077 | const struct skl_ddb_entry **entries, | |
5eff503b ML |
2078 | const struct skl_ddb_entry *ddb, |
2079 | int ignore); | |
ed4a6a7c | 2080 | bool ilk_disable_lp_wm(struct drm_device *dev); |
73b0ca8e MK |
2081 | int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, |
2082 | struct intel_crtc_state *cstate); | |
2503a0fe KM |
2083 | void intel_init_ipc(struct drm_i915_private *dev_priv); |
2084 | void intel_enable_ipc(struct drm_i915_private *dev_priv); | |
72662e10 | 2085 | |
5f1aae65 | 2086 | /* intel_sdvo.c */ |
76203467 VS |
2087 | bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, |
2088 | i915_reg_t sdvo_reg, enum pipe *pipe); | |
c39055b0 | 2089 | bool intel_sdvo_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2090 | i915_reg_t reg, enum port port); |
96a02917 | 2091 | |
2b28bb1b | 2092 | |
5f1aae65 | 2093 | /* intel_sprite.c */ |
dfd2e9ab VS |
2094 | int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
2095 | int usecs); | |
580503c7 | 2096 | struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, |
b079bd17 | 2097 | enum pipe pipe, int plane); |
6a20fe7b VS |
2098 | int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, |
2099 | struct drm_file *file_priv); | |
d3a8fb32 VS |
2100 | void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state); |
2101 | void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state); | |
9a8cc576 JPH |
2102 | void skl_update_plane(struct intel_plane *plane, |
2103 | const struct intel_crtc_state *crtc_state, | |
2104 | const struct intel_plane_state *plane_state); | |
779d4d8f | 2105 | void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc); |
eade6c89 | 2106 | bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe); |
77064e2e VS |
2107 | bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, |
2108 | enum pipe pipe, enum plane_id plane_id); | |
c0b56ab5 CK |
2109 | bool skl_plane_has_planar(struct drm_i915_private *dev_priv, |
2110 | enum pipe pipe, enum plane_id plane_id); | |
5f1aae65 PZ |
2111 | |
2112 | /* intel_tv.c */ | |
c39055b0 | 2113 | void intel_tv_init(struct drm_i915_private *dev_priv); |
20ddf665 | 2114 | |
ea2c67bb | 2115 | /* intel_atomic.c */ |
11c1a9ec ML |
2116 | int intel_digital_connector_atomic_get_property(struct drm_connector *connector, |
2117 | const struct drm_connector_state *state, | |
2118 | struct drm_property *property, | |
2119 | uint64_t *val); | |
2120 | int intel_digital_connector_atomic_set_property(struct drm_connector *connector, | |
2121 | struct drm_connector_state *state, | |
2122 | struct drm_property *property, | |
2123 | uint64_t val); | |
2124 | int intel_digital_connector_atomic_check(struct drm_connector *conn, | |
2125 | struct drm_connector_state *new_state); | |
2126 | struct drm_connector_state * | |
2127 | intel_digital_connector_duplicate_state(struct drm_connector *connector); | |
2128 | ||
1356837e MR |
2129 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
2130 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
2131 | struct drm_crtc_state *state); | |
de419ab6 ML |
2132 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
2133 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
de419ab6 | 2134 | |
10f81c19 ACO |
2135 | static inline struct intel_crtc_state * |
2136 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
2137 | struct intel_crtc *crtc) | |
2138 | { | |
2139 | struct drm_crtc_state *crtc_state; | |
2140 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
2141 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 2142 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
2143 | |
2144 | return to_intel_crtc_state(crtc_state); | |
2145 | } | |
e3bddded | 2146 | |
6ebc6923 ACO |
2147 | int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, |
2148 | struct intel_crtc *intel_crtc, | |
2149 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
2150 | |
2151 | /* intel_atomic_plane.c */ | |
8e7d688b | 2152 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
ea2c67bb MR |
2153 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
2154 | void intel_plane_destroy_state(struct drm_plane *plane, | |
2155 | struct drm_plane_state *state); | |
2156 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
b2b55502 VS |
2157 | int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, |
2158 | struct intel_crtc_state *crtc_state, | |
2159 | const struct intel_plane_state *old_plane_state, | |
f79f2692 | 2160 | struct intel_plane_state *intel_state); |
ea2c67bb | 2161 | |
8563b1e8 LL |
2162 | /* intel_color.c */ |
2163 | void intel_color_init(struct drm_crtc *crtc); | |
82cf435b | 2164 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
b95c5321 ML |
2165 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
2166 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); | |
8563b1e8 | 2167 | |
dbe9e61b SS |
2168 | /* intel_lspcon.c */ |
2169 | bool lspcon_init(struct intel_digital_port *intel_dig_port); | |
910530c0 | 2170 | void lspcon_resume(struct intel_lspcon *lspcon); |
357c0ae9 | 2171 | void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); |
731035fe TV |
2172 | |
2173 | /* intel_pipe_crc.c */ | |
8c6b709d TV |
2174 | #ifdef CONFIG_DEBUG_FS |
2175 | int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, | |
2176 | size_t *values_cnt); | |
033b7a23 ML |
2177 | void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc); |
2178 | void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc); | |
8c6b709d TV |
2179 | #else |
2180 | #define intel_crtc_set_crc_source NULL | |
033b7a23 ML |
2181 | static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) |
2182 | { | |
2183 | } | |
2184 | ||
2185 | static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) | |
2186 | { | |
2187 | } | |
8c6b709d | 2188 | #endif |
79e53945 | 2189 | #endif /* __INTEL_DRV_H__ */ |