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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
760285e7 | 31 | #include <drm/i915_drm.h> |
80824003 | 32 | #include "i915_drv.h" |
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
0e32b39c | 36 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 37 | #include <drm/drm_rect.h> |
913d8d11 | 38 | |
1d5bfac9 SV |
39 | /** |
40 | * _wait_for - magic (register) wait macro | |
41 | * | |
42 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
43 | * contexts. Note that it's important that we check the condition again after | |
44 | * having timed out, since the timeout could be due to preemption or similar and | |
45 | * we've never had a chance to check the condition before the timeout. | |
46 | */ | |
481b6af3 | 47 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 48 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 49 | int ret__ = 0; \ |
0206e353 | 50 | while (!(COND)) { \ |
913d8d11 | 51 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 SV |
52 | if (!(COND)) \ |
53 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
54 | break; \ |
55 | } \ | |
0cc2764c BW |
56 | if (W && drm_can_sleep()) { \ |
57 | msleep(W); \ | |
58 | } else { \ | |
59 | cpu_relax(); \ | |
60 | } \ | |
913d8d11 CW |
61 | } \ |
62 | ret__; \ | |
63 | }) | |
64 | ||
481b6af3 CW |
65 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
66 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b SV |
67 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
68 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 69 | |
49938ac4 JN |
70 | #define KHz(x) (1000 * (x)) |
71 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 72 | |
79e53945 JB |
73 | /* |
74 | * Display related stuff | |
75 | */ | |
76 | ||
77 | /* store information about an Ixxx DVO */ | |
78 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
79 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
80 | #define MAX_OUTPUTS 6 | |
81 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 82 | |
4726e0b0 SK |
83 | /* Maximum cursor sizes */ |
84 | #define GEN2_CURSOR_WIDTH 64 | |
85 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
86 | #define MAX_CURSOR_WIDTH 256 |
87 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 88 | |
79e53945 JB |
89 | #define INTEL_I2C_BUS_DVO 1 |
90 | #define INTEL_I2C_BUS_SDVO 2 | |
91 | ||
92 | /* these are outputs from the chip - integrated only | |
93 | external chips are via DVO or SDVO output */ | |
94 | #define INTEL_OUTPUT_UNUSED 0 | |
95 | #define INTEL_OUTPUT_ANALOG 1 | |
96 | #define INTEL_OUTPUT_DVO 2 | |
97 | #define INTEL_OUTPUT_SDVO 3 | |
98 | #define INTEL_OUTPUT_LVDS 4 | |
99 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 100 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 101 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 102 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
103 | #define INTEL_OUTPUT_DSI 9 |
104 | #define INTEL_OUTPUT_UNKNOWN 10 | |
0e32b39c | 105 | #define INTEL_OUTPUT_DP_MST 11 |
79e53945 JB |
106 | |
107 | #define INTEL_DVO_CHIP_NONE 0 | |
108 | #define INTEL_DVO_CHIP_LVDS 1 | |
109 | #define INTEL_DVO_CHIP_TMDS 2 | |
110 | #define INTEL_DVO_CHIP_TVOUT 4 | |
111 | ||
dfba2e2d SK |
112 | #define INTEL_DSI_VIDEO_MODE 0 |
113 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 114 | |
79e53945 JB |
115 | struct intel_framebuffer { |
116 | struct drm_framebuffer base; | |
05394f39 | 117 | struct drm_i915_gem_object *obj; |
79e53945 JB |
118 | }; |
119 | ||
37811fcc CW |
120 | struct intel_fbdev { |
121 | struct drm_fb_helper helper; | |
8bcd4553 | 122 | struct intel_framebuffer *fb; |
37811fcc CW |
123 | struct list_head fbdev_list; |
124 | struct drm_display_mode *our_mode; | |
d978ef14 | 125 | int preferred_bpp; |
37811fcc | 126 | }; |
79e53945 | 127 | |
21d40d37 | 128 | struct intel_encoder { |
4ef69c7a | 129 | struct drm_encoder base; |
9a935856 SV |
130 | /* |
131 | * The new crtc this encoder will be driven from. Only differs from | |
132 | * base->crtc while a modeset is in progress. | |
133 | */ | |
134 | struct intel_crtc *new_crtc; | |
135 | ||
79e53945 | 136 | int type; |
bc079e8b | 137 | unsigned int cloneable; |
5ab432ef | 138 | bool connectors_active; |
21d40d37 | 139 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 SV |
140 | bool (*compute_config)(struct intel_encoder *, |
141 | struct intel_crtc_config *); | |
dafd226c | 142 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 143 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 144 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 145 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 146 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 147 | void (*post_disable)(struct intel_encoder *); |
f0947c37 SV |
148 | /* Read out the current hw state of this connector, returning true if |
149 | * the encoder is active. If the encoder is enabled it also set the pipe | |
150 | * it is connected to in the pipe parameter. */ | |
151 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 152 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 153 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
154 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
155 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
156 | void (*get_config)(struct intel_encoder *, |
157 | struct intel_crtc_config *pipe_config); | |
07f9cd0b ID |
158 | /* |
159 | * Called during system suspend after all pending requests for the | |
160 | * encoder are flushed (for example for DP AUX transactions) and | |
161 | * device interrupts are disabled. | |
162 | */ | |
163 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 164 | int crtc_mask; |
1d843f9d | 165 | enum hpd_pin hpd_pin; |
79e53945 JB |
166 | }; |
167 | ||
1d508706 | 168 | struct intel_panel { |
dd06f90e | 169 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 170 | struct drm_display_mode *downclock_mode; |
4d891523 | 171 | int fitting_mode; |
58c68779 JN |
172 | |
173 | /* backlight */ | |
174 | struct { | |
c91c9f32 | 175 | bool present; |
58c68779 | 176 | u32 level; |
6dda730e | 177 | u32 min; |
7bd688cd | 178 | u32 max; |
58c68779 | 179 | bool enabled; |
636baebf JN |
180 | bool combination_mode; /* gen 2/4 only */ |
181 | bool active_low_pwm; | |
58c68779 JN |
182 | struct backlight_device *device; |
183 | } backlight; | |
ab656bb9 JN |
184 | |
185 | void (*backlight_power)(struct intel_connector *, bool enable); | |
1d508706 JN |
186 | }; |
187 | ||
5daa55eb ZW |
188 | struct intel_connector { |
189 | struct drm_connector base; | |
9a935856 SV |
190 | /* |
191 | * The fixed encoder this connector is connected to. | |
192 | */ | |
df0e9248 | 193 | struct intel_encoder *encoder; |
9a935856 SV |
194 | |
195 | /* | |
196 | * The new encoder this connector will be driven. Only differs from | |
197 | * encoder while a modeset is in progress. | |
198 | */ | |
199 | struct intel_encoder *new_encoder; | |
200 | ||
f0947c37 SV |
201 | /* Reads out the current hw, returning true if the connector is enabled |
202 | * and active (i.e. dpms ON state). */ | |
203 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 204 | |
4932e2c3 ID |
205 | /* |
206 | * Removes all interfaces through which the connector is accessible | |
207 | * - like sysfs, debugfs entries -, so that no new operations can be | |
208 | * started on the connector. Also makes sure all currently pending | |
209 | * operations finish before returing. | |
210 | */ | |
211 | void (*unregister)(struct intel_connector *); | |
212 | ||
1d508706 JN |
213 | /* Panel info for eDP and LVDS */ |
214 | struct intel_panel panel; | |
9cd300e0 JN |
215 | |
216 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
217 | struct edid *edid; | |
beb60608 | 218 | struct edid *detect_edid; |
821450c6 EE |
219 | |
220 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
221 | state of connector->polled in case hotplug storm detection changes it */ | |
222 | u8 polled; | |
0e32b39c DA |
223 | |
224 | void *port; /* store this opaque as its illegal to dereference it */ | |
225 | ||
226 | struct intel_dp *mst_port; | |
5daa55eb ZW |
227 | }; |
228 | ||
80ad9206 VS |
229 | typedef struct dpll { |
230 | /* given values */ | |
231 | int n; | |
232 | int m1, m2; | |
233 | int p1, p2; | |
234 | /* derived values */ | |
235 | int dot; | |
236 | int vco; | |
237 | int m; | |
238 | int p; | |
239 | } intel_clock_t; | |
240 | ||
eeca778a GP |
241 | struct intel_plane_state { |
242 | struct drm_crtc *crtc; | |
243 | struct drm_framebuffer *fb; | |
244 | struct drm_rect src; | |
245 | struct drm_rect dst; | |
246 | struct drm_rect clip; | |
247 | struct drm_rect orig_src; | |
248 | struct drm_rect orig_dst; | |
249 | bool visible; | |
250 | }; | |
251 | ||
46f297fb | 252 | struct intel_plane_config { |
46f297fb JB |
253 | bool tiled; |
254 | int size; | |
255 | u32 base; | |
256 | }; | |
257 | ||
b8cecdf5 | 258 | struct intel_crtc_config { |
bb760063 SV |
259 | /** |
260 | * quirks - bitfield with hw state readout quirks | |
261 | * | |
262 | * For various reasons the hw state readout code might not be able to | |
263 | * completely faithfully read out the current state. These cases are | |
264 | * tracked with quirk flags so that fastboot and state checker can act | |
265 | * accordingly. | |
266 | */ | |
9953599b SV |
267 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
268 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ | |
bb760063 SV |
269 | unsigned long quirks; |
270 | ||
5113bc9b VS |
271 | /* User requested mode, only valid as a starting point to |
272 | * compute adjusted_mode, except in the case of (S)DVO where | |
273 | * it's also for the output timings of the (S)DVO chip. | |
274 | * adjusted_mode will then correspond to the S(DVO) chip's | |
275 | * preferred input timings. */ | |
b8cecdf5 | 276 | struct drm_display_mode requested_mode; |
3c52f4eb | 277 | /* Actual pipe timings ie. what we program into the pipe timing |
241bfc38 | 278 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
b8cecdf5 | 279 | struct drm_display_mode adjusted_mode; |
37327abd VS |
280 | |
281 | /* Pipe source size (ie. panel fitter input size) | |
282 | * All planes will be positioned inside this space, | |
283 | * and get clipped at the edges. */ | |
284 | int pipe_src_w, pipe_src_h; | |
285 | ||
5bfe2ac0 SV |
286 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
287 | * between pch encoders and cpu encoders. */ | |
288 | bool has_pch_encoder; | |
50f3b016 | 289 | |
3b117c8f SV |
290 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
291 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
292 | enum transcoder cpu_transcoder; | |
293 | ||
50f3b016 SV |
294 | /* |
295 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
296 | * range fed into the crtcs. | |
297 | */ | |
298 | bool limited_color_range; | |
299 | ||
03afc4a2 SV |
300 | /* DP has a bunch of special case unfortunately, so mark the pipe |
301 | * accordingly. */ | |
302 | bool has_dp_encoder; | |
d8b32247 | 303 | |
6897b4b5 SV |
304 | /* Whether we should send NULL infoframes. Required for audio. */ |
305 | bool has_hdmi_sink; | |
306 | ||
9ed109a7 SV |
307 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
308 | * has_dp_encoder is set. */ | |
309 | bool has_audio; | |
310 | ||
d8b32247 SV |
311 | /* |
312 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
313 | * plane bpp. | |
314 | */ | |
965e0c48 | 315 | bool dither; |
f47709a9 SV |
316 | |
317 | /* Controls for the clock computation, to override various stages. */ | |
318 | bool clock_set; | |
319 | ||
09ede541 SV |
320 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
321 | * work correctly, we need to track this at runtime.*/ | |
322 | bool sdvo_tv_clock; | |
323 | ||
e29c22c0 SV |
324 | /* |
325 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
326 | * required. This is set in the 2nd loop of calling encoder's | |
327 | * ->compute_config if the first pick doesn't work out. | |
328 | */ | |
329 | bool bw_constrained; | |
330 | ||
f47709a9 SV |
331 | /* Settings for the intel dpll used on pretty much everything but |
332 | * haswell. */ | |
80ad9206 | 333 | struct dpll dpll; |
f47709a9 | 334 | |
a43f6e0f SV |
335 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
336 | enum intel_dpll_id shared_dpll; | |
337 | ||
de7cfc63 SV |
338 | /* PORT_CLK_SEL for DDI ports. */ |
339 | uint32_t ddi_pll_sel; | |
340 | ||
66e985c0 SV |
341 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
342 | struct intel_dpll_hw_state dpll_hw_state; | |
343 | ||
965e0c48 | 344 | int pipe_bpp; |
6cf86a5e | 345 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 346 | |
439d7ac0 PB |
347 | /* m2_n2 for eDP downclock */ |
348 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 349 | bool has_drrs; |
439d7ac0 | 350 | |
ff9a6750 SV |
351 | /* |
352 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
353 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
354 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 355 | */ |
ff9a6750 SV |
356 | int port_clock; |
357 | ||
6cc5f341 SV |
358 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
359 | unsigned pixel_multiplier; | |
2dd24552 JB |
360 | |
361 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
362 | struct { |
363 | u32 control; | |
364 | u32 pgm_ratios; | |
68fc8742 | 365 | u32 lvds_border_bits; |
b074cec8 JB |
366 | } gmch_pfit; |
367 | ||
368 | /* Panel fitter placement and size for Ironlake+ */ | |
369 | struct { | |
370 | u32 pos; | |
371 | u32 size; | |
fd4daa9c | 372 | bool enabled; |
fabf6e51 | 373 | bool force_thru; |
b074cec8 | 374 | } pch_pfit; |
33d29b14 | 375 | |
ca3a0ff8 | 376 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 377 | int fdi_lanes; |
ca3a0ff8 | 378 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
379 | |
380 | bool ips_enabled; | |
cf532bb2 VS |
381 | |
382 | bool double_wide; | |
0e32b39c DA |
383 | |
384 | bool dp_encoder_is_mst; | |
385 | int pbn; | |
b8cecdf5 SV |
386 | }; |
387 | ||
0b2ae6d7 VS |
388 | struct intel_pipe_wm { |
389 | struct intel_wm_level wm[5]; | |
390 | uint32_t linetime; | |
391 | bool fbc_wm_enabled; | |
2a44b76b VS |
392 | bool pipe_enabled; |
393 | bool sprites_enabled; | |
394 | bool sprites_scaled; | |
0b2ae6d7 VS |
395 | }; |
396 | ||
84c33a64 SG |
397 | struct intel_mmio_flip { |
398 | u32 seqno; | |
399 | u32 ring_id; | |
400 | }; | |
401 | ||
79e53945 JB |
402 | struct intel_crtc { |
403 | struct drm_crtc base; | |
80824003 JB |
404 | enum pipe pipe; |
405 | enum plane plane; | |
79e53945 | 406 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 SV |
407 | /* |
408 | * Whether the crtc and the connected output pipeline is active. Implies | |
409 | * that crtc->enabled is set, i.e. the current mode configuration has | |
410 | * some outputs connected to this crtc. | |
08a48469 SV |
411 | */ |
412 | bool active; | |
6efdf354 | 413 | unsigned long enabled_power_domains; |
4c445e0e | 414 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
652c393a | 415 | bool lowfreq_avail; |
02e792fb | 416 | struct intel_overlay *overlay; |
6b95a207 | 417 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 418 | |
b4a98e57 CW |
419 | atomic_t unpin_work_count; |
420 | ||
e506a0c6 SV |
421 | /* Display surface base address adjustement for pageflips. Note that on |
422 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
423 | * handled in the hw itself (with the TILEOFF register). */ | |
424 | unsigned long dspaddr_offset; | |
425 | ||
05394f39 | 426 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 | 427 | uint32_t cursor_addr; |
cda4b7d3 | 428 | int16_t cursor_width, cursor_height; |
4b0e333e | 429 | uint32_t cursor_cntl; |
dc41c154 | 430 | uint32_t cursor_size; |
4b0e333e | 431 | uint32_t cursor_base; |
4b645f14 | 432 | |
46f297fb | 433 | struct intel_plane_config plane_config; |
b8cecdf5 | 434 | struct intel_crtc_config config; |
50741abc | 435 | struct intel_crtc_config *new_config; |
7668851f | 436 | bool new_enabled; |
b8cecdf5 | 437 | |
10d83730 VS |
438 | /* reset counter value when the last flip was submitted */ |
439 | unsigned int reset_counter; | |
8664281b PZ |
440 | |
441 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
442 | bool cpu_fifo_underrun_disabled; | |
443 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
444 | |
445 | /* per-pipe watermark state */ | |
446 | struct { | |
447 | /* watermarks currently being used */ | |
448 | struct intel_pipe_wm active; | |
449 | } wm; | |
8d7849db | 450 | |
80715b2f | 451 | int scanline_offset; |
84c33a64 | 452 | struct intel_mmio_flip mmio_flip; |
79e53945 JB |
453 | }; |
454 | ||
c35426d2 VS |
455 | struct intel_plane_wm_parameters { |
456 | uint32_t horiz_pixels; | |
ed57cb8a | 457 | uint32_t vert_pixels; |
c35426d2 VS |
458 | uint8_t bytes_per_pixel; |
459 | bool enabled; | |
460 | bool scaled; | |
461 | }; | |
462 | ||
b840d907 JB |
463 | struct intel_plane { |
464 | struct drm_plane base; | |
7f1f3851 | 465 | int plane; |
b840d907 JB |
466 | enum pipe pipe; |
467 | struct drm_i915_gem_object *obj; | |
2d354c34 | 468 | bool can_scale; |
b840d907 | 469 | int max_downscale; |
5e1bac2f JB |
470 | int crtc_x, crtc_y; |
471 | unsigned int crtc_w, crtc_h; | |
472 | uint32_t src_x, src_y; | |
473 | uint32_t src_w, src_h; | |
76eebda7 | 474 | unsigned int rotation; |
526682e9 PZ |
475 | |
476 | /* Since we need to change the watermarks before/after | |
477 | * enabling/disabling the planes, we need to store the parameters here | |
478 | * as the other pieces of the struct may not reflect the values we want | |
479 | * for the watermark calculations. Currently only Haswell uses this. | |
480 | */ | |
c35426d2 | 481 | struct intel_plane_wm_parameters wm; |
526682e9 | 482 | |
b840d907 | 483 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 484 | struct drm_crtc *crtc, |
b840d907 JB |
485 | struct drm_framebuffer *fb, |
486 | struct drm_i915_gem_object *obj, | |
487 | int crtc_x, int crtc_y, | |
488 | unsigned int crtc_w, unsigned int crtc_h, | |
489 | uint32_t x, uint32_t y, | |
490 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
491 | void (*disable_plane)(struct drm_plane *plane, |
492 | struct drm_crtc *crtc); | |
8ea30864 JB |
493 | int (*update_colorkey)(struct drm_plane *plane, |
494 | struct drm_intel_sprite_colorkey *key); | |
495 | void (*get_colorkey)(struct drm_plane *plane, | |
496 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
497 | }; |
498 | ||
b445e3b0 ED |
499 | struct intel_watermark_params { |
500 | unsigned long fifo_size; | |
501 | unsigned long max_wm; | |
502 | unsigned long default_wm; | |
503 | unsigned long guard_size; | |
504 | unsigned long cacheline_size; | |
505 | }; | |
506 | ||
507 | struct cxsr_latency { | |
508 | int is_desktop; | |
509 | int is_ddr3; | |
510 | unsigned long fsb_freq; | |
511 | unsigned long mem_freq; | |
512 | unsigned long display_sr; | |
513 | unsigned long display_hpll_disable; | |
514 | unsigned long cursor_sr; | |
515 | unsigned long cursor_hpll_disable; | |
516 | }; | |
517 | ||
79e53945 | 518 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 519 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 520 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 521 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 522 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
155e6369 | 523 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 524 | |
f5bbfca3 | 525 | struct intel_hdmi { |
b242b7f7 | 526 | u32 hdmi_reg; |
f5bbfca3 | 527 | int ddc_bus; |
f5bbfca3 | 528 | uint32_t color_range; |
55bc60db | 529 | bool color_range_auto; |
f5bbfca3 ED |
530 | bool has_hdmi_sink; |
531 | bool has_audio; | |
532 | enum hdmi_force_audio force_audio; | |
abedc077 | 533 | bool rgb_quant_range_selectable; |
94a11ddc | 534 | enum hdmi_picture_aspect aspect_ratio; |
f5bbfca3 | 535 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 536 | enum hdmi_infoframe_type type, |
fff63867 | 537 | const void *frame, ssize_t len); |
687f4d06 | 538 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 539 | bool enable, |
687f4d06 | 540 | struct drm_display_mode *adjusted_mode); |
f5bbfca3 ED |
541 | }; |
542 | ||
0e32b39c | 543 | struct intel_dp_mst_encoder; |
b091cd92 | 544 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 545 | |
4f9db5b5 PB |
546 | /** |
547 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
548 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
549 | * parsing for same resolution. | |
550 | */ | |
551 | enum edp_drrs_refresh_rate_type { | |
552 | DRRS_HIGH_RR, | |
553 | DRRS_LOW_RR, | |
554 | DRRS_MAX_RR, /* RR count */ | |
555 | }; | |
556 | ||
54d63ca6 | 557 | struct intel_dp { |
54d63ca6 | 558 | uint32_t output_reg; |
9ed35ab1 | 559 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 560 | uint32_t DP; |
54d63ca6 SK |
561 | bool has_audio; |
562 | enum hdmi_force_audio force_audio; | |
563 | uint32_t color_range; | |
55bc60db | 564 | bool color_range_auto; |
54d63ca6 SK |
565 | uint8_t link_bw; |
566 | uint8_t lane_count; | |
567 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 568 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 569 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
9d1a1031 | 570 | struct drm_dp_aux aux; |
54d63ca6 SK |
571 | uint8_t train_set[4]; |
572 | int panel_power_up_delay; | |
573 | int panel_power_down_delay; | |
574 | int panel_power_cycle_delay; | |
575 | int backlight_on_delay; | |
576 | int backlight_off_delay; | |
54d63ca6 SK |
577 | struct delayed_work panel_vdd_work; |
578 | bool want_panel_vdd; | |
dce56b3c PZ |
579 | unsigned long last_power_cycle; |
580 | unsigned long last_power_on; | |
581 | unsigned long last_backlight_off; | |
5d42f82a | 582 | |
01527b31 CT |
583 | struct notifier_block edp_notifier; |
584 | ||
a4a5d2f8 VS |
585 | /* |
586 | * Pipe whose power sequencer is currently locked into | |
587 | * this port. Only relevant on VLV/CHV. | |
588 | */ | |
589 | enum pipe pps_pipe; | |
590 | ||
06ea66b6 | 591 | bool use_tps3; |
0e32b39c DA |
592 | bool can_mst; /* this port supports mst */ |
593 | bool is_mst; | |
594 | int active_mst_links; | |
595 | /* connector directly attached - won't be use for modeset in mst world */ | |
dd06f90e | 596 | struct intel_connector *attached_connector; |
ec5b01dd | 597 | |
0e32b39c DA |
598 | /* mst connector list */ |
599 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
600 | struct drm_dp_mst_topology_mgr mst_mgr; | |
601 | ||
ec5b01dd | 602 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
603 | /* |
604 | * This function returns the value we have to program the AUX_CTL | |
605 | * register with to kick off an AUX transaction. | |
606 | */ | |
607 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
608 | bool has_aux_irq, | |
609 | int send_bytes, | |
610 | uint32_t aux_clock_divider); | |
4f9db5b5 PB |
611 | struct { |
612 | enum drrs_support_type type; | |
613 | enum edp_drrs_refresh_rate_type refresh_rate_type; | |
439d7ac0 | 614 | struct mutex mutex; |
4f9db5b5 PB |
615 | } drrs_state; |
616 | ||
54d63ca6 SK |
617 | }; |
618 | ||
da63a9f2 PZ |
619 | struct intel_digital_port { |
620 | struct intel_encoder base; | |
174edf1f | 621 | enum port port; |
bcf53de4 | 622 | u32 saved_port_bits; |
da63a9f2 PZ |
623 | struct intel_dp dp; |
624 | struct intel_hdmi hdmi; | |
13cf5504 | 625 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
da63a9f2 PZ |
626 | }; |
627 | ||
0e32b39c DA |
628 | struct intel_dp_mst_encoder { |
629 | struct intel_encoder base; | |
630 | enum pipe pipe; | |
631 | struct intel_digital_port *primary; | |
632 | void *port; /* store this opaque as its illegal to dereference it */ | |
633 | }; | |
634 | ||
89b667f8 JB |
635 | static inline int |
636 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
637 | { | |
638 | switch (dport->port) { | |
639 | case PORT_B: | |
00fc31b7 | 640 | case PORT_D: |
e4607fcf | 641 | return DPIO_CH0; |
89b667f8 | 642 | case PORT_C: |
e4607fcf | 643 | return DPIO_CH1; |
89b667f8 JB |
644 | default: |
645 | BUG(); | |
646 | } | |
647 | } | |
648 | ||
eb69b0e5 CML |
649 | static inline int |
650 | vlv_pipe_to_channel(enum pipe pipe) | |
651 | { | |
652 | switch (pipe) { | |
653 | case PIPE_A: | |
654 | case PIPE_C: | |
655 | return DPIO_CH0; | |
656 | case PIPE_B: | |
657 | return DPIO_CH1; | |
658 | default: | |
659 | BUG(); | |
660 | } | |
661 | } | |
662 | ||
f875c15a CW |
663 | static inline struct drm_crtc * |
664 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
665 | { | |
666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
667 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
668 | } | |
669 | ||
417ae147 CW |
670 | static inline struct drm_crtc * |
671 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
672 | { | |
673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
674 | return dev_priv->plane_to_crtc_mapping[plane]; | |
675 | } | |
676 | ||
4e5359cd SF |
677 | struct intel_unpin_work { |
678 | struct work_struct work; | |
b4a98e57 | 679 | struct drm_crtc *crtc; |
05394f39 CW |
680 | struct drm_i915_gem_object *old_fb_obj; |
681 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 682 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
683 | atomic_t pending; |
684 | #define INTEL_FLIP_INACTIVE 0 | |
685 | #define INTEL_FLIP_PENDING 1 | |
686 | #define INTEL_FLIP_COMPLETE 2 | |
75f7f3ec VS |
687 | u32 flip_count; |
688 | u32 gtt_offset; | |
d6bbafa1 CW |
689 | struct intel_engine_cs *flip_queued_ring; |
690 | u32 flip_queued_seqno; | |
691 | int flip_queued_vblank; | |
692 | int flip_ready_vblank; | |
4e5359cd SF |
693 | bool enable_stall_check; |
694 | }; | |
695 | ||
d9e55608 | 696 | struct intel_set_config { |
1aa4b628 SV |
697 | struct drm_encoder **save_connector_encoders; |
698 | struct drm_crtc **save_encoder_crtcs; | |
7668851f | 699 | bool *save_crtc_enabled; |
5e2b584e SV |
700 | |
701 | bool fb_changed; | |
702 | bool mode_changed; | |
d9e55608 SV |
703 | }; |
704 | ||
5f1aae65 PZ |
705 | struct intel_load_detect_pipe { |
706 | struct drm_framebuffer *release_fb; | |
707 | bool load_detect_temp; | |
708 | int dpms_mode; | |
709 | }; | |
79e53945 | 710 | |
5f1aae65 PZ |
711 | static inline struct intel_encoder * |
712 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
713 | { |
714 | return to_intel_connector(connector)->encoder; | |
715 | } | |
716 | ||
da63a9f2 PZ |
717 | static inline struct intel_digital_port * |
718 | enc_to_dig_port(struct drm_encoder *encoder) | |
719 | { | |
720 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
721 | } |
722 | ||
0e32b39c DA |
723 | static inline struct intel_dp_mst_encoder * |
724 | enc_to_mst(struct drm_encoder *encoder) | |
725 | { | |
726 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
727 | } | |
728 | ||
9ff8c9ba ID |
729 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
730 | { | |
731 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
732 | } |
733 | ||
734 | static inline struct intel_digital_port * | |
735 | dp_to_dig_port(struct intel_dp *intel_dp) | |
736 | { | |
737 | return container_of(intel_dp, struct intel_digital_port, dp); | |
738 | } | |
739 | ||
740 | static inline struct intel_digital_port * | |
741 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
742 | { | |
743 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
744 | } |
745 | ||
5f1aae65 PZ |
746 | |
747 | /* i915_irq.c */ | |
87440425 PZ |
748 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
749 | enum pipe pipe, bool enable); | |
750 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
751 | enum transcoder pch_transcoder, | |
752 | bool enable); | |
480c8033 SV |
753 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
754 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
755 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
756 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
757 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
758 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
730488b2 PZ |
759 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev); |
760 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev); | |
9df7575f JB |
761 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
762 | { | |
763 | /* | |
764 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
765 | * this is the only thing we need to check. | |
766 | */ | |
767 | return !dev_priv->pm._irqs_disabled; | |
768 | } | |
769 | ||
a225f079 | 770 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
56b80e1f | 771 | void i9xx_check_fifo_underruns(struct drm_device *dev); |
d49bdb0e | 772 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
5f1aae65 | 773 | |
5f1aae65 | 774 | /* intel_crt.c */ |
87440425 | 775 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
776 | |
777 | ||
778 | /* intel_ddi.c */ | |
87440425 PZ |
779 | void intel_prepare_ddi(struct drm_device *dev); |
780 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
781 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
782 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
783 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
784 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); | |
785 | void intel_ddi_pll_init(struct drm_device *dev); | |
786 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
787 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
788 | enum transcoder cpu_transcoder); | |
789 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
790 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
566b734a | 791 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
87440425 PZ |
792 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
793 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
794 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
795 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
796 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
797 | struct intel_crtc_config *pipe_config); | |
5f1aae65 | 798 | |
44905a27 | 799 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
0e32b39c DA |
800 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
801 | struct intel_crtc_config *pipe_config); | |
802 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); | |
5f1aae65 PZ |
803 | |
804 | /* intel_display.c */ | |
ba0fbca4 | 805 | const char *intel_output_name(int output); |
5dce5b93 | 806 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
5f1aae65 | 807 | int intel_pch_rawclk(struct drm_device *dev); |
87440425 | 808 | void intel_mark_busy(struct drm_device *dev); |
f99d7069 SV |
809 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
810 | struct intel_engine_cs *ring); | |
811 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
812 | unsigned frontbuffer_bits); | |
813 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
814 | unsigned frontbuffer_bits); | |
815 | void intel_frontbuffer_flush(struct drm_device *dev, | |
816 | unsigned frontbuffer_bits); | |
817 | /** | |
818 | * intel_frontbuffer_flip - prepare frontbuffer flip | |
819 | * @dev: DRM device | |
820 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
821 | * | |
822 | * This function gets called after scheduling a flip on @obj. This is for | |
823 | * synchronous plane updates which will happen on the next vblank and which will | |
824 | * not get delayed by pending gpu rendering. | |
825 | * | |
826 | * Can be called without any locks held. | |
827 | */ | |
828 | static inline | |
829 | void intel_frontbuffer_flip(struct drm_device *dev, | |
830 | unsigned frontbuffer_bits) | |
831 | { | |
832 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
833 | } | |
834 | ||
835 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); | |
87440425 PZ |
836 | void intel_mark_idle(struct drm_device *dev); |
837 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
b04c5bd6 | 838 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
87440425 PZ |
839 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
840 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
841 | void intel_connector_dpms(struct drm_connector *, int mode); | |
842 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
843 | void intel_modeset_check_state(struct drm_device *dev); | |
b0ea7d37 DL |
844 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
845 | struct intel_digital_port *port); | |
87440425 PZ |
846 | void intel_connector_attach_encoder(struct intel_connector *connector, |
847 | struct intel_encoder *encoder); | |
848 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
849 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
850 | struct drm_crtc *crtc); | |
752aa88a | 851 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
852 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
853 | struct drm_file *file_priv); | |
87440425 PZ |
854 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
855 | enum pipe pipe); | |
856 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); | |
87440425 | 857 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf CML |
858 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
859 | struct intel_digital_port *dport); | |
87440425 PZ |
860 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
861 | struct drm_display_mode *mode, | |
51fd371b RC |
862 | struct intel_load_detect_pipe *old, |
863 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 864 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 865 | struct intel_load_detect_pipe *old); |
87440425 PZ |
866 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
867 | struct drm_i915_gem_object *obj, | |
a4872ba6 | 868 | struct intel_engine_cs *pipelined); |
87440425 | 869 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
a8bb6818 SV |
870 | struct drm_framebuffer * |
871 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
872 | struct drm_mode_fb_cmd2 *mode_cmd, |
873 | struct drm_i915_gem_object *obj); | |
87440425 PZ |
874 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
875 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
876 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
d6bbafa1 | 877 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
716c2e55 SV |
878 | |
879 | /* shared dpll functions */ | |
5f1aae65 | 880 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a SV |
881 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
882 | struct intel_shared_dpll *pll, | |
883 | bool state); | |
884 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
885 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
716c2e55 SV |
886 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
887 | void intel_put_shared_dpll(struct intel_crtc *crtc); | |
888 | ||
889 | /* modesetting asserts */ | |
55607e8a SV |
890 | void assert_pll(struct drm_i915_private *dev_priv, |
891 | enum pipe pipe, bool state); | |
892 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
893 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
894 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
895 | enum pipe pipe, bool state); | |
896 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
897 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 898 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
899 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
900 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
87440425 PZ |
901 | void intel_write_eld(struct drm_encoder *encoder, |
902 | struct drm_display_mode *mode); | |
903 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, | |
904 | unsigned int tiling_mode, | |
905 | unsigned int bpp, | |
906 | unsigned int pitch); | |
907 | void intel_display_handle_reset(struct drm_device *dev); | |
a14cb6fc PZ |
908 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
909 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
87440425 PZ |
910 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
911 | struct intel_crtc_config *pipe_config); | |
f769cd24 | 912 | void intel_dp_set_m_n(struct intel_crtc *crtc); |
87440425 PZ |
913 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
914 | void | |
5f1aae65 PZ |
915 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
916 | int dotclock); | |
87440425 | 917 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
918 | void hsw_enable_ips(struct intel_crtc *crtc); |
919 | void hsw_disable_ips(struct intel_crtc *crtc); | |
da7e29bd | 920 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
319be8ae ID |
921 | enum intel_display_power_domain |
922 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
f6a83288 SV |
923 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
924 | struct intel_crtc_config *pipe_config); | |
46f297fb | 925 | int intel_format_to_fourcc(int format); |
46a55d30 | 926 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
e2fcdaa9 | 927 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
8ea30864 | 928 | |
5f1aae65 | 929 | /* intel_dp.c */ |
87440425 PZ |
930 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
931 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
932 | struct intel_connector *intel_connector); | |
87440425 PZ |
933 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
934 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
935 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
936 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
937 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
938 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
d2e216d0 | 939 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 PZ |
940 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
941 | struct intel_crtc_config *pipe_config); | |
5d8a7752 | 942 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
13cf5504 DA |
943 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
944 | bool long_hpd); | |
4be73780 SV |
945 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
946 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 947 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
aba86890 | 948 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder); |
4be73780 SV |
949 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
950 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
87440425 PZ |
951 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
952 | void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
439d7ac0 | 953 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
9ca15301 SV |
954 | void intel_edp_psr_invalidate(struct drm_device *dev, |
955 | unsigned frontbuffer_bits); | |
956 | void intel_edp_psr_flush(struct drm_device *dev, | |
957 | unsigned frontbuffer_bits); | |
7c8f8a70 RV |
958 | void intel_edp_psr_init(struct drm_device *dev); |
959 | ||
0e32b39c DA |
960 | int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd); |
961 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); | |
962 | void intel_dp_mst_suspend(struct drm_device *dev); | |
963 | void intel_dp_mst_resume(struct drm_device *dev); | |
964 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); | |
965 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); | |
773538e8 | 966 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0e32b39c DA |
967 | /* intel_dp_mst.c */ |
968 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
969 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 970 | /* intel_dsi.c */ |
4328633d | 971 | void intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
972 | |
973 | ||
974 | /* intel_dvo.c */ | |
87440425 | 975 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
976 | |
977 | ||
0632fef6 | 978 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a SV |
979 | #ifdef CONFIG_DRM_I915_FBDEV |
980 | extern int intel_fbdev_init(struct drm_device *dev); | |
d1d70677 | 981 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
4520f53a | 982 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 983 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 SV |
984 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
985 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a SV |
986 | #else |
987 | static inline int intel_fbdev_init(struct drm_device *dev) | |
988 | { | |
989 | return 0; | |
990 | } | |
5f1aae65 | 991 | |
d1d70677 | 992 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
4520f53a SV |
993 | { |
994 | } | |
995 | ||
996 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
997 | { | |
998 | } | |
999 | ||
82e3b8c1 | 1000 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a SV |
1001 | { |
1002 | } | |
1003 | ||
0632fef6 | 1004 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a SV |
1005 | { |
1006 | } | |
1007 | #endif | |
5f1aae65 PZ |
1008 | |
1009 | /* intel_hdmi.c */ | |
87440425 PZ |
1010 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
1011 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
1012 | struct intel_connector *intel_connector); | |
1013 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1014 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
1015 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
1016 | |
1017 | ||
1018 | /* intel_lvds.c */ | |
87440425 PZ |
1019 | void intel_lvds_init(struct drm_device *dev); |
1020 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
1021 | |
1022 | ||
1023 | /* intel_modes.c */ | |
1024 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1025 | struct edid *edid); |
5f1aae65 | 1026 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1027 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1028 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
1029 | |
1030 | ||
1031 | /* intel_overlay.c */ | |
87440425 PZ |
1032 | void intel_setup_overlay(struct drm_device *dev); |
1033 | void intel_cleanup_overlay(struct drm_device *dev); | |
1034 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
1035 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
1036 | struct drm_file *file_priv); | |
1037 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
1038 | struct drm_file *file_priv); | |
5f1aae65 PZ |
1039 | |
1040 | ||
1041 | /* intel_panel.c */ | |
87440425 | 1042 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1043 | struct drm_display_mode *fixed_mode, |
1044 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1045 | void intel_panel_fini(struct intel_panel *panel); |
1046 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1047 | struct drm_display_mode *adjusted_mode); | |
1048 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
1049 | struct intel_crtc_config *pipe_config, | |
1050 | int fitting_mode); | |
1051 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
1052 | struct intel_crtc_config *pipe_config, | |
1053 | int fitting_mode); | |
6dda730e JN |
1054 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1055 | u32 level, u32 max); | |
87440425 | 1056 | int intel_panel_setup_backlight(struct drm_connector *connector); |
752aa88a JB |
1057 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1058 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1059 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
7bd688cd | 1060 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
87440425 | 1061 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
1062 | extern struct drm_display_mode *intel_find_panel_downclock( |
1063 | struct drm_device *dev, | |
1064 | struct drm_display_mode *fixed_mode, | |
1065 | struct drm_connector *connector); | |
5f1aae65 PZ |
1066 | |
1067 | /* intel_pm.c */ | |
87440425 PZ |
1068 | void intel_init_clock_gating(struct drm_device *dev); |
1069 | void intel_suspend_hw(struct drm_device *dev); | |
546c81fd | 1070 | int ilk_wm_max_level(const struct drm_device *dev); |
87440425 PZ |
1071 | void intel_update_watermarks(struct drm_crtc *crtc); |
1072 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
1073 | struct drm_crtc *crtc, | |
ed57cb8a DL |
1074 | uint32_t sprite_width, |
1075 | uint32_t sprite_height, | |
1076 | int pixel_size, | |
87440425 PZ |
1077 | bool enabled, bool scaled); |
1078 | void intel_init_pm(struct drm_device *dev); | |
f742a552 | 1079 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
1080 | bool intel_fbc_enabled(struct drm_device *dev); |
1081 | void intel_update_fbc(struct drm_device *dev); | |
1082 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
1083 | void intel_gpu_ips_teardown(void); | |
da7e29bd ID |
1084 | int intel_power_domains_init(struct drm_i915_private *); |
1085 | void intel_power_domains_remove(struct drm_i915_private *); | |
1086 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, | |
87440425 | 1087 | enum intel_display_power_domain domain); |
bfafe93a ID |
1088 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
1089 | enum intel_display_power_domain domain); | |
da7e29bd | 1090 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
87440425 | 1091 | enum intel_display_power_domain domain); |
da7e29bd | 1092 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
87440425 | 1093 | enum intel_display_power_domain domain); |
da7e29bd | 1094 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
ae48434c ID |
1095 | void intel_init_gt_powersave(struct drm_device *dev); |
1096 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
87440425 PZ |
1097 | void intel_enable_gt_powersave(struct drm_device *dev); |
1098 | void intel_disable_gt_powersave(struct drm_device *dev); | |
156c7ca0 | 1099 | void intel_suspend_gt_powersave(struct drm_device *dev); |
c6df39b5 | 1100 | void intel_reset_gt_powersave(struct drm_device *dev); |
87440425 | 1101 | void ironlake_teardown_rc6(struct drm_device *dev); |
c67a470b | 1102 | void gen6_update_ring_freq(struct drm_device *dev); |
076e29f2 SV |
1103 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1104 | void gen6_rps_boost(struct drm_i915_private *dev_priv); | |
87440425 PZ |
1105 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
1106 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
8a187455 | 1107 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
c6df39b5 | 1108 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
8a187455 PZ |
1109 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
1110 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); | |
1111 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); | |
243e6a44 | 1112 | void ilk_wm_get_hw_state(struct drm_device *dev); |
d2011dc8 | 1113 | |
72662e10 | 1114 | |
5f1aae65 | 1115 | /* intel_sdvo.c */ |
87440425 | 1116 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 1117 | |
2b28bb1b | 1118 | |
5f1aae65 | 1119 | /* intel_sprite.c */ |
87440425 | 1120 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
1dba99f4 | 1121 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
87440425 | 1122 | enum plane plane); |
48404c1e SJ |
1123 | int intel_plane_set_property(struct drm_plane *plane, |
1124 | struct drm_property *prop, | |
1125 | uint64_t val); | |
e57465f3 | 1126 | int intel_plane_restore(struct drm_plane *plane); |
87440425 PZ |
1127 | void intel_plane_disable(struct drm_plane *plane); |
1128 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
1129 | struct drm_file *file_priv); | |
1130 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
1131 | struct drm_file *file_priv); | |
5f1aae65 PZ |
1132 | |
1133 | ||
1134 | /* intel_tv.c */ | |
87440425 | 1135 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 1136 | |
79e53945 | 1137 | #endif /* __INTEL_DRV_H__ */ |