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drm/i915: hw readout support for ->has_pch_encoders
[people/ms/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
1d5bfac9
DV		 36/**
37 * _wait_for - magic (register) wait macro
38 *
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
43 */
481b6af3 44#define _wait_for(COND, MS, W) ({ \
1d5bfac9 45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 46 int ret__ = 0; \
0206e353 47 while (!(COND)) { \
913d8d11 48 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV		 49 if (!(COND)) \
50 ret__ = -ETIMEDOUT; \
913d8d11
CW		 51 break; \
52 } \
0cc2764c
BW		 53 if (W && drm_can_sleep()) { \
54 msleep(W); \
55 } else { \
56 cpu_relax(); \
57 } \
913d8d11
CW		 58 } \
59 ret__; \
60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV		 64#define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
481b6af3 66
021357ac
CW		 67#define KHz(x) (1000*x)
68#define MHz(x) KHz(1000*x)
69
79e53945
JB		 70/*
71 * Display related stuff
72 */
73
74/* store information about an Ixxx DVO */
75/* The i830->i865 use multiple DVOs with multiple i2cs */
76/* the i915, i945 have a single sDVO i2c bus - which is different */
77#define MAX_OUTPUTS 6
78/* maximum connectors per crtcs in the mode set */
79#define INTELFB_CONN_LIMIT 4
80
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
7d57382e 92#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 93#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 94#define INTEL_OUTPUT_EDP 8
00c09d70 95#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 96
97#define INTEL_DVO_CHIP_NONE 0
98#define INTEL_DVO_CHIP_LVDS 1
99#define INTEL_DVO_CHIP_TMDS 2
100#define INTEL_DVO_CHIP_TVOUT 4
101
79e53945
JB		 102struct intel_framebuffer {
103 struct drm_framebuffer base;
05394f39 104 struct drm_i915_gem_object *obj;
79e53945
JB		 105};
106
37811fcc
CW		 107struct intel_fbdev {
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
112};
79e53945 113
21d40d37 114struct intel_encoder {
4ef69c7a 115 struct drm_encoder base;
9a935856
DV		 116 /*
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
119 */
120 struct intel_crtc *new_crtc;
121
79e53945 122 int type;
e2f0ba97 123 bool needs_tv_clock;
66a9278e
DV		 124 /*
125 * Intel hw has only one MUX where encoders could be clone, hence a
126 * simple flag is enough to compute the possible_clones mask.
127 */
128 bool cloneable;
5ab432ef 129 bool connectors_active;
21d40d37 130 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV		 131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
dafd226c 133 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 134 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 135 void (*enable)(struct intel_encoder *);
6cc5f341 136 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 137 void (*disable)(struct intel_encoder *);
bf49ec8c 138 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 143 int crtc_mask;
1d843f9d 144 enum hpd_pin hpd_pin;
79e53945
JB		 145};
146
1d508706 147struct intel_panel {
dd06f90e 148 struct drm_display_mode *fixed_mode;
4d891523 149 int fitting_mode;
1d508706
JN		 150};
151
5daa55eb
ZW		 152struct intel_connector {
153 struct drm_connector base;
9a935856
DV		 154 /*
155 * The fixed encoder this connector is connected to.
156 */
df0e9248 157 struct intel_encoder *encoder;
9a935856
DV		 158
159 /*
160 * The new encoder this connector will be driven. Only differs from
161 * encoder while a modeset is in progress.
162 */
163 struct intel_encoder *new_encoder;
164
f0947c37
DV		 165 /* Reads out the current hw, returning true if the connector is enabled
166 * and active (i.e. dpms ON state). */
167 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 168
169 /* Panel info for eDP and LVDS */
170 struct intel_panel panel;
9cd300e0
JN		 171
172 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
173 struct edid *edid;
5daa55eb
ZW		 174};
175
b8cecdf5
DV		 176struct intel_crtc_config {
177 struct drm_display_mode requested_mode;
178 struct drm_display_mode adjusted_mode;
7ae89233
DV		 179 /* This flag must be set by the encoder's compute_config callback if it
180 * changes the crtc timings in the mode to prevent the crtc fixup from
181 * overwriting them. Currently only lvds needs that. */
182 bool timings_set;
5bfe2ac0
DV		 183 /* Whether to set up the PCH/FDI. Note that we never allow sharing
184 * between pch encoders and cpu encoders. */
185 bool has_pch_encoder;
50f3b016
DV		 186
187 /*
188 * Use reduced/limited/broadcast rbg range, compressing from the full
189 * range fed into the crtcs.
190 */
191 bool limited_color_range;
192
03afc4a2
DV		 193 /* DP has a bunch of special case unfortunately, so mark the pipe
194 * accordingly. */
195 bool has_dp_encoder;
965e0c48
DV		 196 bool dither;
197 int pipe_bpp;
6cf86a5e 198 struct intel_link_m_n dp_m_n;
df92b1e6
DV		 199 /**
200 * This is currently used by DP and HDMI encoders since those can have a
201 * target pixel clock != the port link clock (which is currently stored
202 * in adjusted_mode->clock).
203 */
204 int pixel_target_clock;
6cc5f341
DV		 205 /* Used by SDVO (and if we ever fix it, HDMI). */
206 unsigned pixel_multiplier;
b8cecdf5
DV		 207};
208
79e53945
JB		 209struct intel_crtc {
210 struct drm_crtc base;
80824003
JB		 211 enum pipe pipe;
212 enum plane plane;
a5c961d1 213 enum transcoder cpu_transcoder;
79e53945 214 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 215 /*
216 * Whether the crtc and the connected output pipeline is active. Implies
217 * that crtc->enabled is set, i.e. the current mode configuration has
218 * some outputs connected to this crtc.
08a48469
DV		 219 */
220 bool active;
7b9f35a6 221 bool eld_vld;
93314b5b 222 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 223 bool lowfreq_avail;
02e792fb 224 struct intel_overlay *overlay;
6b95a207 225 struct intel_unpin_work *unpin_work;
77ffb597 226 int fdi_lanes;
cda4b7d3 227
b4a98e57
CW		 228 atomic_t unpin_work_count;
229
e506a0c6
DV		 230 /* Display surface base address adjustement for pageflips. Note that on
231 * gen4+ this only adjusts up to a tile, offsets within a tile are
232 * handled in the hw itself (with the TILEOFF register). */
233 unsigned long dspaddr_offset;
234
05394f39 235 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 236 uint32_t cursor_addr;
237 int16_t cursor_x, cursor_y;
238 int16_t cursor_width, cursor_height;
6b383a7f 239 bool cursor_visible;
4b645f14 240
b8cecdf5
DV		 241 struct intel_crtc_config config;
242
ee7b9f93
JB		 243 /* We can share PLLs across outputs if the timings match */
244 struct intel_pch_pll *pch_pll;
6441ab5f 245 uint32_t ddi_pll_sel;
10d83730
VS		 246
247 /* reset counter value when the last flip was submitted */
248 unsigned int reset_counter;
79e53945
JB		 249};
250
b840d907
JB		 251struct intel_plane {
252 struct drm_plane base;
7f1f3851 253 int plane;
b840d907
JB		 254 enum pipe pipe;
255 struct drm_i915_gem_object *obj;
2d354c34 256 bool can_scale;
b840d907
JB		 257 int max_downscale;
258 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB		 259 int crtc_x, crtc_y;
260 unsigned int crtc_w, crtc_h;
261 uint32_t src_x, src_y;
262 uint32_t src_w, src_h;
b840d907
JB		 263 void (*update_plane)(struct drm_plane *plane,
264 struct drm_framebuffer *fb,
265 struct drm_i915_gem_object *obj,
266 int crtc_x, int crtc_y,
267 unsigned int crtc_w, unsigned int crtc_h,
268 uint32_t x, uint32_t y,
269 uint32_t src_w, uint32_t src_h);
270 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 271 int (*update_colorkey)(struct drm_plane *plane,
272 struct drm_intel_sprite_colorkey *key);
273 void (*get_colorkey)(struct drm_plane *plane,
274 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 275};
276
b445e3b0
ED		 277struct intel_watermark_params {
278 unsigned long fifo_size;
279 unsigned long max_wm;
280 unsigned long default_wm;
281 unsigned long guard_size;
282 unsigned long cacheline_size;
283};
284
285struct cxsr_latency {
286 int is_desktop;
287 int is_ddr3;
288 unsigned long fsb_freq;
289 unsigned long mem_freq;
290 unsigned long display_sr;
291 unsigned long display_hpll_disable;
292 unsigned long cursor_sr;
293 unsigned long cursor_hpll_disable;
294};
295
79e53945 296#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 297#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 298#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 299#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 300#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 301
45187ace
JB		 302#define DIP_HEADER_SIZE 5
303
3c17fe4b
DH		 304#define DIP_TYPE_AVI 0x82
305#define DIP_VERSION_AVI 0x2
306#define DIP_LEN_AVI 13
c846b619
PZ		 307#define DIP_AVI_PR_1 0
308#define DIP_AVI_PR_2 1
abedc077
VS		 309#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
310#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
311#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 312
26005210 313#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 314#define DIP_VERSION_SPD 0x1
315#define DIP_LEN_SPD 25
316#define DIP_SPD_UNKNOWN 0
317#define DIP_SPD_DSTB 0x1
318#define DIP_SPD_DVDP 0x2
319#define DIP_SPD_DVHS 0x3
320#define DIP_SPD_HDDVR 0x4
321#define DIP_SPD_DVC 0x5
322#define DIP_SPD_DSC 0x6
323#define DIP_SPD_VCD 0x7
324#define DIP_SPD_GAME 0x8
325#define DIP_SPD_PC 0x9
326#define DIP_SPD_BD 0xa
327#define DIP_SPD_SCD 0xb
328
3c17fe4b
DH		 329struct dip_infoframe {
330 uint8_t type; /* HB0 */
331 uint8_t ver; /* HB1 */
332 uint8_t len; /* HB2 - body len, not including checksum */
333 uint8_t ecc; /* Header ECC */
334 uint8_t checksum; /* PB0 */
335 union {
336 struct {
337 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
338 uint8_t Y_A_B_S;
339 /* PB2 - C 7:6, M 5:4, R 3:0 */
340 uint8_t C_M_R;
341 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
342 uint8_t ITC_EC_Q_SC;
343 /* PB4 - VIC 6:0 */
344 uint8_t VIC;
0aa534df
PZ		 345 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
346 uint8_t YQ_CN_PR;
3c17fe4b
DH		 347 /* PB6 to PB13 */
348 uint16_t top_bar_end;
349 uint16_t bottom_bar_start;
350 uint16_t left_bar_end;
351 uint16_t right_bar_start;
81014b9d 352 } __attribute__ ((packed)) avi;
c0864cb3
JB		 353 struct {
354 uint8_t vn[8];
355 uint8_t pd[16];
356 uint8_t sdi;
81014b9d 357 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 358 uint8_t payload[27];
359 } __attribute__ ((packed)) body;
360} __attribute__((packed));
361
f5bbfca3 362struct intel_hdmi {
b242b7f7 363 u32 hdmi_reg;
f5bbfca3 364 int ddc_bus;
f5bbfca3 365 uint32_t color_range;
55bc60db 366 bool color_range_auto;
f5bbfca3
ED		 367 bool has_hdmi_sink;
368 bool has_audio;
369 enum hdmi_force_audio force_audio;
abedc077 370 bool rgb_quant_range_selectable;
f5bbfca3
ED		 371 void (*write_infoframe)(struct drm_encoder *encoder,
372 struct dip_infoframe *frame);
687f4d06
PZ		 373 void (*set_infoframes)(struct drm_encoder *encoder,
374 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 375};
376
b091cd92 377#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 378#define DP_LINK_CONFIGURATION_SIZE 9
379
380struct intel_dp {
54d63ca6 381 uint32_t output_reg;
9ed35ab1 382 uint32_t aux_ch_ctl_reg;
54d63ca6
SK		 383 uint32_t DP;
384 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
385 bool has_audio;
386 enum hdmi_force_audio force_audio;
387 uint32_t color_range;
55bc60db 388 bool color_range_auto;
54d63ca6
SK		 389 uint8_t link_bw;
390 uint8_t lane_count;
391 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 392 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 393 struct i2c_adapter adapter;
394 struct i2c_algo_dp_aux_data algo;
395 bool is_pch_edp;
396 uint8_t train_set[4];
397 int panel_power_up_delay;
398 int panel_power_down_delay;
399 int panel_power_cycle_delay;
400 int backlight_on_delay;
401 int backlight_off_delay;
54d63ca6
SK		 402 struct delayed_work panel_vdd_work;
403 bool want_panel_vdd;
dd06f90e 404 struct intel_connector *attached_connector;
54d63ca6
SK		 405};
406
da63a9f2
PZ		 407struct intel_digital_port {
408 struct intel_encoder base;
174edf1f 409 enum port port;
876a8cdf 410 u32 port_reversal;
da63a9f2
PZ		 411 struct intel_dp dp;
412 struct intel_hdmi hdmi;
413};
414
f875c15a
CW		 415static inline struct drm_crtc *
416intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
417{
418 struct drm_i915_private *dev_priv = dev->dev_private;
419 return dev_priv->pipe_to_crtc_mapping[pipe];
420}
421
417ae147
CW		 422static inline struct drm_crtc *
423intel_get_crtc_for_plane(struct drm_device *dev, int plane)
424{
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 return dev_priv->plane_to_crtc_mapping[plane];
427}
428
4e5359cd
SF		 429struct intel_unpin_work {
430 struct work_struct work;
b4a98e57 431 struct drm_crtc *crtc;
05394f39
CW		 432 struct drm_i915_gem_object *old_fb_obj;
433 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 434 struct drm_pending_vblank_event *event;
e7d841ca
CW		 435 atomic_t pending;
436#define INTEL_FLIP_INACTIVE 0
437#define INTEL_FLIP_PENDING 1
438#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 439 bool enable_stall_check;
440};
441
1630fe75
CW		 442struct intel_fbc_work {
443 struct delayed_work work;
444 struct drm_crtc *crtc;
445 struct drm_framebuffer *fb;
446 int interval;
447};
448
d2acd215
DV		 449int intel_pch_rawclk(struct drm_device *dev);
450
4eab8136
JN		 451int intel_connector_update_modes(struct drm_connector *connector,
452 struct edid *edid);
335af9a2 453int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 454
3f43c48d 455extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 456extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
457
79e53945 458extern void intel_crt_init(struct drm_device *dev);
08d644ad 459extern void intel_hdmi_init(struct drm_device *dev,
b242b7f7 460 int hdmi_reg, enum port port);
00c09d70
PZ		 461extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
462 struct intel_connector *intel_connector);
f5bbfca3 463extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
5bfe2ac0
DV		 464extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
465 struct intel_crtc_config *pipe_config);
f5bbfca3 466extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 467extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
468 bool is_sdvob);
79e53945
JB		 469extern void intel_dvo_init(struct drm_device *dev);
470extern void intel_tv_init(struct drm_device *dev);
f047e395 471extern void intel_mark_busy(struct drm_device *dev);
f047e395 472extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 473extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 474extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 475extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 476extern void intel_dp_init(struct drm_device *dev, int output_reg,
477 enum port port);
00c09d70
PZ		 478extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
479 struct intel_connector *intel_connector);
247d89f6 480extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 481extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
482extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
483extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 484extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
485extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
5bfe2ac0
DV		 486extern bool intel_dp_compute_config(struct intel_encoder *encoder,
487 struct intel_crtc_config *pipe_config);
cb0953d7 488extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 489extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
490extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 491extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
492extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
493extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
494extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
814948ad 495extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
7f1f3851 496extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
6f1d69b0
ED		 497extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
498 enum plane plane);
32f9d658 499
a9573556 500/* intel_panel.c */
dd06f90e
JN		 501extern int intel_panel_init(struct intel_panel *panel,
502 struct drm_display_mode *fixed_mode);
1d508706
JN		 503extern void intel_panel_fini(struct intel_panel *panel);
504
1d8e1c75
CW		 505extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
506 struct drm_display_mode *adjusted_mode);
507extern void intel_pch_panel_fitting(struct drm_device *dev,
508 int fitting_mode,
cb1793ce 509 const struct drm_display_mode *mode,
1d8e1c75 510 struct drm_display_mode *adjusted_mode);
a9573556 511extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 512extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 513extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 514extern void intel_panel_enable_backlight(struct drm_device *dev,
515 enum pipe pipe);
47356eb6 516extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 517extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 518extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 519
d9e55608 520struct intel_set_config {
1aa4b628
DV		 521 struct drm_encoder **save_connector_encoders;
522 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 523
524 bool fb_changed;
525 bool mode_changed;
d9e55608
DV		 526};
527
c0c36b94
CW		 528extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
529 int x, int y, struct drm_framebuffer *old_fb);
a261b246 530extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 531extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 532extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 533extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
ea5b213a 534extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 535extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 536extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 537extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 538extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c 539extern void intel_modeset_check_state(struct drm_device *dev);
5e1bac2f 540extern void intel_plane_restore(struct drm_plane *plane);
b980514c 541
79e53945 542
df0e9248
CW		 543static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
544{
545 return to_intel_connector(connector)->encoder;
546}
547
7739c33b
PZ		 548static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
549{
da63a9f2
PZ		 550 struct intel_digital_port *intel_dig_port =
551 container_of(encoder, struct intel_digital_port, base.base);
552 return &intel_dig_port->dp;
553}
554
555static inline struct intel_digital_port *
556enc_to_dig_port(struct drm_encoder *encoder)
557{
558 return container_of(encoder, struct intel_digital_port, base.base);
559}
560
561static inline struct intel_digital_port *
562dp_to_dig_port(struct intel_dp *intel_dp)
563{
564 return container_of(intel_dp, struct intel_digital_port, dp);
565}
566
567static inline struct intel_digital_port *
568hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
569{
570 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 571}
572
b0ea7d37
DL		 573bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
574 struct intel_digital_port *port);
575
df0e9248
CW		 576extern void intel_connector_attach_encoder(struct intel_connector *connector,
577 struct intel_encoder *encoder);
578extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 579
580extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
581 struct drm_crtc *crtc);
08d7b3d1
CW		 582int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
583 struct drm_file *file_priv);
a5c961d1
PZ		 584extern enum transcoder
585intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
586 enum pipe pipe);
9d0498a2 587extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 588extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 589extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
8261b191
CW		 590
591struct intel_load_detect_pipe {
d2dff872 592 struct drm_framebuffer *release_fb;
8261b191
CW		 593 bool load_detect_temp;
594 int dpms_mode;
595};
d2434ab7 596extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 597 struct drm_display_mode *mode,
8261b191 598 struct intel_load_detect_pipe *old);
d2434ab7 599extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 600 struct intel_load_detect_pipe *old);
79e53945 601
79e53945
JB		 602extern void intelfb_restore(void);
603extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
604 u16 blue, int regno);
b8c00ac5
DA		 605extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
606 u16 *blue, int regno);
0cdab21f 607extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 608
127bd2ac 609extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 610 struct drm_i915_gem_object *obj,
919926ae 611 struct intel_ring_buffer *pipelined);
1690e1eb 612extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 613
38651674
DA		 614extern int intel_framebuffer_init(struct drm_device *dev,
615 struct intel_framebuffer *ifb,
308e5bcb 616 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 617 struct drm_i915_gem_object *obj);
38651674 618extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 619extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 620extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 621extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 622extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
623extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 624extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 625
02e792fb
DV		 626extern void intel_setup_overlay(struct drm_device *dev);
627extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 628extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 629extern int intel_overlay_put_image(struct drm_device *dev, void *data,
630 struct drm_file *file_priv);
631extern int intel_overlay_attrs(struct drm_device *dev, void *data,
632 struct drm_file *file_priv);
4abe3520 633
eb1f8e4f 634extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 635extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 636
b840d907
JB		 637extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
638 bool state);
639#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
640#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
641
645c62a5 642extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 643extern void intel_write_eld(struct drm_encoder *encoder,
644 struct drm_display_mode *mode);
d4270e57 645extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
6cf86a5e
DV		 646extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
647 struct intel_link_m_n *m_n);
648extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
649 struct intel_link_m_n *m_n);
45244b87 650extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 651extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 652extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 653
b840d907 654/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 655extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 656extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
657 uint32_t sprite_width,
658 int pixel_size);
1f8eeabf
ED		 659extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
660 struct drm_display_mode *mode);
8ea30864 661
bc752862
CW		 662extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
663 unsigned int tiling_mode,
664 unsigned int bpp,
665 unsigned int pitch);
5a35e99e 666
8ea30864
JB		 667extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671
57f350b6
JB		 672extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
673
85208be0 674/* Power-related functions, located in intel_pm.c */
1fa61106 675extern void intel_init_pm(struct drm_device *dev);
85208be0 676/* FBC */
85208be0
ED		 677extern bool intel_fbc_enabled(struct drm_device *dev);
678extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
679extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 680/* IPS */
681extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
682extern void intel_gpu_ips_teardown(void);
85208be0 683
fa42e23c 684extern void intel_init_power_well(struct drm_device *dev);
cb10799c 685extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 686extern void intel_enable_gt_powersave(struct drm_device *dev);
687extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 688extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 689extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 690
85234cdc
DV		 691extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
692 enum pipe *pipe);
b8fc2f6a 693extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 694extern void intel_ddi_pll_init(struct drm_device *dev);
8228c251 695extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
ad80a810
PZ		 696extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
697 enum transcoder cpu_transcoder);
fc914639
PZ		 698extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
699extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 700extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
701extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 702extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 703extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 704extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 705extern bool
706intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
707extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 708
96a02917
VS		 709extern void intel_display_handle_reset(struct drm_device *dev);
710
79e53945 711#endif /* __INTEL_DRV_H__ */
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