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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
e6017571 | 31 | #include <linux/sched/clock.h> |
16e4dd03 | 32 | #include <linux/stackdepot.h> |
760285e7 | 33 | #include <drm/i915_drm.h> |
80824003 | 34 | #include "i915_drv.h" |
760285e7 | 35 | #include <drm/drm_crtc.h> |
9338203c | 36 | #include <drm/drm_encoder.h> |
760285e7 | 37 | #include <drm/drm_fb_helper.h> |
b1ba124d | 38 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 39 | #include <drm/drm_dp_mst_helper.h> |
fcd70cd3 | 40 | #include <drm/drm_probe_helper.h> |
eeca778a | 41 | #include <drm/drm_rect.h> |
fcd70cd3 | 42 | #include <drm/drm_vblank.h> |
10f81c19 | 43 | #include <drm/drm_atomic.h> |
9055aac7 | 44 | #include <drm/i915_mei_hdcp_interface.h> |
9c229127 | 45 | #include <media/cec-notifier.h> |
913d8d11 | 46 | |
bd780f37 CW |
47 | struct drm_printer; |
48 | ||
1d5bfac9 | 49 | /** |
23fdbdd7 | 50 | * __wait_for - magic wait macro |
1d5bfac9 | 51 | * |
23fdbdd7 SP |
52 | * Macro to help avoid open coding check/wait/timeout patterns. Note that it's |
53 | * important that we check the condition again after having timed out, since the | |
54 | * timeout could be due to preemption or similar and we've never had a chance to | |
55 | * check the condition before the timeout. | |
1d5bfac9 | 56 | */ |
23fdbdd7 | 57 | #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ |
3085982c | 58 | const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ |
a54b1873 | 59 | long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ |
b0876afd | 60 | int ret__; \ |
290b20a6 | 61 | might_sleep(); \ |
b0876afd | 62 | for (;;) { \ |
3085982c | 63 | const bool expired__ = ktime_after(ktime_get_raw(), end__); \ |
23fdbdd7 | 64 | OP; \ |
1c3c1dc6 MK |
65 | /* Guarantee COND check prior to timeout */ \ |
66 | barrier(); \ | |
b0876afd DG |
67 | if (COND) { \ |
68 | ret__ = 0; \ | |
69 | break; \ | |
70 | } \ | |
71 | if (expired__) { \ | |
72 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
73 | break; \ |
74 | } \ | |
a54b1873 CW |
75 | usleep_range(wait__, wait__ * 2); \ |
76 | if (wait__ < (Wmax)) \ | |
77 | wait__ <<= 1; \ | |
913d8d11 CW |
78 | } \ |
79 | ret__; \ | |
80 | }) | |
81 | ||
23fdbdd7 SP |
82 | #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ |
83 | (Wmax)) | |
84 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) | |
3f177625 | 85 | |
0351b939 TU |
86 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
87 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
18f4b843 | 88 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic()) |
0351b939 | 89 | #else |
18f4b843 | 90 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0) |
0351b939 TU |
91 | #endif |
92 | ||
18f4b843 TU |
93 | #define _wait_for_atomic(COND, US, ATOMIC) \ |
94 | ({ \ | |
95 | int cpu, ret, timeout = (US) * 1000; \ | |
96 | u64 base; \ | |
97 | _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \ | |
18f4b843 TU |
98 | if (!(ATOMIC)) { \ |
99 | preempt_disable(); \ | |
100 | cpu = smp_processor_id(); \ | |
101 | } \ | |
102 | base = local_clock(); \ | |
103 | for (;;) { \ | |
104 | u64 now = local_clock(); \ | |
105 | if (!(ATOMIC)) \ | |
106 | preempt_enable(); \ | |
1c3c1dc6 MK |
107 | /* Guarantee COND check prior to timeout */ \ |
108 | barrier(); \ | |
18f4b843 TU |
109 | if (COND) { \ |
110 | ret = 0; \ | |
111 | break; \ | |
112 | } \ | |
113 | if (now - base >= timeout) { \ | |
114 | ret = -ETIMEDOUT; \ | |
0351b939 TU |
115 | break; \ |
116 | } \ | |
117 | cpu_relax(); \ | |
18f4b843 TU |
118 | if (!(ATOMIC)) { \ |
119 | preempt_disable(); \ | |
120 | if (unlikely(cpu != smp_processor_id())) { \ | |
121 | timeout -= now - base; \ | |
122 | cpu = smp_processor_id(); \ | |
123 | base = local_clock(); \ | |
124 | } \ | |
125 | } \ | |
0351b939 | 126 | } \ |
18f4b843 TU |
127 | ret; \ |
128 | }) | |
129 | ||
130 | #define wait_for_us(COND, US) \ | |
131 | ({ \ | |
132 | int ret__; \ | |
133 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
134 | if ((US) > 10) \ | |
a54b1873 | 135 | ret__ = _wait_for((COND), (US), 10, 10); \ |
18f4b843 TU |
136 | else \ |
137 | ret__ = _wait_for_atomic((COND), (US), 0); \ | |
0351b939 TU |
138 | ret__; \ |
139 | }) | |
140 | ||
939cf46c TU |
141 | #define wait_for_atomic_us(COND, US) \ |
142 | ({ \ | |
143 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
144 | BUILD_BUG_ON((US) > 50000); \ | |
145 | _wait_for_atomic((COND), (US), 1); \ | |
146 | }) | |
147 | ||
148 | #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000) | |
481b6af3 | 149 | |
49938ac4 JN |
150 | #define KHz(x) (1000 * (x)) |
151 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 152 | |
aa9664ff MK |
153 | #define KBps(x) (1000 * (x)) |
154 | #define MBps(x) KBps(1000 * (x)) | |
155 | #define GBps(x) ((u64)1000 * MBps((x))) | |
156 | ||
79e53945 JB |
157 | /* |
158 | * Display related stuff | |
159 | */ | |
160 | ||
161 | /* store information about an Ixxx DVO */ | |
162 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
163 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
164 | #define MAX_OUTPUTS 6 | |
165 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
166 | |
167 | #define INTEL_I2C_BUS_DVO 1 | |
168 | #define INTEL_I2C_BUS_SDVO 2 | |
169 | ||
170 | /* these are outputs from the chip - integrated only | |
171 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
172 | enum intel_output_type { |
173 | INTEL_OUTPUT_UNUSED = 0, | |
174 | INTEL_OUTPUT_ANALOG = 1, | |
175 | INTEL_OUTPUT_DVO = 2, | |
176 | INTEL_OUTPUT_SDVO = 3, | |
177 | INTEL_OUTPUT_LVDS = 4, | |
178 | INTEL_OUTPUT_TVOUT = 5, | |
179 | INTEL_OUTPUT_HDMI = 6, | |
cca0502b | 180 | INTEL_OUTPUT_DP = 7, |
6847d71b PZ |
181 | INTEL_OUTPUT_EDP = 8, |
182 | INTEL_OUTPUT_DSI = 9, | |
7e732cac | 183 | INTEL_OUTPUT_DDI = 10, |
6847d71b PZ |
184 | INTEL_OUTPUT_DP_MST = 11, |
185 | }; | |
79e53945 JB |
186 | |
187 | #define INTEL_DVO_CHIP_NONE 0 | |
188 | #define INTEL_DVO_CHIP_LVDS 1 | |
189 | #define INTEL_DVO_CHIP_TMDS 2 | |
190 | #define INTEL_DVO_CHIP_TVOUT 4 | |
191 | ||
dfba2e2d SK |
192 | #define INTEL_DSI_VIDEO_MODE 0 |
193 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 194 | |
79e53945 JB |
195 | struct intel_framebuffer { |
196 | struct drm_framebuffer base; | |
2d7a215f | 197 | struct intel_rotation_info rot_info; |
6687c906 VS |
198 | |
199 | /* for each plane in the normal GTT view */ | |
200 | struct { | |
201 | unsigned int x, y; | |
202 | } normal[2]; | |
203 | /* for each plane in the rotated GTT view */ | |
204 | struct { | |
205 | unsigned int x, y; | |
206 | unsigned int pitch; /* pixels */ | |
207 | } rotated[2]; | |
79e53945 JB |
208 | }; |
209 | ||
37811fcc CW |
210 | struct intel_fbdev { |
211 | struct drm_fb_helper helper; | |
8bcd4553 | 212 | struct intel_framebuffer *fb; |
058d88c4 | 213 | struct i915_vma *vma; |
5935485f | 214 | unsigned long vma_flags; |
43cee314 | 215 | async_cookie_t cookie; |
d978ef14 | 216 | int preferred_bpp; |
fe5ec656 LP |
217 | |
218 | /* Whether or not fbdev hpd processing is temporarily suspended */ | |
219 | bool hpd_suspended : 1; | |
220 | /* Set when a hotplug was received while HPD processing was | |
221 | * suspended | |
222 | */ | |
223 | bool hpd_waiting : 1; | |
224 | ||
225 | /* Protects hpd_suspended */ | |
226 | struct mutex hpd_lock; | |
37811fcc | 227 | }; |
79e53945 | 228 | |
21d40d37 | 229 | struct intel_encoder { |
4ef69c7a | 230 | struct drm_encoder base; |
9a935856 | 231 | |
6847d71b | 232 | enum intel_output_type type; |
03cdc1d4 | 233 | enum port port; |
bc079e8b | 234 | unsigned int cloneable; |
dba14b27 VS |
235 | bool (*hotplug)(struct intel_encoder *encoder, |
236 | struct intel_connector *connector); | |
7e732cac VS |
237 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
238 | struct intel_crtc_state *, | |
239 | struct drm_connector_state *); | |
204474a6 LP |
240 | int (*compute_config)(struct intel_encoder *, |
241 | struct intel_crtc_state *, | |
242 | struct drm_connector_state *); | |
fd6bbda9 | 243 | void (*pre_pll_enable)(struct intel_encoder *, |
5f88a9c6 VS |
244 | const struct intel_crtc_state *, |
245 | const struct drm_connector_state *); | |
fd6bbda9 | 246 | void (*pre_enable)(struct intel_encoder *, |
5f88a9c6 VS |
247 | const struct intel_crtc_state *, |
248 | const struct drm_connector_state *); | |
fd6bbda9 | 249 | void (*enable)(struct intel_encoder *, |
5f88a9c6 VS |
250 | const struct intel_crtc_state *, |
251 | const struct drm_connector_state *); | |
fd6bbda9 | 252 | void (*disable)(struct intel_encoder *, |
5f88a9c6 VS |
253 | const struct intel_crtc_state *, |
254 | const struct drm_connector_state *); | |
fd6bbda9 | 255 | void (*post_disable)(struct intel_encoder *, |
5f88a9c6 VS |
256 | const struct intel_crtc_state *, |
257 | const struct drm_connector_state *); | |
fd6bbda9 | 258 | void (*post_pll_disable)(struct intel_encoder *, |
5f88a9c6 VS |
259 | const struct intel_crtc_state *, |
260 | const struct drm_connector_state *); | |
608ed4ab HG |
261 | void (*update_pipe)(struct intel_encoder *, |
262 | const struct intel_crtc_state *, | |
263 | const struct drm_connector_state *); | |
f0947c37 SV |
264 | /* Read out the current hw state of this connector, returning true if |
265 | * the encoder is active. If the encoder is enabled it also set the pipe | |
266 | * it is connected to in the pipe parameter. */ | |
267 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 268 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 269 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
270 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
271 | * be set correctly before calling this function. */ | |
045ac3b5 | 272 | void (*get_config)(struct intel_encoder *, |
5cec258b | 273 | struct intel_crtc_state *pipe_config); |
62b69566 ACO |
274 | /* Returns a mask of power domains that need to be referenced as part |
275 | * of the hardware state readout code. */ | |
52528055 ID |
276 | u64 (*get_power_domains)(struct intel_encoder *encoder, |
277 | struct intel_crtc_state *crtc_state); | |
07f9cd0b ID |
278 | /* |
279 | * Called during system suspend after all pending requests for the | |
280 | * encoder are flushed (for example for DP AUX transactions) and | |
281 | * device interrupts are disabled. | |
282 | */ | |
283 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 284 | int crtc_mask; |
1d843f9d | 285 | enum hpd_pin hpd_pin; |
79f255a0 | 286 | enum intel_display_power_domain power_domain; |
f1a3acea PD |
287 | /* for communication with audio component; protected by av_mutex */ |
288 | const struct drm_connector *audio_connector; | |
79e53945 JB |
289 | }; |
290 | ||
1d508706 | 291 | struct intel_panel { |
dd06f90e | 292 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 293 | struct drm_display_mode *downclock_mode; |
58c68779 JN |
294 | |
295 | /* backlight */ | |
296 | struct { | |
c91c9f32 | 297 | bool present; |
58c68779 | 298 | u32 level; |
6dda730e | 299 | u32 min; |
7bd688cd | 300 | u32 max; |
58c68779 | 301 | bool enabled; |
636baebf JN |
302 | bool combination_mode; /* gen 2/4 only */ |
303 | bool active_low_pwm; | |
32b421e7 | 304 | bool alternate_pwm_increment; /* lpt+ */ |
b029e66f SK |
305 | |
306 | /* PWM chip */ | |
022e4e52 SK |
307 | bool util_pin_active_low; /* bxt+ */ |
308 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
309 | struct pwm_device *pwm; |
310 | ||
58c68779 | 311 | struct backlight_device *device; |
ab656bb9 | 312 | |
5507faeb JN |
313 | /* Connector and platform specific backlight functions */ |
314 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
d25236a3 JN |
315 | u32 (*get)(struct intel_connector *connector); |
316 | void (*set)(const struct drm_connector_state *conn_state, u32 level); | |
7d025e08 ML |
317 | void (*disable)(const struct drm_connector_state *conn_state); |
318 | void (*enable)(const struct intel_crtc_state *crtc_state, | |
319 | const struct drm_connector_state *conn_state); | |
d25236a3 | 320 | u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); |
5507faeb JN |
321 | void (*power)(struct intel_connector *, bool enable); |
322 | } backlight; | |
1d508706 JN |
323 | }; |
324 | ||
b6ca3eee VS |
325 | struct intel_digital_port; |
326 | ||
22ce2d94 R |
327 | enum check_link_response { |
328 | HDCP_LINK_PROTECTED = 0, | |
329 | HDCP_TOPOLOGY_CHANGE, | |
330 | HDCP_LINK_INTEGRITY_FAILURE, | |
331 | HDCP_REAUTH_REQUEST | |
332 | }; | |
333 | ||
ee5e5e7a SP |
334 | /* |
335 | * This structure serves as a translation layer between the generic HDCP code | |
336 | * and the bus-specific code. What that means is that HDCP over HDMI differs | |
337 | * from HDCP over DP, so to account for these differences, we need to | |
338 | * communicate with the receiver through this shim. | |
339 | * | |
340 | * For completeness, the 2 buses differ in the following ways: | |
341 | * - DP AUX vs. DDC | |
342 | * HDCP registers on the receiver are set via DP AUX for DP, and | |
343 | * they are set via DDC for HDMI. | |
344 | * - Receiver register offsets | |
345 | * The offsets of the registers are different for DP vs. HDMI | |
346 | * - Receiver register masks/offsets | |
347 | * For instance, the ready bit for the KSV fifo is in a different | |
348 | * place on DP vs HDMI | |
349 | * - Receiver register names | |
350 | * Seriously. In the DP spec, the 16-bit register containing | |
351 | * downstream information is called BINFO, on HDMI it's called | |
352 | * BSTATUS. To confuse matters further, DP has a BSTATUS register | |
353 | * with a completely different definition. | |
354 | * - KSV FIFO | |
355 | * On HDMI, the ksv fifo is read all at once, whereas on DP it must | |
356 | * be read 3 keys at a time | |
357 | * - Aksv output | |
358 | * Since Aksv is hidden in hardware, there's different procedures | |
359 | * to send it over DP AUX vs DDC | |
360 | */ | |
361 | struct intel_hdcp_shim { | |
362 | /* Outputs the transmitter's An and Aksv values to the receiver. */ | |
363 | int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); | |
364 | ||
365 | /* Reads the receiver's key selection vector */ | |
366 | int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); | |
367 | ||
368 | /* | |
369 | * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The | |
370 | * definitions are the same in the respective specs, but the names are | |
371 | * different. Call it BSTATUS since that's the name the HDMI spec | |
372 | * uses and it was there first. | |
373 | */ | |
374 | int (*read_bstatus)(struct intel_digital_port *intel_dig_port, | |
375 | u8 *bstatus); | |
376 | ||
377 | /* Determines whether a repeater is present downstream */ | |
378 | int (*repeater_present)(struct intel_digital_port *intel_dig_port, | |
379 | bool *repeater_present); | |
380 | ||
381 | /* Reads the receiver's Ri' value */ | |
382 | int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); | |
383 | ||
384 | /* Determines if the receiver's KSV FIFO is ready for consumption */ | |
385 | int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, | |
386 | bool *ksv_ready); | |
387 | ||
388 | /* Reads the ksv fifo for num_downstream devices */ | |
389 | int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, | |
390 | int num_downstream, u8 *ksv_fifo); | |
391 | ||
392 | /* Reads a 32-bit part of V' from the receiver */ | |
393 | int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, | |
394 | int i, u32 *part); | |
395 | ||
396 | /* Enables HDCP signalling on the port */ | |
397 | int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, | |
398 | bool enable); | |
399 | ||
400 | /* Ensures the link is still protected */ | |
401 | bool (*check_link)(struct intel_digital_port *intel_dig_port); | |
791a98dd R |
402 | |
403 | /* Detects panel's hdcp capability. This is optional for HDMI. */ | |
404 | int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, | |
405 | bool *hdcp_capable); | |
9055aac7 R |
406 | |
407 | /* HDCP adaptation(DP/HDMI) required on the port */ | |
408 | enum hdcp_wired_protocol protocol; | |
49a630b0 R |
409 | |
410 | /* Detects whether sink is HDCP2.2 capable */ | |
411 | int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, | |
412 | bool *capable); | |
bd90d7c7 R |
413 | |
414 | /* Write HDCP2.2 messages */ | |
415 | int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, | |
416 | void *buf, size_t size); | |
417 | ||
418 | /* Read HDCP2.2 messages */ | |
419 | int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, | |
420 | u8 msg_id, void *buf, size_t size); | |
421 | ||
422 | /* | |
423 | * Implementation of DP HDCP2.2 Errata for the communication of stream | |
424 | * type to Receivers. In DP HDCP2.2 Stream type is one of the input to | |
425 | * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. | |
426 | */ | |
427 | int (*config_stream_type)(struct intel_digital_port *intel_dig_port, | |
428 | bool is_repeater, u8 type); | |
22ce2d94 R |
429 | |
430 | /* HDCP2.2 Link Integrity Check */ | |
431 | int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); | |
ee5e5e7a SP |
432 | }; |
433 | ||
d3dacc70 R |
434 | struct intel_hdcp { |
435 | const struct intel_hdcp_shim *shim; | |
436 | /* Mutex for hdcp state of the connector */ | |
437 | struct mutex mutex; | |
438 | u64 value; | |
439 | struct delayed_work check_work; | |
440 | struct work_struct prop_work; | |
04707f97 | 441 | |
09d56393 R |
442 | /* HDCP1.4 Encryption status */ |
443 | bool hdcp_encrypted; | |
444 | ||
04707f97 R |
445 | /* HDCP2.2 related definitions */ |
446 | /* Flag indicates whether this connector supports HDCP2.2 or not. */ | |
447 | bool hdcp2_supported; | |
448 | ||
49a630b0 R |
449 | /* HDCP2.2 Encryption status */ |
450 | bool hdcp2_encrypted; | |
451 | ||
04707f97 R |
452 | /* |
453 | * Content Stream Type defined by content owner. TYPE0(0x0) content can | |
454 | * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) | |
455 | * content can flow only through a link protected by HDCP2.2. | |
456 | */ | |
457 | u8 content_type; | |
9055aac7 | 458 | struct hdcp_port_data port_data; |
bd90d7c7 R |
459 | |
460 | bool is_paired; | |
461 | bool is_repeater; | |
462 | ||
463 | /* | |
464 | * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. | |
465 | * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. | |
466 | * When it rolls over re-auth has to be triggered. | |
467 | */ | |
468 | u32 seq_num_v; | |
469 | ||
470 | /* | |
471 | * Count of RepeaterAuth_Stream_Manage msg propagated. | |
472 | * Initialized to 0 on AKE_INIT. Incremented after every successful | |
473 | * transmission of RepeaterAuth_Stream_Manage message. When it rolls | |
474 | * over re-Auth has to be triggered. | |
475 | */ | |
476 | u32 seq_num_m; | |
cf9cb35f R |
477 | |
478 | /* | |
479 | * Work queue to signal the CP_IRQ. Used for the waiters to read the | |
480 | * available information from HDCP DP sink. | |
481 | */ | |
482 | wait_queue_head_t cp_irq_queue; | |
483 | atomic_t cp_irq_count; | |
484 | int cp_irq_count_cached; | |
d3dacc70 R |
485 | }; |
486 | ||
5daa55eb ZW |
487 | struct intel_connector { |
488 | struct drm_connector base; | |
9a935856 SV |
489 | /* |
490 | * The fixed encoder this connector is connected to. | |
491 | */ | |
df0e9248 | 492 | struct intel_encoder *encoder; |
9a935856 | 493 | |
8e1b56a4 JN |
494 | /* ACPI device id for ACPI and driver cooperation */ |
495 | u32 acpi_device_id; | |
496 | ||
f0947c37 SV |
497 | /* Reads out the current hw, returning true if the connector is enabled |
498 | * and active (i.e. dpms ON state). */ | |
499 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
500 | |
501 | /* Panel info for eDP and LVDS */ | |
502 | struct intel_panel panel; | |
9cd300e0 JN |
503 | |
504 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
505 | struct edid *edid; | |
beb60608 | 506 | struct edid *detect_edid; |
821450c6 EE |
507 | |
508 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
509 | state of connector->polled in case hotplug storm detection changes it */ | |
510 | u8 polled; | |
0e32b39c DA |
511 | |
512 | void *port; /* store this opaque as its illegal to dereference it */ | |
513 | ||
514 | struct intel_dp *mst_port; | |
9301397a MN |
515 | |
516 | /* Work struct to schedule a uevent on link train failure */ | |
517 | struct work_struct modeset_retry_work; | |
ee5e5e7a | 518 | |
d3dacc70 | 519 | struct intel_hdcp hdcp; |
5daa55eb ZW |
520 | }; |
521 | ||
11c1a9ec ML |
522 | struct intel_digital_connector_state { |
523 | struct drm_connector_state base; | |
524 | ||
525 | enum hdmi_force_audio force_audio; | |
526 | int broadcast_rgb; | |
527 | }; | |
528 | ||
529 | #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) | |
530 | ||
9e2c8475 | 531 | struct dpll { |
80ad9206 VS |
532 | /* given values */ |
533 | int n; | |
534 | int m1, m2; | |
535 | int p1, p2; | |
536 | /* derived values */ | |
537 | int dot; | |
538 | int vco; | |
539 | int m; | |
540 | int p; | |
9e2c8475 | 541 | }; |
80ad9206 | 542 | |
de419ab6 ML |
543 | struct intel_atomic_state { |
544 | struct drm_atomic_state base; | |
545 | ||
bb0f4aab VS |
546 | struct { |
547 | /* | |
548 | * Logical state of cdclk (used for all scaling, watermark, | |
549 | * etc. calculations and checks). This is computed as if all | |
550 | * enabled crtcs were active. | |
551 | */ | |
552 | struct intel_cdclk_state logical; | |
553 | ||
554 | /* | |
555 | * Actual state of cdclk, can be different from the logical | |
556 | * state only when all crtc's are DPMS off. | |
557 | */ | |
558 | struct intel_cdclk_state actual; | |
905801fe VS |
559 | |
560 | int force_min_cdclk; | |
561 | bool force_min_cdclk_changed; | |
59f9e9ca VS |
562 | /* pipe to which cd2x update is synchronized */ |
563 | enum pipe pipe; | |
bb0f4aab | 564 | } cdclk; |
1a617b77 | 565 | |
565602d7 ML |
566 | bool dpll_set, modeset; |
567 | ||
8b4a7d05 MR |
568 | /* |
569 | * Does this transaction change the pipes that are active? This mask | |
570 | * tracks which CRTC's have changed their active state at the end of | |
571 | * the transaction (not counting the temporary disable during modesets). | |
572 | * This mask should only be non-zero when intel_state->modeset is true, | |
573 | * but the converse is not necessarily true; simply changing a mode may | |
574 | * not flip the final active status of any CRTC's | |
575 | */ | |
576 | unsigned int active_pipe_changes; | |
577 | ||
565602d7 | 578 | unsigned int active_crtcs; |
d305e061 VS |
579 | /* minimum acceptable cdclk for each pipe */ |
580 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
581 | /* minimum acceptable voltage level for each pipe */ |
582 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 583 | |
2c42e535 | 584 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
ed4a6a7c MR |
585 | |
586 | /* | |
587 | * Current watermarks can't be trusted during hardware readout, so | |
588 | * don't bother calculating intermediate watermarks. | |
589 | */ | |
590 | bool skip_intermediate_wm; | |
98d39494 | 591 | |
60548c55 CW |
592 | bool rps_interactive; |
593 | ||
98d39494 | 594 | /* Gen9+ only */ |
60f8e873 | 595 | struct skl_ddb_values wm_results; |
c004a90b CW |
596 | |
597 | struct i915_sw_fence commit_ready; | |
eb955eee CW |
598 | |
599 | struct llist_node freed; | |
de419ab6 ML |
600 | }; |
601 | ||
eeca778a | 602 | struct intel_plane_state { |
2b875c22 | 603 | struct drm_plane_state base; |
f5929c53 | 604 | struct i915_ggtt_view view; |
be1e3415 | 605 | struct i915_vma *vma; |
5935485f CW |
606 | unsigned long flags; |
607 | #define PLANE_HAS_FENCE BIT(0) | |
32b7eeec | 608 | |
b63a16f6 VS |
609 | struct { |
610 | u32 offset; | |
df79cf44 VS |
611 | /* |
612 | * Plane stride in: | |
613 | * bytes for 0/180 degree rotation | |
614 | * pixels for 90/270 degree rotation | |
615 | */ | |
616 | u32 stride; | |
b63a16f6 | 617 | int x, y; |
c11ada07 | 618 | } color_plane[2]; |
b63a16f6 | 619 | |
a0864d59 VS |
620 | /* plane control register */ |
621 | u32 ctl; | |
622 | ||
4036c78c JA |
623 | /* plane color control register */ |
624 | u32 color_ctl; | |
625 | ||
be41e336 CK |
626 | /* |
627 | * scaler_id | |
628 | * = -1 : not using a scaler | |
629 | * >= 0 : using a scalers | |
630 | * | |
631 | * plane requiring a scaler: | |
632 | * - During check_plane, its bit is set in | |
633 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 634 | * update_scaler_plane. |
be41e336 CK |
635 | * - scaler_id indicates the scaler it got assigned. |
636 | * | |
637 | * plane doesn't require a scaler: | |
638 | * - this can happen when scaling is no more required or plane simply | |
639 | * got disabled. | |
640 | * - During check_plane, corresponding bit is reset in | |
641 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 642 | * update_scaler_plane. |
be41e336 CK |
643 | */ |
644 | int scaler_id; | |
818ed961 | 645 | |
1ab554b0 ML |
646 | /* |
647 | * linked_plane: | |
648 | * | |
649 | * ICL planar formats require 2 planes that are updated as pairs. | |
650 | * This member is used to make sure the other plane is also updated | |
651 | * when required, and for update_slave() to find the correct | |
652 | * plane_state to pass as argument. | |
653 | */ | |
654 | struct intel_plane *linked_plane; | |
655 | ||
656 | /* | |
657 | * slave: | |
658 | * If set don't update use the linked plane's state for updating | |
659 | * this plane during atomic commit with the update_slave() callback. | |
660 | * | |
661 | * It's also used by the watermark code to ignore wm calculations on | |
662 | * this plane. They're calculated by the linked plane's wm code. | |
663 | */ | |
664 | u32 slave; | |
665 | ||
818ed961 | 666 | struct drm_intel_sprite_colorkey ckey; |
eeca778a GP |
667 | }; |
668 | ||
5724dbd1 | 669 | struct intel_initial_plane_config { |
2d14030b | 670 | struct intel_framebuffer *fb; |
49af449b | 671 | unsigned int tiling; |
46f297fb JB |
672 | int size; |
673 | u32 base; | |
f43348a3 | 674 | u8 rotation; |
46f297fb JB |
675 | }; |
676 | ||
be41e336 CK |
677 | #define SKL_MIN_SRC_W 8 |
678 | #define SKL_MAX_SRC_W 4096 | |
679 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 680 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
681 | #define SKL_MIN_DST_W 8 |
682 | #define SKL_MAX_DST_W 4096 | |
683 | #define SKL_MIN_DST_H 8 | |
6156a456 | 684 | #define SKL_MAX_DST_H 4096 |
323301af NM |
685 | #define ICL_MAX_SRC_W 5120 |
686 | #define ICL_MAX_SRC_H 4096 | |
687 | #define ICL_MAX_DST_W 5120 | |
688 | #define ICL_MAX_DST_H 4096 | |
77224cd5 CK |
689 | #define SKL_MIN_YUV_420_SRC_W 16 |
690 | #define SKL_MIN_YUV_420_SRC_H 16 | |
be41e336 CK |
691 | |
692 | struct intel_scaler { | |
be41e336 | 693 | int in_use; |
d25236a3 | 694 | u32 mode; |
be41e336 CK |
695 | }; |
696 | ||
697 | struct intel_crtc_scaler_state { | |
698 | #define SKL_NUM_SCALERS 2 | |
699 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
700 | ||
701 | /* | |
702 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
703 | * | |
704 | * If a bit is set, a user is using a scaler. | |
705 | * Here user can be a plane or crtc as defined below: | |
706 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
707 | * bit 31 - crtc | |
708 | * | |
709 | * Instead of creating a new index to cover planes and crtc, using | |
710 | * existing drm_plane_index for planes which is well less than 31 | |
711 | * planes and bit 31 for crtc. This should be fine to cover all | |
712 | * our platforms. | |
713 | * | |
714 | * intel_atomic_setup_scalers will setup available scalers to users | |
715 | * requesting scalers. It will gracefully fail if request exceeds | |
716 | * avilability. | |
717 | */ | |
718 | #define SKL_CRTC_INDEX 31 | |
719 | unsigned scaler_users; | |
720 | ||
721 | /* scaler used by crtc for panel fitting purpose */ | |
722 | int scaler_id; | |
723 | }; | |
724 | ||
1ed51de9 | 725 | /* drm_mode->private_flags */ |
8a920e24 | 726 | #define I915_MODE_FLAG_INHERITED (1<<0) |
aec0246f US |
727 | /* Flag to get scanline using frame time stamps */ |
728 | #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) | |
8a920e24 VS |
729 | /* Flag to use the scanline counter instead of the pixel counter */ |
730 | #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) | |
1ed51de9 | 731 | |
4e0963c7 MR |
732 | struct intel_pipe_wm { |
733 | struct intel_wm_level wm[5]; | |
d25236a3 | 734 | u32 linetime; |
4e0963c7 MR |
735 | bool fbc_wm_enabled; |
736 | bool pipe_enabled; | |
737 | bool sprites_enabled; | |
738 | bool sprites_scaled; | |
739 | }; | |
740 | ||
a62163e9 | 741 | struct skl_plane_wm { |
4e0963c7 | 742 | struct skl_wm_level wm[8]; |
942aa2d0 | 743 | struct skl_wm_level uv_wm[8]; |
4e0963c7 | 744 | struct skl_wm_level trans_wm; |
b879d58f | 745 | bool is_planar; |
a62163e9 L |
746 | }; |
747 | ||
748 | struct skl_pipe_wm { | |
749 | struct skl_plane_wm planes[I915_MAX_PLANES]; | |
d25236a3 | 750 | u32 linetime; |
4e0963c7 MR |
751 | }; |
752 | ||
855c79f5 VS |
753 | enum vlv_wm_level { |
754 | VLV_WM_LEVEL_PM2, | |
755 | VLV_WM_LEVEL_PM5, | |
756 | VLV_WM_LEVEL_DDR_DVFS, | |
757 | NUM_VLV_WM_LEVELS, | |
758 | }; | |
759 | ||
760 | struct vlv_wm_state { | |
114d7dc0 VS |
761 | struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; |
762 | struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; | |
d25236a3 | 763 | u8 num_levels; |
855c79f5 VS |
764 | bool cxsr; |
765 | }; | |
766 | ||
814e7f0b VS |
767 | struct vlv_fifo_state { |
768 | u16 plane[I915_MAX_PLANES]; | |
769 | }; | |
770 | ||
04548cba VS |
771 | enum g4x_wm_level { |
772 | G4X_WM_LEVEL_NORMAL, | |
773 | G4X_WM_LEVEL_SR, | |
774 | G4X_WM_LEVEL_HPLL, | |
775 | NUM_G4X_WM_LEVELS, | |
776 | }; | |
777 | ||
778 | struct g4x_wm_state { | |
779 | struct g4x_pipe_wm wm; | |
780 | struct g4x_sr_wm sr; | |
781 | struct g4x_sr_wm hpll; | |
782 | bool cxsr; | |
783 | bool hpll_en; | |
784 | bool fbc_en; | |
785 | }; | |
786 | ||
e8f1f02e MR |
787 | struct intel_crtc_wm_state { |
788 | union { | |
789 | struct { | |
790 | /* | |
791 | * Intermediate watermarks; these can be | |
792 | * programmed immediately since they satisfy | |
793 | * both the current configuration we're | |
794 | * switching away from and the new | |
795 | * configuration we're switching to. | |
796 | */ | |
797 | struct intel_pipe_wm intermediate; | |
798 | ||
799 | /* | |
800 | * Optimal watermarks, programmed post-vblank | |
801 | * when this state is committed. | |
802 | */ | |
803 | struct intel_pipe_wm optimal; | |
804 | } ilk; | |
805 | ||
806 | struct { | |
807 | /* gen9+ only needs 1-step wm programming */ | |
808 | struct skl_pipe_wm optimal; | |
ce0ba283 | 809 | struct skl_ddb_entry ddb; |
ff43bc37 VS |
810 | struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; |
811 | struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; | |
e8f1f02e | 812 | } skl; |
855c79f5 VS |
813 | |
814 | struct { | |
5012e604 | 815 | /* "raw" watermarks (not inverted) */ |
114d7dc0 | 816 | struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; |
4841da51 VS |
817 | /* intermediate watermarks (inverted) */ |
818 | struct vlv_wm_state intermediate; | |
855c79f5 VS |
819 | /* optimal watermarks (inverted) */ |
820 | struct vlv_wm_state optimal; | |
814e7f0b VS |
821 | /* display FIFO split */ |
822 | struct vlv_fifo_state fifo_state; | |
855c79f5 | 823 | } vlv; |
04548cba VS |
824 | |
825 | struct { | |
826 | /* "raw" watermarks */ | |
827 | struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; | |
828 | /* intermediate watermarks */ | |
829 | struct g4x_wm_state intermediate; | |
830 | /* optimal watermarks */ | |
831 | struct g4x_wm_state optimal; | |
832 | } g4x; | |
e8f1f02e MR |
833 | }; |
834 | ||
835 | /* | |
836 | * Platforms with two-step watermark programming will need to | |
837 | * update watermark programming post-vblank to switch from the | |
838 | * safe intermediate watermarks to the optimal final | |
839 | * watermarks. | |
840 | */ | |
841 | bool need_postvbl_update; | |
842 | }; | |
843 | ||
d9facae6 SS |
844 | enum intel_output_format { |
845 | INTEL_OUTPUT_FORMAT_INVALID, | |
846 | INTEL_OUTPUT_FORMAT_RGB, | |
33b7f3ee | 847 | INTEL_OUTPUT_FORMAT_YCBCR420, |
8c79f844 | 848 | INTEL_OUTPUT_FORMAT_YCBCR444, |
d9facae6 SS |
849 | }; |
850 | ||
5cec258b | 851 | struct intel_crtc_state { |
2d112de7 ACO |
852 | struct drm_crtc_state base; |
853 | ||
bb760063 SV |
854 | /** |
855 | * quirks - bitfield with hw state readout quirks | |
856 | * | |
857 | * For various reasons the hw state readout code might not be able to | |
858 | * completely faithfully read out the current state. These cases are | |
859 | * tracked with quirk flags so that fastboot and state checker can act | |
860 | * accordingly. | |
861 | */ | |
9953599b | 862 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 SV |
863 | unsigned long quirks; |
864 | ||
cd202f69 | 865 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
866 | bool update_pipe; /* can a fast modeset be performed? */ |
867 | bool disable_cxsr; | |
caed361d | 868 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 869 | bool fb_changed; /* fb on any of the planes is changed */ |
236c48e6 | 870 | bool fifo_changed; /* FIFO split is changed */ |
bfd16b2a | 871 | |
37327abd VS |
872 | /* Pipe source size (ie. panel fitter input size) |
873 | * All planes will be positioned inside this space, | |
874 | * and get clipped at the edges. */ | |
875 | int pipe_src_w, pipe_src_h; | |
876 | ||
a7d1b3f4 VS |
877 | /* |
878 | * Pipe pixel rate, adjusted for | |
879 | * panel fitter/pipe scaler downscaling. | |
880 | */ | |
881 | unsigned int pixel_rate; | |
882 | ||
5bfe2ac0 SV |
883 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
884 | * between pch encoders and cpu encoders. */ | |
885 | bool has_pch_encoder; | |
50f3b016 | 886 | |
e43823ec JB |
887 | /* Are we sending infoframes on the attached port */ |
888 | bool has_infoframe; | |
889 | ||
3b117c8f | 890 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
891 | * pipe on Haswell and later (where we have a special eDP transcoder) |
892 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f SV |
893 | enum transcoder cpu_transcoder; |
894 | ||
50f3b016 SV |
895 | /* |
896 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
897 | * range fed into the crtcs. | |
898 | */ | |
899 | bool limited_color_range; | |
900 | ||
253c84c8 VS |
901 | /* Bitmask of encoder types (enum intel_output_type) |
902 | * driven by the pipe. | |
903 | */ | |
904 | unsigned int output_types; | |
905 | ||
6897b4b5 SV |
906 | /* Whether we should send NULL infoframes. Required for audio. */ |
907 | bool has_hdmi_sink; | |
908 | ||
9ed109a7 SV |
909 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
910 | * has_dp_encoder is set. */ | |
911 | bool has_audio; | |
912 | ||
d8b32247 SV |
913 | /* |
914 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
915 | * plane bpp. | |
916 | */ | |
965e0c48 | 917 | bool dither; |
f47709a9 | 918 | |
611032bf MN |
919 | /* |
920 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for | |
921 | * compliance video pattern tests. | |
922 | * Disable dither only if it is a compliance test request for | |
923 | * 18bpp. | |
924 | */ | |
925 | bool dither_force_disable; | |
926 | ||
f47709a9 SV |
927 | /* Controls for the clock computation, to override various stages. */ |
928 | bool clock_set; | |
929 | ||
09ede541 SV |
930 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
931 | * work correctly, we need to track this at runtime.*/ | |
932 | bool sdvo_tv_clock; | |
933 | ||
e29c22c0 SV |
934 | /* |
935 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
936 | * required. This is set in the 2nd loop of calling encoder's | |
937 | * ->compute_config if the first pick doesn't work out. | |
938 | */ | |
939 | bool bw_constrained; | |
940 | ||
f47709a9 SV |
941 | /* Settings for the intel dpll used on pretty much everything but |
942 | * haswell. */ | |
80ad9206 | 943 | struct dpll dpll; |
f47709a9 | 944 | |
8106ddbd ACO |
945 | /* Selected dpll when shared or NULL. */ |
946 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 947 | |
66e985c0 SV |
948 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
949 | struct intel_dpll_hw_state dpll_hw_state; | |
950 | ||
47eacbab VS |
951 | /* DSI PLL registers */ |
952 | struct { | |
953 | u32 ctrl, div; | |
954 | } dsi_pll; | |
955 | ||
965e0c48 | 956 | int pipe_bpp; |
6cf86a5e | 957 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 958 | |
439d7ac0 PB |
959 | /* m2_n2 for eDP downclock */ |
960 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 961 | bool has_drrs; |
439d7ac0 | 962 | |
4d90f2d5 VS |
963 | bool has_psr; |
964 | bool has_psr2; | |
965 | ||
ff9a6750 SV |
966 | /* |
967 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
968 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
969 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 970 | */ |
ff9a6750 SV |
971 | int port_clock; |
972 | ||
6cc5f341 SV |
973 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
974 | unsigned pixel_multiplier; | |
2dd24552 | 975 | |
d25236a3 | 976 | u8 lane_count; |
90a6b7b0 | 977 | |
95a7a2ae ID |
978 | /* |
979 | * Used by platforms having DP/HDMI PHY with programmable lane | |
980 | * latency optimization. | |
981 | */ | |
d25236a3 | 982 | u8 lane_lat_optim_mask; |
95a7a2ae | 983 | |
53e9bf5e VS |
984 | /* minimum acceptable voltage level */ |
985 | u8 min_voltage_level; | |
986 | ||
2dd24552 | 987 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
988 | struct { |
989 | u32 control; | |
990 | u32 pgm_ratios; | |
68fc8742 | 991 | u32 lvds_border_bits; |
b074cec8 JB |
992 | } gmch_pfit; |
993 | ||
994 | /* Panel fitter placement and size for Ironlake+ */ | |
995 | struct { | |
996 | u32 pos; | |
997 | u32 size; | |
fd4daa9c | 998 | bool enabled; |
fabf6e51 | 999 | bool force_thru; |
b074cec8 | 1000 | } pch_pfit; |
33d29b14 | 1001 | |
ca3a0ff8 | 1002 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 1003 | int fdi_lanes; |
ca3a0ff8 | 1004 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
1005 | |
1006 | bool ips_enabled; | |
a8ebf607 JRS |
1007 | |
1008 | bool crc_enabled; | |
cf532bb2 | 1009 | |
f51be2e0 PZ |
1010 | bool enable_fbc; |
1011 | ||
cf532bb2 | 1012 | bool double_wide; |
0e32b39c | 1013 | |
0e32b39c | 1014 | int pbn; |
be41e336 CK |
1015 | |
1016 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
1017 | |
1018 | /* w/a for waiting 2 vblanks during crtc enable */ | |
1019 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
1020 | |
1021 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
1022 | bool disable_lp_wm; | |
4e0963c7 | 1023 | |
e8f1f02e | 1024 | struct intel_crtc_wm_state wm; |
05dc698c LL |
1025 | |
1026 | /* Gamma mode programmed on the pipe */ | |
d25236a3 | 1027 | u32 gamma_mode; |
e9728bd8 | 1028 | |
9fdfb8e7 VS |
1029 | union { |
1030 | /* CSC mode programmed on the pipe */ | |
1031 | u32 csc_mode; | |
1032 | ||
1033 | /* CHV CGM mode */ | |
1034 | u32 cgm_mode; | |
1035 | }; | |
a91de580 | 1036 | |
e9728bd8 VS |
1037 | /* bitmask of visible planes (enum plane_id) */ |
1038 | u8 active_planes; | |
8e021151 | 1039 | u8 nv12_planes; |
02c52f1e | 1040 | u8 c8_planes; |
15953637 | 1041 | |
afbd8a72 VS |
1042 | /* bitmask of planes that will be updated during the commit */ |
1043 | u8 update_planes; | |
1044 | ||
e5e70d4a VS |
1045 | struct { |
1046 | u32 enable; | |
fbf08556 VS |
1047 | u32 gcp; |
1048 | union hdmi_infoframe avi; | |
1049 | union hdmi_infoframe spd; | |
1050 | union hdmi_infoframe hdmi; | |
e5e70d4a VS |
1051 | } infoframes; |
1052 | ||
15953637 SS |
1053 | /* HDMI scrambling status */ |
1054 | bool hdmi_scrambling; | |
1055 | ||
1056 | /* HDMI High TMDS char rate ratio */ | |
1057 | bool hdmi_high_tmds_clock_ratio; | |
60436fd4 | 1058 | |
d9facae6 SS |
1059 | /* Output format RGB/YCBCR etc */ |
1060 | enum intel_output_format output_format; | |
668b6c17 SS |
1061 | |
1062 | /* Output down scaling is done in LSPCON device */ | |
1063 | bool lspcon_downsampling; | |
7b610f1f | 1064 | |
5f29ab23 VS |
1065 | /* enable pipe gamma? */ |
1066 | bool gamma_enable; | |
1067 | ||
8271b2ef VS |
1068 | /* enable pipe csc? */ |
1069 | bool csc_enable; | |
1070 | ||
7b610f1f MN |
1071 | /* Display Stream compression state */ |
1072 | struct { | |
1073 | bool compression_enable; | |
1074 | bool dsc_split; | |
1075 | u16 compressed_bpp; | |
1076 | u8 slice_count; | |
1077 | } dsc_params; | |
1078 | struct drm_dsc_config dp_dsc_cfg; | |
240999cf AS |
1079 | |
1080 | /* Forward Error correction State */ | |
1081 | bool fec_enable; | |
b8cecdf5 SV |
1082 | }; |
1083 | ||
79e53945 JB |
1084 | struct intel_crtc { |
1085 | struct drm_crtc base; | |
80824003 | 1086 | enum pipe pipe; |
08a48469 SV |
1087 | /* |
1088 | * Whether the crtc and the connected output pipeline is active. Implies | |
1089 | * that crtc->enabled is set, i.e. the current mode configuration has | |
1090 | * some outputs connected to this crtc. | |
08a48469 SV |
1091 | */ |
1092 | bool active; | |
d97d7b48 | 1093 | u8 plane_ids_mask; |
d8fc70b7 | 1094 | unsigned long long enabled_power_domains; |
02e792fb | 1095 | struct intel_overlay *overlay; |
cda4b7d3 | 1096 | |
6e3c9717 | 1097 | struct intel_crtc_state *config; |
b8cecdf5 | 1098 | |
8664281b PZ |
1099 | /* Access to these should be protected by dev_priv->irq_lock. */ |
1100 | bool cpu_fifo_underrun_disabled; | |
1101 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
1102 | |
1103 | /* per-pipe watermark state */ | |
1104 | struct { | |
1105 | /* watermarks currently being used */ | |
4e0963c7 MR |
1106 | union { |
1107 | struct intel_pipe_wm ilk; | |
7eb4941f | 1108 | struct vlv_wm_state vlv; |
04548cba | 1109 | struct g4x_wm_state g4x; |
4e0963c7 | 1110 | } active; |
0b2ae6d7 | 1111 | } wm; |
8d7849db | 1112 | |
80715b2f | 1113 | int scanline_offset; |
32b7eeec | 1114 | |
eb120ef6 JB |
1115 | struct { |
1116 | unsigned start_vbl_count; | |
1117 | ktime_t start_vbl_time; | |
1118 | int min_vbl, max_vbl; | |
1119 | int scanline_start; | |
1120 | } debug; | |
85a62bf9 | 1121 | |
be41e336 CK |
1122 | /* scalers available on this crtc */ |
1123 | int num_scalers; | |
79e53945 JB |
1124 | }; |
1125 | ||
b840d907 JB |
1126 | struct intel_plane { |
1127 | struct drm_plane base; | |
ed15030d | 1128 | enum i9xx_plane_id i9xx_plane; |
b14e5848 | 1129 | enum plane_id id; |
b840d907 | 1130 | enum pipe pipe; |
cf1805e6 | 1131 | bool has_fbc; |
a38189c5 | 1132 | bool has_ccs; |
d25236a3 | 1133 | u32 frontbuffer_bit; |
526682e9 | 1134 | |
cd5dcbf1 VS |
1135 | struct { |
1136 | u32 base, cntl, size; | |
1137 | } cursor; | |
1138 | ||
8e7d688b MR |
1139 | /* |
1140 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
1141 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 1142 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
1143 | */ |
1144 | ||
ddd5713d VS |
1145 | unsigned int (*max_stride)(struct intel_plane *plane, |
1146 | u32 pixel_format, u64 modifier, | |
1147 | unsigned int rotation); | |
282dbf9b | 1148 | void (*update_plane)(struct intel_plane *plane, |
2fde1391 ML |
1149 | const struct intel_crtc_state *crtc_state, |
1150 | const struct intel_plane_state *plane_state); | |
1ab554b0 ML |
1151 | void (*update_slave)(struct intel_plane *plane, |
1152 | const struct intel_crtc_state *crtc_state, | |
1153 | const struct intel_plane_state *plane_state); | |
282dbf9b | 1154 | void (*disable_plane)(struct intel_plane *plane, |
0dd14be3 | 1155 | const struct intel_crtc_state *crtc_state); |
eade6c89 | 1156 | bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); |
eb0f5044 VS |
1157 | int (*check_plane)(struct intel_crtc_state *crtc_state, |
1158 | struct intel_plane_state *plane_state); | |
b840d907 JB |
1159 | }; |
1160 | ||
b445e3b0 | 1161 | struct intel_watermark_params { |
ae9400ca TU |
1162 | u16 fifo_size; |
1163 | u16 max_wm; | |
1164 | u8 default_wm; | |
1165 | u8 guard_size; | |
1166 | u8 cacheline_size; | |
b445e3b0 ED |
1167 | }; |
1168 | ||
1169 | struct cxsr_latency { | |
c13fb778 TU |
1170 | bool is_desktop : 1; |
1171 | bool is_ddr3 : 1; | |
44a655ca TU |
1172 | u16 fsb_freq; |
1173 | u16 mem_freq; | |
1174 | u16 display_sr; | |
1175 | u16 display_hpll_disable; | |
1176 | u16 cursor_sr; | |
1177 | u16 cursor_hpll_disable; | |
b445e3b0 ED |
1178 | }; |
1179 | ||
de419ab6 | 1180 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 1181 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 1182 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 1183 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 1184 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 1185 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 1186 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 1187 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
a268bcd7 | 1188 | #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) |
79e53945 | 1189 | |
f5bbfca3 | 1190 | struct intel_hdmi { |
f0f59a00 | 1191 | i915_reg_t hdmi_reg; |
f5bbfca3 | 1192 | int ddc_bus; |
b1ba124d VS |
1193 | struct { |
1194 | enum drm_dp_dual_mode_type type; | |
1195 | int max_tmds_clock; | |
1196 | } dp_dual_mode; | |
f5bbfca3 ED |
1197 | bool has_hdmi_sink; |
1198 | bool has_audio; | |
d8b4c43a | 1199 | struct intel_connector *attached_connector; |
9c229127 | 1200 | struct cec_notifier *cec_notifier; |
f5bbfca3 ED |
1201 | }; |
1202 | ||
0e32b39c | 1203 | struct intel_dp_mst_encoder; |
b091cd92 | 1204 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 1205 | |
fe3cd48d R |
1206 | /* |
1207 | * enum link_m_n_set: | |
1208 | * When platform provides two set of M_N registers for dp, we can | |
1209 | * program them and switch between them incase of DRRS. | |
1210 | * But When only one such register is provided, we have to program the | |
1211 | * required divider value on that registers itself based on the DRRS state. | |
1212 | * | |
1213 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
1214 | * dp_m2_n2 on M2_N2 registers (If supported) | |
1215 | * | |
1216 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
1217 | * M2_N2 registers are not supported | |
1218 | */ | |
1219 | ||
1220 | enum link_m_n_set { | |
1221 | /* Sets the m1_n1 and m2_n2 */ | |
1222 | M1_N1 = 0, | |
1223 | M2_N2 | |
1224 | }; | |
1225 | ||
c1617abc MN |
1226 | struct intel_dp_compliance_data { |
1227 | unsigned long edid; | |
d25236a3 JN |
1228 | u8 video_pattern; |
1229 | u16 hdisplay, vdisplay; | |
1230 | u8 bpc; | |
c1617abc MN |
1231 | }; |
1232 | ||
1233 | struct intel_dp_compliance { | |
1234 | unsigned long test_type; | |
1235 | struct intel_dp_compliance_data test_data; | |
1236 | bool test_active; | |
da15f7cb MN |
1237 | int test_link_rate; |
1238 | u8 test_lane_count; | |
c1617abc MN |
1239 | }; |
1240 | ||
54d63ca6 | 1241 | struct intel_dp { |
f0f59a00 | 1242 | i915_reg_t output_reg; |
d25236a3 | 1243 | u32 DP; |
901c2daf | 1244 | int link_rate; |
d25236a3 JN |
1245 | u8 lane_count; |
1246 | u8 sink_count; | |
64ee2fd2 | 1247 | bool link_mst; |
edb2e530 | 1248 | bool link_trained; |
54d63ca6 | 1249 | bool has_audio; |
d7e8ef02 | 1250 | bool reset_link_params; |
d25236a3 JN |
1251 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1252 | u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; | |
1253 | u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; | |
1254 | u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; | |
93ac092f | 1255 | u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; |
08cadae8 | 1256 | u8 fec_capable; |
55cfc580 JN |
1257 | /* source rates */ |
1258 | int num_source_rates; | |
1259 | const int *source_rates; | |
68f357cb JN |
1260 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
1261 | int num_sink_rates; | |
94ca719e | 1262 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
68f357cb | 1263 | bool use_rate_select; |
975ee5fc JN |
1264 | /* intersection of source and sink rates */ |
1265 | int num_common_rates; | |
1266 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
e6c0c64a JN |
1267 | /* Max lane count for the current link */ |
1268 | int max_link_lane_count; | |
1269 | /* Max rate for the current link */ | |
1270 | int max_link_rate; | |
7b3fc170 | 1271 | /* sink or branch descriptor */ |
84c36753 | 1272 | struct drm_dp_desc desc; |
9d1a1031 | 1273 | struct drm_dp_aux aux; |
d25236a3 | 1274 | u8 train_set[4]; |
54d63ca6 SK |
1275 | int panel_power_up_delay; |
1276 | int panel_power_down_delay; | |
1277 | int panel_power_cycle_delay; | |
1278 | int backlight_on_delay; | |
1279 | int backlight_off_delay; | |
54d63ca6 SK |
1280 | struct delayed_work panel_vdd_work; |
1281 | bool want_panel_vdd; | |
dce56b3c PZ |
1282 | unsigned long last_power_on; |
1283 | unsigned long last_backlight_off; | |
d28d4731 | 1284 | ktime_t panel_power_off_time; |
5d42f82a | 1285 | |
01527b31 CT |
1286 | struct notifier_block edp_notifier; |
1287 | ||
a4a5d2f8 VS |
1288 | /* |
1289 | * Pipe whose power sequencer is currently locked into | |
1290 | * this port. Only relevant on VLV/CHV. | |
1291 | */ | |
1292 | enum pipe pps_pipe; | |
9f2bdb00 VS |
1293 | /* |
1294 | * Pipe currently driving the port. Used for preventing | |
1295 | * the use of the PPS for any pipe currentrly driving | |
1296 | * external DP as that will mess things up on VLV. | |
1297 | */ | |
1298 | enum pipe active_pipe; | |
78597996 ID |
1299 | /* |
1300 | * Set if the sequencer may be reset due to a power transition, | |
1301 | * requiring a reinitialization. Only relevant on BXT. | |
1302 | */ | |
1303 | bool pps_reset; | |
36b5f425 | 1304 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 1305 | |
0e32b39c DA |
1306 | bool can_mst; /* this port supports mst */ |
1307 | bool is_mst; | |
19e0b4ca | 1308 | int active_mst_links; |
0e32b39c | 1309 | /* connector directly attached - won't be use for modeset in mst world */ |
dd06f90e | 1310 | struct intel_connector *attached_connector; |
ec5b01dd | 1311 | |
0e32b39c DA |
1312 | /* mst connector list */ |
1313 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
1314 | struct drm_dp_mst_topology_mgr mst_mgr; | |
1315 | ||
d25236a3 | 1316 | u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
1317 | /* |
1318 | * This function returns the value we have to program the AUX_CTL | |
1319 | * register with to kick off an AUX transaction. | |
1320 | */ | |
d25236a3 JN |
1321 | u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, |
1322 | u32 aux_clock_divider); | |
ad64217b | 1323 | |
4904fa66 VS |
1324 | i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); |
1325 | i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); | |
1326 | ||
ad64217b ACO |
1327 | /* This is called before a link training is starterd */ |
1328 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
1329 | ||
c5d5ab7a | 1330 | /* Displayport compliance testing */ |
c1617abc | 1331 | struct intel_dp_compliance compliance; |
e845f099 MN |
1332 | |
1333 | /* Display stream compression testing */ | |
1334 | bool force_dsc_en; | |
54d63ca6 SK |
1335 | }; |
1336 | ||
96e35598 SS |
1337 | enum lspcon_vendor { |
1338 | LSPCON_VENDOR_MCA, | |
1339 | LSPCON_VENDOR_PARADE | |
1340 | }; | |
1341 | ||
dbe9e61b SS |
1342 | struct intel_lspcon { |
1343 | bool active; | |
1344 | enum drm_lspcon_mode mode; | |
96e35598 | 1345 | enum lspcon_vendor vendor; |
dbe9e61b SS |
1346 | }; |
1347 | ||
da63a9f2 PZ |
1348 | struct intel_digital_port { |
1349 | struct intel_encoder base; | |
bcf53de4 | 1350 | u32 saved_port_bits; |
da63a9f2 PZ |
1351 | struct intel_dp dp; |
1352 | struct intel_hdmi hdmi; | |
dbe9e61b | 1353 | struct intel_lspcon lspcon; |
b2c5c181 | 1354 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 1355 | bool release_cl2_override; |
d25236a3 | 1356 | u8 max_lanes; |
563d22a0 ID |
1357 | /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ |
1358 | enum aux_ch aux_ch; | |
62b69566 | 1359 | enum intel_display_power_domain ddi_io_power_domain; |
f6bff60e | 1360 | bool tc_legacy_port:1; |
6075546f | 1361 | enum tc_port_type tc_type; |
f99be1b3 | 1362 | |
790ea70c | 1363 | void (*write_infoframe)(struct intel_encoder *encoder, |
f99be1b3 | 1364 | const struct intel_crtc_state *crtc_state, |
1d776538 | 1365 | unsigned int type, |
f99be1b3 | 1366 | const void *frame, ssize_t len); |
f2a10d61 VS |
1367 | void (*read_infoframe)(struct intel_encoder *encoder, |
1368 | const struct intel_crtc_state *crtc_state, | |
1369 | unsigned int type, | |
1370 | void *frame, ssize_t len); | |
790ea70c | 1371 | void (*set_infoframes)(struct intel_encoder *encoder, |
f99be1b3 VS |
1372 | bool enable, |
1373 | const struct intel_crtc_state *crtc_state, | |
1374 | const struct drm_connector_state *conn_state); | |
509efa2b | 1375 | u32 (*infoframes_enabled)(struct intel_encoder *encoder, |
f99be1b3 | 1376 | const struct intel_crtc_state *pipe_config); |
da63a9f2 PZ |
1377 | }; |
1378 | ||
0e32b39c DA |
1379 | struct intel_dp_mst_encoder { |
1380 | struct intel_encoder base; | |
1381 | enum pipe pipe; | |
1382 | struct intel_digital_port *primary; | |
0552f765 | 1383 | struct intel_connector *connector; |
0e32b39c DA |
1384 | }; |
1385 | ||
65d64cc5 | 1386 | static inline enum dpio_channel |
89b667f8 JB |
1387 | vlv_dport_to_channel(struct intel_digital_port *dport) |
1388 | { | |
8f4f2797 | 1389 | switch (dport->base.port) { |
89b667f8 | 1390 | case PORT_B: |
00fc31b7 | 1391 | case PORT_D: |
e4607fcf | 1392 | return DPIO_CH0; |
89b667f8 | 1393 | case PORT_C: |
e4607fcf | 1394 | return DPIO_CH1; |
89b667f8 JB |
1395 | default: |
1396 | BUG(); | |
1397 | } | |
1398 | } | |
1399 | ||
65d64cc5 VS |
1400 | static inline enum dpio_phy |
1401 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
1402 | { | |
8f4f2797 | 1403 | switch (dport->base.port) { |
65d64cc5 VS |
1404 | case PORT_B: |
1405 | case PORT_C: | |
1406 | return DPIO_PHY0; | |
1407 | case PORT_D: | |
1408 | return DPIO_PHY1; | |
1409 | default: | |
1410 | BUG(); | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | static inline enum dpio_channel | |
eb69b0e5 CML |
1415 | vlv_pipe_to_channel(enum pipe pipe) |
1416 | { | |
1417 | switch (pipe) { | |
1418 | case PIPE_A: | |
1419 | case PIPE_C: | |
1420 | return DPIO_CH0; | |
1421 | case PIPE_B: | |
1422 | return DPIO_CH1; | |
1423 | default: | |
1424 | BUG(); | |
1425 | } | |
1426 | } | |
1427 | ||
e2af48c6 | 1428 | static inline struct intel_crtc * |
b91eb5cc | 1429 | intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
f875c15a | 1430 | { |
f875c15a CW |
1431 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
1432 | } | |
1433 | ||
e2af48c6 | 1434 | static inline struct intel_crtc * |
ed15030d | 1435 | intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) |
417ae147 | 1436 | { |
417ae147 CW |
1437 | return dev_priv->plane_to_crtc_mapping[plane]; |
1438 | } | |
1439 | ||
5f1aae65 | 1440 | struct intel_load_detect_pipe { |
edde3617 | 1441 | struct drm_atomic_state *restore_state; |
5f1aae65 | 1442 | }; |
79e53945 | 1443 | |
5f1aae65 PZ |
1444 | static inline struct intel_encoder * |
1445 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
1446 | { |
1447 | return to_intel_connector(connector)->encoder; | |
1448 | } | |
1449 | ||
4ef03f83 | 1450 | static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) |
da63a9f2 | 1451 | { |
4ef03f83 | 1452 | switch (encoder->type) { |
7e732cac | 1453 | case INTEL_OUTPUT_DDI: |
9a5da00b ACO |
1454 | case INTEL_OUTPUT_DP: |
1455 | case INTEL_OUTPUT_EDP: | |
1456 | case INTEL_OUTPUT_HDMI: | |
4ef03f83 VS |
1457 | return true; |
1458 | default: | |
1459 | return false; | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | static inline struct intel_digital_port * | |
1464 | enc_to_dig_port(struct drm_encoder *encoder) | |
1465 | { | |
1466 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
1467 | ||
1468 | if (intel_encoder_is_dig_port(intel_encoder)) | |
9a5da00b ACO |
1469 | return container_of(encoder, struct intel_digital_port, |
1470 | base.base); | |
4ef03f83 | 1471 | else |
9a5da00b | 1472 | return NULL; |
9ff8c9ba ID |
1473 | } |
1474 | ||
bdc93fe0 R |
1475 | static inline struct intel_digital_port * |
1476 | conn_to_dig_port(struct intel_connector *connector) | |
1477 | { | |
1478 | return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base); | |
1479 | } | |
1480 | ||
0e32b39c DA |
1481 | static inline struct intel_dp_mst_encoder * |
1482 | enc_to_mst(struct drm_encoder *encoder) | |
1483 | { | |
1484 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
1485 | } | |
1486 | ||
9ff8c9ba ID |
1487 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1488 | { | |
1489 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1490 | } |
1491 | ||
14aa521c VS |
1492 | static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) |
1493 | { | |
1494 | switch (encoder->type) { | |
1495 | case INTEL_OUTPUT_DP: | |
1496 | case INTEL_OUTPUT_EDP: | |
1497 | return true; | |
1498 | case INTEL_OUTPUT_DDI: | |
1499 | /* Skip pure HDMI/DVI DDI encoders */ | |
1500 | return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg); | |
1501 | default: | |
1502 | return false; | |
1503 | } | |
1504 | } | |
1505 | ||
06c812d7 SS |
1506 | static inline struct intel_lspcon * |
1507 | enc_to_intel_lspcon(struct drm_encoder *encoder) | |
1508 | { | |
1509 | return &enc_to_dig_port(encoder)->lspcon; | |
1510 | } | |
1511 | ||
da63a9f2 PZ |
1512 | static inline struct intel_digital_port * |
1513 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1514 | { | |
1515 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1516 | } | |
1517 | ||
dd75f6dd ID |
1518 | static inline struct intel_lspcon * |
1519 | dp_to_lspcon(struct intel_dp *intel_dp) | |
1520 | { | |
1521 | return &dp_to_dig_port(intel_dp)->lspcon; | |
1522 | } | |
1523 | ||
de25eb7f RV |
1524 | static inline struct drm_i915_private * |
1525 | dp_to_i915(struct intel_dp *intel_dp) | |
1526 | { | |
1527 | return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
1528 | } | |
1529 | ||
da63a9f2 PZ |
1530 | static inline struct intel_digital_port * |
1531 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1532 | { | |
1533 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1534 | } |
1535 | ||
1ab554b0 ML |
1536 | static inline struct intel_plane_state * |
1537 | intel_atomic_get_plane_state(struct intel_atomic_state *state, | |
1538 | struct intel_plane *plane) | |
1539 | { | |
1540 | struct drm_plane_state *ret = | |
1541 | drm_atomic_get_plane_state(&state->base, &plane->base); | |
1542 | ||
1543 | if (IS_ERR(ret)) | |
1544 | return ERR_CAST(ret); | |
1545 | ||
1546 | return to_intel_plane_state(ret); | |
1547 | } | |
1548 | ||
1549 | static inline struct intel_plane_state * | |
1550 | intel_atomic_get_old_plane_state(struct intel_atomic_state *state, | |
1551 | struct intel_plane *plane) | |
1552 | { | |
1553 | return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, | |
1554 | &plane->base)); | |
1555 | } | |
1556 | ||
b2b55502 VS |
1557 | static inline struct intel_plane_state * |
1558 | intel_atomic_get_new_plane_state(struct intel_atomic_state *state, | |
1559 | struct intel_plane *plane) | |
1560 | { | |
1561 | return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, | |
1562 | &plane->base)); | |
1563 | } | |
1564 | ||
7b510451 VS |
1565 | static inline struct intel_crtc_state * |
1566 | intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, | |
1567 | struct intel_crtc *crtc) | |
1568 | { | |
1569 | return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, | |
1570 | &crtc->base)); | |
1571 | } | |
1572 | ||
d3a8fb32 VS |
1573 | static inline struct intel_crtc_state * |
1574 | intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, | |
1575 | struct intel_crtc *crtc) | |
1576 | { | |
1577 | return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, | |
1578 | &crtc->base)); | |
1579 | } | |
1580 | ||
47339cd9 | 1581 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1582 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1583 | enum pipe pipe, bool enable); |
a72e4c9f | 1584 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
a2196033 | 1585 | enum pipe pch_transcoder, |
87440425 | 1586 | bool enable); |
1f7247c0 SV |
1587 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1588 | enum pipe pipe); | |
1589 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
a2196033 | 1590 | enum pipe pch_transcoder); |
aca7b684 VS |
1591 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1592 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 SV |
1593 | |
1594 | /* i915_irq.c */ | |
d25236a3 JN |
1595 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); |
1596 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); | |
f4e9af4f AG |
1597 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); |
1598 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); | |
d02b98b8 | 1599 | void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
dc97997a | 1600 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
91d14251 TU |
1601 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
1602 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); | |
1300b4f8 CW |
1603 | |
1604 | static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, | |
1605 | u32 mask) | |
1606 | { | |
562d9bae | 1607 | return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; |
1300b4f8 CW |
1608 | } |
1609 | ||
b963291c SV |
1610 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1611 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1612 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1613 | { | |
1614 | /* | |
1615 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1616 | * this is the only thing we need to check. | |
1617 | */ | |
ad1443f0 | 1618 | return dev_priv->runtime_pm.irqs_enabled; |
9df7575f JB |
1619 | } |
1620 | ||
a225f079 | 1621 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be | 1622 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
001bd2cb | 1623 | u8 pipe_mask); |
aae8ba84 | 1624 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
001bd2cb | 1625 | u8 pipe_mask); |
26705e20 SAK |
1626 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); |
1627 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); | |
1628 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); | |
5f1aae65 | 1629 | |
5f1aae65 | 1630 | /* intel_ddi.c */ |
b7076546 | 1631 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
5f88a9c6 VS |
1632 | const struct intel_crtc_state *old_crtc_state, |
1633 | const struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
1634 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
1635 | const struct intel_crtc_state *crtc_state); | |
c39055b0 | 1636 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); |
87440425 | 1637 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
3dc38eea | 1638 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); |
90c3e219 | 1639 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); |
3dc38eea ACO |
1640 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1641 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); | |
3dc38eea | 1642 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); |
ad64217b | 1643 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 | 1644 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
87440425 | 1645 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1646 | struct intel_crtc_state *pipe_config); |
5f1aae65 | 1647 | |
3dc38eea ACO |
1648 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1649 | bool state); | |
53e9bf5e VS |
1650 | void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, |
1651 | struct intel_crtc_state *crtc_state); | |
d509af6c | 1652 | u32 bxt_signal_levels(struct intel_dp *intel_dp); |
d25236a3 | 1653 | u32 ddi_signal_levels(struct intel_dp *intel_dp); |
ffe5111e | 1654 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); |
4718a365 VS |
1655 | u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, |
1656 | u8 voltage_swing); | |
2320175f SP |
1657 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, |
1658 | bool enable); | |
70332ac5 | 1659 | void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); |
8327af28 | 1660 | int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
5e65216d | 1661 | struct intel_dpll_hw_state *state); |
ffe5111e | 1662 | |
d88c4afd | 1663 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, |
5d2a1950 | 1664 | int color_plane, unsigned int height); |
b680c37a | 1665 | |
7ff89ca2 | 1666 | /* intel_cdclk.c */ |
d305e061 | 1667 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); |
e1cd3325 PZ |
1668 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
1669 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
d8d4a512 VS |
1670 | void cnl_init_cdclk(struct drm_i915_private *dev_priv); |
1671 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
e1cd3325 PZ |
1672 | void bxt_init_cdclk(struct drm_i915_private *dev_priv); |
1673 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); | |
186a277e PZ |
1674 | void icl_init_cdclk(struct drm_i915_private *dev_priv); |
1675 | void icl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
7ff89ca2 VS |
1676 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); |
1677 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv); | |
1678 | void intel_update_cdclk(struct drm_i915_private *dev_priv); | |
1679 | void intel_update_rawclk(struct drm_i915_private *dev_priv); | |
59f9e9ca VS |
1680 | bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, |
1681 | const struct intel_cdclk_state *a, | |
1682 | const struct intel_cdclk_state *b); | |
64600bd5 | 1683 | bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, |
49cd97a3 | 1684 | const struct intel_cdclk_state *b); |
64600bd5 VS |
1685 | bool intel_cdclk_changed(const struct intel_cdclk_state *a, |
1686 | const struct intel_cdclk_state *b); | |
48d9f87d | 1687 | void intel_cdclk_swap_state(struct intel_atomic_state *state); |
59f9e9ca VS |
1688 | void |
1689 | intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, | |
1690 | const struct intel_cdclk_state *old_state, | |
1691 | const struct intel_cdclk_state *new_state, | |
1692 | enum pipe pipe); | |
1693 | void | |
1694 | intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, | |
1695 | const struct intel_cdclk_state *old_state, | |
1696 | const struct intel_cdclk_state *new_state, | |
1697 | enum pipe pipe); | |
cfddadc9 VS |
1698 | void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, |
1699 | const char *context); | |
7ff89ca2 | 1700 | |
b680c37a | 1701 | /* intel_display.c */ |
2ee0da16 VS |
1702 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); |
1703 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
a2196033 | 1704 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); |
49cd97a3 | 1705 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1706 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1707 | const char *name, u32 reg, int ref_freq); | |
7ff89ca2 VS |
1708 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
1709 | const char *name, u32 reg); | |
b7076546 ML |
1710 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); |
1711 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
88212941 | 1712 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
6687c906 | 1713 | unsigned int intel_fb_xy_to_linear(int x, int y, |
2949056c VS |
1714 | const struct intel_plane_state *state, |
1715 | int plane); | |
6687c906 | 1716 | void intel_add_fb_offsets(int *x, int *y, |
2949056c | 1717 | const struct intel_plane_state *state, int plane); |
1663b9d6 | 1718 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
49d73912 | 1719 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); |
7d993739 TU |
1720 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1721 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
70e0bd74 | 1722 | int intel_display_suspend(struct drm_device *dev); |
8090ba8c | 1723 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); |
87440425 | 1724 | void intel_encoder_destroy(struct drm_encoder *encoder); |
de330815 VS |
1725 | struct drm_display_mode * |
1726 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
176597a1 | 1727 | bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port); |
ac213c1b PZ |
1728 | bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); |
1729 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, | |
1730 | enum port port); | |
6a20fe7b VS |
1731 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
1732 | struct drm_file *file_priv); | |
87440425 PZ |
1733 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1734 | enum pipe pipe); | |
2d84d2b3 VS |
1735 | static inline bool |
1736 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, | |
1737 | enum intel_output_type type) | |
1738 | { | |
1739 | return crtc_state->output_types & (1 << type); | |
1740 | } | |
37a5650b VS |
1741 | static inline bool |
1742 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) | |
1743 | { | |
1744 | return crtc_state->output_types & | |
cca0502b | 1745 | ((1 << INTEL_OUTPUT_DP) | |
37a5650b VS |
1746 | (1 << INTEL_OUTPUT_DP_MST) | |
1747 | (1 << INTEL_OUTPUT_EDP)); | |
1748 | } | |
4f905cf9 | 1749 | static inline void |
0f0f74bc | 1750 | intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) |
4f905cf9 | 1751 | { |
0f0f74bc | 1752 | drm_wait_one_vblank(&dev_priv->drm, pipe); |
4f905cf9 | 1753 | } |
0c241d5b | 1754 | static inline void |
0f0f74bc | 1755 | intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) |
0c241d5b | 1756 | { |
b91eb5cc | 1757 | const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
0c241d5b VS |
1758 | |
1759 | if (crtc->active) | |
0f0f74bc | 1760 | intel_wait_for_vblank(dev_priv, pipe); |
0c241d5b | 1761 | } |
a2991414 ML |
1762 | |
1763 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
1764 | ||
87440425 | 1765 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1766 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1767 | struct intel_digital_port *dport, |
1768 | unsigned int expected_mask); | |
6c5ed5ae | 1769 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 1770 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
1771 | struct intel_load_detect_pipe *old, |
1772 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1773 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1774 | struct intel_load_detect_pipe *old, |
1775 | struct drm_modeset_acquire_ctx *ctx); | |
058d88c4 | 1776 | struct i915_vma * |
5935485f | 1777 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
f5929c53 | 1778 | const struct i915_ggtt_view *view, |
f7a02ad7 | 1779 | bool uses_fence, |
5935485f CW |
1780 | unsigned long *out_flags); |
1781 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); | |
a8bb6818 | 1782 | struct drm_framebuffer * |
24dbf51a CW |
1783 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
1784 | struct drm_mode_fb_cmd2 *mode_cmd); | |
6beb8c23 | 1785 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1832040d | 1786 | struct drm_plane_state *new_state); |
38f3ce3a | 1787 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
1832040d | 1788 | struct drm_plane_state *old_state); |
a98b3431 MR |
1789 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1790 | const struct drm_plane_state *state, | |
1791 | struct drm_property *property, | |
d25236a3 | 1792 | u64 *val); |
a98b3431 MR |
1793 | int intel_plane_atomic_set_property(struct drm_plane *plane, |
1794 | struct drm_plane_state *state, | |
1795 | struct drm_property *property, | |
d25236a3 | 1796 | u64 val); |
b2b55502 VS |
1797 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
1798 | struct drm_crtc_state *crtc_state, | |
1799 | const struct intel_plane_state *old_plane_state, | |
da20eabd | 1800 | struct drm_plane_state *plane_state); |
716c2e55 | 1801 | |
7abd4b35 ACO |
1802 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1803 | enum pipe pipe); | |
1804 | ||
30ad9814 | 1805 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 1806 | const struct dpll *dpll); |
30ad9814 | 1807 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); |
8802e5b6 | 1808 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1809 | |
716c2e55 | 1810 | /* modesetting asserts */ |
b680c37a SV |
1811 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1812 | enum pipe pipe); | |
55607e8a SV |
1813 | void assert_pll(struct drm_i915_private *dev_priv, |
1814 | enum pipe pipe, bool state); | |
1815 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1816 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1817 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1818 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1819 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a SV |
1820 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1821 | enum pipe pipe, bool state); | |
1822 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1823 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1824 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1825 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1826 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
c033666a CW |
1827 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1828 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
a14cb6fc PZ |
1829 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1830 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
da2f41d1 | 1831 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
664326f8 SK |
1832 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1833 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
f62c79b3 | 1834 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
c89e39f3 | 1835 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
3e68928b | 1836 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
87440425 | 1837 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1838 | struct intel_crtc_state *pipe_config); |
4c354754 ML |
1839 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, |
1840 | enum link_m_n_set m_n); | |
87440425 | 1841 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
e40396d0 | 1842 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
1843 | struct dpll *best_clock); |
1844 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1845 | |
525b9311 | 1846 | bool intel_crtc_active(struct intel_crtc *crtc); |
24f28450 | 1847 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); |
199ea381 ML |
1848 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state); |
1849 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state); | |
79f255a0 | 1850 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); |
337837ac ID |
1851 | enum intel_display_power_domain |
1852 | intel_aux_power_domain(struct intel_digital_port *dig_port); | |
f6a83288 | 1853 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1854 | struct intel_crtc_state *pipe_config); |
d52ad9cb ML |
1855 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
1856 | struct intel_crtc_state *crtc_state); | |
86adf9d7 | 1857 | |
e7a278a3 | 1858 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); |
e435d6e5 | 1859 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
4e0b83a5 VS |
1860 | int skl_max_scale(const struct intel_crtc_state *crtc_state, |
1861 | u32 pixel_format); | |
8ea30864 | 1862 | |
be1e3415 CW |
1863 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) |
1864 | { | |
1865 | return i915_ggtt_offset(state->vma); | |
1866 | } | |
dedf278c | 1867 | |
4036c78c JA |
1868 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
1869 | const struct intel_plane_state *plane_state); | |
7eb31a0b | 1870 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); |
2e881264 VS |
1871 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
1872 | const struct intel_plane_state *plane_state); | |
7eb31a0b | 1873 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); |
df79cf44 VS |
1874 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
1875 | int plane); | |
73266595 | 1876 | int skl_check_plane_surface(struct intel_plane_state *plane_state); |
f9407ae1 | 1877 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); |
ddf34319 | 1878 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); |
ddd5713d VS |
1879 | unsigned int i9xx_plane_max_stride(struct intel_plane *plane, |
1880 | u32 pixel_format, u64 modifier, | |
1881 | unsigned int rotation); | |
121920fa | 1882 | |
360fa66a | 1883 | /* intel_connector.c */ |
1c21348d JN |
1884 | int intel_connector_init(struct intel_connector *connector); |
1885 | struct intel_connector *intel_connector_alloc(void); | |
1886 | void intel_connector_free(struct intel_connector *connector); | |
1887 | void intel_connector_destroy(struct drm_connector *connector); | |
1888 | int intel_connector_register(struct drm_connector *connector); | |
1889 | void intel_connector_unregister(struct drm_connector *connector); | |
1890 | void intel_connector_attach_encoder(struct intel_connector *connector, | |
1891 | struct intel_encoder *encoder); | |
1892 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
046c9bca | 1893 | enum pipe intel_connector_get_pipe(struct intel_connector *connector); |
360fa66a JN |
1894 | int intel_connector_update_modes(struct drm_connector *connector, |
1895 | struct edid *edid); | |
1896 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); | |
1897 | void intel_attach_force_audio_property(struct drm_connector *connector); | |
1898 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
1899 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); | |
2f146b78 | 1900 | void intel_attach_colorspace_property(struct drm_connector *connector); |
360fa66a | 1901 | |
eb805623 | 1902 | /* intel_csr.c */ |
f4448375 | 1903 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1904 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1905 | void intel_csr_ucode_fini(struct drm_i915_private *); |
f74ed08d ID |
1906 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
1907 | void intel_csr_ucode_resume(struct drm_i915_private *); | |
eb805623 | 1908 | |
5f1aae65 | 1909 | /* intel_dp.c */ |
f1477219 VS |
1910 | struct link_config_limits { |
1911 | int min_clock, max_clock; | |
1912 | int min_lane_count, max_lane_count; | |
1913 | int min_bpp, max_bpp; | |
1914 | }; | |
1915 | void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, | |
1916 | struct intel_crtc_state *pipe_config, | |
1917 | struct link_config_limits *limits); | |
37aa52bf VS |
1918 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
1919 | const struct drm_connector_state *conn_state); | |
59b74c49 VS |
1920 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, |
1921 | i915_reg_t dp_reg, enum port port, | |
1922 | enum pipe *pipe); | |
c39055b0 ACO |
1923 | bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, |
1924 | enum port port); | |
87440425 PZ |
1925 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1926 | struct intel_connector *intel_connector); | |
901c2daf | 1927 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
d25236a3 | 1928 | int link_rate, u8 lane_count, |
dfa10480 | 1929 | bool link_mst); |
fdb14d33 | 1930 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
d25236a3 | 1931 | int link_rate, u8 lane_count); |
87440425 | 1932 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 | 1933 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c85d200e VS |
1934 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
1935 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1936 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
2279298d GS |
1937 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
1938 | const struct intel_crtc_state *crtc_state, | |
1939 | bool enable); | |
bf93ba67 ID |
1940 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1941 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | |
f6bff60e | 1942 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder); |
204474a6 LP |
1943 | int intel_dp_compute_config(struct intel_encoder *encoder, |
1944 | struct intel_crtc_state *pipe_config, | |
1945 | struct drm_connector_state *conn_state); | |
1853a9da | 1946 | bool intel_dp_is_edp(struct intel_dp *intel_dp); |
7b91bf7f | 1947 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
b2c5c181 SV |
1948 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1949 | bool long_hpd); | |
b037d58f ML |
1950 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
1951 | const struct drm_connector_state *conn_state); | |
1952 | void intel_edp_backlight_off(const struct drm_connector_state *conn_state); | |
24f3e092 | 1953 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 SV |
1954 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1955 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
1a4313d1 VS |
1956 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); |
1957 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv); | |
50fec21a | 1958 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
3d65a735 | 1959 | int intel_dp_max_lane_count(struct intel_dp *intel_dp); |
ed4e9c1d | 1960 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1961 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
78597996 | 1962 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); |
d25236a3 | 1963 | u32 intel_dp_pack_aux(const u8 *src, int src_bytes); |
4a3b8769 | 1964 | void intel_plane_destroy(struct drm_plane *plane); |
85cb48a1 | 1965 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 1966 | const struct intel_crtc_state *crtc_state); |
85cb48a1 | 1967 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 1968 | const struct intel_crtc_state *crtc_state); |
5748b6a1 CW |
1969 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
1970 | unsigned int frontbuffer_bits); | |
1971 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, | |
1972 | unsigned int frontbuffer_bits); | |
0bc12bcb | 1973 | |
94223d04 ACO |
1974 | void |
1975 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
d25236a3 | 1976 | u8 dp_train_pat); |
94223d04 ACO |
1977 | void |
1978 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1979 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
d25236a3 | 1980 | u8 |
94223d04 | 1981 | intel_dp_voltage_max(struct intel_dp *intel_dp); |
d25236a3 JN |
1982 | u8 |
1983 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing); | |
94223d04 | 1984 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
d25236a3 | 1985 | u8 *link_bw, u8 *rate_select); |
e588fa18 | 1986 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
2edd5327 | 1987 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); |
94223d04 | 1988 | bool |
d25236a3 JN |
1989 | intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]); |
1990 | u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count, | |
1991 | int mode_clock, int mode_hdisplay); | |
1992 | u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, | |
1993 | int mode_hdisplay); | |
94223d04 | 1994 | |
168243c1 GS |
1995 | /* intel_vdsc.c */ |
1996 | int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, | |
1997 | struct intel_crtc_state *pipe_config); | |
a24c62f9 MN |
1998 | enum intel_display_power_domain |
1999 | intel_dsc_power_domain(const struct intel_crtc_state *crtc_state); | |
168243c1 | 2000 | |
419b1b7a ACO |
2001 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
2002 | { | |
2003 | return ~((1 << lane_count) - 1) & 0xf; | |
2004 | } | |
2005 | ||
24e807e7 | 2006 | bool intel_dp_read_dpcd(struct intel_dp *intel_dp); |
22a2c8e0 DP |
2007 | int intel_dp_link_required(int pixel_clock, int bpp); |
2008 | int intel_dp_max_data_rate(int max_link_clock, int max_lanes); | |
7533eb4f | 2009 | bool intel_digital_port_connected(struct intel_encoder *encoder); |
f6bff60e ID |
2010 | void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv, |
2011 | struct intel_digital_port *dig_port); | |
24e807e7 | 2012 | |
e7156c83 YA |
2013 | /* intel_dp_aux_backlight.c */ |
2014 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); | |
2015 | ||
0e32b39c DA |
2016 | /* intel_dp_mst.c */ |
2017 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
2018 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
ca3589c1 | 2019 | /* vlv_dsi.c */ |
e518634b | 2020 | void vlv_dsi_init(struct drm_i915_private *dev_priv); |
5f1aae65 | 2021 | |
bf4d57ff MC |
2022 | /* icl_dsi.c */ |
2023 | void icl_dsi_init(struct drm_i915_private *dev_priv); | |
2024 | ||
90198355 JN |
2025 | /* intel_dsi_dcs_backlight.c */ |
2026 | int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); | |
5f1aae65 PZ |
2027 | |
2028 | /* intel_dvo.c */ | |
c39055b0 | 2029 | void intel_dvo_init(struct drm_i915_private *dev_priv); |
19625e85 L |
2030 | /* intel_hotplug.c */ |
2031 | void intel_hpd_poll_init(struct drm_i915_private *dev_priv); | |
dba14b27 VS |
2032 | bool intel_encoder_hotplug(struct intel_encoder *encoder, |
2033 | struct intel_connector *connector); | |
5f1aae65 | 2034 | |
0632fef6 | 2035 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 2036 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 2037 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 2038 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4f256d82 SV |
2039 | extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); |
2040 | extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); | |
82e3b8c1 | 2041 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 SV |
2042 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
2043 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a SV |
2044 | #else |
2045 | static inline int intel_fbdev_init(struct drm_device *dev) | |
2046 | { | |
2047 | return 0; | |
2048 | } | |
5f1aae65 | 2049 | |
e00bf696 | 2050 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a SV |
2051 | { |
2052 | } | |
2053 | ||
4f256d82 SV |
2054 | static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) |
2055 | { | |
2056 | } | |
2057 | ||
2058 | static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) | |
4520f53a SV |
2059 | { |
2060 | } | |
2061 | ||
82e3b8c1 | 2062 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a SV |
2063 | { |
2064 | } | |
2065 | ||
d9c409d6 JN |
2066 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
2067 | { | |
2068 | } | |
2069 | ||
0632fef6 | 2070 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a SV |
2071 | { |
2072 | } | |
2073 | #endif | |
5f1aae65 | 2074 | |
7ff0ebcc | 2075 | /* intel_fbc.c */ |
f51be2e0 | 2076 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
dd57602e | 2077 | struct intel_atomic_state *state); |
0e631adc | 2078 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
faf68d92 ML |
2079 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
2080 | struct intel_crtc_state *crtc_state, | |
2081 | struct intel_plane_state *plane_state); | |
1eb52238 | 2082 | void intel_fbc_post_update(struct intel_crtc *crtc); |
7ff0ebcc | 2083 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 2084 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
faf68d92 ML |
2085 | void intel_fbc_enable(struct intel_crtc *crtc, |
2086 | struct intel_crtc_state *crtc_state, | |
2087 | struct intel_plane_state *plane_state); | |
c937ab3e PZ |
2088 | void intel_fbc_disable(struct intel_crtc *crtc); |
2089 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
2090 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
2091 | unsigned int frontbuffer_bits, | |
2092 | enum fb_op_origin origin); | |
2093 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 2094 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 2095 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
61a585d6 | 2096 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); |
d52ad9cb | 2097 | int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); |
7ff0ebcc | 2098 | |
5f1aae65 | 2099 | /* intel_hdmi.c */ |
c39055b0 ACO |
2100 | void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, |
2101 | enum port port); | |
87440425 PZ |
2102 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2103 | struct intel_connector *intel_connector); | |
2104 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
204474a6 LP |
2105 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2106 | struct intel_crtc_state *pipe_config, | |
2107 | struct drm_connector_state *conn_state); | |
277ab5ab | 2108 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2109 | struct drm_connector *connector, |
2110 | bool high_tmds_clock_ratio, | |
2111 | bool scrambling); | |
b2ccb822 | 2112 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
385e4de0 | 2113 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port); |
509efa2b VS |
2114 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
2115 | const struct intel_crtc_state *crtc_state); | |
fbf08556 | 2116 | u32 intel_hdmi_infoframe_enable(unsigned int type); |
f2a10d61 VS |
2117 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
2118 | struct intel_crtc_state *crtc_state); | |
2119 | void intel_read_infoframe(struct intel_encoder *encoder, | |
2120 | const struct intel_crtc_state *crtc_state, | |
2121 | enum hdmi_infoframe_type type, | |
2122 | union hdmi_infoframe *frame); | |
5f1aae65 | 2123 | |
5f1aae65 | 2124 | /* intel_lvds.c */ |
a44628b9 VS |
2125 | bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, |
2126 | i915_reg_t lvds_reg, enum pipe *pipe); | |
c39055b0 | 2127 | void intel_lvds_init(struct drm_i915_private *dev_priv); |
17be4942 | 2128 | struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv); |
d2daff2c | 2129 | bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv); |
5f1aae65 | 2130 | |
5f1aae65 | 2131 | /* intel_overlay.c */ |
58db08a7 JRS |
2132 | void intel_overlay_setup(struct drm_i915_private *dev_priv); |
2133 | void intel_overlay_cleanup(struct drm_i915_private *dev_priv); | |
87440425 | 2134 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
1ee8da6d CW |
2135 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
2136 | struct drm_file *file_priv); | |
2137 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
2138 | struct drm_file *file_priv); | |
1362b776 | 2139 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
2140 | |
2141 | ||
2142 | /* intel_panel.c */ | |
87440425 | 2143 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
2144 | struct drm_display_mode *fixed_mode, |
2145 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
2146 | void intel_panel_fini(struct intel_panel *panel); |
2147 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
2148 | struct drm_display_mode *adjusted_mode); | |
2149 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 2150 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
2151 | int fitting_mode); |
2152 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 2153 | struct intel_crtc_state *pipe_config, |
87440425 | 2154 | int fitting_mode); |
90d7cd24 | 2155 | void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state, |
6dda730e | 2156 | u32 level, u32 max); |
fda9ee98 CW |
2157 | int intel_panel_setup_backlight(struct drm_connector *connector, |
2158 | enum pipe pipe); | |
b037d58f ML |
2159 | void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, |
2160 | const struct drm_connector_state *conn_state); | |
63a23d24 ML |
2161 | void intel_panel_update_backlight(struct intel_encoder *encoder, |
2162 | const struct intel_crtc_state *crtc_state, | |
2163 | const struct drm_connector_state *conn_state); | |
b037d58f | 2164 | void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state); |
abf1aae8 VS |
2165 | struct drm_display_mode * |
2166 | intel_panel_edid_downclock_mode(struct intel_connector *connector, | |
2167 | const struct drm_display_mode *fixed_mode); | |
0dc927eb VS |
2168 | struct drm_display_mode * |
2169 | intel_panel_edid_fixed_mode(struct intel_connector *connector); | |
325710d3 VS |
2170 | struct drm_display_mode * |
2171 | intel_panel_vbt_fixed_mode(struct intel_connector *connector); | |
e63d87c0 CW |
2172 | |
2173 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) | |
1ebaa0b9 | 2174 | int intel_backlight_device_register(struct intel_connector *connector); |
e63d87c0 CW |
2175 | void intel_backlight_device_unregister(struct intel_connector *connector); |
2176 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
2de2d0b0 | 2177 | static inline int intel_backlight_device_register(struct intel_connector *connector) |
1ebaa0b9 CW |
2178 | { |
2179 | return 0; | |
2180 | } | |
e63d87c0 CW |
2181 | static inline void intel_backlight_device_unregister(struct intel_connector *connector) |
2182 | { | |
2183 | } | |
2184 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
0962c3c9 | 2185 | |
ee5e5e7a SP |
2186 | /* intel_hdcp.c */ |
2187 | void intel_hdcp_atomic_check(struct drm_connector *connector, | |
2188 | struct drm_connector_state *old_state, | |
2189 | struct drm_connector_state *new_state); | |
2190 | int intel_hdcp_init(struct intel_connector *connector, | |
2191 | const struct intel_hdcp_shim *hdcp_shim); | |
2192 | int intel_hdcp_enable(struct intel_connector *connector); | |
2193 | int intel_hdcp_disable(struct intel_connector *connector); | |
fdddd08c | 2194 | bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); |
bdc93fe0 | 2195 | bool intel_hdcp_capable(struct intel_connector *connector); |
9055aac7 R |
2196 | void intel_hdcp_component_init(struct drm_i915_private *dev_priv); |
2197 | void intel_hdcp_component_fini(struct drm_i915_private *dev_priv); | |
2198 | void intel_hdcp_cleanup(struct intel_connector *connector); | |
09d56393 | 2199 | void intel_hdcp_handle_cp_irq(struct intel_connector *connector); |
5f1aae65 | 2200 | |
0bc12bcb | 2201 | /* intel_psr.c */ |
4371d896 | 2202 | #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) |
77fe36ff | 2203 | void intel_psr_init_dpcd(struct intel_dp *intel_dp); |
d2419ffc VS |
2204 | void intel_psr_enable(struct intel_dp *intel_dp, |
2205 | const struct intel_crtc_state *crtc_state); | |
2206 | void intel_psr_disable(struct intel_dp *intel_dp, | |
2207 | const struct intel_crtc_state *old_crtc_state); | |
23ec9f52 JRS |
2208 | void intel_psr_update(struct intel_dp *intel_dp, |
2209 | const struct intel_crtc_state *crtc_state); | |
2210 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value); | |
5748b6a1 | 2211 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc RV |
2212 | unsigned frontbuffer_bits, |
2213 | enum fb_op_origin origin); | |
5748b6a1 | 2214 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 RV |
2215 | unsigned frontbuffer_bits, |
2216 | enum fb_op_origin origin); | |
c39055b0 | 2217 | void intel_psr_init(struct drm_i915_private *dev_priv); |
4d90f2d5 VS |
2218 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
2219 | struct intel_crtc_state *crtc_state); | |
1aeb1b5f | 2220 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug); |
54fd3149 | 2221 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); |
cc3054ff | 2222 | void intel_psr_short_pulse(struct intel_dp *intel_dp); |
63ec132d DP |
2223 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
2224 | u32 *out_value); | |
2f8e7ea9 | 2225 | bool intel_psr_enabled(struct intel_dp *intel_dp); |
0bc12bcb | 2226 | |
593a21a0 | 2227 | /* intel_quirks.c */ |
27a981b6 | 2228 | void intel_init_quirks(struct drm_i915_private *dev_priv); |
593a21a0 | 2229 | |
9c065a7d | 2230 | /* intel_runtime_pm.c */ |
bd780f37 | 2231 | void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv); |
9c065a7d | 2232 | int intel_power_domains_init(struct drm_i915_private *); |
f28ec6f4 | 2233 | void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); |
73dfc227 | 2234 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
48a287ed | 2235 | void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv); |
3e68928b AM |
2236 | void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
2237 | void icl_display_core_uninit(struct drm_i915_private *dev_priv); | |
2cd9a689 ID |
2238 | void intel_power_domains_enable(struct drm_i915_private *dev_priv); |
2239 | void intel_power_domains_disable(struct drm_i915_private *dev_priv); | |
2240 | ||
2241 | enum i915_drm_suspend_mode { | |
2242 | I915_DRM_SUSPEND_IDLE, | |
2243 | I915_DRM_SUSPEND_MEM, | |
2244 | I915_DRM_SUSPEND_HIBERNATE, | |
2245 | }; | |
2246 | ||
2247 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv, | |
2248 | enum i915_drm_suspend_mode); | |
2249 | void intel_power_domains_resume(struct drm_i915_private *dev_priv); | |
d7d7c9ee ID |
2250 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
2251 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); | |
f458ebbc | 2252 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
07d80572 | 2253 | void intel_runtime_pm_disable(struct drm_i915_private *dev_priv); |
bd780f37 | 2254 | void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv); |
9895ad03 DS |
2255 | const char * |
2256 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 2257 | |
f458ebbc SV |
2258 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
2259 | enum intel_display_power_domain domain); | |
2260 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
2261 | enum intel_display_power_domain domain); | |
0e6e0be4 | 2262 | intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, |
09731280 | 2263 | enum intel_display_power_domain domain); |
0e6e0be4 CW |
2264 | intel_wakeref_t |
2265 | intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, | |
2266 | enum intel_display_power_domain domain); | |
2267 | void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, | |
2268 | enum intel_display_power_domain domain); | |
2269 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) | |
9c065a7d | 2270 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
0e6e0be4 CW |
2271 | enum intel_display_power_domain domain, |
2272 | intel_wakeref_t wakeref); | |
2273 | #else | |
2274 | #define intel_display_power_put(i915, domain, wakeref) \ | |
2275 | intel_display_power_put_unchecked(i915, domain) | |
2276 | #endif | |
aa9664ff MK |
2277 | void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, |
2278 | u8 req_slices); | |
da5827c3 ID |
2279 | |
2280 | static inline void | |
eb17af67 | 2281 | assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm) |
da5827c3 | 2282 | { |
eb17af67 | 2283 | WARN_ONCE(rpm->suspended, |
da5827c3 ID |
2284 | "Device suspended during HW access\n"); |
2285 | } | |
2286 | ||
2287 | static inline void | |
eb17af67 | 2288 | __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm) |
da5827c3 | 2289 | { |
eb17af67 DCS |
2290 | assert_rpm_device_not_suspended(rpm); |
2291 | WARN_ONCE(!atomic_read(&rpm->wakeref_count), | |
1f58c8e7 | 2292 | "RPM wakelock ref not held during HW access"); |
da5827c3 ID |
2293 | } |
2294 | ||
eb17af67 DCS |
2295 | static inline void |
2296 | assert_rpm_wakelock_held(struct drm_i915_private *i915) | |
2297 | { | |
2298 | __assert_rpm_wakelock_held(&i915->runtime_pm); | |
2299 | } | |
2300 | ||
1f814dac ID |
2301 | /** |
2302 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
bd780f37 | 2303 | * @i915: i915 device instance |
1f814dac ID |
2304 | * |
2305 | * This function disable asserts that check if we hold an RPM wakelock | |
2306 | * reference, while keeping the device-not-suspended checks still enabled. | |
2307 | * It's meant to be used only in special circumstances where our rule about | |
2308 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
2309 | * to this rule at any point where we access the HW or want to keep the HW in | |
2310 | * an active state we must hold an RPM wakelock reference acquired via one of | |
2311 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
2312 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
2313 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
2314 | * users should avoid using this function. | |
2315 | * | |
2316 | * Any calls to this function must have a symmetric call to | |
2317 | * enable_rpm_wakeref_asserts(). | |
2318 | */ | |
2319 | static inline void | |
bd780f37 | 2320 | disable_rpm_wakeref_asserts(struct drm_i915_private *i915) |
1f814dac | 2321 | { |
bd780f37 | 2322 | atomic_inc(&i915->runtime_pm.wakeref_count); |
1f814dac ID |
2323 | } |
2324 | ||
2325 | /** | |
2326 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
bd780f37 | 2327 | * @i915: i915 device instance |
1f814dac ID |
2328 | * |
2329 | * This function re-enables the RPM assert checks after disabling them with | |
2330 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
2331 | * circumstances otherwise its use should be avoided. | |
2332 | * | |
2333 | * Any calls to this function must have a symmetric call to | |
2334 | * disable_rpm_wakeref_asserts(). | |
2335 | */ | |
2336 | static inline void | |
bd780f37 | 2337 | enable_rpm_wakeref_asserts(struct drm_i915_private *i915) |
1f814dac | 2338 | { |
bd780f37 | 2339 | atomic_dec(&i915->runtime_pm.wakeref_count); |
1f814dac ID |
2340 | } |
2341 | ||
16e4dd03 CW |
2342 | intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915); |
2343 | intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915); | |
2344 | intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915); | |
2345 | ||
d4225a53 CW |
2346 | #define with_intel_runtime_pm(i915, wf) \ |
2347 | for ((wf) = intel_runtime_pm_get(i915); (wf); \ | |
2348 | intel_runtime_pm_put((i915), (wf)), (wf) = 0) | |
2349 | ||
2350 | #define with_intel_runtime_pm_if_in_use(i915, wf) \ | |
2351 | for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \ | |
2352 | intel_runtime_pm_put((i915), (wf)), (wf) = 0) | |
2353 | ||
16e4dd03 CW |
2354 | void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915); |
2355 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) | |
2356 | void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref); | |
2357 | #else | |
2358 | #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915) | |
2359 | #endif | |
bd780f37 CW |
2360 | |
2361 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) | |
2362 | void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915, | |
2363 | struct drm_printer *p); | |
2364 | #else | |
2365 | static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915, | |
2366 | struct drm_printer *p) | |
2367 | { | |
2368 | } | |
2369 | #endif | |
9c065a7d | 2370 | |
e0fce78f VS |
2371 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
2372 | bool override, unsigned int mask); | |
b0b33846 VS |
2373 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
2374 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
2375 | |
2376 | ||
5f1aae65 | 2377 | /* intel_pm.c */ |
46f16e63 | 2378 | void intel_init_clock_gating(struct drm_i915_private *dev_priv); |
712bf364 | 2379 | void intel_suspend_hw(struct drm_i915_private *dev_priv); |
5db94019 | 2380 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv); |
432081bc | 2381 | void intel_update_watermarks(struct intel_crtc *crtc); |
62d75df7 | 2382 | void intel_init_pm(struct drm_i915_private *dev_priv); |
bb400da9 | 2383 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
192aa181 | 2384 | void intel_pm_setup(struct drm_i915_private *dev_priv); |
87440425 PZ |
2385 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
2386 | void intel_gpu_ips_teardown(void); | |
dc97997a | 2387 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f CW |
2388 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); |
2389 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); | |
dc97997a CW |
2390 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); |
2391 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); | |
43cf3bf0 CW |
2392 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
2393 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 2394 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
62eb3c24 | 2395 | void gen6_rps_boost(struct i915_request *rq); |
cd1d3ee9 MR |
2396 | void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); |
2397 | void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
2398 | void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
2399 | void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
ff43bc37 VS |
2400 | void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, |
2401 | struct skl_ddb_entry *ddb_y, | |
2402 | struct skl_ddb_entry *ddb_uv); | |
08db6652 DL |
2403 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2404 | struct skl_ddb_allocation *ddb /* out */); | |
cd1d3ee9 | 2405 | void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, |
bf9d99ad | 2406 | struct skl_pipe_wm *out); |
04548cba | 2407 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv); |
602ae835 | 2408 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv); |
16dcdc4e PZ |
2409 | bool intel_can_enable_sagv(struct drm_atomic_state *state); |
2410 | int intel_enable_sagv(struct drm_i915_private *dev_priv); | |
2411 | int intel_disable_sagv(struct drm_i915_private *dev_priv); | |
45ece230 | 2412 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
2413 | const struct skl_wm_level *l2); | |
53cc6880 VS |
2414 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, |
2415 | const struct skl_ddb_entry entries[], | |
2416 | int num_entries, int ignore_idx); | |
ff43bc37 VS |
2417 | void skl_write_plane_wm(struct intel_plane *plane, |
2418 | const struct intel_crtc_state *crtc_state); | |
2419 | void skl_write_cursor_wm(struct intel_plane *plane, | |
2420 | const struct intel_crtc_state *crtc_state); | |
ed4a6a7c | 2421 | bool ilk_disable_lp_wm(struct drm_device *dev); |
73b0ca8e MK |
2422 | int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, |
2423 | struct intel_crtc_state *cstate); | |
2503a0fe KM |
2424 | void intel_init_ipc(struct drm_i915_private *dev_priv); |
2425 | void intel_enable_ipc(struct drm_i915_private *dev_priv); | |
72662e10 | 2426 | |
5f1aae65 | 2427 | /* intel_sdvo.c */ |
76203467 VS |
2428 | bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, |
2429 | i915_reg_t sdvo_reg, enum pipe *pipe); | |
c39055b0 | 2430 | bool intel_sdvo_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2431 | i915_reg_t reg, enum port port); |
96a02917 | 2432 | |
2b28bb1b | 2433 | |
5f1aae65 | 2434 | /* intel_sprite.c */ |
df7d4156 | 2435 | bool is_planar_yuv_format(u32 pixelformat); |
dfd2e9ab VS |
2436 | int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
2437 | int usecs); | |
580503c7 | 2438 | struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, |
b079bd17 | 2439 | enum pipe pipe, int plane); |
6a20fe7b VS |
2440 | int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, |
2441 | struct drm_file *file_priv); | |
d3a8fb32 VS |
2442 | void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state); |
2443 | void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state); | |
fc3fed5d | 2444 | int intel_plane_check_stride(const struct intel_plane_state *plane_state); |
4e0b83a5 | 2445 | int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); |
25721f82 | 2446 | int chv_plane_check_rotation(const struct intel_plane_state *plane_state); |
b7c80600 VS |
2447 | struct intel_plane * |
2448 | skl_universal_plane_create(struct drm_i915_private *dev_priv, | |
2449 | enum pipe pipe, enum plane_id plane_id); | |
5f1aae65 | 2450 | |
1ab554b0 ML |
2451 | static inline bool icl_is_nv12_y_plane(enum plane_id id) |
2452 | { | |
2453 | /* Don't need to do a gen check, these planes are only available on gen11 */ | |
2454 | if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5) | |
2455 | return true; | |
2456 | ||
2457 | return false; | |
2458 | } | |
2459 | ||
42fd20ed KS |
2460 | static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, |
2461 | enum plane_id plane_id) | |
b1554e23 | 2462 | { |
42fd20ed | 2463 | if (INTEL_GEN(dev_priv) < 11) |
b1554e23 ML |
2464 | return false; |
2465 | ||
42fd20ed | 2466 | return plane_id < PLANE_SPRITE2; |
b1554e23 ML |
2467 | } |
2468 | ||
5f1aae65 | 2469 | /* intel_tv.c */ |
c39055b0 | 2470 | void intel_tv_init(struct drm_i915_private *dev_priv); |
20ddf665 | 2471 | |
ea2c67bb | 2472 | /* intel_atomic.c */ |
11c1a9ec ML |
2473 | int intel_digital_connector_atomic_get_property(struct drm_connector *connector, |
2474 | const struct drm_connector_state *state, | |
2475 | struct drm_property *property, | |
d25236a3 | 2476 | u64 *val); |
11c1a9ec ML |
2477 | int intel_digital_connector_atomic_set_property(struct drm_connector *connector, |
2478 | struct drm_connector_state *state, | |
2479 | struct drm_property *property, | |
d25236a3 | 2480 | u64 val); |
11c1a9ec ML |
2481 | int intel_digital_connector_atomic_check(struct drm_connector *conn, |
2482 | struct drm_connector_state *new_state); | |
2483 | struct drm_connector_state * | |
2484 | intel_digital_connector_duplicate_state(struct drm_connector *connector); | |
2485 | ||
1356837e MR |
2486 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
2487 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
2488 | struct drm_crtc_state *state); | |
de419ab6 ML |
2489 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
2490 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
de419ab6 | 2491 | |
10f81c19 ACO |
2492 | static inline struct intel_crtc_state * |
2493 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
2494 | struct intel_crtc *crtc) | |
2495 | { | |
2496 | struct drm_crtc_state *crtc_state; | |
2497 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
2498 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 2499 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
2500 | |
2501 | return to_intel_crtc_state(crtc_state); | |
2502 | } | |
e3bddded | 2503 | |
6ebc6923 ACO |
2504 | int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, |
2505 | struct intel_crtc *intel_crtc, | |
2506 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
2507 | |
2508 | /* intel_atomic_plane.c */ | |
c48b86f9 VS |
2509 | void intel_update_plane(struct intel_plane *plane, |
2510 | const struct intel_crtc_state *crtc_state, | |
2511 | const struct intel_plane_state *plane_state); | |
2512 | void intel_update_slave(struct intel_plane *plane, | |
2513 | const struct intel_crtc_state *crtc_state, | |
2514 | const struct intel_plane_state *plane_state); | |
2515 | void intel_disable_plane(struct intel_plane *plane, | |
2516 | const struct intel_crtc_state *crtc_state); | |
87b94026 ML |
2517 | struct intel_plane *intel_plane_alloc(void); |
2518 | void intel_plane_free(struct intel_plane *plane); | |
ea2c67bb MR |
2519 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
2520 | void intel_plane_destroy_state(struct drm_plane *plane, | |
2521 | struct drm_plane_state *state); | |
2522 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
5f2e5112 VS |
2523 | void skl_update_planes_on_crtc(struct intel_atomic_state *state, |
2524 | struct intel_crtc *crtc); | |
2525 | void i9xx_update_planes_on_crtc(struct intel_atomic_state *state, | |
2526 | struct intel_crtc *crtc); | |
b2b55502 VS |
2527 | int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, |
2528 | struct intel_crtc_state *crtc_state, | |
2529 | const struct intel_plane_state *old_plane_state, | |
f79f2692 | 2530 | struct intel_plane_state *intel_state); |
ea2c67bb | 2531 | |
8563b1e8 | 2532 | /* intel_color.c */ |
302da0cd MR |
2533 | void intel_color_init(struct intel_crtc *crtc); |
2534 | int intel_color_check(struct intel_crtc_state *crtc_state); | |
4d8ed54c | 2535 | void intel_color_commit(const struct intel_crtc_state *crtc_state); |
23b03a27 | 2536 | void intel_color_load_luts(const struct intel_crtc_state *crtc_state); |
8563b1e8 | 2537 | |
dbe9e61b SS |
2538 | /* intel_lspcon.c */ |
2539 | bool lspcon_init(struct intel_digital_port *intel_dig_port); | |
910530c0 | 2540 | void lspcon_resume(struct intel_lspcon *lspcon); |
357c0ae9 | 2541 | void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); |
7cbf19fd SS |
2542 | void lspcon_write_infoframe(struct intel_encoder *encoder, |
2543 | const struct intel_crtc_state *crtc_state, | |
2544 | unsigned int type, | |
2545 | const void *buf, ssize_t len); | |
f2a10d61 VS |
2546 | void lspcon_read_infoframe(struct intel_encoder *encoder, |
2547 | const struct intel_crtc_state *crtc_state, | |
2548 | unsigned int type, | |
2549 | void *frame, ssize_t len); | |
06c812d7 SS |
2550 | void lspcon_set_infoframes(struct intel_encoder *encoder, |
2551 | bool enable, | |
2552 | const struct intel_crtc_state *crtc_state, | |
2553 | const struct drm_connector_state *conn_state); | |
509efa2b | 2554 | u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, |
06c812d7 | 2555 | const struct intel_crtc_state *pipe_config); |
668b6c17 SS |
2556 | void lspcon_ycbcr420_config(struct drm_connector *connector, |
2557 | struct intel_crtc_state *crtc_state); | |
731035fe TV |
2558 | |
2559 | /* intel_pipe_crc.c */ | |
8c6b709d | 2560 | #ifdef CONFIG_DEBUG_FS |
c0811a7d | 2561 | int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name); |
a8c20833 MK |
2562 | int intel_crtc_verify_crc_source(struct drm_crtc *crtc, |
2563 | const char *source_name, size_t *values_cnt); | |
260bc551 MK |
2564 | const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, |
2565 | size_t *count); | |
033b7a23 ML |
2566 | void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc); |
2567 | void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc); | |
8c6b709d TV |
2568 | #else |
2569 | #define intel_crtc_set_crc_source NULL | |
a8c20833 | 2570 | #define intel_crtc_verify_crc_source NULL |
260bc551 | 2571 | #define intel_crtc_get_crc_sources NULL |
033b7a23 ML |
2572 | static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) |
2573 | { | |
2574 | } | |
2575 | ||
2576 | static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) | |
2577 | { | |
2578 | } | |
8c6b709d | 2579 | #endif |
79e53945 | 2580 | #endif /* __INTEL_DRV_H__ */ |