[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / intel_dsi.h

/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef _INTEL_DSI_H
#define _INTEL_DSI_H

#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include "intel_drv.h"

/* Dual Link support */
#define DSI_DUAL_LINK_NONE		0
#define DSI_DUAL_LINK_FRONT_BACK	1
#define DSI_DUAL_LINK_PIXEL_ALT		2

struct intel_dsi_host;

struct intel_dsi {
	struct intel_encoder base;

	struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
	intel_wakeref_t io_wakeref[I915_MAX_PORTS];

	/* GPIO Desc for CRC based Panel control */
	struct gpio_desc *gpio_panel;

	struct intel_connector *attached_connector;

	/* bit mask of ports being driven */
	u16 ports;

	/* if true, use HS mode, otherwise LP */
	bool hs;

	/* virtual channel */
	int channel;

	/* Video mode or command mode */
	u16 operation_mode;

	/* number of DSI lanes */
	unsigned int lane_count;

	/*
	 * video mode pixel format
	 *
	 * XXX: consolidate on .format in struct mipi_dsi_device.
	 */
	enum mipi_dsi_pixel_format pixel_format;

	/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
	u32 video_mode_format;

	/* eot for MIPI_EOT_DISABLE register */
	u8 eotp_pkt;
	u8 clock_stop;

	u8 escape_clk_div;
	u8 dual_link;

	u16 dcs_backlight_ports;
	u16 dcs_cabc_ports;

	/* RGB or BGR */
	bool bgr_enabled;

	u8 pixel_overlap;
	u32 port_bits;
	u32 bw_timer;
	u32 dphy_reg;

	/* data lanes dphy timing */
	u32 dphy_data_lane_reg;
	u32 video_frmt_cfg_bits;
	u16 lp_byte_clk;

	/* timeouts in byte clocks */
	u16 hs_tx_timeout;
	u16 lp_rx_timeout;
	u16 turn_arnd_val;
	u16 rst_timer_val;
	u16 hs_to_lp_count;
	u16 clk_lp_to_hs_count;
	u16 clk_hs_to_lp_count;

	u16 init_count;
	u32 pclk;
	u16 burst_mode_ratio;

	/* all delays in ms */
	u16 backlight_off_delay;
	u16 backlight_on_delay;
	u16 panel_on_delay;
	u16 panel_off_delay;
	u16 panel_pwr_cycle_delay;
};

struct intel_dsi_host {
	struct mipi_dsi_host base;
	struct intel_dsi *intel_dsi;
	enum port port;

	/* our little hack */
	struct mipi_dsi_device *device;
};

static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
{
	return container_of(h, struct intel_dsi_host, base);
}

#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)

static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dsi, base.base);
}

static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
{
	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
}

static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
{
	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
}

static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
{
	return enc_to_intel_dsi(&encoder->base)->ports;
}

/* intel_dsi.c */
int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
enum drm_panel_orientation
intel_dsi_get_panel_orientation(struct intel_connector *connector);

/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
int intel_dsi_get_modes(struct drm_connector *connector);
enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
					  struct drm_display_mode *mode);
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
					   const struct mipi_dsi_host_ops *funcs,
					   enum port port);

/* vlv_dsi_pll.c */
int vlv_dsi_pll_compute(struct intel_encoder *encoder,
			struct intel_crtc_state *config);
void vlv_dsi_pll_enable(struct intel_encoder *encoder,
			const struct intel_crtc_state *config);
void vlv_dsi_pll_disable(struct intel_encoder *encoder);
u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
		     struct intel_crtc_state *config);
void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);

bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
int bxt_dsi_pll_compute(struct intel_encoder *encoder,
			struct intel_crtc_state *config);
void bxt_dsi_pll_enable(struct intel_encoder *encoder,
			const struct intel_crtc_state *config);
void bxt_dsi_pll_disable(struct intel_encoder *encoder);
u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
		     struct intel_crtc_state *config);
void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);

/* intel_dsi_vbt.c */
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
				 enum mipi_seq seq_id);
void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);

#endif /* _INTEL_DSI_H */
Commit	Line	Data
f5e11b06 JN	1	/*
	2	* Copyright © 2013 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#ifndef _INTEL_DSI_H
	25	#define _INTEL_DSI_H
	26
f5e11b06	27	#include <drm/drm_crtc.h>
7e9804fd	28	#include <drm/drm_mipi_dsi.h>
f5e11b06 JN	29	#include "intel_drv.h"
f5e11b06 JN	30
a9da9bce GS	31	/* Dual Link support */
	32	#define DSI_DUAL_LINK_NONE 0
	33	#define DSI_DUAL_LINK_FRONT_BACK 1
	34	#define DSI_DUAL_LINK_PIXEL_ALT 2
	35
7e9804fd JN	36	struct intel_dsi_host;
7e9804fd JN	37
f5e11b06 JN	38	struct intel_dsi {
	39	struct intel_encoder base;
	40
7e9804fd	41	struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
0e6e0be4	42	intel_wakeref_t io_wakeref[I915_MAX_PORTS];
f5e11b06	43
fc45e821 SK	44	/* GPIO Desc for CRC based Panel control */
	45	struct gpio_desc *gpio_panel;
	46
f5e11b06 JN	47	struct intel_connector *attached_connector;
f5e11b06 JN	48
17af40a8 JN	49	/* bit mask of ports being driven */
	50	u16 ports;
	51
f5e11b06 JN	52	/* if true, use HS mode, otherwise LP */
	53	bool hs;
	54
	55	/* virtual channel */
	56	int channel;
	57
dfba2e2d SK	58	/* Video mode or command mode */
	59	u16 operation_mode;
	60
f5e11b06 JN	61	/* number of DSI lanes */
	62	unsigned int lane_count;
	63
1e78aa01 JN	64	/*
	65	* video mode pixel format
	66	*
	67	* XXX: consolidate on .format in struct mipi_dsi_device.
	68	*/
	69	enum mipi_dsi_pixel_format pixel_format;
f5e11b06 JN	70
	71	/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
	72	u32 video_mode_format;
	73
	74	/* eot for MIPI_EOT_DISABLE register */
f1c79f16 SK	75	u8 eotp_pkt;
f1c79f16 SK	76	u8 clock_stop;
f6da2842	77
f1c79f16	78	u8 escape_clk_div;
369602d3	79	u8 dual_link;
90198355 JN	80
90198355 JN	81	u16 dcs_backlight_ports;
1ecc1c6c	82	u16 dcs_cabc_ports;
90198355	83
d364dc66 MC	84	/* RGB or BGR */
	85	bool bgr_enabled;
	86
a9da9bce	87	u8 pixel_overlap;
f6da2842 SK	88	u32 port_bits;
	89	u32 bw_timer;
	90	u32 dphy_reg;
e72cce53 MC	91
	92	/* data lanes dphy timing */
	93	u32 dphy_data_lane_reg;
f6da2842 SK	94	u32 video_frmt_cfg_bits;
	95	u16 lp_byte_clk;
	96
	97	/* timeouts in byte clocks */
5a4712f4	98	u16 hs_tx_timeout;
f6da2842 SK	99	u16 lp_rx_timeout;
	100	u16 turn_arnd_val;
	101	u16 rst_timer_val;
	102	u16 hs_to_lp_count;
	103	u16 clk_lp_to_hs_count;
	104	u16 clk_hs_to_lp_count;
cf4dbd2e SK	105
cf4dbd2e SK	106	u16 init_count;
7f0c8605 SK	107	u32 pclk;
7f0c8605 SK	108	u16 burst_mode_ratio;
df38e655 SK	109
	110	/* all delays in ms */
	111	u16 backlight_off_delay;
	112	u16 backlight_on_delay;
	113	u16 panel_on_delay;
	114	u16 panel_off_delay;
	115	u16 panel_pwr_cycle_delay;
f5e11b06 JN	116	};
f5e11b06 JN	117
7e9804fd JN	118	struct intel_dsi_host {
	119	struct mipi_dsi_host base;
	120	struct intel_dsi *intel_dsi;
	121	enum port port;
	122
	123	/* our little hack */
	124	struct mipi_dsi_device *device;
	125	};
	126
	127	static inline struct intel_dsi_host to_intel_dsi_host(struct mipi_dsi_host h)
	128	{
	129	return container_of(h, struct intel_dsi_host, base);
	130	}
	131
c3aeadc8	132	#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
e7d7cad0	133
f5e11b06 JN	134	static inline struct intel_dsi enc_to_intel_dsi(struct drm_encoder encoder)
	135	{
	136	return container_of(encoder, struct intel_dsi, base.base);
	137	}
	138
b687c198 MC	139	static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
	140	{
	141	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
	142	}
	143
	144	static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
	145	{
	146	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
	147	}
	148
1dd07e56 ID	149	static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
	150	{
	151	return enc_to_intel_dsi(&encoder->base)->ports;
	152	}
	153
2bf3f59d JN	154	/* intel_dsi.c */
2bf3f59d JN	155	int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
9ec9a87b	156	int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
c1cd5b24 VS	157	enum drm_panel_orientation
c1cd5b24 VS	158	intel_dsi_get_panel_orientation(struct intel_connector *connector);
2bf3f59d	159
ca3589c1	160	/* vlv_dsi.c */
e518634b	161	void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
7fba8306	162	enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
0d90c61a MC	163	int intel_dsi_get_modes(struct drm_connector *connector);
	164	enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
	165	struct drm_display_mode *mode);
8e54d4fe MC	166	struct intel_dsi_host intel_dsi_host_init(struct intel_dsi intel_dsi,
	167	const struct mipi_dsi_host_ops *funcs,
	168	enum port port);
3870b89a	169
ca3589c1	170	/* vlv_dsi_pll.c */
e518634b JN	171	int vlv_dsi_pll_compute(struct intel_encoder *encoder,
	172	struct intel_crtc_state *config);
	173	void vlv_dsi_pll_enable(struct intel_encoder *encoder,
	174	const struct intel_crtc_state *config);
	175	void vlv_dsi_pll_disable(struct intel_encoder *encoder);
ca0b04db	176	u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
e518634b JN	177	struct intel_crtc_state *config);
	178	void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
	179
	180	bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
	181	int bxt_dsi_pll_compute(struct intel_encoder *encoder,
	182	struct intel_crtc_state *config);
	183	void bxt_dsi_pll_enable(struct intel_encoder *encoder,
	184	const struct intel_crtc_state *config);
	185	void bxt_dsi_pll_disable(struct intel_encoder *encoder);
ca0b04db	186	u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
e518634b JN	187	struct intel_crtc_state *config);
e518634b JN	188	void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
be4fc046	189
7fba8306	190	/* intel_dsi_vbt.c */
3f751d65 JN	191	bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
3f751d65 JN	192	int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
b0dd6887 JN	193	void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
b0dd6887 JN	194	enum mipi_seq seq_id);
b687c198	195	void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
2ab8b458	196
f5e11b06	197	#endif /* _INTEL_DSI_H */