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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
f899fc64 | 3 | * Copyright © 2006-2008,2010 Intel Corporation |
79e53945 JB |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
f899fc64 | 27 | * Chris Wilson <chris@chris-wilson.co.uk> |
79e53945 JB |
28 | */ |
29 | #include <linux/i2c.h> | |
79e53945 | 30 | #include <linux/i2c-algo-bit.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
07e17a75 | 32 | #include <drm/drm_hdcp.h> |
79e53945 | 33 | #include "intel_drv.h" |
760285e7 | 34 | #include <drm/i915_drm.h> |
79e53945 JB |
35 | #include "i915_drv.h" |
36 | ||
5ea6e5e3 | 37 | struct gmbus_pin { |
2ed06c93 | 38 | const char *name; |
dce88879 | 39 | enum i915_gpio gpio; |
2ed06c93 DK |
40 | }; |
41 | ||
5ea6e5e3 JN |
42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { | |
44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, | |
45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, | |
47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
2ed06c93 DK |
50 | }; |
51 | ||
c1bad5b6 JN |
52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
57 | }; | |
58 | ||
6364e67e JN |
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
63 | }; | |
64 | ||
4c272834 | 65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
b2e8c6cd VS |
66 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, |
67 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
68 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
4c272834 JN |
69 | }; |
70 | ||
3d02352c RV |
71 | static const struct gmbus_pin gmbus_pins_cnp[] = { |
72 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, | |
73 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
74 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
75 | [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, | |
76 | }; | |
77 | ||
5c749c52 | 78 | static const struct gmbus_pin gmbus_pins_icp[] = { |
af1f1b81 MK |
79 | [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, |
80 | [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, | |
81 | [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, | |
82 | [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, | |
83 | [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, | |
84 | [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, | |
5c749c52 AS |
85 | }; |
86 | ||
4c272834 JN |
87 | /* pin is expected to be valid */ |
88 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, | |
89 | unsigned int pin) | |
90 | { | |
5c749c52 AS |
91 | if (HAS_PCH_ICP(dev_priv)) |
92 | return &gmbus_pins_icp[pin]; | |
93 | else if (HAS_PCH_CNP(dev_priv)) | |
3d02352c RV |
94 | return &gmbus_pins_cnp[pin]; |
95 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 96 | return &gmbus_pins_bxt[pin]; |
b976dc53 | 97 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 98 | return &gmbus_pins_skl[pin]; |
c1bad5b6 JN |
99 | else if (IS_BROADWELL(dev_priv)) |
100 | return &gmbus_pins_bdw[pin]; | |
4c272834 JN |
101 | else |
102 | return &gmbus_pins[pin]; | |
103 | } | |
104 | ||
88ac7939 JN |
105 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
106 | unsigned int pin) | |
107 | { | |
4c272834 JN |
108 | unsigned int size; |
109 | ||
5c749c52 AS |
110 | if (HAS_PCH_ICP(dev_priv)) |
111 | size = ARRAY_SIZE(gmbus_pins_icp); | |
112 | else if (HAS_PCH_CNP(dev_priv)) | |
3d02352c RV |
113 | size = ARRAY_SIZE(gmbus_pins_cnp); |
114 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 115 | size = ARRAY_SIZE(gmbus_pins_bxt); |
b976dc53 | 116 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 117 | size = ARRAY_SIZE(gmbus_pins_skl); |
c1bad5b6 JN |
118 | else if (IS_BROADWELL(dev_priv)) |
119 | size = ARRAY_SIZE(gmbus_pins_bdw); | |
4c272834 JN |
120 | else |
121 | size = ARRAY_SIZE(gmbus_pins); | |
122 | ||
dce88879 | 123 | return pin < size && get_gmbus_pin(dev_priv, pin)->name; |
88ac7939 JN |
124 | } |
125 | ||
f899fc64 CW |
126 | /* Intel GPIO access functions */ |
127 | ||
1849ecb2 | 128 | #define I2C_RISEFALL_TIME 10 |
f899fc64 | 129 | |
e957d772 CW |
130 | static inline struct intel_gmbus * |
131 | to_intel_gmbus(struct i2c_adapter *i2c) | |
132 | { | |
133 | return container_of(i2c, struct intel_gmbus, adapter); | |
134 | } | |
135 | ||
f899fc64 | 136 | void |
af6dc742 | 137 | intel_i2c_reset(struct drm_i915_private *dev_priv) |
0ba0e9e1 | 138 | { |
699fc401 VS |
139 | I915_WRITE(GMBUS0, 0); |
140 | I915_WRITE(GMBUS4, 0); | |
f899fc64 CW |
141 | } |
142 | ||
ad8059cf VS |
143 | static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, |
144 | bool enable) | |
f899fc64 | 145 | { |
b222f267 | 146 | u32 val; |
0ba0e9e1 SL |
147 | |
148 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | |
b222f267 | 149 | val = I915_READ(DSPCLK_GATE_D); |
ad8059cf VS |
150 | if (!enable) |
151 | val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
0ba0e9e1 | 152 | else |
ad8059cf | 153 | val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; |
b222f267 | 154 | I915_WRITE(DSPCLK_GATE_D, val); |
0ba0e9e1 SL |
155 | } |
156 | ||
6481d5ed VS |
157 | static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, |
158 | bool enable) | |
159 | { | |
160 | u32 val; | |
161 | ||
162 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
163 | if (!enable) | |
164 | val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
165 | else | |
166 | val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
167 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
168 | } | |
169 | ||
170 | static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, | |
171 | bool enable) | |
172 | { | |
173 | u32 val; | |
174 | ||
175 | val = I915_READ(GEN9_CLKGATE_DIS_4); | |
176 | if (!enable) | |
177 | val |= BXT_GMBUS_GATING_DIS; | |
178 | else | |
179 | val &= ~BXT_GMBUS_GATING_DIS; | |
180 | I915_WRITE(GEN9_CLKGATE_DIS_4, val); | |
181 | } | |
182 | ||
36c785f0 | 183 | static u32 get_reserved(struct intel_gmbus *bus) |
e957d772 | 184 | { |
36c785f0 | 185 | struct drm_i915_private *dev_priv = bus->dev_priv; |
e957d772 CW |
186 | u32 reserved = 0; |
187 | ||
188 | /* On most chips, these bits must be preserved in software. */ | |
2a307c2e | 189 | if (!IS_I830(dev_priv) && !IS_I845G(dev_priv)) |
36c785f0 | 190 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
db5e4172 YL |
191 | (GPIO_DATA_PULLUP_DISABLE | |
192 | GPIO_CLOCK_PULLUP_DISABLE); | |
e957d772 CW |
193 | |
194 | return reserved; | |
195 | } | |
196 | ||
79e53945 JB |
197 | static int get_clock(void *data) |
198 | { | |
36c785f0 SV |
199 | struct intel_gmbus *bus = data; |
200 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
201 | u32 reserved = get_reserved(bus); | |
202 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); | |
203 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
204 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; | |
79e53945 JB |
205 | } |
206 | ||
207 | static int get_data(void *data) | |
208 | { | |
36c785f0 SV |
209 | struct intel_gmbus *bus = data; |
210 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
211 | u32 reserved = get_reserved(bus); | |
212 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); | |
213 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
214 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; | |
79e53945 JB |
215 | } |
216 | ||
217 | static void set_clock(void *data, int state_high) | |
218 | { | |
36c785f0 SV |
219 | struct intel_gmbus *bus = data; |
220 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
221 | u32 reserved = get_reserved(bus); | |
e957d772 | 222 | u32 clock_bits; |
79e53945 JB |
223 | |
224 | if (state_high) | |
225 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; | |
226 | else | |
227 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | | |
228 | GPIO_CLOCK_VAL_MASK; | |
f899fc64 | 229 | |
36c785f0 SV |
230 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
231 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
232 | } |
233 | ||
234 | static void set_data(void *data, int state_high) | |
235 | { | |
36c785f0 SV |
236 | struct intel_gmbus *bus = data; |
237 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
238 | u32 reserved = get_reserved(bus); | |
e957d772 | 239 | u32 data_bits; |
79e53945 JB |
240 | |
241 | if (state_high) | |
242 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; | |
243 | else | |
244 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | | |
245 | GPIO_DATA_VAL_MASK; | |
246 | ||
36c785f0 SV |
247 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
248 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
249 | } |
250 | ||
489fbc10 DK |
251 | static int |
252 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) | |
253 | { | |
254 | struct intel_gmbus *bus = container_of(adapter, | |
255 | struct intel_gmbus, | |
256 | adapter); | |
257 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
258 | ||
af6dc742 | 259 | intel_i2c_reset(dev_priv); |
ad8059cf VS |
260 | |
261 | if (IS_PINEVIEW(dev_priv)) | |
262 | pnv_gmbus_clock_gating(dev_priv, false); | |
263 | ||
489fbc10 DK |
264 | set_data(bus, 1); |
265 | set_clock(bus, 1); | |
266 | udelay(I2C_RISEFALL_TIME); | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static void | |
271 | intel_gpio_post_xfer(struct i2c_adapter *adapter) | |
272 | { | |
273 | struct intel_gmbus *bus = container_of(adapter, | |
274 | struct intel_gmbus, | |
275 | adapter); | |
276 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
277 | ||
278 | set_data(bus, 1); | |
279 | set_clock(bus, 1); | |
ad8059cf VS |
280 | |
281 | if (IS_PINEVIEW(dev_priv)) | |
282 | pnv_gmbus_clock_gating(dev_priv, true); | |
489fbc10 DK |
283 | } |
284 | ||
2ed06c93 | 285 | static void |
5ea6e5e3 | 286 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
f0217c42 | 287 | { |
36c785f0 | 288 | struct drm_i915_private *dev_priv = bus->dev_priv; |
36c785f0 | 289 | struct i2c_algo_bit_data *algo; |
f0217c42 | 290 | |
c167a6fc | 291 | algo = &bus->bit_algo; |
36c785f0 | 292 | |
dce88879 | 293 | bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); |
c167a6fc | 294 | bus->adapter.algo_data = algo; |
36c785f0 SV |
295 | algo->setsda = set_data; |
296 | algo->setscl = set_clock; | |
297 | algo->getsda = get_data; | |
298 | algo->getscl = get_clock; | |
489fbc10 DK |
299 | algo->pre_xfer = intel_gpio_pre_xfer; |
300 | algo->post_xfer = intel_gpio_post_xfer; | |
36c785f0 SV |
301 | algo->udelay = I2C_RISEFALL_TIME; |
302 | algo->timeout = usecs_to_jiffies(2200); | |
303 | algo->data = bus; | |
79e53945 JB |
304 | } |
305 | ||
4e6c2d58 | 306 | static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) |
61168c53 | 307 | { |
28c70f16 | 308 | DEFINE_WAIT(wait); |
4e6c2d58 CW |
309 | u32 gmbus2; |
310 | int ret; | |
c12aba5a | 311 | |
28c70f16 SV |
312 | /* Important: The hw handles only the first bit, so set only one! Since |
313 | * we also need to check for NAKs besides the hw ready/idle signal, we | |
4e6c2d58 CW |
314 | * need to wake up periodically and check that ourselves. |
315 | */ | |
316 | if (!HAS_GMBUS_IRQ(dev_priv)) | |
317 | irq_en = 0; | |
28c70f16 | 318 | |
4e6c2d58 CW |
319 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
320 | I915_WRITE_FW(GMBUS4, irq_en); | |
61168c53 | 321 | |
4e6c2d58 CW |
322 | status |= GMBUS_SATOER; |
323 | ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); | |
324 | if (ret) | |
325 | ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); | |
28c70f16 | 326 | |
4e6c2d58 CW |
327 | I915_WRITE_FW(GMBUS4, 0); |
328 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
61168c53 SV |
329 | |
330 | if (gmbus2 & GMBUS_SATOER) | |
331 | return -ENXIO; | |
4e6c2d58 CW |
332 | |
333 | return ret; | |
61168c53 SV |
334 | } |
335 | ||
2c438c02 SV |
336 | static int |
337 | gmbus_wait_idle(struct drm_i915_private *dev_priv) | |
338 | { | |
4e6c2d58 CW |
339 | DEFINE_WAIT(wait); |
340 | u32 irq_enable; | |
2c438c02 | 341 | int ret; |
2c438c02 | 342 | |
2c438c02 | 343 | /* Important: The hw handles only the first bit, so set only one! */ |
4e6c2d58 CW |
344 | irq_enable = 0; |
345 | if (HAS_GMBUS_IRQ(dev_priv)) | |
346 | irq_enable = GMBUS_IDLE_EN; | |
2c438c02 | 347 | |
4e6c2d58 CW |
348 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
349 | I915_WRITE_FW(GMBUS4, irq_enable); | |
2c438c02 | 350 | |
4e6c2d58 CW |
351 | ret = intel_wait_for_register_fw(dev_priv, |
352 | GMBUS2, GMBUS_ACTIVE, 0, | |
353 | 10); | |
2c438c02 | 354 | |
4e6c2d58 CW |
355 | I915_WRITE_FW(GMBUS4, 0); |
356 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
357 | ||
358 | return ret; | |
2c438c02 SV |
359 | } |
360 | ||
73675cf6 R |
361 | static inline |
362 | unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) | |
363 | { | |
364 | return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : | |
365 | GMBUS_BYTE_COUNT_MAX; | |
366 | } | |
367 | ||
924a93ed | 368 | static int |
9535c475 DT |
369 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
370 | unsigned short addr, u8 *buf, unsigned int len, | |
d5dc0f43 | 371 | u32 gmbus0_reg, u32 gmbus1_index) |
924a93ed | 372 | { |
d5dc0f43 R |
373 | unsigned int size = len; |
374 | bool burst_read = len > gmbus_max_xfer_size(dev_priv); | |
375 | bool extra_byte_added = false; | |
376 | ||
377 | if (burst_read) { | |
378 | /* | |
379 | * As per HW Spec, for 512Bytes need to read extra Byte and | |
380 | * Ignore the extra byte read. | |
381 | */ | |
382 | if (len == 512) { | |
383 | extra_byte_added = true; | |
384 | len++; | |
385 | } | |
386 | size = len % 256 + 256; | |
387 | I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); | |
388 | } | |
389 | ||
4e6c2d58 CW |
390 | I915_WRITE_FW(GMBUS1, |
391 | gmbus1_index | | |
392 | GMBUS_CYCLE_WAIT | | |
d5dc0f43 | 393 | (size << GMBUS_BYTE_COUNT_SHIFT) | |
4e6c2d58 CW |
394 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | |
395 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); | |
79985eee | 396 | while (len) { |
90e6b26d | 397 | int ret; |
924a93ed DK |
398 | u32 val, loop = 0; |
399 | ||
4e6c2d58 | 400 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 401 | if (ret) |
61168c53 | 402 | return ret; |
924a93ed | 403 | |
4e6c2d58 | 404 | val = I915_READ_FW(GMBUS3); |
924a93ed | 405 | do { |
d5dc0f43 R |
406 | if (extra_byte_added && len == 1) |
407 | break; | |
408 | ||
924a93ed DK |
409 | *buf++ = val & 0xff; |
410 | val >>= 8; | |
411 | } while (--len && ++loop < 4); | |
d5dc0f43 R |
412 | |
413 | if (burst_read && len == size - 4) | |
414 | /* Reset the override bit */ | |
415 | I915_WRITE_FW(GMBUS0, gmbus0_reg); | |
79985eee | 416 | } |
924a93ed DK |
417 | |
418 | return 0; | |
419 | } | |
420 | ||
d5dc0f43 R |
421 | /* |
422 | * HW spec says that 512Bytes in Burst read need special treatment. | |
423 | * But it doesn't talk about other multiple of 256Bytes. And couldn't locate | |
424 | * an I2C slave, which supports such a lengthy burst read too for experiments. | |
425 | * | |
426 | * So until things get clarified on HW support, to avoid the burst read length | |
427 | * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. | |
428 | */ | |
429 | #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U | |
430 | ||
924a93ed | 431 | static int |
9535c475 | 432 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
d5dc0f43 | 433 | u32 gmbus0_reg, u32 gmbus1_index) |
924a93ed | 434 | { |
924a93ed | 435 | u8 *buf = msg->buf; |
9535c475 DT |
436 | unsigned int rx_size = msg->len; |
437 | unsigned int len; | |
438 | int ret; | |
439 | ||
440 | do { | |
d5dc0f43 R |
441 | if (HAS_GMBUS_BURST_READ(dev_priv)) |
442 | len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); | |
443 | else | |
444 | len = min(rx_size, gmbus_max_xfer_size(dev_priv)); | |
9535c475 | 445 | |
d5dc0f43 R |
446 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, |
447 | gmbus0_reg, gmbus1_index); | |
9535c475 DT |
448 | if (ret) |
449 | return ret; | |
450 | ||
451 | rx_size -= len; | |
452 | buf += len; | |
453 | } while (rx_size != 0); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
458 | static int | |
459 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, | |
d02cf0a4 SP |
460 | unsigned short addr, u8 *buf, unsigned int len, |
461 | u32 gmbus1_index) | |
9535c475 | 462 | { |
9535c475 | 463 | unsigned int chunk_size = len; |
924a93ed DK |
464 | u32 val, loop; |
465 | ||
466 | val = loop = 0; | |
26883c31 DK |
467 | while (len && loop < 4) { |
468 | val |= *buf++ << (8 * loop++); | |
469 | len -= 1; | |
470 | } | |
924a93ed | 471 | |
4e6c2d58 CW |
472 | I915_WRITE_FW(GMBUS3, val); |
473 | I915_WRITE_FW(GMBUS1, | |
d02cf0a4 | 474 | gmbus1_index | GMBUS_CYCLE_WAIT | |
4e6c2d58 CW |
475 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | |
476 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
477 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); | |
924a93ed | 478 | while (len) { |
90e6b26d | 479 | int ret; |
90e6b26d | 480 | |
924a93ed DK |
481 | val = loop = 0; |
482 | do { | |
483 | val |= *buf++ << (8 * loop); | |
484 | } while (--len && ++loop < 4); | |
485 | ||
4e6c2d58 | 486 | I915_WRITE_FW(GMBUS3, val); |
7a39a9d4 | 487 | |
4e6c2d58 | 488 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 489 | if (ret) |
61168c53 | 490 | return ret; |
924a93ed | 491 | } |
9535c475 DT |
492 | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static int | |
d02cf0a4 SP |
497 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
498 | u32 gmbus1_index) | |
9535c475 DT |
499 | { |
500 | u8 *buf = msg->buf; | |
501 | unsigned int tx_size = msg->len; | |
502 | unsigned int len; | |
503 | int ret; | |
504 | ||
505 | do { | |
73675cf6 | 506 | len = min(tx_size, gmbus_max_xfer_size(dev_priv)); |
9535c475 | 507 | |
d02cf0a4 SP |
508 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, |
509 | gmbus1_index); | |
9535c475 DT |
510 | if (ret) |
511 | return ret; | |
512 | ||
513 | buf += len; | |
514 | tx_size -= len; | |
515 | } while (tx_size != 0); | |
516 | ||
924a93ed DK |
517 | return 0; |
518 | } | |
519 | ||
56f9eac0 | 520 | /* |
d02cf0a4 SP |
521 | * The gmbus controller can combine a 1 or 2 byte write with another read/write |
522 | * that immediately follows it by using an "INDEX" cycle. | |
56f9eac0 DK |
523 | */ |
524 | static bool | |
d02cf0a4 | 525 | gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) |
56f9eac0 DK |
526 | { |
527 | return (i + 1 < num && | |
c4deb62d | 528 | msgs[i].addr == msgs[i + 1].addr && |
bb9e0d4b VS |
529 | !(msgs[i].flags & I2C_M_RD) && |
530 | (msgs[i].len == 1 || msgs[i].len == 2) && | |
d02cf0a4 | 531 | msgs[i + 1].len > 0); |
56f9eac0 DK |
532 | } |
533 | ||
534 | static int | |
d5dc0f43 R |
535 | gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, |
536 | u32 gmbus0_reg) | |
56f9eac0 | 537 | { |
56f9eac0 DK |
538 | u32 gmbus1_index = 0; |
539 | u32 gmbus5 = 0; | |
540 | int ret; | |
541 | ||
542 | if (msgs[0].len == 2) | |
543 | gmbus5 = GMBUS_2BYTE_INDEX_EN | | |
544 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); | |
545 | if (msgs[0].len == 1) | |
546 | gmbus1_index = GMBUS_CYCLE_INDEX | | |
547 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); | |
548 | ||
549 | /* GMBUS5 holds 16-bit index */ | |
550 | if (gmbus5) | |
4e6c2d58 | 551 | I915_WRITE_FW(GMBUS5, gmbus5); |
56f9eac0 | 552 | |
d02cf0a4 | 553 | if (msgs[1].flags & I2C_M_RD) |
d5dc0f43 R |
554 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, |
555 | gmbus1_index); | |
d02cf0a4 SP |
556 | else |
557 | ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); | |
56f9eac0 DK |
558 | |
559 | /* Clear GMBUS5 after each index transfer */ | |
560 | if (gmbus5) | |
4e6c2d58 | 561 | I915_WRITE_FW(GMBUS5, 0); |
56f9eac0 DK |
562 | |
563 | return ret; | |
564 | } | |
565 | ||
f899fc64 | 566 | static int |
07e17a75 SP |
567 | do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, |
568 | u32 gmbus0_source) | |
f899fc64 CW |
569 | { |
570 | struct intel_gmbus *bus = container_of(adapter, | |
571 | struct intel_gmbus, | |
572 | adapter); | |
c2b9152f | 573 | struct drm_i915_private *dev_priv = bus->dev_priv; |
699fc401 | 574 | int i = 0, inc, try = 0; |
72d66afd | 575 | int ret = 0; |
f899fc64 | 576 | |
6481d5ed VS |
577 | /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ |
578 | if (IS_GEN9_LP(dev_priv)) | |
579 | bxt_gmbus_clock_gating(dev_priv, false); | |
580 | else if (HAS_PCH_SPT(dev_priv) || | |
581 | HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) | |
582 | pch_gmbus_clock_gating(dev_priv, false); | |
583 | ||
3f5f1554 | 584 | retry: |
07e17a75 | 585 | I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); |
f899fc64 | 586 | |
3f5f1554 JN |
587 | for (; i < num; i += inc) { |
588 | inc = 1; | |
d02cf0a4 | 589 | if (gmbus_is_index_xfer(msgs, i, num)) { |
d5dc0f43 R |
590 | ret = gmbus_index_xfer(dev_priv, &msgs[i], |
591 | gmbus0_source | bus->reg0); | |
d02cf0a4 | 592 | inc = 2; /* an index transmission is two msgs */ |
56f9eac0 | 593 | } else if (msgs[i].flags & I2C_M_RD) { |
d5dc0f43 R |
594 | ret = gmbus_xfer_read(dev_priv, &msgs[i], |
595 | gmbus0_source | bus->reg0, 0); | |
56f9eac0 | 596 | } else { |
d02cf0a4 | 597 | ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); |
56f9eac0 | 598 | } |
924a93ed | 599 | |
0aeb9048 | 600 | if (!ret) |
4e6c2d58 CW |
601 | ret = gmbus_wait(dev_priv, |
602 | GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); | |
924a93ed DK |
603 | if (ret == -ETIMEDOUT) |
604 | goto timeout; | |
0aeb9048 | 605 | else if (ret) |
924a93ed | 606 | goto clear_err; |
f899fc64 CW |
607 | } |
608 | ||
72d66afd DK |
609 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
610 | * a STOP on the very first cycle. To simplify the code we | |
611 | * unconditionally generate the STOP condition with an additional gmbus | |
612 | * cycle. */ | |
4e6c2d58 | 613 | I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
72d66afd | 614 | |
e646d577 DK |
615 | /* Mark the GMBUS interface as disabled after waiting for idle. |
616 | * We will re-enable it at the start of the next xfer, | |
617 | * till then let it sleep. | |
618 | */ | |
2c438c02 | 619 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f | 620 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
e646d577 | 621 | adapter->name); |
72d66afd DK |
622 | ret = -ETIMEDOUT; |
623 | } | |
4e6c2d58 | 624 | I915_WRITE_FW(GMBUS0, 0); |
72d66afd | 625 | ret = ret ?: i; |
e646d577 | 626 | goto out; |
7f58aabc CW |
627 | |
628 | clear_err: | |
e646d577 DK |
629 | /* |
630 | * Wait for bus to IDLE before clearing NAK. | |
631 | * If we clear the NAK while bus is still active, then it will stay | |
632 | * active and the next transaction may fail. | |
65e81866 SV |
633 | * |
634 | * If no ACK is received during the address phase of a transaction, the | |
635 | * adapter must report -ENXIO. It is not clear what to return if no ACK | |
636 | * is received at other times. But we have to be careful to not return | |
637 | * spurious -ENXIO because that will prevent i2c and drm edid functions | |
638 | * from retrying. So return -ENXIO only when gmbus properly quiescents - | |
639 | * timing out seems to happen when there _is_ a ddc chip present, but | |
640 | * it's slow responding and only answers on the 2nd retry. | |
e646d577 | 641 | */ |
65e81866 | 642 | ret = -ENXIO; |
2c438c02 | 643 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f DK |
644 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
645 | adapter->name); | |
65e81866 SV |
646 | ret = -ETIMEDOUT; |
647 | } | |
e646d577 | 648 | |
7f58aabc CW |
649 | /* Toggle the Software Clear Interrupt bit. This has the effect |
650 | * of resetting the GMBUS controller and so clearing the | |
651 | * BUS_ERROR raised by the slave's NAK. | |
652 | */ | |
4e6c2d58 CW |
653 | I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); |
654 | I915_WRITE_FW(GMBUS1, 0); | |
655 | I915_WRITE_FW(GMBUS0, 0); | |
7f58aabc | 656 | |
56fa6d6f | 657 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
e646d577 DK |
658 | adapter->name, msgs[i].addr, |
659 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); | |
660 | ||
3f5f1554 JN |
661 | /* |
662 | * Passive adapters sometimes NAK the first probe. Retry the first | |
663 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm | |
664 | * has retries internally. See also the retry loop in | |
665 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. | |
666 | */ | |
667 | if (ret == -ENXIO && i == 0 && try++ == 0) { | |
668 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", | |
669 | adapter->name); | |
670 | goto retry; | |
671 | } | |
672 | ||
8a8ed1f5 | 673 | goto out; |
f899fc64 CW |
674 | |
675 | timeout: | |
70677801 VS |
676 | DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
677 | bus->adapter.name, bus->reg0 & 0xff); | |
4e6c2d58 | 678 | I915_WRITE_FW(GMBUS0, 0); |
7f58aabc | 679 | |
bffce907 JN |
680 | /* |
681 | * Hardware may not support GMBUS over these pins? Try GPIO bitbanging | |
682 | * instead. Use EAGAIN to have i2c core retry. | |
683 | */ | |
bffce907 | 684 | ret = -EAGAIN; |
489fbc10 | 685 | |
8a8ed1f5 | 686 | out: |
6481d5ed VS |
687 | /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ |
688 | if (IS_GEN9_LP(dev_priv)) | |
689 | bxt_gmbus_clock_gating(dev_priv, true); | |
690 | else if (HAS_PCH_SPT(dev_priv) || | |
691 | HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) | |
692 | pch_gmbus_clock_gating(dev_priv, true); | |
693 | ||
bffce907 JN |
694 | return ret; |
695 | } | |
696 | ||
697 | static int | |
698 | gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) | |
699 | { | |
0e6e0be4 CW |
700 | struct intel_gmbus *bus = |
701 | container_of(adapter, struct intel_gmbus, adapter); | |
bffce907 | 702 | struct drm_i915_private *dev_priv = bus->dev_priv; |
0e6e0be4 | 703 | intel_wakeref_t wakeref; |
bffce907 JN |
704 | int ret; |
705 | ||
0e6e0be4 | 706 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
bffce907 | 707 | |
3e4d44e0 | 708 | if (bus->force_bit) { |
bffce907 | 709 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
3e4d44e0 VS |
710 | if (ret < 0) |
711 | bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; | |
712 | } else { | |
07e17a75 | 713 | ret = do_gmbus_xfer(adapter, msgs, num, 0); |
3e4d44e0 VS |
714 | if (ret == -EAGAIN) |
715 | bus->force_bit |= GMBUS_FORCE_BIT_RETRY; | |
716 | } | |
f0ab43e6 | 717 | |
0e6e0be4 | 718 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
f0ab43e6 | 719 | |
8a8ed1f5 | 720 | return ret; |
f899fc64 CW |
721 | } |
722 | ||
07e17a75 SP |
723 | int intel_gmbus_output_aksv(struct i2c_adapter *adapter) |
724 | { | |
0e6e0be4 CW |
725 | struct intel_gmbus *bus = |
726 | container_of(adapter, struct intel_gmbus, adapter); | |
07e17a75 | 727 | struct drm_i915_private *dev_priv = bus->dev_priv; |
07e17a75 SP |
728 | u8 cmd = DRM_HDCP_DDC_AKSV; |
729 | u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; | |
730 | struct i2c_msg msgs[] = { | |
731 | { | |
732 | .addr = DRM_HDCP_DDC_ADDR, | |
733 | .flags = 0, | |
734 | .len = sizeof(cmd), | |
735 | .buf = &cmd, | |
736 | }, | |
737 | { | |
738 | .addr = DRM_HDCP_DDC_ADDR, | |
739 | .flags = 0, | |
740 | .len = sizeof(buf), | |
741 | .buf = buf, | |
742 | } | |
743 | }; | |
0e6e0be4 CW |
744 | intel_wakeref_t wakeref; |
745 | int ret; | |
07e17a75 | 746 | |
0e6e0be4 | 747 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
07e17a75 SP |
748 | mutex_lock(&dev_priv->gmbus_mutex); |
749 | ||
750 | /* | |
751 | * In order to output Aksv to the receiver, use an indexed write to | |
752 | * pass the i2c command, and tell GMBUS to use the HW-provided value | |
753 | * instead of sourcing GMBUS3 for the data. | |
754 | */ | |
755 | ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); | |
756 | ||
757 | mutex_unlock(&dev_priv->gmbus_mutex); | |
0e6e0be4 | 758 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
07e17a75 SP |
759 | |
760 | return ret; | |
761 | } | |
762 | ||
f899fc64 CW |
763 | static u32 gmbus_func(struct i2c_adapter *adapter) |
764 | { | |
f6f808c8 SV |
765 | return i2c_bit_algo.functionality(adapter) & |
766 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
f899fc64 CW |
767 | /* I2C_FUNC_10BIT_ADDR | */ |
768 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
769 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); | |
770 | } | |
771 | ||
772 | static const struct i2c_algorithm gmbus_algorithm = { | |
773 | .master_xfer = gmbus_xfer, | |
774 | .functionality = gmbus_func | |
775 | }; | |
776 | ||
a8506684 SV |
777 | static void gmbus_lock_bus(struct i2c_adapter *adapter, |
778 | unsigned int flags) | |
779 | { | |
780 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
781 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
782 | ||
783 | mutex_lock(&dev_priv->gmbus_mutex); | |
784 | } | |
785 | ||
786 | static int gmbus_trylock_bus(struct i2c_adapter *adapter, | |
787 | unsigned int flags) | |
788 | { | |
789 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
790 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
791 | ||
792 | return mutex_trylock(&dev_priv->gmbus_mutex); | |
793 | } | |
794 | ||
795 | static void gmbus_unlock_bus(struct i2c_adapter *adapter, | |
796 | unsigned int flags) | |
797 | { | |
798 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
799 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
800 | ||
801 | mutex_unlock(&dev_priv->gmbus_mutex); | |
802 | } | |
803 | ||
0db1aa42 | 804 | static const struct i2c_lock_operations gmbus_lock_ops = { |
a8506684 SV |
805 | .lock_bus = gmbus_lock_bus, |
806 | .trylock_bus = gmbus_trylock_bus, | |
807 | .unlock_bus = gmbus_unlock_bus, | |
808 | }; | |
809 | ||
79e53945 | 810 | /** |
f899fc64 | 811 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
40196446 | 812 | * @dev_priv: i915 device private |
79e53945 | 813 | */ |
40196446 | 814 | int intel_setup_gmbus(struct drm_i915_private *dev_priv) |
f899fc64 | 815 | { |
52a05c30 | 816 | struct pci_dev *pdev = dev_priv->drm.pdev; |
5ea6e5e3 JN |
817 | struct intel_gmbus *bus; |
818 | unsigned int pin; | |
819 | int ret; | |
f899fc64 | 820 | |
e1bf094b | 821 | if (!HAS_DISPLAY(dev_priv)) |
ab5c608b | 822 | return 0; |
b2e8c6cd | 823 | |
920a14b2 | 824 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
d8112150 | 825 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
b2ae318a | 826 | else if (!HAS_GMCH(dev_priv)) |
dce88879 LDM |
827 | /* |
828 | * Broxton uses the same PCH offsets for South Display Engine, | |
829 | * even though it doesn't have a PCH. | |
830 | */ | |
831 | dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; | |
110447fc | 832 | |
8a8ed1f5 | 833 | mutex_init(&dev_priv->gmbus_mutex); |
28c70f16 | 834 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
8a8ed1f5 | 835 | |
5ea6e5e3 | 836 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
88ac7939 | 837 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
838 | continue; |
839 | ||
840 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
841 | |
842 | bus->adapter.owner = THIS_MODULE; | |
843 | bus->adapter.class = I2C_CLASS_DDC; | |
844 | snprintf(bus->adapter.name, | |
69669455 JD |
845 | sizeof(bus->adapter.name), |
846 | "i915 gmbus %s", | |
4c272834 | 847 | get_gmbus_pin(dev_priv, pin)->name); |
f899fc64 | 848 | |
52a05c30 | 849 | bus->adapter.dev.parent = &pdev->dev; |
c2b9152f | 850 | bus->dev_priv = dev_priv; |
f899fc64 CW |
851 | |
852 | bus->adapter.algo = &gmbus_algorithm; | |
a8506684 | 853 | bus->adapter.lock_ops = &gmbus_lock_ops; |
f899fc64 | 854 | |
8b1f165a VS |
855 | /* |
856 | * We wish to retry with bit banging | |
857 | * after a timed out GMBUS attempt. | |
858 | */ | |
859 | bus->adapter.retries = 1; | |
860 | ||
e957d772 | 861 | /* By default use a conservative clock rate */ |
5ea6e5e3 | 862 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
cb8ea752 | 863 | |
83ee9e64 | 864 | /* gmbus seems to be broken on i830 */ |
50a0bc90 | 865 | if (IS_I830(dev_priv)) |
f2ce9faf | 866 | bus->force_bit = 1; |
83ee9e64 | 867 | |
5ea6e5e3 | 868 | intel_gpio_setup(bus, pin); |
cee25168 JN |
869 | |
870 | ret = i2c_add_adapter(&bus->adapter); | |
871 | if (ret) | |
872 | goto err; | |
f899fc64 CW |
873 | } |
874 | ||
af6dc742 | 875 | intel_i2c_reset(dev_priv); |
f899fc64 CW |
876 | |
877 | return 0; | |
878 | ||
879 | err: | |
2417c8c0 | 880 | while (pin--) { |
88ac7939 | 881 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
882 | continue; |
883 | ||
884 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
885 | i2c_del_adapter(&bus->adapter); |
886 | } | |
f899fc64 CW |
887 | return ret; |
888 | } | |
889 | ||
3bd7d909 | 890 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
0184df46 | 891 | unsigned int pin) |
3bd7d909 | 892 | { |
88ac7939 | 893 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
5ea6e5e3 JN |
894 | return NULL; |
895 | ||
896 | return &dev_priv->gmbus[pin].adapter; | |
3bd7d909 DK |
897 | } |
898 | ||
e957d772 CW |
899 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
900 | { | |
901 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
902 | ||
d5090b96 | 903 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
e957d772 CW |
904 | } |
905 | ||
906 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) | |
907 | { | |
908 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
ade754ec VS |
909 | struct drm_i915_private *dev_priv = bus->dev_priv; |
910 | ||
911 | mutex_lock(&dev_priv->gmbus_mutex); | |
e957d772 | 912 | |
f2ce9faf CW |
913 | bus->force_bit += force_bit ? 1 : -1; |
914 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", | |
915 | force_bit ? "en" : "dis", adapter->name, | |
916 | bus->force_bit); | |
ade754ec VS |
917 | |
918 | mutex_unlock(&dev_priv->gmbus_mutex); | |
e957d772 CW |
919 | } |
920 | ||
40196446 | 921 | void intel_teardown_gmbus(struct drm_i915_private *dev_priv) |
79e53945 | 922 | { |
5ea6e5e3 JN |
923 | struct intel_gmbus *bus; |
924 | unsigned int pin; | |
925 | ||
926 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { | |
88ac7939 | 927 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 | 928 | continue; |
f9c10a9b | 929 | |
5ea6e5e3 | 930 | bus = &dev_priv->gmbus[pin]; |
f899fc64 CW |
931 | i2c_del_adapter(&bus->adapter); |
932 | } | |
79e53945 | 933 | } |