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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
7c2fa7fa | 139 | #include "i915_gem_render_state.h" |
578f1ac6 | 140 | #include "intel_lrc_reg.h" |
3bbaba0c | 141 | #include "intel_mocs.h" |
7d3c425f | 142 | #include "intel_workarounds.h" |
127f1003 | 143 | |
e981e7b1 TD |
144 | #define RING_EXECLIST_QFULL (1 << 0x2) |
145 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
146 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
147 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
148 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
149 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
150 | ||
151 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
152 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
153 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
154 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
155 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
156 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 157 | |
70c2a24d | 158 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
d8747afb | 159 | (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) |
70c2a24d | 160 | |
0e93cdd4 CW |
161 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
162 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
a3aabe86 | 163 | #define WA_TAIL_DWORDS 2 |
7e4992ac | 164 | #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) |
a3aabe86 | 165 | |
e2efd130 | 166 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
1fc44d9b CW |
167 | struct intel_engine_cs *engine, |
168 | struct intel_context *ce); | |
a3aabe86 CW |
169 | static void execlists_init_reg_state(u32 *reg_state, |
170 | struct i915_gem_context *ctx, | |
171 | struct intel_engine_cs *engine, | |
172 | struct intel_ring *ring); | |
7ba717cf | 173 | |
f6322edd CW |
174 | static inline struct i915_priolist *to_priolist(struct rb_node *rb) |
175 | { | |
176 | return rb_entry(rb, struct i915_priolist, node); | |
177 | } | |
178 | ||
179 | static inline int rq_prio(const struct i915_request *rq) | |
180 | { | |
b7268c5e | 181 | return rq->sched.attr.priority; |
f6322edd CW |
182 | } |
183 | ||
184 | static inline bool need_preempt(const struct intel_engine_cs *engine, | |
185 | const struct i915_request *last, | |
186 | int prio) | |
187 | { | |
2a694feb | 188 | return (intel_engine_has_preemption(engine) && |
c5ce3b8d CW |
189 | __execlists_need_preempt(prio, rq_prio(last)) && |
190 | !i915_request_completed(last)); | |
f6322edd CW |
191 | } |
192 | ||
1fc44d9b | 193 | /* |
ca82580c TU |
194 | * The context descriptor encodes various attributes of a context, |
195 | * including its GTT address and some flags. Because it's fairly | |
196 | * expensive to calculate, we'll just do it once and cache the result, | |
197 | * which remains valid until the context is unpinned. | |
198 | * | |
6e5248b5 DV |
199 | * This is what a descriptor looks like, from LSB to MSB:: |
200 | * | |
2355cf08 | 201 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 | 202 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
218b5000 | 203 | * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) |
6e5248b5 DV |
204 | * bits 53-54: mbz, reserved for use by hardware |
205 | * bits 55-63: group ID, currently unused and set to 0 | |
ac52da6a DCS |
206 | * |
207 | * Starting from Gen11, the upper dword of the descriptor has a new format: | |
208 | * | |
209 | * bits 32-36: reserved | |
210 | * bits 37-47: SW context ID | |
211 | * bits 48:53: engine instance | |
212 | * bit 54: mbz, reserved for use by hardware | |
213 | * bits 55-60: SW counter | |
214 | * bits 61-63: engine class | |
215 | * | |
216 | * engine info, SW context ID and SW counter need to form a unique number | |
217 | * (Context ID) per lrc. | |
73e4d07f | 218 | */ |
ca82580c | 219 | static void |
e2efd130 | 220 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
1fc44d9b CW |
221 | struct intel_engine_cs *engine, |
222 | struct intel_context *ce) | |
84b790f8 | 223 | { |
7069b144 | 224 | u64 desc; |
84b790f8 | 225 | |
ac52da6a DCS |
226 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); |
227 | BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); | |
84b790f8 | 228 | |
2355cf08 | 229 | desc = ctx->desc_template; /* bits 0-11 */ |
ac52da6a DCS |
230 | GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); |
231 | ||
0b29c75a | 232 | desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; |
9021ad03 | 233 | /* bits 12-31 */ |
ac52da6a DCS |
234 | GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); |
235 | ||
61d5676b LL |
236 | /* |
237 | * The following 32bits are copied into the OA reports (dword 2). | |
238 | * Consider updating oa_get_render_ctx_id in i915_perf.c when changing | |
239 | * anything below. | |
240 | */ | |
ac52da6a DCS |
241 | if (INTEL_GEN(ctx->i915) >= 11) { |
242 | GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); | |
243 | desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; | |
244 | /* bits 37-47 */ | |
245 | ||
246 | desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; | |
247 | /* bits 48-53 */ | |
248 | ||
249 | /* TODO: decide what to do with SW counter (bits 55-60) */ | |
250 | ||
251 | desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; | |
252 | /* bits 61-63 */ | |
253 | } else { | |
254 | GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); | |
255 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ | |
256 | } | |
5af05fef | 257 | |
9021ad03 | 258 | ce->lrc_desc = desc; |
5af05fef MT |
259 | } |
260 | ||
27606fd8 | 261 | static struct i915_priolist * |
87c7acf8 | 262 | lookup_priolist(struct intel_engine_cs *engine, int prio) |
08dd3e1a | 263 | { |
b620e870 | 264 | struct intel_engine_execlists * const execlists = &engine->execlists; |
08dd3e1a CW |
265 | struct i915_priolist *p; |
266 | struct rb_node **parent, *rb; | |
267 | bool first = true; | |
268 | ||
b620e870 | 269 | if (unlikely(execlists->no_priolist)) |
08dd3e1a CW |
270 | prio = I915_PRIORITY_NORMAL; |
271 | ||
272 | find_priolist: | |
273 | /* most positive priority is scheduled first, equal priorities fifo */ | |
274 | rb = NULL; | |
b620e870 | 275 | parent = &execlists->queue.rb_node; |
08dd3e1a CW |
276 | while (*parent) { |
277 | rb = *parent; | |
f6322edd | 278 | p = to_priolist(rb); |
08dd3e1a CW |
279 | if (prio > p->priority) { |
280 | parent = &rb->rb_left; | |
281 | } else if (prio < p->priority) { | |
282 | parent = &rb->rb_right; | |
283 | first = false; | |
284 | } else { | |
27606fd8 | 285 | return p; |
08dd3e1a CW |
286 | } |
287 | } | |
288 | ||
289 | if (prio == I915_PRIORITY_NORMAL) { | |
b620e870 | 290 | p = &execlists->default_priolist; |
08dd3e1a CW |
291 | } else { |
292 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); | |
293 | /* Convert an allocation failure to a priority bump */ | |
294 | if (unlikely(!p)) { | |
295 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
296 | ||
297 | /* To maintain ordering with all rendering, after an | |
298 | * allocation failure we have to disable all scheduling. | |
299 | * Requests will then be executed in fifo, and schedule | |
300 | * will ensure that dependencies are emitted in fifo. | |
301 | * There will be still some reordering with existing | |
302 | * requests, so if userspace lied about their | |
303 | * dependencies that reordering may be visible. | |
304 | */ | |
b620e870 | 305 | execlists->no_priolist = true; |
08dd3e1a CW |
306 | goto find_priolist; |
307 | } | |
308 | } | |
309 | ||
310 | p->priority = prio; | |
27606fd8 | 311 | INIT_LIST_HEAD(&p->requests); |
08dd3e1a | 312 | rb_link_node(&p->node, rb, parent); |
b620e870 | 313 | rb_insert_color(&p->node, &execlists->queue); |
08dd3e1a | 314 | |
08dd3e1a | 315 | if (first) |
b620e870 | 316 | execlists->first = &p->node; |
08dd3e1a | 317 | |
f6322edd | 318 | return p; |
08dd3e1a CW |
319 | } |
320 | ||
e61e0f51 | 321 | static void unwind_wa_tail(struct i915_request *rq) |
7e4992ac CW |
322 | { |
323 | rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); | |
324 | assert_ring_tail_valid(rq->ring, rq->tail); | |
325 | } | |
326 | ||
a4598d17 | 327 | static void __unwind_incomplete_requests(struct intel_engine_cs *engine) |
7e4992ac | 328 | { |
e61e0f51 | 329 | struct i915_request *rq, *rn; |
097a9481 MW |
330 | struct i915_priolist *uninitialized_var(p); |
331 | int last_prio = I915_PRIORITY_INVALID; | |
7e4992ac | 332 | |
a89d1f92 | 333 | lockdep_assert_held(&engine->timeline.lock); |
7e4992ac CW |
334 | |
335 | list_for_each_entry_safe_reverse(rq, rn, | |
a89d1f92 | 336 | &engine->timeline.requests, |
7e4992ac | 337 | link) { |
e61e0f51 | 338 | if (i915_request_completed(rq)) |
7e4992ac CW |
339 | return; |
340 | ||
e61e0f51 | 341 | __i915_request_unsubmit(rq); |
7e4992ac CW |
342 | unwind_wa_tail(rq); |
343 | ||
f6322edd CW |
344 | GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); |
345 | if (rq_prio(rq) != last_prio) { | |
346 | last_prio = rq_prio(rq); | |
87c7acf8 | 347 | p = lookup_priolist(engine, last_prio); |
097a9481 MW |
348 | } |
349 | ||
a02eb975 | 350 | GEM_BUG_ON(p->priority != rq_prio(rq)); |
0c7112a0 | 351 | list_add(&rq->sched.link, &p->requests); |
7e4992ac CW |
352 | } |
353 | } | |
354 | ||
c41937fd | 355 | void |
a4598d17 MW |
356 | execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) |
357 | { | |
358 | struct intel_engine_cs *engine = | |
359 | container_of(execlists, typeof(*engine), execlists); | |
4413c474 CW |
360 | unsigned long flags; |
361 | ||
362 | spin_lock_irqsave(&engine->timeline.lock, flags); | |
a4598d17 | 363 | |
a4598d17 | 364 | __unwind_incomplete_requests(engine); |
4413c474 CW |
365 | |
366 | spin_unlock_irqrestore(&engine->timeline.lock, flags); | |
a4598d17 MW |
367 | } |
368 | ||
bbd6c47e | 369 | static inline void |
e61e0f51 | 370 | execlists_context_status_change(struct i915_request *rq, unsigned long status) |
84b790f8 | 371 | { |
bbd6c47e CW |
372 | /* |
373 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
374 | * The compiler should eliminate this function as dead-code. | |
375 | */ | |
376 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
377 | return; | |
6daccb0b | 378 | |
3fc03069 CD |
379 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
380 | status, rq); | |
84b790f8 BW |
381 | } |
382 | ||
f2605207 CW |
383 | inline void |
384 | execlists_user_begin(struct intel_engine_execlists *execlists, | |
385 | const struct execlist_port *port) | |
386 | { | |
387 | execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); | |
388 | } | |
389 | ||
390 | inline void | |
391 | execlists_user_end(struct intel_engine_execlists *execlists) | |
392 | { | |
393 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); | |
394 | } | |
395 | ||
73fd9d38 | 396 | static inline void |
e61e0f51 | 397 | execlists_context_schedule_in(struct i915_request *rq) |
73fd9d38 TU |
398 | { |
399 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
30e17b78 | 400 | intel_engine_context_in(rq->engine); |
73fd9d38 TU |
401 | } |
402 | ||
403 | static inline void | |
b9b77426 | 404 | execlists_context_schedule_out(struct i915_request *rq, unsigned long status) |
73fd9d38 | 405 | { |
30e17b78 | 406 | intel_engine_context_out(rq->engine); |
b9b77426 CW |
407 | execlists_context_status_change(rq, status); |
408 | trace_i915_request_out(rq); | |
73fd9d38 TU |
409 | } |
410 | ||
c6a2ac71 TU |
411 | static void |
412 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
413 | { | |
414 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
415 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
416 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
417 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
418 | } | |
419 | ||
e61e0f51 | 420 | static u64 execlists_update_context(struct i915_request *rq) |
ae1250b9 | 421 | { |
1fc44d9b | 422 | struct intel_context *ce = rq->hw_context; |
04da811b | 423 | struct i915_hw_ppgtt *ppgtt = |
4e0d64db | 424 | rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt; |
70c2a24d | 425 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 426 | |
e6ba9992 | 427 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 428 | |
c6a2ac71 TU |
429 | /* True 32b PPGTT with dynamic page allocation: update PDP |
430 | * registers and point the unallocated PDPs to scratch page. | |
431 | * PML4 is allocated during ppgtt init, so this is not needed | |
432 | * in 48-bit mode. | |
433 | */ | |
82ad6443 | 434 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm)) |
c6a2ac71 | 435 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
436 | |
437 | return ce->lrc_desc; | |
ae1250b9 OM |
438 | } |
439 | ||
05f0addd | 440 | static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) |
beecec90 | 441 | { |
05f0addd TD |
442 | if (execlists->ctrl_reg) { |
443 | writel(lower_32_bits(desc), execlists->submit_reg + port * 2); | |
444 | writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); | |
445 | } else { | |
446 | writel(upper_32_bits(desc), execlists->submit_reg); | |
447 | writel(lower_32_bits(desc), execlists->submit_reg); | |
448 | } | |
beecec90 CW |
449 | } |
450 | ||
70c2a24d | 451 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 452 | { |
05f0addd TD |
453 | struct intel_engine_execlists *execlists = &engine->execlists; |
454 | struct execlist_port *port = execlists->port; | |
77f0d0e9 | 455 | unsigned int n; |
bbd6c47e | 456 | |
05f0addd TD |
457 | /* |
458 | * ELSQ note: the submit queue is not cleared after being submitted | |
459 | * to the HW so we need to make sure we always clean it up. This is | |
460 | * currently ensured by the fact that we always write the same number | |
461 | * of elsq entries, keep this in mind before changing the loop below. | |
462 | */ | |
463 | for (n = execlists_num_ports(execlists); n--; ) { | |
e61e0f51 | 464 | struct i915_request *rq; |
77f0d0e9 CW |
465 | unsigned int count; |
466 | u64 desc; | |
467 | ||
468 | rq = port_unpack(&port[n], &count); | |
469 | if (rq) { | |
470 | GEM_BUG_ON(count > !n); | |
471 | if (!count++) | |
73fd9d38 | 472 | execlists_context_schedule_in(rq); |
77f0d0e9 CW |
473 | port_set(&port[n], port_pack(rq, count)); |
474 | desc = execlists_update_context(rq); | |
475 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
bccd3b83 | 476 | |
0c5c7df3 | 477 | GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n", |
bccd3b83 | 478 | engine->name, n, |
16c8619a | 479 | port[n].context_id, count, |
f6322edd | 480 | rq->global_seqno, |
0c5c7df3 | 481 | rq->fence.context, rq->fence.seqno, |
e7702760 | 482 | intel_engine_get_seqno(engine), |
f6322edd | 483 | rq_prio(rq)); |
77f0d0e9 CW |
484 | } else { |
485 | GEM_BUG_ON(!n); | |
486 | desc = 0; | |
487 | } | |
bbd6c47e | 488 | |
05f0addd | 489 | write_desc(execlists, desc, n); |
77f0d0e9 | 490 | } |
05f0addd TD |
491 | |
492 | /* we need to manually load the submit queue */ | |
493 | if (execlists->ctrl_reg) | |
494 | writel(EL_CTRL_LOAD, execlists->ctrl_reg); | |
495 | ||
496 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); | |
bbd6c47e CW |
497 | } |
498 | ||
1fc44d9b | 499 | static bool ctx_single_port_submission(const struct intel_context *ce) |
84b790f8 | 500 | { |
70c2a24d | 501 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
1fc44d9b | 502 | i915_gem_context_force_single_submission(ce->gem_context)); |
70c2a24d | 503 | } |
84b790f8 | 504 | |
1fc44d9b CW |
505 | static bool can_merge_ctx(const struct intel_context *prev, |
506 | const struct intel_context *next) | |
70c2a24d CW |
507 | { |
508 | if (prev != next) | |
509 | return false; | |
26720ab9 | 510 | |
70c2a24d CW |
511 | if (ctx_single_port_submission(prev)) |
512 | return false; | |
26720ab9 | 513 | |
70c2a24d | 514 | return true; |
84b790f8 BW |
515 | } |
516 | ||
e61e0f51 | 517 | static void port_assign(struct execlist_port *port, struct i915_request *rq) |
77f0d0e9 CW |
518 | { |
519 | GEM_BUG_ON(rq == port_request(port)); | |
520 | ||
521 | if (port_isset(port)) | |
e61e0f51 | 522 | i915_request_put(port_request(port)); |
77f0d0e9 | 523 | |
e61e0f51 | 524 | port_set(port, port_pack(i915_request_get(rq), port_count(port))); |
77f0d0e9 CW |
525 | } |
526 | ||
beecec90 CW |
527 | static void inject_preempt_context(struct intel_engine_cs *engine) |
528 | { | |
05f0addd | 529 | struct intel_engine_execlists *execlists = &engine->execlists; |
beecec90 | 530 | struct intel_context *ce = |
ab82a063 | 531 | to_intel_context(engine->i915->preempt_context, engine); |
beecec90 CW |
532 | unsigned int n; |
533 | ||
05f0addd | 534 | GEM_BUG_ON(execlists->preempt_complete_status != |
d6376374 | 535 | upper_32_bits(ce->lrc_desc)); |
09b1a4e4 CW |
536 | GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] & |
537 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
538 | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) != | |
539 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
540 | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)); | |
541 | ||
f6322edd CW |
542 | /* |
543 | * Switch to our empty preempt context so | |
544 | * the state of the GPU is known (idle). | |
545 | */ | |
16a87394 | 546 | GEM_TRACE("%s\n", engine->name); |
05f0addd TD |
547 | for (n = execlists_num_ports(execlists); --n; ) |
548 | write_desc(execlists, 0, n); | |
549 | ||
550 | write_desc(execlists, ce->lrc_desc, n); | |
551 | ||
552 | /* we need to manually load the submit queue */ | |
553 | if (execlists->ctrl_reg) | |
554 | writel(EL_CTRL_LOAD, execlists->ctrl_reg); | |
beecec90 | 555 | |
ef2fb720 CW |
556 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); |
557 | execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); | |
558 | } | |
559 | ||
560 | static void complete_preempt_context(struct intel_engine_execlists *execlists) | |
561 | { | |
562 | GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); | |
563 | ||
564 | execlists_cancel_port_requests(execlists); | |
565 | execlists_unwind_incomplete_requests(execlists); | |
566 | ||
567 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT); | |
beecec90 CW |
568 | } |
569 | ||
0b02befa | 570 | static void __execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 571 | { |
7a62cc61 MK |
572 | struct intel_engine_execlists * const execlists = &engine->execlists; |
573 | struct execlist_port *port = execlists->port; | |
76e70087 MK |
574 | const struct execlist_port * const last_port = |
575 | &execlists->port[execlists->port_mask]; | |
e61e0f51 | 576 | struct i915_request *last = port_request(port); |
20311bd3 | 577 | struct rb_node *rb; |
70c2a24d CW |
578 | bool submit = false; |
579 | ||
4413c474 CW |
580 | lockdep_assert_held(&engine->timeline.lock); |
581 | ||
70c2a24d CW |
582 | /* Hardware submission is through 2 ports. Conceptually each port |
583 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
584 | * static for a context, and unique to each, so we only execute | |
585 | * requests belonging to a single context from each ring. RING_HEAD | |
586 | * is maintained by the CS in the context image, it marks the place | |
587 | * where it got up to last time, and through RING_TAIL we tell the CS | |
588 | * where we want to execute up to this time. | |
589 | * | |
590 | * In this list the requests are in order of execution. Consecutive | |
591 | * requests from the same context are adjacent in the ringbuffer. We | |
592 | * can combine these requests into a single RING_TAIL update: | |
593 | * | |
594 | * RING_HEAD...req1...req2 | |
595 | * ^- RING_TAIL | |
596 | * since to execute req2 the CS must first execute req1. | |
597 | * | |
598 | * Our goal then is to point each port to the end of a consecutive | |
599 | * sequence of requests as being the most optimal (fewest wake ups | |
600 | * and context switches) submission. | |
779949f4 | 601 | */ |
acdd884a | 602 | |
7a62cc61 MK |
603 | rb = execlists->first; |
604 | GEM_BUG_ON(rb_first(&execlists->queue) != rb); | |
beecec90 CW |
605 | |
606 | if (last) { | |
607 | /* | |
608 | * Don't resubmit or switch until all outstanding | |
609 | * preemptions (lite-restore) are seen. Then we | |
610 | * know the next preemption status we see corresponds | |
611 | * to this ELSP update. | |
612 | */ | |
eed7ec52 CW |
613 | GEM_BUG_ON(!execlists_is_active(execlists, |
614 | EXECLISTS_ACTIVE_USER)); | |
ba74cb10 | 615 | GEM_BUG_ON(!port_count(&port[0])); |
beecec90 | 616 | |
ba74cb10 MT |
617 | /* |
618 | * If we write to ELSP a second time before the HW has had | |
619 | * a chance to respond to the previous write, we can confuse | |
620 | * the HW and hit "undefined behaviour". After writing to ELSP, | |
621 | * we must then wait until we see a context-switch event from | |
622 | * the HW to indicate that it has had a chance to respond. | |
623 | */ | |
624 | if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) | |
0b02befa | 625 | return; |
ba74cb10 | 626 | |
f6322edd | 627 | if (need_preempt(engine, last, execlists->queue_priority)) { |
beecec90 | 628 | inject_preempt_context(engine); |
0b02befa | 629 | return; |
beecec90 | 630 | } |
f6322edd CW |
631 | |
632 | /* | |
633 | * In theory, we could coalesce more requests onto | |
634 | * the second port (the first port is active, with | |
635 | * no preemptions pending). However, that means we | |
636 | * then have to deal with the possible lite-restore | |
637 | * of the second port (as we submit the ELSP, there | |
638 | * may be a context-switch) but also we may complete | |
639 | * the resubmission before the context-switch. Ergo, | |
640 | * coalescing onto the second port will cause a | |
641 | * preemption event, but we cannot predict whether | |
642 | * that will affect port[0] or port[1]. | |
643 | * | |
644 | * If the second port is already active, we can wait | |
645 | * until the next context-switch before contemplating | |
646 | * new requests. The GPU will be busy and we should be | |
647 | * able to resubmit the new ELSP before it idles, | |
648 | * avoiding pipeline bubbles (momentary pauses where | |
649 | * the driver is unable to keep up the supply of new | |
650 | * work). However, we have to double check that the | |
651 | * priorities of the ports haven't been switch. | |
652 | */ | |
653 | if (port_count(&port[1])) | |
0b02befa | 654 | return; |
f6322edd CW |
655 | |
656 | /* | |
657 | * WaIdleLiteRestore:bdw,skl | |
658 | * Apply the wa NOOPs to prevent | |
659 | * ring:HEAD == rq:TAIL as we resubmit the | |
660 | * request. See gen8_emit_breadcrumb() for | |
661 | * where we prepare the padding after the | |
662 | * end of the request. | |
663 | */ | |
664 | last->tail = last->wa_tail; | |
beecec90 CW |
665 | } |
666 | ||
f6322edd CW |
667 | while (rb) { |
668 | struct i915_priolist *p = to_priolist(rb); | |
e61e0f51 | 669 | struct i915_request *rq, *rn; |
6c067579 | 670 | |
0c7112a0 | 671 | list_for_each_entry_safe(rq, rn, &p->requests, sched.link) { |
6c067579 CW |
672 | /* |
673 | * Can we combine this request with the current port? | |
674 | * It has to be the same context/ringbuffer and not | |
675 | * have any exceptions (e.g. GVT saying never to | |
676 | * combine contexts). | |
677 | * | |
678 | * If we can combine the requests, we can execute both | |
679 | * by updating the RING_TAIL to point to the end of the | |
680 | * second request, and so we never need to tell the | |
681 | * hardware about the first. | |
70c2a24d | 682 | */ |
1fc44d9b CW |
683 | if (last && |
684 | !can_merge_ctx(rq->hw_context, last->hw_context)) { | |
6c067579 CW |
685 | /* |
686 | * If we are on the second port and cannot | |
687 | * combine this request with the last, then we | |
688 | * are done. | |
689 | */ | |
76e70087 | 690 | if (port == last_port) { |
6c067579 | 691 | __list_del_many(&p->requests, |
0c7112a0 | 692 | &rq->sched.link); |
6c067579 CW |
693 | goto done; |
694 | } | |
695 | ||
696 | /* | |
697 | * If GVT overrides us we only ever submit | |
698 | * port[0], leaving port[1] empty. Note that we | |
699 | * also have to be careful that we don't queue | |
700 | * the same context (even though a different | |
701 | * request) to the second port. | |
702 | */ | |
1fc44d9b CW |
703 | if (ctx_single_port_submission(last->hw_context) || |
704 | ctx_single_port_submission(rq->hw_context)) { | |
6c067579 | 705 | __list_del_many(&p->requests, |
0c7112a0 | 706 | &rq->sched.link); |
6c067579 CW |
707 | goto done; |
708 | } | |
709 | ||
1fc44d9b | 710 | GEM_BUG_ON(last->hw_context == rq->hw_context); |
6c067579 CW |
711 | |
712 | if (submit) | |
713 | port_assign(port, last); | |
714 | port++; | |
7a62cc61 MK |
715 | |
716 | GEM_BUG_ON(port_isset(port)); | |
6c067579 | 717 | } |
70c2a24d | 718 | |
0c7112a0 | 719 | INIT_LIST_HEAD(&rq->sched.link); |
e61e0f51 CW |
720 | __i915_request_submit(rq); |
721 | trace_i915_request_in(rq, port_index(port, execlists)); | |
6c067579 CW |
722 | last = rq; |
723 | submit = true; | |
70c2a24d | 724 | } |
d55ac5bf | 725 | |
20311bd3 | 726 | rb = rb_next(rb); |
7a62cc61 | 727 | rb_erase(&p->node, &execlists->queue); |
6c067579 CW |
728 | INIT_LIST_HEAD(&p->requests); |
729 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 730 | kmem_cache_free(engine->i915->priorities, p); |
f6322edd | 731 | } |
15c83c43 | 732 | |
6c067579 | 733 | done: |
15c83c43 CW |
734 | /* |
735 | * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. | |
736 | * | |
737 | * We choose queue_priority such that if we add a request of greater | |
738 | * priority than this, we kick the submission tasklet to decide on | |
739 | * the right order of submitting the requests to hardware. We must | |
740 | * also be prepared to reorder requests as they are in-flight on the | |
741 | * HW. We derive the queue_priority then as the first "hole" in | |
742 | * the HW submission ports and if there are no available slots, | |
743 | * the priority of the lowest executing request, i.e. last. | |
744 | * | |
745 | * When we do receive a higher priority request ready to run from the | |
746 | * user, see queue_request(), the queue_priority is bumped to that | |
747 | * request triggering preemption on the next dequeue (or subsequent | |
748 | * interrupt for secondary ports). | |
749 | */ | |
750 | execlists->queue_priority = | |
751 | port != execlists->port ? rq_prio(last) : INT_MIN; | |
752 | ||
7a62cc61 | 753 | execlists->first = rb; |
0b02befa | 754 | if (submit) { |
77f0d0e9 | 755 | port_assign(port, last); |
0b02befa CW |
756 | execlists_submit_ports(engine); |
757 | } | |
339ccd35 CW |
758 | |
759 | /* We must always keep the beast fed if we have work piled up */ | |
339ccd35 CW |
760 | GEM_BUG_ON(execlists->first && !port_isset(execlists->port)); |
761 | ||
4413c474 CW |
762 | /* Re-evaluate the executing context setup after each preemptive kick */ |
763 | if (last) | |
f2605207 | 764 | execlists_user_begin(execlists, execlists->port); |
4413c474 | 765 | |
0b02befa CW |
766 | /* If the engine is now idle, so should be the flag; and vice versa. */ |
767 | GEM_BUG_ON(execlists_is_active(&engine->execlists, | |
768 | EXECLISTS_ACTIVE_USER) == | |
769 | !port_isset(engine->execlists.port)); | |
4413c474 CW |
770 | } |
771 | ||
772 | static void execlists_dequeue(struct intel_engine_cs *engine) | |
773 | { | |
4413c474 | 774 | unsigned long flags; |
4413c474 CW |
775 | |
776 | spin_lock_irqsave(&engine->timeline.lock, flags); | |
0b02befa | 777 | __execlists_dequeue(engine); |
4413c474 | 778 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
acdd884a MT |
779 | } |
780 | ||
c41937fd | 781 | void |
a4598d17 | 782 | execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) |
cf4591d1 | 783 | { |
3f9e6cd8 | 784 | struct execlist_port *port = execlists->port; |
dc2279e1 | 785 | unsigned int num_ports = execlists_num_ports(execlists); |
cf4591d1 | 786 | |
3f9e6cd8 | 787 | while (num_ports-- && port_isset(port)) { |
e61e0f51 | 788 | struct i915_request *rq = port_request(port); |
7e44fc28 | 789 | |
0c5c7df3 TU |
790 | GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n", |
791 | rq->engine->name, | |
792 | (unsigned int)(port - execlists->port), | |
793 | rq->global_seqno, | |
794 | rq->fence.context, rq->fence.seqno, | |
795 | intel_engine_get_seqno(rq->engine)); | |
796 | ||
4a118ecb | 797 | GEM_BUG_ON(!execlists->active); |
b9b77426 CW |
798 | execlists_context_schedule_out(rq, |
799 | i915_request_completed(rq) ? | |
800 | INTEL_CONTEXT_SCHEDULE_OUT : | |
801 | INTEL_CONTEXT_SCHEDULE_PREEMPTED); | |
702791f7 | 802 | |
e61e0f51 | 803 | i915_request_put(rq); |
7e44fc28 | 804 | |
3f9e6cd8 CW |
805 | memset(port, 0, sizeof(*port)); |
806 | port++; | |
807 | } | |
eed7ec52 | 808 | |
38057aa1 | 809 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); |
f2605207 | 810 | execlists_user_end(execlists); |
cf4591d1 MK |
811 | } |
812 | ||
46b3617d CW |
813 | static void clear_gtiir(struct intel_engine_cs *engine) |
814 | { | |
46b3617d CW |
815 | struct drm_i915_private *dev_priv = engine->i915; |
816 | int i; | |
817 | ||
46b3617d CW |
818 | /* |
819 | * Clear any pending interrupt state. | |
820 | * | |
821 | * We do it twice out of paranoia that some of the IIR are | |
822 | * double buffered, and so if we only reset it once there may | |
823 | * still be an interrupt pending. | |
824 | */ | |
ff047a87 OM |
825 | if (INTEL_GEN(dev_priv) >= 11) { |
826 | static const struct { | |
827 | u8 bank; | |
828 | u8 bit; | |
829 | } gen11_gtiir[] = { | |
830 | [RCS] = {0, GEN11_RCS0}, | |
831 | [BCS] = {0, GEN11_BCS}, | |
832 | [_VCS(0)] = {1, GEN11_VCS(0)}, | |
833 | [_VCS(1)] = {1, GEN11_VCS(1)}, | |
834 | [_VCS(2)] = {1, GEN11_VCS(2)}, | |
835 | [_VCS(3)] = {1, GEN11_VCS(3)}, | |
836 | [_VECS(0)] = {1, GEN11_VECS(0)}, | |
837 | [_VECS(1)] = {1, GEN11_VECS(1)}, | |
838 | }; | |
839 | unsigned long irqflags; | |
840 | ||
841 | GEM_BUG_ON(engine->id >= ARRAY_SIZE(gen11_gtiir)); | |
842 | ||
843 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
844 | for (i = 0; i < 2; i++) { | |
845 | gen11_reset_one_iir(dev_priv, | |
846 | gen11_gtiir[engine->id].bank, | |
847 | gen11_gtiir[engine->id].bit); | |
848 | } | |
849 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
850 | } else { | |
851 | static const u8 gtiir[] = { | |
852 | [RCS] = 0, | |
853 | [BCS] = 0, | |
854 | [VCS] = 1, | |
855 | [VCS2] = 1, | |
856 | [VECS] = 3, | |
857 | }; | |
858 | ||
859 | GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); | |
860 | ||
861 | for (i = 0; i < 2; i++) { | |
862 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
863 | engine->irq_keep_mask); | |
864 | POSTING_READ(GEN8_GT_IIR(gtiir[engine->id])); | |
865 | } | |
866 | GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) & | |
46b3617d | 867 | engine->irq_keep_mask); |
46b3617d | 868 | } |
46b3617d CW |
869 | } |
870 | ||
871 | static void reset_irq(struct intel_engine_cs *engine) | |
872 | { | |
873 | /* Mark all CS interrupts as complete */ | |
874 | smp_store_mb(engine->execlists.active, 0); | |
875 | synchronize_hardirq(engine->i915->drm.irq); | |
876 | ||
877 | clear_gtiir(engine); | |
878 | ||
879 | /* | |
880 | * The port is checked prior to scheduling a tasklet, but | |
881 | * just in case we have suspended the tasklet to do the | |
882 | * wedging make sure that when it wakes, it decides there | |
883 | * is no work to do by clearing the irq_posted bit. | |
884 | */ | |
885 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
886 | } | |
887 | ||
27a5f61b CW |
888 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
889 | { | |
b620e870 | 890 | struct intel_engine_execlists * const execlists = &engine->execlists; |
e61e0f51 | 891 | struct i915_request *rq, *rn; |
27a5f61b CW |
892 | struct rb_node *rb; |
893 | unsigned long flags; | |
27a5f61b | 894 | |
0c5c7df3 TU |
895 | GEM_TRACE("%s current %d\n", |
896 | engine->name, intel_engine_get_seqno(engine)); | |
963ddd63 | 897 | |
a3e38836 CW |
898 | /* |
899 | * Before we call engine->cancel_requests(), we should have exclusive | |
900 | * access to the submission state. This is arranged for us by the | |
901 | * caller disabling the interrupt generation, the tasklet and other | |
902 | * threads that may then access the same state, giving us a free hand | |
903 | * to reset state. However, we still need to let lockdep be aware that | |
904 | * we know this state may be accessed in hardirq context, so we | |
905 | * disable the irq around this manipulation and we want to keep | |
906 | * the spinlock focused on its duties and not accidentally conflate | |
907 | * coverage to the submission's irq state. (Similarly, although we | |
908 | * shouldn't need to disable irq around the manipulation of the | |
909 | * submission's irq state, we also wish to remind ourselves that | |
910 | * it is irq state.) | |
911 | */ | |
912 | local_irq_save(flags); | |
27a5f61b CW |
913 | |
914 | /* Cancel the requests on the HW and clear the ELSP tracker. */ | |
a4598d17 | 915 | execlists_cancel_port_requests(execlists); |
46b3617d | 916 | reset_irq(engine); |
27a5f61b | 917 | |
a89d1f92 | 918 | spin_lock(&engine->timeline.lock); |
a3e38836 | 919 | |
27a5f61b | 920 | /* Mark all executing requests as skipped. */ |
a89d1f92 | 921 | list_for_each_entry(rq, &engine->timeline.requests, link) { |
27a5f61b | 922 | GEM_BUG_ON(!rq->global_seqno); |
e61e0f51 | 923 | if (!i915_request_completed(rq)) |
27a5f61b CW |
924 | dma_fence_set_error(&rq->fence, -EIO); |
925 | } | |
926 | ||
927 | /* Flush the queued requests to the timeline list (for retiring). */ | |
b620e870 | 928 | rb = execlists->first; |
27a5f61b | 929 | while (rb) { |
f6322edd | 930 | struct i915_priolist *p = to_priolist(rb); |
27a5f61b | 931 | |
0c7112a0 CW |
932 | list_for_each_entry_safe(rq, rn, &p->requests, sched.link) { |
933 | INIT_LIST_HEAD(&rq->sched.link); | |
27a5f61b CW |
934 | |
935 | dma_fence_set_error(&rq->fence, -EIO); | |
e61e0f51 | 936 | __i915_request_submit(rq); |
27a5f61b CW |
937 | } |
938 | ||
939 | rb = rb_next(rb); | |
b620e870 | 940 | rb_erase(&p->node, &execlists->queue); |
27a5f61b CW |
941 | INIT_LIST_HEAD(&p->requests); |
942 | if (p->priority != I915_PRIORITY_NORMAL) | |
943 | kmem_cache_free(engine->i915->priorities, p); | |
944 | } | |
945 | ||
946 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
947 | ||
f6322edd | 948 | execlists->queue_priority = INT_MIN; |
b620e870 MK |
949 | execlists->queue = RB_ROOT; |
950 | execlists->first = NULL; | |
3f9e6cd8 | 951 | GEM_BUG_ON(port_isset(execlists->port)); |
27a5f61b | 952 | |
a89d1f92 | 953 | spin_unlock(&engine->timeline.lock); |
a3e38836 | 954 | |
a3e38836 | 955 | local_irq_restore(flags); |
27a5f61b CW |
956 | } |
957 | ||
73377dbc | 958 | static void process_csb(struct intel_engine_cs *engine) |
e981e7b1 | 959 | { |
b620e870 | 960 | struct intel_engine_execlists * const execlists = &engine->execlists; |
f2605207 | 961 | struct execlist_port *port = execlists->port; |
73377dbc | 962 | struct drm_i915_private *i915 = engine->i915; |
bb5db7e1 | 963 | bool fw = false; |
c6a2ac71 | 964 | |
73377dbc | 965 | do { |
6d2cb5aa CW |
966 | /* The HWSP contains a (cacheable) mirror of the CSB */ |
967 | const u32 *buf = | |
968 | &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; | |
4af0d727 | 969 | unsigned int head, tail; |
70c2a24d | 970 | |
9153e6b7 CW |
971 | /* Clear before reading to catch new interrupts */ |
972 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
973 | smp_mb__after_atomic(); | |
974 | ||
b2209e62 | 975 | if (unlikely(execlists->csb_use_mmio)) { |
bb5db7e1 | 976 | if (!fw) { |
73377dbc | 977 | intel_uncore_forcewake_get(i915, execlists->fw_domains); |
bb5db7e1 CW |
978 | fw = true; |
979 | } | |
980 | ||
b2209e62 CW |
981 | buf = (u32 * __force) |
982 | (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); | |
983 | ||
73377dbc | 984 | head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); |
767a983a CW |
985 | tail = GEN8_CSB_WRITE_PTR(head); |
986 | head = GEN8_CSB_READ_PTR(head); | |
b620e870 | 987 | execlists->csb_head = head; |
767a983a CW |
988 | } else { |
989 | const int write_idx = | |
73377dbc | 990 | intel_hws_csb_write_index(i915) - |
767a983a CW |
991 | I915_HWS_CSB_BUF0_INDEX; |
992 | ||
b620e870 | 993 | head = execlists->csb_head; |
767a983a | 994 | tail = READ_ONCE(buf[write_idx]); |
77dfedb5 | 995 | rmb(); /* Hopefully paired with a wmb() in HW */ |
767a983a | 996 | } |
bb5db7e1 | 997 | GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n", |
bccd3b83 | 998 | engine->name, |
73377dbc CW |
999 | head, GEN8_CSB_READ_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?", |
1000 | tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?"); | |
b620e870 | 1001 | |
4af0d727 | 1002 | while (head != tail) { |
e61e0f51 | 1003 | struct i915_request *rq; |
4af0d727 | 1004 | unsigned int status; |
77f0d0e9 | 1005 | unsigned int count; |
4af0d727 CW |
1006 | |
1007 | if (++head == GEN8_CSB_ENTRIES) | |
1008 | head = 0; | |
70c2a24d | 1009 | |
73377dbc CW |
1010 | /* |
1011 | * We are flying near dragons again. | |
2ffe80aa CW |
1012 | * |
1013 | * We hold a reference to the request in execlist_port[] | |
1014 | * but no more than that. We are operating in softirq | |
1015 | * context and so cannot hold any mutex or sleep. That | |
1016 | * prevents us stopping the requests we are processing | |
1017 | * in port[] from being retired simultaneously (the | |
1018 | * breadcrumb will be complete before we see the | |
1019 | * context-switch). As we only hold the reference to the | |
1020 | * request, any pointer chasing underneath the request | |
1021 | * is subject to a potential use-after-free. Thus we | |
1022 | * store all of the bookkeeping within port[] as | |
1023 | * required, and avoid using unguarded pointers beneath | |
1024 | * request itself. The same applies to the atomic | |
1025 | * status notifier. | |
1026 | */ | |
1027 | ||
6d2cb5aa | 1028 | status = READ_ONCE(buf[2 * head]); /* maybe mmio! */ |
193a98dc | 1029 | GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", |
bccd3b83 | 1030 | engine->name, head, |
193a98dc CW |
1031 | status, buf[2*head + 1], |
1032 | execlists->active); | |
ba74cb10 MT |
1033 | |
1034 | if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | | |
1035 | GEN8_CTX_STATUS_PREEMPTED)) | |
1036 | execlists_set_active(execlists, | |
1037 | EXECLISTS_ACTIVE_HWACK); | |
1038 | if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) | |
1039 | execlists_clear_active(execlists, | |
1040 | EXECLISTS_ACTIVE_HWACK); | |
1041 | ||
70c2a24d CW |
1042 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
1043 | continue; | |
1044 | ||
1f5f9edb CW |
1045 | /* We should never get a COMPLETED | IDLE_ACTIVE! */ |
1046 | GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); | |
1047 | ||
e40dd226 | 1048 | if (status & GEN8_CTX_STATUS_COMPLETE && |
d6376374 | 1049 | buf[2*head + 1] == execlists->preempt_complete_status) { |
193a98dc | 1050 | GEM_TRACE("%s preempt-idle\n", engine->name); |
ef2fb720 | 1051 | complete_preempt_context(execlists); |
beecec90 CW |
1052 | continue; |
1053 | } | |
1054 | ||
1055 | if (status & GEN8_CTX_STATUS_PREEMPTED && | |
4a118ecb CW |
1056 | execlists_is_active(execlists, |
1057 | EXECLISTS_ACTIVE_PREEMPT)) | |
beecec90 CW |
1058 | continue; |
1059 | ||
4a118ecb CW |
1060 | GEM_BUG_ON(!execlists_is_active(execlists, |
1061 | EXECLISTS_ACTIVE_USER)); | |
1062 | ||
77f0d0e9 | 1063 | rq = port_unpack(port, &count); |
0c5c7df3 | 1064 | GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n", |
bccd3b83 | 1065 | engine->name, |
16c8619a | 1066 | port->context_id, count, |
f6322edd | 1067 | rq ? rq->global_seqno : 0, |
0c5c7df3 TU |
1068 | rq ? rq->fence.context : 0, |
1069 | rq ? rq->fence.seqno : 0, | |
e7702760 | 1070 | intel_engine_get_seqno(engine), |
f6322edd | 1071 | rq ? rq_prio(rq) : 0); |
e084039b CW |
1072 | |
1073 | /* Check the context/desc id for this event matches */ | |
1074 | GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); | |
1075 | ||
77f0d0e9 CW |
1076 | GEM_BUG_ON(count == 0); |
1077 | if (--count == 0) { | |
f2605207 CW |
1078 | /* |
1079 | * On the final event corresponding to the | |
1080 | * submission of this context, we expect either | |
1081 | * an element-switch event or a completion | |
1082 | * event (and on completion, the active-idle | |
1083 | * marker). No more preemptions, lite-restore | |
1084 | * or otherwise. | |
1085 | */ | |
70c2a24d | 1086 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
d8747afb CW |
1087 | GEM_BUG_ON(port_isset(&port[1]) && |
1088 | !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); | |
f2605207 CW |
1089 | GEM_BUG_ON(!port_isset(&port[1]) && |
1090 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
1091 | ||
1092 | /* | |
1093 | * We rely on the hardware being strongly | |
1094 | * ordered, that the breadcrumb write is | |
1095 | * coherent (visible from the CPU) before the | |
1096 | * user interrupt and CSB is processed. | |
1097 | */ | |
e61e0f51 | 1098 | GEM_BUG_ON(!i915_request_completed(rq)); |
f2605207 | 1099 | |
b9b77426 CW |
1100 | execlists_context_schedule_out(rq, |
1101 | INTEL_CONTEXT_SCHEDULE_OUT); | |
e61e0f51 | 1102 | i915_request_put(rq); |
70c2a24d | 1103 | |
65cb8c0f CW |
1104 | GEM_TRACE("%s completed ctx=%d\n", |
1105 | engine->name, port->context_id); | |
1106 | ||
f2605207 CW |
1107 | port = execlists_port_complete(execlists, port); |
1108 | if (port_isset(port)) | |
1109 | execlists_user_begin(execlists, port); | |
1110 | else | |
1111 | execlists_user_end(execlists); | |
77f0d0e9 CW |
1112 | } else { |
1113 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 1114 | } |
4af0d727 | 1115 | } |
e1fee72c | 1116 | |
b620e870 MK |
1117 | if (head != execlists->csb_head) { |
1118 | execlists->csb_head = head; | |
767a983a | 1119 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
73377dbc | 1120 | i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); |
767a983a | 1121 | } |
73377dbc | 1122 | } while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)); |
e981e7b1 | 1123 | |
73377dbc CW |
1124 | if (unlikely(fw)) |
1125 | intel_uncore_forcewake_put(i915, execlists->fw_domains); | |
1126 | } | |
c6a2ac71 | 1127 | |
73377dbc CW |
1128 | /* |
1129 | * Check the unread Context Status Buffers and manage the submission of new | |
1130 | * contexts to the ELSP accordingly. | |
1131 | */ | |
1132 | static void execlists_submission_tasklet(unsigned long data) | |
1133 | { | |
1134 | struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; | |
1135 | ||
1136 | GEM_TRACE("%s awake?=%d, active=%x, irq-posted?=%d\n", | |
1137 | engine->name, | |
1138 | engine->i915->gt.awake, | |
1139 | engine->execlists.active, | |
1140 | test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)); | |
1141 | ||
1142 | /* | |
1143 | * We can skip acquiring intel_runtime_pm_get() here as it was taken | |
1144 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
1145 | * not be relinquished until the device is idle (see | |
1146 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
1147 | * that all ELSP are drained i.e. we have processed the CSB, | |
1148 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
1149 | */ | |
1150 | GEM_BUG_ON(!engine->i915->gt.awake); | |
1151 | ||
1152 | /* | |
1153 | * Prefer doing test_and_clear_bit() as a two stage operation to avoid | |
1154 | * imposing the cost of a locked atomic transaction when submitting a | |
1155 | * new request (outside of the context-switch interrupt). | |
1156 | */ | |
1157 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
1158 | process_csb(engine); | |
1159 | ||
1160 | if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) | |
1161 | execlists_dequeue(engine); | |
e981e7b1 TD |
1162 | } |
1163 | ||
f6322edd | 1164 | static void queue_request(struct intel_engine_cs *engine, |
0c7112a0 | 1165 | struct i915_sched_node *node, |
f6322edd | 1166 | int prio) |
27606fd8 | 1167 | { |
0c7112a0 | 1168 | list_add_tail(&node->link, |
87c7acf8 | 1169 | &lookup_priolist(engine, prio)->requests); |
f6322edd | 1170 | } |
27606fd8 | 1171 | |
ae2f5c00 CW |
1172 | static void __submit_queue(struct intel_engine_cs *engine, int prio) |
1173 | { | |
1174 | engine->execlists.queue_priority = prio; | |
1175 | tasklet_hi_schedule(&engine->execlists.tasklet); | |
1176 | } | |
1177 | ||
f6322edd CW |
1178 | static void submit_queue(struct intel_engine_cs *engine, int prio) |
1179 | { | |
ae2f5c00 CW |
1180 | if (prio > engine->execlists.queue_priority) |
1181 | __submit_queue(engine, prio); | |
27606fd8 CW |
1182 | } |
1183 | ||
e61e0f51 | 1184 | static void execlists_submit_request(struct i915_request *request) |
acdd884a | 1185 | { |
4a570db5 | 1186 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 1187 | unsigned long flags; |
acdd884a | 1188 | |
663f71e7 | 1189 | /* Will be called from irq-context when using foreign fences. */ |
a89d1f92 | 1190 | spin_lock_irqsave(&engine->timeline.lock, flags); |
acdd884a | 1191 | |
0c7112a0 | 1192 | queue_request(engine, &request->sched, rq_prio(request)); |
f6322edd | 1193 | submit_queue(engine, rq_prio(request)); |
acdd884a | 1194 | |
b620e870 | 1195 | GEM_BUG_ON(!engine->execlists.first); |
0c7112a0 | 1196 | GEM_BUG_ON(list_empty(&request->sched.link)); |
6c067579 | 1197 | |
a89d1f92 | 1198 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
acdd884a MT |
1199 | } |
1200 | ||
0c7112a0 | 1201 | static struct i915_request *sched_to_request(struct i915_sched_node *node) |
1f181225 | 1202 | { |
0c7112a0 | 1203 | return container_of(node, struct i915_request, sched); |
1f181225 CW |
1204 | } |
1205 | ||
20311bd3 | 1206 | static struct intel_engine_cs * |
0c7112a0 | 1207 | sched_lock_engine(struct i915_sched_node *node, struct intel_engine_cs *locked) |
20311bd3 | 1208 | { |
0c7112a0 | 1209 | struct intel_engine_cs *engine = sched_to_request(node)->engine; |
a79a524e CW |
1210 | |
1211 | GEM_BUG_ON(!locked); | |
20311bd3 | 1212 | |
20311bd3 | 1213 | if (engine != locked) { |
a89d1f92 CW |
1214 | spin_unlock(&locked->timeline.lock); |
1215 | spin_lock(&engine->timeline.lock); | |
20311bd3 CW |
1216 | } |
1217 | ||
1218 | return engine; | |
1219 | } | |
1220 | ||
b7268c5e CW |
1221 | static void execlists_schedule(struct i915_request *request, |
1222 | const struct i915_sched_attr *attr) | |
20311bd3 | 1223 | { |
a02eb975 CW |
1224 | struct i915_priolist *uninitialized_var(pl); |
1225 | struct intel_engine_cs *engine, *last; | |
20311bd3 CW |
1226 | struct i915_dependency *dep, *p; |
1227 | struct i915_dependency stack; | |
b7268c5e | 1228 | const int prio = attr->priority; |
20311bd3 CW |
1229 | LIST_HEAD(dfs); |
1230 | ||
7d1ea609 CW |
1231 | GEM_BUG_ON(prio == I915_PRIORITY_INVALID); |
1232 | ||
e61e0f51 | 1233 | if (i915_request_completed(request)) |
c218ee03 CW |
1234 | return; |
1235 | ||
b7268c5e | 1236 | if (prio <= READ_ONCE(request->sched.attr.priority)) |
20311bd3 CW |
1237 | return; |
1238 | ||
70cd1476 CW |
1239 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
1240 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 | 1241 | |
0c7112a0 | 1242 | stack.signaler = &request->sched; |
20311bd3 CW |
1243 | list_add(&stack.dfs_link, &dfs); |
1244 | ||
ce01b173 CW |
1245 | /* |
1246 | * Recursively bump all dependent priorities to match the new request. | |
20311bd3 CW |
1247 | * |
1248 | * A naive approach would be to use recursion: | |
0c7112a0 CW |
1249 | * static void update_priorities(struct i915_sched_node *node, prio) { |
1250 | * list_for_each_entry(dep, &node->signalers_list, signal_link) | |
20311bd3 | 1251 | * update_priorities(dep->signal, prio) |
0c7112a0 | 1252 | * queue_request(node); |
20311bd3 CW |
1253 | * } |
1254 | * but that may have unlimited recursion depth and so runs a very | |
1255 | * real risk of overunning the kernel stack. Instead, we build | |
1256 | * a flat list of all dependencies starting with the current request. | |
1257 | * As we walk the list of dependencies, we add all of its dependencies | |
1258 | * to the end of the list (this may include an already visited | |
1259 | * request) and continue to walk onwards onto the new dependencies. The | |
1260 | * end result is a topological list of requests in reverse order, the | |
1261 | * last element in the list is the request we must execute first. | |
1262 | */ | |
2221c5b7 | 1263 | list_for_each_entry(dep, &dfs, dfs_link) { |
0c7112a0 | 1264 | struct i915_sched_node *node = dep->signaler; |
20311bd3 | 1265 | |
ce01b173 CW |
1266 | /* |
1267 | * Within an engine, there can be no cycle, but we may | |
a79a524e CW |
1268 | * refer to the same dependency chain multiple times |
1269 | * (redundant dependencies are not eliminated) and across | |
1270 | * engines. | |
1271 | */ | |
0c7112a0 | 1272 | list_for_each_entry(p, &node->signalers_list, signal_link) { |
ce01b173 CW |
1273 | GEM_BUG_ON(p == dep); /* no cycles! */ |
1274 | ||
0c7112a0 | 1275 | if (i915_sched_node_signaled(p->signaler)) |
1f181225 CW |
1276 | continue; |
1277 | ||
b7268c5e CW |
1278 | GEM_BUG_ON(p->signaler->attr.priority < node->attr.priority); |
1279 | if (prio > READ_ONCE(p->signaler->attr.priority)) | |
20311bd3 | 1280 | list_move_tail(&p->dfs_link, &dfs); |
a79a524e | 1281 | } |
20311bd3 CW |
1282 | } |
1283 | ||
ce01b173 CW |
1284 | /* |
1285 | * If we didn't need to bump any existing priorities, and we haven't | |
349bdb68 CW |
1286 | * yet submitted this request (i.e. there is no potential race with |
1287 | * execlists_submit_request()), we can set our own priority and skip | |
1288 | * acquiring the engine locks. | |
1289 | */ | |
b7268c5e | 1290 | if (request->sched.attr.priority == I915_PRIORITY_INVALID) { |
0c7112a0 | 1291 | GEM_BUG_ON(!list_empty(&request->sched.link)); |
b7268c5e | 1292 | request->sched.attr = *attr; |
349bdb68 CW |
1293 | if (stack.dfs_link.next == stack.dfs_link.prev) |
1294 | return; | |
1295 | __list_del_entry(&stack.dfs_link); | |
1296 | } | |
1297 | ||
a02eb975 | 1298 | last = NULL; |
a79a524e | 1299 | engine = request->engine; |
a89d1f92 | 1300 | spin_lock_irq(&engine->timeline.lock); |
a79a524e | 1301 | |
20311bd3 CW |
1302 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
1303 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
0c7112a0 | 1304 | struct i915_sched_node *node = dep->signaler; |
20311bd3 CW |
1305 | |
1306 | INIT_LIST_HEAD(&dep->dfs_link); | |
1307 | ||
0c7112a0 | 1308 | engine = sched_lock_engine(node, engine); |
20311bd3 | 1309 | |
b7268c5e | 1310 | if (prio <= node->attr.priority) |
20311bd3 CW |
1311 | continue; |
1312 | ||
b7268c5e | 1313 | node->attr.priority = prio; |
0c7112a0 | 1314 | if (!list_empty(&node->link)) { |
a02eb975 CW |
1315 | if (last != engine) { |
1316 | pl = lookup_priolist(engine, prio); | |
1317 | last = engine; | |
1318 | } | |
1319 | GEM_BUG_ON(pl->priority != prio); | |
1320 | list_move_tail(&node->link, &pl->requests); | |
a79a524e | 1321 | } |
ae2f5c00 CW |
1322 | |
1323 | if (prio > engine->execlists.queue_priority && | |
0c7112a0 | 1324 | i915_sw_fence_done(&sched_to_request(node)->submit)) |
ae2f5c00 | 1325 | __submit_queue(engine, prio); |
20311bd3 CW |
1326 | } |
1327 | ||
a89d1f92 | 1328 | spin_unlock_irq(&engine->timeline.lock); |
20311bd3 CW |
1329 | } |
1330 | ||
1fc44d9b CW |
1331 | static void execlists_context_destroy(struct intel_context *ce) |
1332 | { | |
1fc44d9b CW |
1333 | GEM_BUG_ON(ce->pin_count); |
1334 | ||
dd12c6ca CW |
1335 | if (!ce->state) |
1336 | return; | |
1337 | ||
1fc44d9b | 1338 | intel_ring_free(ce->ring); |
efe79d48 CW |
1339 | |
1340 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1341 | i915_gem_object_put(ce->state->obj); | |
1fc44d9b CW |
1342 | } |
1343 | ||
867985d4 | 1344 | static void execlists_context_unpin(struct intel_context *ce) |
1fc44d9b CW |
1345 | { |
1346 | intel_ring_unpin(ce->ring); | |
1347 | ||
1348 | ce->state->obj->pin_global--; | |
1349 | i915_gem_object_unpin_map(ce->state->obj); | |
1350 | i915_vma_unpin(ce->state); | |
1351 | ||
1352 | i915_gem_context_put(ce->gem_context); | |
1353 | } | |
1354 | ||
f4e15af7 CW |
1355 | static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma) |
1356 | { | |
1357 | unsigned int flags; | |
1358 | int err; | |
1359 | ||
1360 | /* | |
1361 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
1362 | * We only want to do this on the first bind so that we do not stall | |
1363 | * on an active context (which by nature is already on the GPU). | |
1364 | */ | |
1365 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
1366 | err = i915_gem_object_set_to_gtt_domain(vma->obj, true); | |
1367 | if (err) | |
1368 | return err; | |
1369 | } | |
1370 | ||
1371 | flags = PIN_GLOBAL | PIN_HIGH; | |
1372 | if (ctx->ggtt_offset_bias) | |
1373 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
1374 | ||
1375 | return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
1376 | } | |
1377 | ||
1fc44d9b CW |
1378 | static struct intel_context * |
1379 | __execlists_context_pin(struct intel_engine_cs *engine, | |
1380 | struct i915_gem_context *ctx, | |
1381 | struct intel_context *ce) | |
dcb4c12a | 1382 | { |
7d774cac | 1383 | void *vaddr; |
ca82580c | 1384 | int ret; |
dcb4c12a | 1385 | |
1fc44d9b | 1386 | ret = execlists_context_deferred_alloc(ctx, engine, ce); |
1d2a19c2 CW |
1387 | if (ret) |
1388 | goto err; | |
56f6e0a7 | 1389 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 1390 | |
f4e15af7 | 1391 | ret = __context_pin(ctx, ce->state); |
e84fe803 | 1392 | if (ret) |
24f1d3cc | 1393 | goto err; |
7ba717cf | 1394 | |
bf3783e5 | 1395 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
1396 | if (IS_ERR(vaddr)) { |
1397 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 1398 | goto unpin_vma; |
82352e90 TU |
1399 | } |
1400 | ||
d822bb18 | 1401 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 1402 | if (ret) |
7d774cac | 1403 | goto unpin_map; |
d1675198 | 1404 | |
1fc44d9b | 1405 | intel_lr_context_descriptor_update(ctx, engine, ce); |
9021ad03 | 1406 | |
a3aabe86 CW |
1407 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
1408 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 1409 | i915_ggtt_offset(ce->ring->vma); |
41d37680 | 1410 | GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head)); |
c216e906 | 1411 | ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head; |
a3aabe86 | 1412 | |
3d574a6b | 1413 | ce->state->obj->pin_global++; |
9a6feaf0 | 1414 | i915_gem_context_get(ctx); |
1fc44d9b | 1415 | return ce; |
7ba717cf | 1416 | |
7d774cac | 1417 | unpin_map: |
bf3783e5 CW |
1418 | i915_gem_object_unpin_map(ce->state->obj); |
1419 | unpin_vma: | |
1420 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 1421 | err: |
9021ad03 | 1422 | ce->pin_count = 0; |
266a240b | 1423 | return ERR_PTR(ret); |
e84fe803 NH |
1424 | } |
1425 | ||
1fc44d9b CW |
1426 | static const struct intel_context_ops execlists_context_ops = { |
1427 | .unpin = execlists_context_unpin, | |
1428 | .destroy = execlists_context_destroy, | |
1429 | }; | |
1430 | ||
1431 | static struct intel_context * | |
1432 | execlists_context_pin(struct intel_engine_cs *engine, | |
1433 | struct i915_gem_context *ctx) | |
e84fe803 | 1434 | { |
ab82a063 | 1435 | struct intel_context *ce = to_intel_context(ctx, engine); |
e84fe803 | 1436 | |
91c8a326 | 1437 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
321fe304 | 1438 | |
1fc44d9b CW |
1439 | if (likely(ce->pin_count++)) |
1440 | return ce; | |
1441 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ | |
dcb4c12a | 1442 | |
1fc44d9b | 1443 | ce->ops = &execlists_context_ops; |
321fe304 | 1444 | |
1fc44d9b | 1445 | return __execlists_context_pin(engine, ctx, ce); |
dcb4c12a OM |
1446 | } |
1447 | ||
e61e0f51 | 1448 | static int execlists_request_alloc(struct i915_request *request) |
ef11c01d | 1449 | { |
fd138212 | 1450 | int ret; |
ef11c01d | 1451 | |
1fc44d9b | 1452 | GEM_BUG_ON(!request->hw_context->pin_count); |
e8a9c58f | 1453 | |
ef11c01d CW |
1454 | /* Flush enough space to reduce the likelihood of waiting after |
1455 | * we start building the request - in which case we will just | |
1456 | * have to repeat work. | |
1457 | */ | |
1458 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
1459 | ||
fd138212 CW |
1460 | ret = intel_ring_wait_for_space(request->ring, request->reserved_space); |
1461 | if (ret) | |
1462 | return ret; | |
ef11c01d | 1463 | |
ef11c01d CW |
1464 | /* Note that after this point, we have committed to using |
1465 | * this request as it is being used to both track the | |
1466 | * state of engine initialisation and liveness of the | |
1467 | * golden renderstate above. Think twice before you try | |
1468 | * to cancel/unwind this request now. | |
1469 | */ | |
1470 | ||
1471 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
1472 | return 0; | |
ef11c01d CW |
1473 | } |
1474 | ||
9e000847 AS |
1475 | /* |
1476 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1477 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1478 | * but there is a slight complication as this is applied in WA batch where the | |
1479 | * values are only initialized once so we cannot take register value at the | |
1480 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1481 | * constant value with bit21 set and then we restore it back with the saved value. | |
1482 | * To simplify the WA, a constant value is formed by using the default value | |
1483 | * of this register. This shouldn't be a problem because we are only modifying | |
1484 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1485 | * use additional instructions that read the actual value of the register | |
1486 | * at that time and set our bit of interest but it makes the WA complicated. | |
1487 | * | |
1488 | * This WA is also required for Gen9 so extracting as a function avoids | |
1489 | * code duplication. | |
1490 | */ | |
097d4f1c TU |
1491 | static u32 * |
1492 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 1493 | { |
097d4f1c TU |
1494 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
1495 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1496 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1497 | *batch++ = 0; | |
1498 | ||
1499 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
1500 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1501 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
1502 | ||
9f235dfa TU |
1503 | batch = gen8_emit_pipe_control(batch, |
1504 | PIPE_CONTROL_CS_STALL | | |
1505 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1506 | 0); | |
097d4f1c TU |
1507 | |
1508 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
1509 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1510 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1511 | *batch++ = 0; | |
1512 | ||
1513 | return batch; | |
17ee950d AS |
1514 | } |
1515 | ||
6e5248b5 DV |
1516 | /* |
1517 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1518 | * initialized at the beginning and shared across all contexts but this field | |
1519 | * helps us to have multiple batches at different offsets and select them based | |
1520 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1521 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1522 | * |
6e5248b5 DV |
1523 | * The number of WA applied are not known at the beginning; we use this field |
1524 | * to return the no of DWORDS written. | |
17ee950d | 1525 | * |
6e5248b5 DV |
1526 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1527 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1528 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1529 | * makes a complete batch buffer. | |
17ee950d | 1530 | */ |
097d4f1c | 1531 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1532 | { |
7ad00d1a | 1533 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1534 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1535 | |
c82435bb | 1536 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1537 | if (IS_BROADWELL(engine->i915)) |
1538 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1539 | |
0160f055 AS |
1540 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1541 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1542 | batch = gen8_emit_pipe_control(batch, |
1543 | PIPE_CONTROL_FLUSH_L3 | | |
1544 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1545 | PIPE_CONTROL_CS_STALL | | |
1546 | PIPE_CONTROL_QW_WRITE, | |
1547 | i915_ggtt_offset(engine->scratch) + | |
1548 | 2 * CACHELINE_BYTES); | |
0160f055 | 1549 | |
beecec90 CW |
1550 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1551 | ||
17ee950d | 1552 | /* Pad to end of cacheline */ |
097d4f1c TU |
1553 | while ((unsigned long)batch % CACHELINE_BYTES) |
1554 | *batch++ = MI_NOOP; | |
17ee950d AS |
1555 | |
1556 | /* | |
1557 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1558 | * execution depends on the length specified in terms of cache lines | |
1559 | * in the register CTX_RCS_INDIRECT_CTX | |
1560 | */ | |
1561 | ||
097d4f1c | 1562 | return batch; |
17ee950d AS |
1563 | } |
1564 | ||
5ee4a7a6 CW |
1565 | struct lri { |
1566 | i915_reg_t reg; | |
1567 | u32 value; | |
1568 | }; | |
1569 | ||
1570 | static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) | |
0504cffc | 1571 | { |
5ee4a7a6 | 1572 | GEM_BUG_ON(!count || count > 63); |
beecec90 | 1573 | |
5ee4a7a6 CW |
1574 | *batch++ = MI_LOAD_REGISTER_IMM(count); |
1575 | do { | |
1576 | *batch++ = i915_mmio_reg_offset(lri->reg); | |
1577 | *batch++ = lri->value; | |
1578 | } while (lri++, --count); | |
1579 | *batch++ = MI_NOOP; | |
a4106a78 | 1580 | |
5ee4a7a6 CW |
1581 | return batch; |
1582 | } | |
b77422f8 | 1583 | |
5ee4a7a6 CW |
1584 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
1585 | { | |
1586 | static const struct lri lri[] = { | |
1587 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ | |
1588 | { | |
1589 | COMMON_SLICE_CHICKEN2, | |
1590 | __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, | |
1591 | 0), | |
1592 | }, | |
1593 | ||
1594 | /* BSpec: 11391 */ | |
1595 | { | |
1596 | FF_SLICE_CHICKEN, | |
1597 | __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, | |
1598 | FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), | |
1599 | }, | |
1600 | ||
1601 | /* BSpec: 11299 */ | |
1602 | { | |
1603 | _3D_CHICKEN3, | |
1604 | __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, | |
1605 | _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), | |
1606 | } | |
1607 | }; | |
b77422f8 | 1608 | |
5ee4a7a6 | 1609 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
b77422f8 | 1610 | |
5ee4a7a6 CW |
1611 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
1612 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
b77422f8 | 1613 | |
5ee4a7a6 | 1614 | batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); |
873e8171 | 1615 | |
066d4628 MK |
1616 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1617 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1618 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1619 | batch = gen8_emit_pipe_control(batch, |
1620 | PIPE_CONTROL_FLUSH_L3 | | |
1621 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1622 | PIPE_CONTROL_CS_STALL | | |
1623 | PIPE_CONTROL_QW_WRITE, | |
1624 | i915_ggtt_offset(engine->scratch) | |
1625 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1626 | } |
3485d99e | 1627 | |
9fb5026f | 1628 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1629 | if (HAS_POOLED_EU(engine->i915)) { |
1630 | /* | |
1631 | * EU pool configuration is setup along with golden context | |
1632 | * during context initialization. This value depends on | |
1633 | * device type (2x6 or 3x6) and needs to be updated based | |
1634 | * on which subslice is disabled especially for 2x6 | |
1635 | * devices, however it is safe to load default | |
1636 | * configuration of 3x6 device instead of masking off | |
1637 | * corresponding bits because HW ignores bits of a disabled | |
1638 | * subslice and drops down to appropriate config. Please | |
1639 | * see render_state_setup() in i915_gem_render_state.c for | |
1640 | * possible configurations, to avoid duplication they are | |
1641 | * not shown here again. | |
1642 | */ | |
097d4f1c TU |
1643 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1644 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1645 | *batch++ = 0x00777000; | |
1646 | *batch++ = 0; | |
1647 | *batch++ = 0; | |
1648 | *batch++ = 0; | |
3485d99e TG |
1649 | } |
1650 | ||
beecec90 CW |
1651 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1652 | ||
0504cffc | 1653 | /* Pad to end of cacheline */ |
097d4f1c TU |
1654 | while ((unsigned long)batch % CACHELINE_BYTES) |
1655 | *batch++ = MI_NOOP; | |
0504cffc | 1656 | |
097d4f1c | 1657 | return batch; |
0504cffc AS |
1658 | } |
1659 | ||
4b6ce681 RA |
1660 | static u32 * |
1661 | gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) | |
1662 | { | |
1663 | int i; | |
1664 | ||
1665 | /* | |
1666 | * WaPipeControlBefore3DStateSamplePattern: cnl | |
1667 | * | |
1668 | * Ensure the engine is idle prior to programming a | |
1669 | * 3DSTATE_SAMPLE_PATTERN during a context restore. | |
1670 | */ | |
1671 | batch = gen8_emit_pipe_control(batch, | |
1672 | PIPE_CONTROL_CS_STALL, | |
1673 | 0); | |
1674 | /* | |
1675 | * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for | |
1676 | * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in | |
1677 | * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is | |
1678 | * confusing. Since gen8_emit_pipe_control() already advances the | |
1679 | * batch by 6 dwords, we advance the other 10 here, completing a | |
1680 | * cacheline. It's not clear if the workaround requires this padding | |
1681 | * before other commands, or if it's just the regular padding we would | |
1682 | * already have for the workaround bb, so leave it here for now. | |
1683 | */ | |
1684 | for (i = 0; i < 10; i++) | |
1685 | *batch++ = MI_NOOP; | |
1686 | ||
1687 | /* Pad to end of cacheline */ | |
1688 | while ((unsigned long)batch % CACHELINE_BYTES) | |
1689 | *batch++ = MI_NOOP; | |
1690 | ||
1691 | return batch; | |
1692 | } | |
1693 | ||
097d4f1c TU |
1694 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1695 | ||
1696 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1697 | { |
48bb74e4 CW |
1698 | struct drm_i915_gem_object *obj; |
1699 | struct i915_vma *vma; | |
1700 | int err; | |
17ee950d | 1701 | |
097d4f1c | 1702 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1703 | if (IS_ERR(obj)) |
1704 | return PTR_ERR(obj); | |
17ee950d | 1705 | |
82ad6443 | 1706 | vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); |
48bb74e4 CW |
1707 | if (IS_ERR(vma)) { |
1708 | err = PTR_ERR(vma); | |
1709 | goto err; | |
17ee950d AS |
1710 | } |
1711 | ||
48bb74e4 CW |
1712 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1713 | if (err) | |
1714 | goto err; | |
1715 | ||
1716 | engine->wa_ctx.vma = vma; | |
17ee950d | 1717 | return 0; |
48bb74e4 CW |
1718 | |
1719 | err: | |
1720 | i915_gem_object_put(obj); | |
1721 | return err; | |
17ee950d AS |
1722 | } |
1723 | ||
097d4f1c | 1724 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1725 | { |
19880c4a | 1726 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1727 | } |
1728 | ||
097d4f1c TU |
1729 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1730 | ||
0bc40be8 | 1731 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1732 | { |
48bb74e4 | 1733 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1734 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1735 | &wa_ctx->per_ctx }; | |
1736 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1737 | struct page *page; |
097d4f1c TU |
1738 | void *batch, *batch_ptr; |
1739 | unsigned int i; | |
48bb74e4 | 1740 | int ret; |
17ee950d | 1741 | |
10bde236 | 1742 | if (GEM_WARN_ON(engine->id != RCS)) |
097d4f1c | 1743 | return -EINVAL; |
17ee950d | 1744 | |
097d4f1c | 1745 | switch (INTEL_GEN(engine->i915)) { |
cc38cae7 OM |
1746 | case 11: |
1747 | return 0; | |
90007bca | 1748 | case 10: |
4b6ce681 RA |
1749 | wa_bb_fn[0] = gen10_init_indirectctx_bb; |
1750 | wa_bb_fn[1] = NULL; | |
1751 | break; | |
097d4f1c TU |
1752 | case 9: |
1753 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
b8aa2233 | 1754 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1755 | break; |
1756 | case 8: | |
1757 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
3ad7b52d | 1758 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1759 | break; |
1760 | default: | |
1761 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1762 | return 0; |
0504cffc | 1763 | } |
5e60d790 | 1764 | |
097d4f1c | 1765 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1766 | if (ret) { |
1767 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1768 | return ret; | |
1769 | } | |
1770 | ||
48bb74e4 | 1771 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1772 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1773 | |
097d4f1c TU |
1774 | /* |
1775 | * Emit the two workaround batch buffers, recording the offset from the | |
1776 | * start of the workaround batch buffer object for each and their | |
1777 | * respective sizes. | |
1778 | */ | |
1779 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1780 | wa_bb[i]->offset = batch_ptr - batch; | |
1d2a19c2 CW |
1781 | if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, |
1782 | CACHELINE_BYTES))) { | |
097d4f1c TU |
1783 | ret = -EINVAL; |
1784 | break; | |
1785 | } | |
604a8f6f CW |
1786 | if (wa_bb_fn[i]) |
1787 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
097d4f1c | 1788 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); |
17ee950d AS |
1789 | } |
1790 | ||
097d4f1c TU |
1791 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1792 | ||
17ee950d AS |
1793 | kunmap_atomic(batch); |
1794 | if (ret) | |
097d4f1c | 1795 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1796 | |
1797 | return ret; | |
1798 | } | |
1799 | ||
f3c9d407 | 1800 | static void enable_execlists(struct intel_engine_cs *engine) |
9b1136d5 | 1801 | { |
c033666a | 1802 | struct drm_i915_private *dev_priv = engine->i915; |
f3c9d407 CW |
1803 | |
1804 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
225701fc KG |
1805 | |
1806 | /* | |
1807 | * Make sure we're not enabling the new 12-deep CSB | |
1808 | * FIFO as that requires a slightly updated handling | |
1809 | * in the ctx switch irq. Since we're currently only | |
1810 | * using only 2 elements of the enhanced execlists the | |
1811 | * deeper FIFO it's not needed and it's not worth adding | |
1812 | * more statements to the irq handler to support it. | |
1813 | */ | |
1814 | if (INTEL_GEN(dev_priv) >= 11) | |
1815 | I915_WRITE(RING_MODE_GEN7(engine), | |
1816 | _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); | |
1817 | else | |
1818 | I915_WRITE(RING_MODE_GEN7(engine), | |
1819 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1820 | ||
9a4dc803 CW |
1821 | I915_WRITE(RING_MI_MODE(engine->mmio_base), |
1822 | _MASKED_BIT_DISABLE(STOP_RING)); | |
1823 | ||
f3c9d407 CW |
1824 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1825 | engine->status_page.ggtt_offset); | |
1826 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
1827 | } | |
1828 | ||
9a4dc803 CW |
1829 | static bool unexpected_starting_state(struct intel_engine_cs *engine) |
1830 | { | |
1831 | struct drm_i915_private *dev_priv = engine->i915; | |
1832 | bool unexpected = false; | |
1833 | ||
1834 | if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) { | |
1835 | DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); | |
1836 | unexpected = true; | |
1837 | } | |
1838 | ||
1839 | return unexpected; | |
1840 | } | |
1841 | ||
f3c9d407 CW |
1842 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
1843 | { | |
821ed7df CW |
1844 | int ret; |
1845 | ||
1846 | ret = intel_mocs_init_engine(engine); | |
1847 | if (ret) | |
1848 | return ret; | |
9b1136d5 | 1849 | |
ad07dfcd | 1850 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1851 | intel_engine_init_hangcheck(engine); |
821ed7df | 1852 | |
9a4dc803 CW |
1853 | if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { |
1854 | struct drm_printer p = drm_debug_printer(__func__); | |
1855 | ||
1856 | intel_engine_dump(engine, &p, NULL); | |
1857 | } | |
1858 | ||
f3c9d407 | 1859 | enable_execlists(engine); |
9b1136d5 | 1860 | |
821ed7df | 1861 | return 0; |
9b1136d5 OM |
1862 | } |
1863 | ||
0bc40be8 | 1864 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1865 | { |
c033666a | 1866 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1867 | int ret; |
1868 | ||
0bc40be8 | 1869 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1870 | if (ret) |
1871 | return ret; | |
1872 | ||
f4ecfbfc | 1873 | intel_whitelist_workarounds_apply(engine); |
59b449d5 | 1874 | |
9b1136d5 OM |
1875 | /* We need to disable the AsyncFlip performance optimisations in order |
1876 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1877 | * programmed to '1' on all products. | |
1878 | * | |
1879 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1880 | */ | |
1881 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1882 | ||
9b1136d5 OM |
1883 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1884 | ||
59b449d5 | 1885 | return 0; |
9b1136d5 OM |
1886 | } |
1887 | ||
0bc40be8 | 1888 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1889 | { |
1890 | int ret; | |
1891 | ||
0bc40be8 | 1892 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1893 | if (ret) |
1894 | return ret; | |
1895 | ||
f4ecfbfc | 1896 | intel_whitelist_workarounds_apply(engine); |
59b449d5 OM |
1897 | |
1898 | return 0; | |
82ef822e DL |
1899 | } |
1900 | ||
5adfb772 CW |
1901 | static struct i915_request * |
1902 | execlists_reset_prepare(struct intel_engine_cs *engine) | |
1903 | { | |
1904 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
63572937 | 1905 | struct i915_request *request, *active; |
5adfb772 CW |
1906 | |
1907 | GEM_TRACE("%s\n", engine->name); | |
1908 | ||
1909 | /* | |
1910 | * Prevent request submission to the hardware until we have | |
1911 | * completed the reset in i915_gem_reset_finish(). If a request | |
1912 | * is completed by one engine, it may then queue a request | |
1913 | * to a second via its execlists->tasklet *just* as we are | |
1914 | * calling engine->init_hw() and also writing the ELSP. | |
1915 | * Turning off the execlists->tasklet until the reset is over | |
1916 | * prevents the race. | |
1917 | */ | |
1918 | __tasklet_disable_sync_once(&execlists->tasklet); | |
1919 | ||
63572937 CW |
1920 | /* |
1921 | * We want to flush the pending context switches, having disabled | |
1922 | * the tasklet above, we can assume exclusive access to the execlists. | |
1923 | * For this allows us to catch up with an inflight preemption event, | |
1924 | * and avoid blaming an innocent request if the stall was due to the | |
1925 | * preemption itself. | |
1926 | */ | |
1927 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
1928 | process_csb(engine); | |
1929 | ||
1930 | /* | |
1931 | * The last active request can then be no later than the last request | |
1932 | * now in ELSP[0]. So search backwards from there, so that if the GPU | |
1933 | * has advanced beyond the last CSB update, it will be pardoned. | |
1934 | */ | |
1935 | active = NULL; | |
1936 | request = port_request(execlists->port); | |
1937 | if (request) { | |
1938 | unsigned long flags; | |
1939 | ||
3f6e9822 CW |
1940 | /* |
1941 | * Prevent the breadcrumb from advancing before we decide | |
1942 | * which request is currently active. | |
1943 | */ | |
1944 | intel_engine_stop_cs(engine); | |
1945 | ||
63572937 CW |
1946 | spin_lock_irqsave(&engine->timeline.lock, flags); |
1947 | list_for_each_entry_from_reverse(request, | |
1948 | &engine->timeline.requests, | |
1949 | link) { | |
1950 | if (__i915_request_completed(request, | |
1951 | request->global_seqno)) | |
1952 | break; | |
1953 | ||
1954 | active = request; | |
1955 | } | |
1956 | spin_unlock_irqrestore(&engine->timeline.lock, flags); | |
1957 | } | |
1958 | ||
1959 | return active; | |
5adfb772 CW |
1960 | } |
1961 | ||
1962 | static void execlists_reset(struct intel_engine_cs *engine, | |
1963 | struct i915_request *request) | |
821ed7df | 1964 | { |
b620e870 | 1965 | struct intel_engine_execlists * const execlists = &engine->execlists; |
221ab971 | 1966 | unsigned long flags; |
5692251c | 1967 | u32 *regs; |
cdb6ded4 | 1968 | |
0c5c7df3 TU |
1969 | GEM_TRACE("%s request global=%x, current=%d\n", |
1970 | engine->name, request ? request->global_seqno : 0, | |
1971 | intel_engine_get_seqno(engine)); | |
42232213 | 1972 | |
a3e38836 CW |
1973 | /* See execlists_cancel_requests() for the irq/spinlock split. */ |
1974 | local_irq_save(flags); | |
221ab971 | 1975 | |
cdb6ded4 CW |
1976 | /* |
1977 | * Catch up with any missed context-switch interrupts. | |
1978 | * | |
1979 | * Ideally we would just read the remaining CSB entries now that we | |
1980 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1981 | * often trashed across a GPU reset! Instead we have to rely on | |
1982 | * guessing the missed context-switch events by looking at what | |
1983 | * requests were completed. | |
1984 | */ | |
a4598d17 | 1985 | execlists_cancel_port_requests(execlists); |
46b3617d | 1986 | reset_irq(engine); |
cdb6ded4 | 1987 | |
221ab971 | 1988 | /* Push back any incomplete requests for replay after the reset. */ |
a89d1f92 | 1989 | spin_lock(&engine->timeline.lock); |
a4598d17 | 1990 | __unwind_incomplete_requests(engine); |
a89d1f92 | 1991 | spin_unlock(&engine->timeline.lock); |
cdb6ded4 | 1992 | |
c3160da9 | 1993 | /* Following the reset, we need to reload the CSB read/write pointers */ |
b2209e62 | 1994 | engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1; |
c3160da9 | 1995 | |
a3e38836 | 1996 | local_irq_restore(flags); |
aebbc2d7 | 1997 | |
a3e38836 CW |
1998 | /* |
1999 | * If the request was innocent, we leave the request in the ELSP | |
c0dcb203 CW |
2000 | * and will try to replay it on restarting. The context image may |
2001 | * have been corrupted by the reset, in which case we may have | |
2002 | * to service a new GPU hang, but more likely we can continue on | |
2003 | * without impact. | |
2004 | * | |
2005 | * If the request was guilty, we presume the context is corrupt | |
2006 | * and have to at least restore the RING register in the context | |
2007 | * image back to the expected values to skip over the guilty request. | |
2008 | */ | |
221ab971 | 2009 | if (!request || request->fence.error != -EIO) |
c0dcb203 | 2010 | return; |
821ed7df | 2011 | |
a3e38836 CW |
2012 | /* |
2013 | * We want a simple context + ring to execute the breadcrumb update. | |
a3aabe86 CW |
2014 | * We cannot rely on the context being intact across the GPU hang, |
2015 | * so clear it and rebuild just what we need for the breadcrumb. | |
2016 | * All pending requests for this context will be zapped, and any | |
2017 | * future request will be after userspace has had the opportunity | |
2018 | * to recreate its own state. | |
2019 | */ | |
1fc44d9b | 2020 | regs = request->hw_context->lrc_reg_state; |
fe0c4935 CW |
2021 | if (engine->pinned_default_state) { |
2022 | memcpy(regs, /* skip restoring the vanilla PPHWSP */ | |
2023 | engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, | |
2024 | engine->context_size - PAGE_SIZE); | |
5692251c | 2025 | } |
4e0d64db CW |
2026 | execlists_init_reg_state(regs, |
2027 | request->gem_context, engine, request->ring); | |
a3aabe86 | 2028 | |
821ed7df | 2029 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
5692251c | 2030 | regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma); |
a3aabe86 | 2031 | |
41d37680 CW |
2032 | request->ring->head = intel_ring_wrap(request->ring, request->postfix); |
2033 | regs[CTX_RING_HEAD + 1] = request->ring->head; | |
2034 | ||
821ed7df CW |
2035 | intel_ring_update_space(request->ring); |
2036 | ||
a3aabe86 | 2037 | /* Reset WaIdleLiteRestore:bdw,skl as well */ |
7e4992ac | 2038 | unwind_wa_tail(request); |
821ed7df CW |
2039 | } |
2040 | ||
5adfb772 CW |
2041 | static void execlists_reset_finish(struct intel_engine_cs *engine) |
2042 | { | |
5db1d4ea CW |
2043 | struct intel_engine_execlists * const execlists = &engine->execlists; |
2044 | ||
2045 | /* After a GPU reset, we may have requests to replay */ | |
2046 | if (execlists->first) | |
2047 | tasklet_schedule(&execlists->tasklet); | |
2048 | ||
fe25f304 CW |
2049 | /* |
2050 | * Flush the tasklet while we still have the forcewake to be sure | |
2051 | * that it is not allowed to sleep before we restart and reload a | |
2052 | * context. | |
2053 | * | |
2054 | * As before (with execlists_reset_prepare) we rely on the caller | |
2055 | * serialising multiple attempts to reset so that we know that we | |
2056 | * are the only one manipulating tasklet state. | |
2057 | */ | |
5db1d4ea | 2058 | __tasklet_enable_sync_once(&execlists->tasklet); |
5adfb772 CW |
2059 | |
2060 | GEM_TRACE("%s\n", engine->name); | |
2061 | } | |
2062 | ||
e61e0f51 | 2063 | static int intel_logical_ring_emit_pdps(struct i915_request *rq) |
7a01a0a2 | 2064 | { |
4e0d64db | 2065 | struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt; |
e61e0f51 | 2066 | struct intel_engine_cs *engine = rq->engine; |
e7167769 | 2067 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
2068 | u32 *cs; |
2069 | int i; | |
7a01a0a2 | 2070 | |
e61e0f51 | 2071 | cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2); |
73dec95e TU |
2072 | if (IS_ERR(cs)) |
2073 | return PTR_ERR(cs); | |
7a01a0a2 | 2074 | |
73dec95e | 2075 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 2076 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
2077 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
2078 | ||
73dec95e TU |
2079 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
2080 | *cs++ = upper_32_bits(pd_daddr); | |
2081 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
2082 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
2083 | } |
2084 | ||
73dec95e | 2085 | *cs++ = MI_NOOP; |
e61e0f51 | 2086 | intel_ring_advance(rq, cs); |
7a01a0a2 MT |
2087 | |
2088 | return 0; | |
2089 | } | |
2090 | ||
e61e0f51 | 2091 | static int gen8_emit_bb_start(struct i915_request *rq, |
803688ba | 2092 | u64 offset, u32 len, |
54af56db | 2093 | const unsigned int flags) |
15648585 | 2094 | { |
73dec95e | 2095 | u32 *cs; |
15648585 OM |
2096 | int ret; |
2097 | ||
7a01a0a2 MT |
2098 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
2099 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
2100 | * but we can't. Force Restore would be a second option, but | |
2101 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
2102 | * not idle). PML4 is allocated during ppgtt init so this is |
2103 | * not needed in 48-bit.*/ | |
4e0d64db CW |
2104 | if (rq->gem_context->ppgtt && |
2105 | (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) && | |
82ad6443 | 2106 | !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) && |
e61e0f51 CW |
2107 | !intel_vgpu_active(rq->i915)) { |
2108 | ret = intel_logical_ring_emit_pdps(rq); | |
54af56db MK |
2109 | if (ret) |
2110 | return ret; | |
7a01a0a2 | 2111 | |
4e0d64db | 2112 | rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); |
7a01a0a2 MT |
2113 | } |
2114 | ||
74f94741 | 2115 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
2116 | if (IS_ERR(cs)) |
2117 | return PTR_ERR(cs); | |
15648585 | 2118 | |
279f5a00 CW |
2119 | /* |
2120 | * WaDisableCtxRestoreArbitration:bdw,chv | |
2121 | * | |
2122 | * We don't need to perform MI_ARB_ENABLE as often as we do (in | |
2123 | * particular all the gen that do not need the w/a at all!), if we | |
2124 | * took care to make sure that on every switch into this context | |
2125 | * (both ordinary and for preemption) that arbitrartion was enabled | |
2126 | * we would be fine. However, there doesn't seem to be a downside to | |
2127 | * being paranoid and making sure it is set before each batch and | |
2128 | * every context-switch. | |
2129 | * | |
2130 | * Note that if we fail to enable arbitration before the request | |
2131 | * is complete, then we do not see the context-switch interrupt and | |
2132 | * the engine hangs (with RING_HEAD == RING_TAIL). | |
2133 | * | |
2134 | * That satisfies both the GPGPU w/a and our heavy-handed paranoia. | |
2135 | */ | |
3ad7b52d CW |
2136 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
2137 | ||
15648585 | 2138 | /* FIXME(BDW): Address space and security selectors. */ |
54af56db MK |
2139 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
2140 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
2141 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
2142 | *cs++ = lower_32_bits(offset); |
2143 | *cs++ = upper_32_bits(offset); | |
74f94741 CW |
2144 | |
2145 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; | |
2146 | *cs++ = MI_NOOP; | |
e61e0f51 | 2147 | intel_ring_advance(rq, cs); |
15648585 OM |
2148 | |
2149 | return 0; | |
2150 | } | |
2151 | ||
31bb59cc | 2152 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 2153 | { |
c033666a | 2154 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
2155 | I915_WRITE_IMR(engine, |
2156 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
2157 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
2158 | } |
2159 | ||
31bb59cc | 2160 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 2161 | { |
c033666a | 2162 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 2163 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
2164 | } |
2165 | ||
e61e0f51 | 2166 | static int gen8_emit_flush(struct i915_request *request, u32 mode) |
4712274c | 2167 | { |
73dec95e | 2168 | u32 cmd, *cs; |
4712274c | 2169 | |
73dec95e TU |
2170 | cs = intel_ring_begin(request, 4); |
2171 | if (IS_ERR(cs)) | |
2172 | return PTR_ERR(cs); | |
4712274c OM |
2173 | |
2174 | cmd = MI_FLUSH_DW + 1; | |
2175 | ||
f0a1fb10 CW |
2176 | /* We always require a command barrier so that subsequent |
2177 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2178 | * wrt the contents of the write cache being flushed to memory | |
2179 | * (and thus being coherent from the CPU). | |
2180 | */ | |
2181 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2182 | ||
7c9cf4e3 | 2183 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 2184 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 2185 | if (request->engine->id == VCS) |
f0a1fb10 | 2186 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
2187 | } |
2188 | ||
73dec95e TU |
2189 | *cs++ = cmd; |
2190 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
2191 | *cs++ = 0; /* upper addr */ | |
2192 | *cs++ = 0; /* value */ | |
2193 | intel_ring_advance(request, cs); | |
4712274c OM |
2194 | |
2195 | return 0; | |
2196 | } | |
2197 | ||
e61e0f51 | 2198 | static int gen8_emit_flush_render(struct i915_request *request, |
7c9cf4e3 | 2199 | u32 mode) |
4712274c | 2200 | { |
b5321f30 | 2201 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
2202 | u32 scratch_addr = |
2203 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 2204 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 2205 | u32 *cs, flags = 0; |
0b2d0934 | 2206 | int len; |
4712274c OM |
2207 | |
2208 | flags |= PIPE_CONTROL_CS_STALL; | |
2209 | ||
7c9cf4e3 | 2210 | if (mode & EMIT_FLUSH) { |
4712274c OM |
2211 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
2212 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 2213 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 2214 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
2215 | } |
2216 | ||
7c9cf4e3 | 2217 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
2218 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
2219 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
2220 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
2221 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
2222 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
2223 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
2224 | flags |= PIPE_CONTROL_QW_WRITE; | |
2225 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 2226 | |
1a5a9ce7 BW |
2227 | /* |
2228 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
2229 | * pipe control. | |
2230 | */ | |
c033666a | 2231 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 2232 | vf_flush_wa = true; |
0b2d0934 MK |
2233 | |
2234 | /* WaForGAMHang:kbl */ | |
2235 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
2236 | dc_flush_wa = true; | |
1a5a9ce7 | 2237 | } |
9647ff36 | 2238 | |
0b2d0934 MK |
2239 | len = 6; |
2240 | ||
2241 | if (vf_flush_wa) | |
2242 | len += 6; | |
2243 | ||
2244 | if (dc_flush_wa) | |
2245 | len += 12; | |
2246 | ||
73dec95e TU |
2247 | cs = intel_ring_begin(request, len); |
2248 | if (IS_ERR(cs)) | |
2249 | return PTR_ERR(cs); | |
4712274c | 2250 | |
9f235dfa TU |
2251 | if (vf_flush_wa) |
2252 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 2253 | |
9f235dfa TU |
2254 | if (dc_flush_wa) |
2255 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
2256 | 0); | |
0b2d0934 | 2257 | |
9f235dfa | 2258 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 2259 | |
9f235dfa TU |
2260 | if (dc_flush_wa) |
2261 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 2262 | |
73dec95e | 2263 | intel_ring_advance(request, cs); |
4712274c OM |
2264 | |
2265 | return 0; | |
2266 | } | |
2267 | ||
7c17d377 CW |
2268 | /* |
2269 | * Reserve space for 2 NOOPs at the end of each request to be | |
2270 | * used as a workaround for not being allowed to do lite | |
2271 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
2272 | */ | |
e61e0f51 | 2273 | static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs) |
4da46e1e | 2274 | { |
beecec90 CW |
2275 | /* Ensure there's always at least one preemption point per-request. */ |
2276 | *cs++ = MI_ARB_CHECK; | |
73dec95e TU |
2277 | *cs++ = MI_NOOP; |
2278 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 2279 | } |
4da46e1e | 2280 | |
e61e0f51 | 2281 | static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs) |
caddfe71 | 2282 | { |
7c17d377 CW |
2283 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
2284 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 2285 | |
df77cd83 MW |
2286 | cs = gen8_emit_ggtt_write(cs, request->global_seqno, |
2287 | intel_hws_seqno_address(request->engine)); | |
73dec95e | 2288 | *cs++ = MI_USER_INTERRUPT; |
74f94741 | 2289 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
73dec95e | 2290 | request->tail = intel_ring_offset(request, cs); |
ed1501d4 | 2291 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 2292 | |
73dec95e | 2293 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 2294 | } |
98f29e8d CW |
2295 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
2296 | ||
e61e0f51 | 2297 | static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs) |
7c17d377 | 2298 | { |
ce81a65c MW |
2299 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
2300 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
2301 | ||
df77cd83 MW |
2302 | cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno, |
2303 | intel_hws_seqno_address(request->engine)); | |
73dec95e | 2304 | *cs++ = MI_USER_INTERRUPT; |
74f94741 | 2305 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
73dec95e | 2306 | request->tail = intel_ring_offset(request, cs); |
ed1501d4 | 2307 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 2308 | |
73dec95e | 2309 | gen8_emit_wa_tail(request, cs); |
4da46e1e | 2310 | } |
df77cd83 | 2311 | static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS; |
98f29e8d | 2312 | |
e61e0f51 | 2313 | static int gen8_init_rcs_context(struct i915_request *rq) |
e7778be1 TD |
2314 | { |
2315 | int ret; | |
2316 | ||
59b449d5 | 2317 | ret = intel_ctx_workarounds_emit(rq); |
e7778be1 TD |
2318 | if (ret) |
2319 | return ret; | |
2320 | ||
e61e0f51 | 2321 | ret = intel_rcs_context_init_mocs(rq); |
3bbaba0c PA |
2322 | /* |
2323 | * Failing to program the MOCS is non-fatal.The system will not | |
2324 | * run at peak performance. So generate an error and carry on. | |
2325 | */ | |
2326 | if (ret) | |
2327 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
2328 | ||
e61e0f51 | 2329 | return i915_gem_render_state_emit(rq); |
e7778be1 TD |
2330 | } |
2331 | ||
73e4d07f OM |
2332 | /** |
2333 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 2334 | * @engine: Engine Command Streamer. |
73e4d07f | 2335 | */ |
0bc40be8 | 2336 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 2337 | { |
6402c330 | 2338 | struct drm_i915_private *dev_priv; |
9832b9da | 2339 | |
27af5eea TU |
2340 | /* |
2341 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
2342 | * so this is just for documentation. | |
2343 | */ | |
c6dce8f1 SAK |
2344 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, |
2345 | &engine->execlists.tasklet.state))) | |
2346 | tasklet_kill(&engine->execlists.tasklet); | |
27af5eea | 2347 | |
c033666a | 2348 | dev_priv = engine->i915; |
6402c330 | 2349 | |
0bc40be8 | 2350 | if (engine->buffer) { |
0bc40be8 | 2351 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 2352 | } |
48d82387 | 2353 | |
0bc40be8 TU |
2354 | if (engine->cleanup) |
2355 | engine->cleanup(engine); | |
48d82387 | 2356 | |
e8a9c58f | 2357 | intel_engine_cleanup_common(engine); |
17ee950d | 2358 | |
097d4f1c | 2359 | lrc_destroy_wa_ctx(engine); |
f3c9d407 | 2360 | |
c033666a | 2361 | engine->i915 = NULL; |
3b3f1650 AG |
2362 | dev_priv->engine[engine->id] = NULL; |
2363 | kfree(engine); | |
454afebd OM |
2364 | } |
2365 | ||
ff44ad51 | 2366 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 2367 | { |
ff44ad51 | 2368 | engine->submit_request = execlists_submit_request; |
27a5f61b | 2369 | engine->cancel_requests = execlists_cancel_requests; |
ff44ad51 | 2370 | engine->schedule = execlists_schedule; |
c6dce8f1 | 2371 | engine->execlists.tasklet.func = execlists_submission_tasklet; |
aba5e278 | 2372 | |
1329115c CW |
2373 | engine->reset.prepare = execlists_reset_prepare; |
2374 | ||
aba5e278 CW |
2375 | engine->park = NULL; |
2376 | engine->unpark = NULL; | |
cf669b4e TU |
2377 | |
2378 | engine->flags |= I915_ENGINE_SUPPORTS_STATS; | |
2a694feb CW |
2379 | if (engine->i915->preempt_context) |
2380 | engine->flags |= I915_ENGINE_HAS_PREEMPTION; | |
3fed1808 CW |
2381 | |
2382 | engine->i915->caps.scheduler = | |
2383 | I915_SCHEDULER_CAP_ENABLED | | |
2384 | I915_SCHEDULER_CAP_PRIORITY; | |
2a694feb | 2385 | if (intel_engine_has_preemption(engine)) |
3fed1808 | 2386 | engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION; |
ddd66c51 CW |
2387 | } |
2388 | ||
c9cacf93 | 2389 | static void |
e1382efb | 2390 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
2391 | { |
2392 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 2393 | engine->init_hw = gen8_init_common_ring; |
5adfb772 CW |
2394 | |
2395 | engine->reset.prepare = execlists_reset_prepare; | |
2396 | engine->reset.reset = execlists_reset; | |
2397 | engine->reset.finish = execlists_reset_finish; | |
e8a9c58f CW |
2398 | |
2399 | engine->context_pin = execlists_context_pin; | |
f73e7399 CW |
2400 | engine->request_alloc = execlists_request_alloc; |
2401 | ||
0bc40be8 | 2402 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 2403 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 2404 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
2405 | |
2406 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 2407 | |
d4ccceb0 TU |
2408 | if (INTEL_GEN(engine->i915) < 11) { |
2409 | engine->irq_enable = gen8_logical_ring_enable_irq; | |
2410 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
2411 | } else { | |
2412 | /* | |
2413 | * TODO: On Gen11 interrupt masks need to be clear | |
2414 | * to allow C6 entry. Keep interrupts enabled at | |
2415 | * and take the hit of generating extra interrupts | |
2416 | * until a more refined solution exists. | |
2417 | */ | |
2418 | } | |
0bc40be8 | 2419 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
2420 | } |
2421 | ||
d9f3af96 | 2422 | static inline void |
c2c7f240 | 2423 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 2424 | { |
fa6f071d DCS |
2425 | unsigned int shift = 0; |
2426 | ||
2427 | if (INTEL_GEN(engine->i915) < 11) { | |
2428 | const u8 irq_shifts[] = { | |
2429 | [RCS] = GEN8_RCS_IRQ_SHIFT, | |
2430 | [BCS] = GEN8_BCS_IRQ_SHIFT, | |
2431 | [VCS] = GEN8_VCS1_IRQ_SHIFT, | |
2432 | [VCS2] = GEN8_VCS2_IRQ_SHIFT, | |
2433 | [VECS] = GEN8_VECS_IRQ_SHIFT, | |
2434 | }; | |
2435 | ||
2436 | shift = irq_shifts[engine->id]; | |
2437 | } | |
2438 | ||
0bc40be8 TU |
2439 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
2440 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
2441 | } |
2442 | ||
bb45438f TU |
2443 | static void |
2444 | logical_ring_setup(struct intel_engine_cs *engine) | |
2445 | { | |
2446 | struct drm_i915_private *dev_priv = engine->i915; | |
2447 | enum forcewake_domains fw_domains; | |
2448 | ||
019bf277 TU |
2449 | intel_engine_setup_common(engine); |
2450 | ||
bb45438f TU |
2451 | /* Intentionally left blank. */ |
2452 | engine->buffer = NULL; | |
2453 | ||
2454 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
2455 | RING_ELSP(engine), | |
2456 | FW_REG_WRITE); | |
2457 | ||
2458 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
2459 | RING_CONTEXT_STATUS_PTR(engine), | |
2460 | FW_REG_READ | FW_REG_WRITE); | |
2461 | ||
2462 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
2463 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
2464 | FW_REG_READ); | |
2465 | ||
b620e870 | 2466 | engine->execlists.fw_domains = fw_domains; |
bb45438f | 2467 | |
c6dce8f1 SAK |
2468 | tasklet_init(&engine->execlists.tasklet, |
2469 | execlists_submission_tasklet, (unsigned long)engine); | |
bb45438f | 2470 | |
bb45438f TU |
2471 | logical_ring_default_vfuncs(engine); |
2472 | logical_ring_default_irqs(engine); | |
bb45438f TU |
2473 | } |
2474 | ||
486e93f7 | 2475 | static int logical_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 2476 | { |
a19d6ff2 TU |
2477 | int ret; |
2478 | ||
019bf277 | 2479 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
2480 | if (ret) |
2481 | goto error; | |
2482 | ||
05f0addd TD |
2483 | if (HAS_LOGICAL_RING_ELSQ(engine->i915)) { |
2484 | engine->execlists.submit_reg = engine->i915->regs + | |
2485 | i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine)); | |
2486 | engine->execlists.ctrl_reg = engine->i915->regs + | |
2487 | i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine)); | |
2488 | } else { | |
2489 | engine->execlists.submit_reg = engine->i915->regs + | |
2490 | i915_mmio_reg_offset(RING_ELSP(engine)); | |
2491 | } | |
693cfbf0 | 2492 | |
d6376374 | 2493 | engine->execlists.preempt_complete_status = ~0u; |
ab82a063 CW |
2494 | if (engine->i915->preempt_context) { |
2495 | struct intel_context *ce = | |
2496 | to_intel_context(engine->i915->preempt_context, engine); | |
2497 | ||
d6376374 | 2498 | engine->execlists.preempt_complete_status = |
ab82a063 CW |
2499 | upper_32_bits(ce->lrc_desc); |
2500 | } | |
d6376374 | 2501 | |
b2209e62 | 2502 | engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1; |
c3160da9 | 2503 | |
a19d6ff2 TU |
2504 | return 0; |
2505 | ||
2506 | error: | |
2507 | intel_logical_ring_cleanup(engine); | |
2508 | return ret; | |
2509 | } | |
2510 | ||
88d2ba2e | 2511 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
2512 | { |
2513 | struct drm_i915_private *dev_priv = engine->i915; | |
2514 | int ret; | |
2515 | ||
bb45438f TU |
2516 | logical_ring_setup(engine); |
2517 | ||
a19d6ff2 TU |
2518 | if (HAS_L3_DPF(dev_priv)) |
2519 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
2520 | ||
2521 | /* Override some for render ring. */ | |
2522 | if (INTEL_GEN(dev_priv) >= 9) | |
2523 | engine->init_hw = gen9_init_render_ring; | |
2524 | else | |
2525 | engine->init_hw = gen8_init_render_ring; | |
2526 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 2527 | engine->emit_flush = gen8_emit_flush_render; |
df77cd83 MW |
2528 | engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs; |
2529 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz; | |
a19d6ff2 | 2530 | |
f51455d4 | 2531 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
2532 | if (ret) |
2533 | return ret; | |
2534 | ||
2535 | ret = intel_init_workaround_bb(engine); | |
2536 | if (ret) { | |
2537 | /* | |
2538 | * We continue even if we fail to initialize WA batch | |
2539 | * because we only expect rare glitches but nothing | |
2540 | * critical to prevent us from using GPU | |
2541 | */ | |
2542 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2543 | ret); | |
2544 | } | |
2545 | ||
d038fc7e | 2546 | return logical_ring_init(engine); |
a19d6ff2 TU |
2547 | } |
2548 | ||
88d2ba2e | 2549 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
2550 | { |
2551 | logical_ring_setup(engine); | |
2552 | ||
2553 | return logical_ring_init(engine); | |
454afebd OM |
2554 | } |
2555 | ||
0cea6502 | 2556 | static u32 |
c033666a | 2557 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
2558 | { |
2559 | u32 rpcs = 0; | |
2560 | ||
2561 | /* | |
2562 | * No explicit RPCS request is needed to ensure full | |
2563 | * slice/subslice/EU enablement prior to Gen9. | |
2564 | */ | |
c033666a | 2565 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
2566 | return 0; |
2567 | ||
2568 | /* | |
2569 | * Starting in Gen9, render power gating can leave | |
2570 | * slice/subslice/EU in a partially enabled state. We | |
2571 | * must make an explicit request through RPCS for full | |
2572 | * enablement. | |
2573 | */ | |
43b67998 | 2574 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 2575 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 2576 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
2577 | GEN8_RPCS_S_CNT_SHIFT; |
2578 | rpcs |= GEN8_RPCS_ENABLE; | |
2579 | } | |
2580 | ||
43b67998 | 2581 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 2582 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
8cc76693 | 2583 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) << |
0cea6502 JM |
2584 | GEN8_RPCS_SS_CNT_SHIFT; |
2585 | rpcs |= GEN8_RPCS_ENABLE; | |
2586 | } | |
2587 | ||
43b67998 ID |
2588 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
2589 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 2590 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 2591 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
2592 | GEN8_RPCS_EU_MAX_SHIFT; |
2593 | rpcs |= GEN8_RPCS_ENABLE; | |
2594 | } | |
2595 | ||
2596 | return rpcs; | |
2597 | } | |
2598 | ||
0bc40be8 | 2599 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2600 | { |
2601 | u32 indirect_ctx_offset; | |
2602 | ||
c033666a | 2603 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 2604 | default: |
c033666a | 2605 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 2606 | /* fall through */ |
fd034c77 MT |
2607 | case 11: |
2608 | indirect_ctx_offset = | |
2609 | GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2610 | break; | |
7bd0a2c6 MT |
2611 | case 10: |
2612 | indirect_ctx_offset = | |
2613 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2614 | break; | |
71562919 MT |
2615 | case 9: |
2616 | indirect_ctx_offset = | |
2617 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2618 | break; | |
2619 | case 8: | |
2620 | indirect_ctx_offset = | |
2621 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2622 | break; | |
2623 | } | |
2624 | ||
2625 | return indirect_ctx_offset; | |
2626 | } | |
2627 | ||
56e51bf0 | 2628 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
2629 | struct i915_gem_context *ctx, |
2630 | struct intel_engine_cs *engine, | |
2631 | struct intel_ring *ring) | |
8670d6f9 | 2632 | { |
a3aabe86 CW |
2633 | struct drm_i915_private *dev_priv = engine->i915; |
2634 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 | 2635 | u32 base = engine->mmio_base; |
1fc44d9b | 2636 | bool rcs = engine->class == RENDER_CLASS; |
56e51bf0 TU |
2637 | |
2638 | /* A context is actually a big batch buffer with several | |
2639 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
2640 | * values we are setting here are only for the first context restore: | |
2641 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
2642 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
2643 | * we are not initializing here). | |
2644 | */ | |
2645 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
2646 | MI_LRI_FORCE_POSTED; | |
2647 | ||
2648 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
09b1a4e4 CW |
2649 | _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
2650 | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) | | |
56e51bf0 | 2651 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
56e51bf0 TU |
2652 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
2653 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
2654 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
2655 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
2656 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
2657 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
2658 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
2659 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
2660 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
2661 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
2662 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
2663 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
2664 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
2665 | if (rcs) { | |
604a8f6f CW |
2666 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
2667 | ||
56e51bf0 TU |
2668 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); |
2669 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2670 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
604a8f6f | 2671 | if (wa_ctx->indirect_ctx.size) { |
bde13ebd | 2672 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 2673 | |
56e51bf0 | 2674 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
2675 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
2676 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 2677 | |
56e51bf0 | 2678 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 2679 | intel_lr_indirect_ctx_offset(engine) << 6; |
604a8f6f CW |
2680 | } |
2681 | ||
2682 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
2683 | if (wa_ctx->per_ctx.size) { | |
2684 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); | |
17ee950d | 2685 | |
56e51bf0 | 2686 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 2687 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 2688 | } |
8670d6f9 | 2689 | } |
56e51bf0 TU |
2690 | |
2691 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
2692 | ||
2693 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 2694 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
2695 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
2696 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
2697 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
2698 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
2699 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
2700 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
2701 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
2702 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 2703 | |
82ad6443 | 2704 | if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) { |
2dba3239 MT |
2705 | /* 64b PPGTT (48bit canonical) |
2706 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2707 | * other PDP Descriptors are ignored. | |
2708 | */ | |
56e51bf0 | 2709 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
2710 | } |
2711 | ||
56e51bf0 TU |
2712 | if (rcs) { |
2713 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
2714 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
2715 | make_rpcs(dev_priv)); | |
19f81df2 RB |
2716 | |
2717 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 2718 | } |
a3aabe86 CW |
2719 | } |
2720 | ||
2721 | static int | |
2722 | populate_lr_context(struct i915_gem_context *ctx, | |
2723 | struct drm_i915_gem_object *ctx_obj, | |
2724 | struct intel_engine_cs *engine, | |
2725 | struct intel_ring *ring) | |
2726 | { | |
2727 | void *vaddr; | |
d2b4b979 | 2728 | u32 *regs; |
a3aabe86 CW |
2729 | int ret; |
2730 | ||
2731 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2732 | if (ret) { | |
2733 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2734 | return ret; | |
2735 | } | |
2736 | ||
2737 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2738 | if (IS_ERR(vaddr)) { | |
2739 | ret = PTR_ERR(vaddr); | |
2740 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2741 | return ret; | |
2742 | } | |
a4f5ea64 | 2743 | ctx_obj->mm.dirty = true; |
a3aabe86 | 2744 | |
d2b4b979 CW |
2745 | if (engine->default_state) { |
2746 | /* | |
2747 | * We only want to copy over the template context state; | |
2748 | * skipping over the headers reserved for GuC communication, | |
2749 | * leaving those as zero. | |
2750 | */ | |
2751 | const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; | |
2752 | void *defaults; | |
2753 | ||
2754 | defaults = i915_gem_object_pin_map(engine->default_state, | |
2755 | I915_MAP_WB); | |
aaefa06a MA |
2756 | if (IS_ERR(defaults)) { |
2757 | ret = PTR_ERR(defaults); | |
2758 | goto err_unpin_ctx; | |
2759 | } | |
d2b4b979 CW |
2760 | |
2761 | memcpy(vaddr + start, defaults + start, engine->context_size); | |
2762 | i915_gem_object_unpin_map(engine->default_state); | |
2763 | } | |
2764 | ||
a3aabe86 CW |
2765 | /* The second page of the context object contains some fields which must |
2766 | * be set up prior to the first execution. */ | |
d2b4b979 CW |
2767 | regs = vaddr + LRC_STATE_PN * PAGE_SIZE; |
2768 | execlists_init_reg_state(regs, ctx, engine, ring); | |
2769 | if (!engine->default_state) | |
2770 | regs[CTX_CONTEXT_CONTROL + 1] |= | |
2771 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); | |
05f0addd | 2772 | if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11) |
517aaffe CW |
2773 | regs[CTX_CONTEXT_CONTROL + 1] |= |
2774 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
2775 | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); | |
8670d6f9 | 2776 | |
aaefa06a | 2777 | err_unpin_ctx: |
7d774cac | 2778 | i915_gem_object_unpin_map(ctx_obj); |
aaefa06a | 2779 | return ret; |
8670d6f9 OM |
2780 | } |
2781 | ||
e2efd130 | 2782 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
1fc44d9b CW |
2783 | struct intel_engine_cs *engine, |
2784 | struct intel_context *ce) | |
ede7d42b | 2785 | { |
8c857917 | 2786 | struct drm_i915_gem_object *ctx_obj; |
bf3783e5 | 2787 | struct i915_vma *vma; |
8c857917 | 2788 | uint32_t context_size; |
7e37f889 | 2789 | struct intel_ring *ring; |
a89d1f92 | 2790 | struct i915_timeline *timeline; |
8c857917 OM |
2791 | int ret; |
2792 | ||
1d2a19c2 CW |
2793 | if (ce->state) |
2794 | return 0; | |
ede7d42b | 2795 | |
63ffbcda | 2796 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2797 | |
0b29c75a MT |
2798 | /* |
2799 | * Before the actual start of the context image, we insert a few pages | |
2800 | * for our own use and for sharing with the GuC. | |
2801 | */ | |
2802 | context_size += LRC_HEADER_PAGES * PAGE_SIZE; | |
d1675198 | 2803 | |
12d79d78 | 2804 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
467d3578 CW |
2805 | if (IS_ERR(ctx_obj)) |
2806 | return PTR_ERR(ctx_obj); | |
8c857917 | 2807 | |
82ad6443 | 2808 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL); |
bf3783e5 CW |
2809 | if (IS_ERR(vma)) { |
2810 | ret = PTR_ERR(vma); | |
2811 | goto error_deref_obj; | |
2812 | } | |
2813 | ||
a89d1f92 CW |
2814 | timeline = i915_timeline_create(ctx->i915, ctx->name); |
2815 | if (IS_ERR(timeline)) { | |
2816 | ret = PTR_ERR(timeline); | |
2817 | goto error_deref_obj; | |
2818 | } | |
2819 | ||
2820 | ring = intel_engine_create_ring(engine, timeline, ctx->ring_size); | |
2821 | i915_timeline_put(timeline); | |
dca33ecc CW |
2822 | if (IS_ERR(ring)) { |
2823 | ret = PTR_ERR(ring); | |
e84fe803 | 2824 | goto error_deref_obj; |
8670d6f9 OM |
2825 | } |
2826 | ||
dca33ecc | 2827 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2828 | if (ret) { |
2829 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2830 | goto error_ring_free; |
84c2377f OM |
2831 | } |
2832 | ||
dca33ecc | 2833 | ce->ring = ring; |
bf3783e5 | 2834 | ce->state = vma; |
ede7d42b OM |
2835 | |
2836 | return 0; | |
8670d6f9 | 2837 | |
dca33ecc | 2838 | error_ring_free: |
7e37f889 | 2839 | intel_ring_free(ring); |
e84fe803 | 2840 | error_deref_obj: |
f8c417cd | 2841 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2842 | return ret; |
ede7d42b | 2843 | } |
3e5b6f05 | 2844 | |
821ed7df | 2845 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2846 | { |
e2f80391 | 2847 | struct intel_engine_cs *engine; |
bafb2f7d | 2848 | struct i915_gem_context *ctx; |
3b3f1650 | 2849 | enum intel_engine_id id; |
bafb2f7d CW |
2850 | |
2851 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2852 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2853 | * that stored in context. As we only write new commands from | |
2854 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2855 | * starts reading from its RING_HEAD from the context, it may try to | |
2856 | * execute that junk and die. | |
2857 | * | |
2858 | * So to avoid that we reset the context images upon resume. For | |
2859 | * simplicity, we just zero everything out. | |
2860 | */ | |
829a0af2 | 2861 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
3b3f1650 | 2862 | for_each_engine(engine, dev_priv, id) { |
ab82a063 CW |
2863 | struct intel_context *ce = |
2864 | to_intel_context(ctx, engine); | |
bafb2f7d | 2865 | u32 *reg; |
3e5b6f05 | 2866 | |
bafb2f7d CW |
2867 | if (!ce->state) |
2868 | continue; | |
7d774cac | 2869 | |
bafb2f7d CW |
2870 | reg = i915_gem_object_pin_map(ce->state->obj, |
2871 | I915_MAP_WB); | |
2872 | if (WARN_ON(IS_ERR(reg))) | |
2873 | continue; | |
3e5b6f05 | 2874 | |
bafb2f7d CW |
2875 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2876 | reg[CTX_RING_HEAD+1] = 0; | |
2877 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2878 | |
a4f5ea64 | 2879 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2880 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2881 | |
e6ba9992 | 2882 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2883 | } |
3e5b6f05 TD |
2884 | } |
2885 | } | |
2c66555e CW |
2886 | |
2887 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
2888 | #include "selftests/intel_lrc.c" | |
2889 | #endif |