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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d CW |
159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
160 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
161 | GEN8_CTX_STATUS_PREEMPTED | \ | |
162 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
163 | ||
8670d6f9 OM |
164 | #define CTX_LRI_HEADER_0 0x01 |
165 | #define CTX_CONTEXT_CONTROL 0x02 | |
166 | #define CTX_RING_HEAD 0x04 | |
167 | #define CTX_RING_TAIL 0x06 | |
168 | #define CTX_RING_BUFFER_START 0x08 | |
169 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
170 | #define CTX_BB_HEAD_U 0x0c | |
171 | #define CTX_BB_HEAD_L 0x0e | |
172 | #define CTX_BB_STATE 0x10 | |
173 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
174 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
175 | #define CTX_SECOND_BB_STATE 0x16 | |
176 | #define CTX_BB_PER_CTX_PTR 0x18 | |
177 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
178 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
179 | #define CTX_LRI_HEADER_1 0x21 | |
180 | #define CTX_CTX_TIMESTAMP 0x22 | |
181 | #define CTX_PDP3_UDW 0x24 | |
182 | #define CTX_PDP3_LDW 0x26 | |
183 | #define CTX_PDP2_UDW 0x28 | |
184 | #define CTX_PDP2_LDW 0x2a | |
185 | #define CTX_PDP1_UDW 0x2c | |
186 | #define CTX_PDP1_LDW 0x2e | |
187 | #define CTX_PDP0_UDW 0x30 | |
188 | #define CTX_PDP0_LDW 0x32 | |
189 | #define CTX_LRI_HEADER_2 0x41 | |
190 | #define CTX_R_PWR_CLK_STATE 0x42 | |
191 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
192 | ||
84b790f8 BW |
193 | #define GEN8_CTX_VALID (1<<0) |
194 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
195 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
196 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
197 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 198 | |
0d925ea0 | 199 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 200 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
201 | (reg_state)[(pos)+1] = (val); \ |
202 | } while (0) | |
203 | ||
204 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 205 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
206 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
207 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 208 | } while (0) |
e5815a2e | 209 | |
9244a817 | 210 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
211 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
212 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 213 | } while (0) |
2dba3239 | 214 | |
84b790f8 BW |
215 | enum { |
216 | FAULT_AND_HANG = 0, | |
217 | FAULT_AND_HALT, /* Debug only */ | |
218 | FAULT_AND_STREAM, | |
219 | FAULT_AND_CONTINUE /* Unsupported */ | |
220 | }; | |
221 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 222 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
223 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
224 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 225 | |
0e93cdd4 CW |
226 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
227 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
228 | ||
a3aabe86 CW |
229 | #define WA_TAIL_DWORDS 2 |
230 | ||
e2efd130 | 231 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 232 | struct intel_engine_cs *engine); |
e2efd130 | 233 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
e5292823 | 234 | struct intel_engine_cs *engine); |
a3aabe86 CW |
235 | static void execlists_init_reg_state(u32 *reg_state, |
236 | struct i915_gem_context *ctx, | |
237 | struct intel_engine_cs *engine, | |
238 | struct intel_ring *ring); | |
7ba717cf | 239 | |
73e4d07f OM |
240 | /** |
241 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 242 | * @dev_priv: i915 device private |
73e4d07f OM |
243 | * @enable_execlists: value of i915.enable_execlists module parameter. |
244 | * | |
245 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 246 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
247 | * |
248 | * Return: 1 if Execlists is supported and has to be enabled. | |
249 | */ | |
c033666a | 250 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 251 | { |
a0bd6c31 ZL |
252 | /* On platforms with execlist available, vGPU will only |
253 | * support execlist mode, no ring buffer mode. | |
254 | */ | |
c033666a | 255 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
256 | return 1; |
257 | ||
c033666a | 258 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
259 | return 1; |
260 | ||
127f1003 OM |
261 | if (enable_execlists == 0) |
262 | return 0; | |
263 | ||
5a21b665 DV |
264 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
265 | USES_PPGTT(dev_priv) && | |
266 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
267 | return 1; |
268 | ||
269 | return 0; | |
270 | } | |
ede7d42b | 271 | |
ca82580c | 272 | static void |
0bc40be8 | 273 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 274 | { |
c033666a | 275 | struct drm_i915_private *dev_priv = engine->i915; |
ca82580c | 276 | |
70c2a24d | 277 | engine->disable_lite_restore_wa = |
a117f378 | 278 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && |
70c2a24d | 279 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 280 | |
0bc40be8 | 281 | engine->ctx_desc_template = GEN8_CTX_VALID; |
c033666a | 282 | if (IS_GEN8(dev_priv)) |
0bc40be8 TU |
283 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
284 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
285 | |
286 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
287 | * signalling between Command Streamers */ | |
288 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
289 | ||
290 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
291 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
292 | if (engine->disable_lite_restore_wa) |
293 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
294 | } |
295 | ||
73e4d07f | 296 | /** |
ca82580c TU |
297 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
298 | * descriptor for a pinned context | |
ca82580c | 299 | * @ctx: Context to work on |
9021ad03 | 300 | * @engine: Engine the descriptor will be used with |
73e4d07f | 301 | * |
ca82580c TU |
302 | * The context descriptor encodes various attributes of a context, |
303 | * including its GTT address and some flags. Because it's fairly | |
304 | * expensive to calculate, we'll just do it once and cache the result, | |
305 | * which remains valid until the context is unpinned. | |
306 | * | |
6e5248b5 DV |
307 | * This is what a descriptor looks like, from LSB to MSB:: |
308 | * | |
309 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
310 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
311 | * bits 32-52: ctx ID, a globally unique tag | |
312 | * bits 53-54: mbz, reserved for use by hardware | |
313 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 314 | */ |
ca82580c | 315 | static void |
e2efd130 | 316 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 317 | struct intel_engine_cs *engine) |
84b790f8 | 318 | { |
9021ad03 | 319 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 320 | u64 desc; |
84b790f8 | 321 | |
7069b144 | 322 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 323 | |
c01fc532 ZW |
324 | desc = ctx->desc_template; /* bits 3-4 */ |
325 | desc |= engine->ctx_desc_template; /* bits 0-11 */ | |
bde13ebd | 326 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 327 | /* bits 12-31 */ |
7069b144 | 328 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 329 | |
9021ad03 | 330 | ce->lrc_desc = desc; |
5af05fef MT |
331 | } |
332 | ||
e2efd130 | 333 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 334 | struct intel_engine_cs *engine) |
84b790f8 | 335 | { |
0bc40be8 | 336 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 337 | } |
203a571b | 338 | |
bbd6c47e CW |
339 | static inline void |
340 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
341 | unsigned long status) | |
84b790f8 | 342 | { |
bbd6c47e CW |
343 | /* |
344 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
345 | * The compiler should eliminate this function as dead-code. | |
346 | */ | |
347 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
348 | return; | |
6daccb0b | 349 | |
bbd6c47e | 350 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); |
84b790f8 BW |
351 | } |
352 | ||
c6a2ac71 TU |
353 | static void |
354 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
355 | { | |
356 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
357 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
358 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
359 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
360 | } | |
361 | ||
70c2a24d | 362 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 363 | { |
70c2a24d | 364 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
05d9824b | 365 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
70c2a24d | 366 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 367 | |
caddfe71 | 368 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 369 | |
c6a2ac71 TU |
370 | /* True 32b PPGTT with dynamic page allocation: update PDP |
371 | * registers and point the unallocated PDPs to scratch page. | |
372 | * PML4 is allocated during ppgtt init, so this is not needed | |
373 | * in 48-bit mode. | |
374 | */ | |
375 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
376 | execlists_update_context_pdps(ppgtt, reg_state); | |
70c2a24d CW |
377 | |
378 | return ce->lrc_desc; | |
ae1250b9 OM |
379 | } |
380 | ||
70c2a24d | 381 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 382 | { |
70c2a24d CW |
383 | struct drm_i915_private *dev_priv = engine->i915; |
384 | struct execlist_port *port = engine->execlist_port; | |
bbd6c47e CW |
385 | u32 __iomem *elsp = |
386 | dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
387 | u64 desc[2]; | |
388 | ||
70c2a24d CW |
389 | if (!port[0].count) |
390 | execlists_context_status_change(port[0].request, | |
391 | INTEL_CONTEXT_SCHEDULE_IN); | |
392 | desc[0] = execlists_update_context(port[0].request); | |
393 | engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */ | |
394 | ||
395 | if (port[1].request) { | |
396 | GEM_BUG_ON(port[1].count); | |
397 | execlists_context_status_change(port[1].request, | |
398 | INTEL_CONTEXT_SCHEDULE_IN); | |
399 | desc[1] = execlists_update_context(port[1].request); | |
400 | port[1].count = 1; | |
bbd6c47e CW |
401 | } else { |
402 | desc[1] = 0; | |
403 | } | |
70c2a24d | 404 | GEM_BUG_ON(desc[0] == desc[1]); |
bbd6c47e CW |
405 | |
406 | /* You must always write both descriptors in the order below. */ | |
407 | writel(upper_32_bits(desc[1]), elsp); | |
408 | writel(lower_32_bits(desc[1]), elsp); | |
409 | ||
410 | writel(upper_32_bits(desc[0]), elsp); | |
411 | /* The context is automatically loaded after the following */ | |
412 | writel(lower_32_bits(desc[0]), elsp); | |
413 | } | |
414 | ||
70c2a24d | 415 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 416 | { |
70c2a24d CW |
417 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
418 | ctx->execlists_force_single_submission); | |
419 | } | |
84b790f8 | 420 | |
70c2a24d CW |
421 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
422 | const struct i915_gem_context *next) | |
423 | { | |
424 | if (prev != next) | |
425 | return false; | |
26720ab9 | 426 | |
70c2a24d CW |
427 | if (ctx_single_port_submission(prev)) |
428 | return false; | |
26720ab9 | 429 | |
70c2a24d | 430 | return true; |
84b790f8 BW |
431 | } |
432 | ||
70c2a24d | 433 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 434 | { |
70c2a24d CW |
435 | struct drm_i915_gem_request *cursor, *last; |
436 | struct execlist_port *port = engine->execlist_port; | |
437 | bool submit = false; | |
438 | ||
439 | last = port->request; | |
440 | if (last) | |
441 | /* WaIdleLiteRestore:bdw,skl | |
442 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 443 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
444 | * for where we prepare the padding after the end of the |
445 | * request. | |
446 | */ | |
447 | last->tail = last->wa_tail; | |
e981e7b1 | 448 | |
70c2a24d | 449 | GEM_BUG_ON(port[1].request); |
acdd884a | 450 | |
70c2a24d CW |
451 | /* Hardware submission is through 2 ports. Conceptually each port |
452 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
453 | * static for a context, and unique to each, so we only execute | |
454 | * requests belonging to a single context from each ring. RING_HEAD | |
455 | * is maintained by the CS in the context image, it marks the place | |
456 | * where it got up to last time, and through RING_TAIL we tell the CS | |
457 | * where we want to execute up to this time. | |
458 | * | |
459 | * In this list the requests are in order of execution. Consecutive | |
460 | * requests from the same context are adjacent in the ringbuffer. We | |
461 | * can combine these requests into a single RING_TAIL update: | |
462 | * | |
463 | * RING_HEAD...req1...req2 | |
464 | * ^- RING_TAIL | |
465 | * since to execute req2 the CS must first execute req1. | |
466 | * | |
467 | * Our goal then is to point each port to the end of a consecutive | |
468 | * sequence of requests as being the most optimal (fewest wake ups | |
469 | * and context switches) submission. | |
779949f4 | 470 | */ |
acdd884a | 471 | |
70c2a24d CW |
472 | spin_lock(&engine->execlist_lock); |
473 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) { | |
474 | /* Can we combine this request with the current port? It has to | |
475 | * be the same context/ringbuffer and not have any exceptions | |
476 | * (e.g. GVT saying never to combine contexts). | |
c6a2ac71 | 477 | * |
70c2a24d CW |
478 | * If we can combine the requests, we can execute both by |
479 | * updating the RING_TAIL to point to the end of the second | |
480 | * request, and so we never need to tell the hardware about | |
481 | * the first. | |
53292cdb | 482 | */ |
70c2a24d CW |
483 | if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { |
484 | /* If we are on the second port and cannot combine | |
485 | * this request with the last, then we are done. | |
486 | */ | |
487 | if (port != engine->execlist_port) | |
488 | break; | |
489 | ||
490 | /* If GVT overrides us we only ever submit port[0], | |
491 | * leaving port[1] empty. Note that we also have | |
492 | * to be careful that we don't queue the same | |
493 | * context (even though a different request) to | |
494 | * the second port. | |
495 | */ | |
496 | if (ctx_single_port_submission(cursor->ctx)) | |
497 | break; | |
498 | ||
499 | GEM_BUG_ON(last->ctx == cursor->ctx); | |
500 | ||
501 | i915_gem_request_assign(&port->request, last); | |
502 | port++; | |
503 | } | |
504 | last = cursor; | |
505 | submit = true; | |
506 | } | |
507 | if (submit) { | |
508 | /* Decouple all the requests submitted from the queue */ | |
509 | engine->execlist_queue.next = &cursor->execlist_link; | |
510 | cursor->execlist_link.prev = &engine->execlist_queue; | |
511 | ||
512 | i915_gem_request_assign(&port->request, last); | |
53292cdb | 513 | } |
70c2a24d | 514 | spin_unlock(&engine->execlist_lock); |
53292cdb | 515 | |
70c2a24d CW |
516 | if (submit) |
517 | execlists_submit_ports(engine); | |
acdd884a MT |
518 | } |
519 | ||
70c2a24d | 520 | static bool execlists_elsp_idle(struct intel_engine_cs *engine) |
e981e7b1 | 521 | { |
70c2a24d | 522 | return !engine->execlist_port[0].request; |
e981e7b1 TD |
523 | } |
524 | ||
0cb5670b ID |
525 | /** |
526 | * intel_execlists_idle() - Determine if all engine submission ports are idle | |
527 | * @dev_priv: i915 device private | |
528 | * | |
529 | * Return true if there are no requests pending on any of the submission ports | |
530 | * of any engines. | |
531 | */ | |
532 | bool intel_execlists_idle(struct drm_i915_private *dev_priv) | |
533 | { | |
534 | struct intel_engine_cs *engine; | |
535 | enum intel_engine_id id; | |
536 | ||
537 | if (!i915.enable_execlists) | |
538 | return true; | |
539 | ||
540 | for_each_engine(engine, dev_priv, id) | |
541 | if (!execlists_elsp_idle(engine)) | |
542 | return false; | |
543 | ||
544 | return true; | |
545 | } | |
546 | ||
70c2a24d | 547 | static bool execlists_elsp_ready(struct intel_engine_cs *engine) |
91a41032 | 548 | { |
70c2a24d | 549 | int port; |
91a41032 | 550 | |
70c2a24d CW |
551 | port = 1; /* wait for a free slot */ |
552 | if (engine->disable_lite_restore_wa || engine->preempt_wa) | |
553 | port = 0; /* wait for GPU to be idle before continuing */ | |
c6a2ac71 | 554 | |
70c2a24d | 555 | return !engine->execlist_port[port].request; |
91a41032 BW |
556 | } |
557 | ||
6e5248b5 | 558 | /* |
73e4d07f OM |
559 | * Check the unread Context Status Buffers and manage the submission of new |
560 | * contexts to the ELSP accordingly. | |
561 | */ | |
27af5eea | 562 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 563 | { |
27af5eea | 564 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 565 | struct execlist_port *port = engine->execlist_port; |
c033666a | 566 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 567 | |
3756685a | 568 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 569 | |
70c2a24d CW |
570 | if (!execlists_elsp_idle(engine)) { |
571 | u32 __iomem *csb_mmio = | |
572 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
573 | u32 __iomem *buf = | |
574 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
575 | unsigned int csb, head, tail; | |
576 | ||
577 | csb = readl(csb_mmio); | |
578 | head = GEN8_CSB_READ_PTR(csb); | |
579 | tail = GEN8_CSB_WRITE_PTR(csb); | |
580 | if (tail < head) | |
581 | tail += GEN8_CSB_ENTRIES; | |
582 | while (head < tail) { | |
583 | unsigned int idx = ++head % GEN8_CSB_ENTRIES; | |
584 | unsigned int status = readl(buf + 2 * idx); | |
585 | ||
586 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) | |
587 | continue; | |
588 | ||
589 | GEM_BUG_ON(port[0].count == 0); | |
590 | if (--port[0].count == 0) { | |
591 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); | |
592 | execlists_context_status_change(port[0].request, | |
593 | INTEL_CONTEXT_SCHEDULE_OUT); | |
594 | ||
595 | i915_gem_request_put(port[0].request); | |
596 | port[0] = port[1]; | |
597 | memset(&port[1], 0, sizeof(port[1])); | |
598 | ||
599 | engine->preempt_wa = false; | |
600 | } | |
26720ab9 | 601 | |
70c2a24d CW |
602 | GEM_BUG_ON(port[0].count == 0 && |
603 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
e1fee72c OM |
604 | } |
605 | ||
70c2a24d CW |
606 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, |
607 | GEN8_CSB_WRITE_PTR(csb) << 8), | |
608 | csb_mmio); | |
e981e7b1 TD |
609 | } |
610 | ||
70c2a24d CW |
611 | if (execlists_elsp_ready(engine)) |
612 | execlists_dequeue(engine); | |
c6a2ac71 | 613 | |
70c2a24d | 614 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
615 | } |
616 | ||
f4ea6bdd | 617 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 618 | { |
4a570db5 | 619 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 620 | unsigned long flags; |
acdd884a | 621 | |
5590af3e | 622 | spin_lock_irqsave(&engine->execlist_lock, flags); |
acdd884a | 623 | |
caddfe71 CW |
624 | /* We keep the previous context alive until we retire the following |
625 | * request. This ensures that any the context object is still pinned | |
626 | * for any residual writes the HW makes into it on the context switch | |
627 | * into the next object following the breadcrumb. Otherwise, we may | |
628 | * retire the context too early. | |
629 | */ | |
630 | request->previous_context = engine->last_context; | |
631 | engine->last_context = request->ctx; | |
632 | ||
ba49b2f8 | 633 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
70c2a24d CW |
634 | if (execlists_elsp_idle(engine)) |
635 | tasklet_hi_schedule(&engine->irq_tasklet); | |
acdd884a | 636 | |
5590af3e | 637 | spin_unlock_irqrestore(&engine->execlist_lock, flags); |
acdd884a MT |
638 | } |
639 | ||
40e895ce | 640 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 641 | { |
24f1d3cc | 642 | struct intel_engine_cs *engine = request->engine; |
9021ad03 | 643 | struct intel_context *ce = &request->ctx->engine[engine->id]; |
bfa01200 | 644 | int ret; |
bc0dce3f | 645 | |
6310346e CW |
646 | /* Flush enough space to reduce the likelihood of waiting after |
647 | * we start building the request - in which case we will just | |
648 | * have to repeat work. | |
649 | */ | |
0e93cdd4 | 650 | request->reserved_space += EXECLISTS_REQUEST_SIZE; |
6310346e | 651 | |
9021ad03 | 652 | if (!ce->state) { |
978f1e09 CW |
653 | ret = execlists_context_deferred_alloc(request->ctx, engine); |
654 | if (ret) | |
655 | return ret; | |
656 | } | |
657 | ||
dca33ecc | 658 | request->ring = ce->ring; |
f3cc01f0 | 659 | |
5ba89908 CW |
660 | ret = intel_lr_context_pin(request->ctx, engine); |
661 | if (ret) | |
662 | return ret; | |
663 | ||
a7e02199 AD |
664 | if (i915.enable_guc_submission) { |
665 | /* | |
666 | * Check that the GuC has space for the request before | |
667 | * going any further, as the i915_add_request() call | |
668 | * later on mustn't fail ... | |
669 | */ | |
7a9347f9 | 670 | ret = i915_guc_wq_reserve(request); |
a7e02199 | 671 | if (ret) |
5ba89908 | 672 | goto err_unpin; |
a7e02199 AD |
673 | } |
674 | ||
bfa01200 CW |
675 | ret = intel_ring_begin(request, 0); |
676 | if (ret) | |
5ba89908 | 677 | goto err_unreserve; |
bfa01200 | 678 | |
9021ad03 | 679 | if (!ce->initialised) { |
24f1d3cc CW |
680 | ret = engine->init_context(request); |
681 | if (ret) | |
5ba89908 | 682 | goto err_unreserve; |
24f1d3cc | 683 | |
9021ad03 | 684 | ce->initialised = true; |
24f1d3cc CW |
685 | } |
686 | ||
687 | /* Note that after this point, we have committed to using | |
688 | * this request as it is being used to both track the | |
689 | * state of engine initialisation and liveness of the | |
690 | * golden renderstate above. Think twice before you try | |
691 | * to cancel/unwind this request now. | |
692 | */ | |
693 | ||
0e93cdd4 | 694 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; |
bfa01200 CW |
695 | return 0; |
696 | ||
5ba89908 CW |
697 | err_unreserve: |
698 | if (i915.enable_guc_submission) | |
699 | i915_guc_wq_unreserve(request); | |
bfa01200 | 700 | err_unpin: |
24f1d3cc | 701 | intel_lr_context_unpin(request->ctx, engine); |
e28e404c | 702 | return ret; |
bc0dce3f JH |
703 | } |
704 | ||
e2efd130 | 705 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
24f1d3cc | 706 | struct intel_engine_cs *engine) |
dcb4c12a | 707 | { |
9021ad03 | 708 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac | 709 | void *vaddr; |
ca82580c | 710 | int ret; |
dcb4c12a | 711 | |
91c8a326 | 712 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 713 | |
9021ad03 | 714 | if (ce->pin_count++) |
24f1d3cc CW |
715 | return 0; |
716 | ||
bf3783e5 CW |
717 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, |
718 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL); | |
e84fe803 | 719 | if (ret) |
24f1d3cc | 720 | goto err; |
7ba717cf | 721 | |
bf3783e5 | 722 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
723 | if (IS_ERR(vaddr)) { |
724 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 725 | goto unpin_vma; |
82352e90 TU |
726 | } |
727 | ||
aad29fbb | 728 | ret = intel_ring_pin(ce->ring); |
e84fe803 | 729 | if (ret) |
7d774cac | 730 | goto unpin_map; |
d1675198 | 731 | |
0bc40be8 | 732 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 733 | |
a3aabe86 CW |
734 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
735 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 736 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 737 | |
a4f5ea64 | 738 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 739 | |
e84fe803 | 740 | /* Invalidate GuC TLB. */ |
bf3783e5 CW |
741 | if (i915.enable_guc_submission) { |
742 | struct drm_i915_private *dev_priv = ctx->i915; | |
e84fe803 | 743 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
bf3783e5 | 744 | } |
dcb4c12a | 745 | |
9a6feaf0 | 746 | i915_gem_context_get(ctx); |
24f1d3cc | 747 | return 0; |
7ba717cf | 748 | |
7d774cac | 749 | unpin_map: |
bf3783e5 CW |
750 | i915_gem_object_unpin_map(ce->state->obj); |
751 | unpin_vma: | |
752 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 753 | err: |
9021ad03 | 754 | ce->pin_count = 0; |
e84fe803 NH |
755 | return ret; |
756 | } | |
757 | ||
e2efd130 | 758 | void intel_lr_context_unpin(struct i915_gem_context *ctx, |
24f1d3cc | 759 | struct intel_engine_cs *engine) |
e84fe803 | 760 | { |
9021ad03 | 761 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 762 | |
91c8a326 | 763 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 764 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 765 | |
9021ad03 | 766 | if (--ce->pin_count) |
24f1d3cc | 767 | return; |
e84fe803 | 768 | |
aad29fbb | 769 | intel_ring_unpin(ce->ring); |
dcb4c12a | 770 | |
bf3783e5 CW |
771 | i915_gem_object_unpin_map(ce->state->obj); |
772 | i915_vma_unpin(ce->state); | |
321fe304 | 773 | |
9a6feaf0 | 774 | i915_gem_context_put(ctx); |
dcb4c12a OM |
775 | } |
776 | ||
e2be4faf | 777 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
778 | { |
779 | int ret, i; | |
7e37f889 | 780 | struct intel_ring *ring = req->ring; |
c033666a | 781 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 782 | |
cd7feaaa | 783 | if (w->count == 0) |
771b9a53 MT |
784 | return 0; |
785 | ||
7c9cf4e3 | 786 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
787 | if (ret) |
788 | return ret; | |
789 | ||
987046ad | 790 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
791 | if (ret) |
792 | return ret; | |
793 | ||
1dae2dfb | 794 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
771b9a53 | 795 | for (i = 0; i < w->count; i++) { |
1dae2dfb CW |
796 | intel_ring_emit_reg(ring, w->reg[i].addr); |
797 | intel_ring_emit(ring, w->reg[i].value); | |
771b9a53 | 798 | } |
1dae2dfb | 799 | intel_ring_emit(ring, MI_NOOP); |
771b9a53 | 800 | |
1dae2dfb | 801 | intel_ring_advance(ring); |
771b9a53 | 802 | |
7c9cf4e3 | 803 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
804 | if (ret) |
805 | return ret; | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
83b8a982 | 810 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 811 | do { \ |
83b8a982 AS |
812 | int __index = (index)++; \ |
813 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
814 | return -ENOSPC; \ |
815 | } \ | |
83b8a982 | 816 | batch[__index] = (cmd); \ |
17ee950d AS |
817 | } while (0) |
818 | ||
8f40db77 | 819 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 820 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
821 | |
822 | /* | |
823 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
824 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
825 | * but there is a slight complication as this is applied in WA batch where the | |
826 | * values are only initialized once so we cannot take register value at the | |
827 | * beginning and reuse it further; hence we save its value to memory, upload a | |
828 | * constant value with bit21 set and then we restore it back with the saved value. | |
829 | * To simplify the WA, a constant value is formed by using the default value | |
830 | * of this register. This shouldn't be a problem because we are only modifying | |
831 | * it for a short period and this batch in non-premptible. We can ofcourse | |
832 | * use additional instructions that read the actual value of the register | |
833 | * at that time and set our bit of interest but it makes the WA complicated. | |
834 | * | |
835 | * This WA is also required for Gen9 so extracting as a function avoids | |
836 | * code duplication. | |
837 | */ | |
0bc40be8 | 838 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
6e5248b5 | 839 | uint32_t *batch, |
9e000847 AS |
840 | uint32_t index) |
841 | { | |
5e580523 | 842 | struct drm_i915_private *dev_priv = engine->i915; |
9e000847 AS |
843 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
844 | ||
a4106a78 | 845 | /* |
3be192e9 | 846 | * WaDisableLSQCROPERFforOCL:kbl |
a4106a78 AS |
847 | * This WA is implemented in skl_init_clock_gating() but since |
848 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
849 | * set this bit here to retain the WA during flush. | |
850 | */ | |
3be192e9 | 851 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) |
a4106a78 AS |
852 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
853 | ||
f1afe24f | 854 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 855 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 856 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 857 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 AS |
858 | wa_ctx_emit(batch, index, 0); |
859 | ||
860 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 861 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
862 | wa_ctx_emit(batch, index, l3sqc4_flush); |
863 | ||
864 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
865 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
866 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
867 | wa_ctx_emit(batch, index, 0); | |
868 | wa_ctx_emit(batch, index, 0); | |
869 | wa_ctx_emit(batch, index, 0); | |
870 | wa_ctx_emit(batch, index, 0); | |
871 | ||
f1afe24f | 872 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 873 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 874 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 875 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 | 876 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
877 | |
878 | return index; | |
879 | } | |
880 | ||
17ee950d AS |
881 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
882 | uint32_t offset, | |
883 | uint32_t start_alignment) | |
884 | { | |
885 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
886 | } | |
887 | ||
888 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
889 | uint32_t offset, | |
890 | uint32_t size_alignment) | |
891 | { | |
892 | wa_ctx->size = offset - wa_ctx->offset; | |
893 | ||
894 | WARN(wa_ctx->size % size_alignment, | |
895 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
896 | wa_ctx->size, size_alignment); | |
897 | return 0; | |
898 | } | |
899 | ||
6e5248b5 DV |
900 | /* |
901 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
902 | * initialized at the beginning and shared across all contexts but this field | |
903 | * helps us to have multiple batches at different offsets and select them based | |
904 | * on a criteria. At the moment this batch always start at the beginning of the page | |
905 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 906 | * |
6e5248b5 DV |
907 | * The number of WA applied are not known at the beginning; we use this field |
908 | * to return the no of DWORDS written. | |
17ee950d | 909 | * |
6e5248b5 DV |
910 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
911 | * so it adds NOOPs as padding to make it cacheline aligned. | |
912 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
913 | * makes a complete batch buffer. | |
17ee950d | 914 | */ |
0bc40be8 | 915 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d | 916 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 917 | uint32_t *batch, |
17ee950d AS |
918 | uint32_t *offset) |
919 | { | |
0160f055 | 920 | uint32_t scratch_addr; |
17ee950d AS |
921 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
922 | ||
7ad00d1a | 923 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 924 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 925 | |
c82435bb | 926 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 927 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 928 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
929 | if (rc < 0) |
930 | return rc; | |
931 | index = rc; | |
c82435bb AS |
932 | } |
933 | ||
0160f055 AS |
934 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
935 | /* Actual scratch location is at 128 bytes offset */ | |
bde13ebd | 936 | scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
0160f055 | 937 | |
83b8a982 AS |
938 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
939 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
940 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
941 | PIPE_CONTROL_CS_STALL | | |
942 | PIPE_CONTROL_QW_WRITE)); | |
943 | wa_ctx_emit(batch, index, scratch_addr); | |
944 | wa_ctx_emit(batch, index, 0); | |
945 | wa_ctx_emit(batch, index, 0); | |
946 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 947 | |
17ee950d AS |
948 | /* Pad to end of cacheline */ |
949 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 950 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
951 | |
952 | /* | |
953 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
954 | * execution depends on the length specified in terms of cache lines | |
955 | * in the register CTX_RCS_INDIRECT_CTX | |
956 | */ | |
957 | ||
958 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
959 | } | |
960 | ||
6e5248b5 DV |
961 | /* |
962 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
963 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 964 | * |
6e5248b5 | 965 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
966 | * |
967 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
968 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
969 | */ | |
0bc40be8 | 970 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d | 971 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 972 | uint32_t *batch, |
17ee950d AS |
973 | uint32_t *offset) |
974 | { | |
975 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
976 | ||
7ad00d1a | 977 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 978 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 979 | |
83b8a982 | 980 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
981 | |
982 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
983 | } | |
984 | ||
0bc40be8 | 985 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc | 986 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 987 | uint32_t *batch, |
0504cffc AS |
988 | uint32_t *offset) |
989 | { | |
a4106a78 | 990 | int ret; |
5e580523 | 991 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
992 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
993 | ||
9fc736e8 JN |
994 | /* WaDisableCtxRestoreArbitration:bxt */ |
995 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
0907c8f7 | 996 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 997 | |
a4106a78 | 998 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 999 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1000 | if (ret < 0) |
1001 | return ret; | |
1002 | index = ret; | |
1003 | ||
873e8171 MK |
1004 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ |
1005 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1006 | wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); | |
1007 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( | |
1008 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); | |
1009 | wa_ctx_emit(batch, index, MI_NOOP); | |
1010 | ||
066d4628 MK |
1011 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1012 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1013 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
56c0f1a7 | 1014 | u32 scratch_addr = |
bde13ebd | 1015 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
066d4628 MK |
1016 | |
1017 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1018 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1019 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1020 | PIPE_CONTROL_CS_STALL | | |
1021 | PIPE_CONTROL_QW_WRITE)); | |
1022 | wa_ctx_emit(batch, index, scratch_addr); | |
1023 | wa_ctx_emit(batch, index, 0); | |
1024 | wa_ctx_emit(batch, index, 0); | |
1025 | wa_ctx_emit(batch, index, 0); | |
1026 | } | |
3485d99e TG |
1027 | |
1028 | /* WaMediaPoolStateCmdInWABB:bxt */ | |
1029 | if (HAS_POOLED_EU(engine->i915)) { | |
1030 | /* | |
1031 | * EU pool configuration is setup along with golden context | |
1032 | * during context initialization. This value depends on | |
1033 | * device type (2x6 or 3x6) and needs to be updated based | |
1034 | * on which subslice is disabled especially for 2x6 | |
1035 | * devices, however it is safe to load default | |
1036 | * configuration of 3x6 device instead of masking off | |
1037 | * corresponding bits because HW ignores bits of a disabled | |
1038 | * subslice and drops down to appropriate config. Please | |
1039 | * see render_state_setup() in i915_gem_render_state.c for | |
1040 | * possible configurations, to avoid duplication they are | |
1041 | * not shown here again. | |
1042 | */ | |
1043 | u32 eu_pool_config = 0x00777000; | |
1044 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1045 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1046 | wa_ctx_emit(batch, index, eu_pool_config); | |
1047 | wa_ctx_emit(batch, index, 0); | |
1048 | wa_ctx_emit(batch, index, 0); | |
1049 | wa_ctx_emit(batch, index, 0); | |
1050 | } | |
1051 | ||
0504cffc AS |
1052 | /* Pad to end of cacheline */ |
1053 | while (index % CACHELINE_DWORDS) | |
1054 | wa_ctx_emit(batch, index, MI_NOOP); | |
1055 | ||
1056 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1057 | } | |
1058 | ||
0bc40be8 | 1059 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1060 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1061 | uint32_t *batch, |
0504cffc AS |
1062 | uint32_t *offset) |
1063 | { | |
1064 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1065 | ||
a117f378 JN |
1066 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ |
1067 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { | |
9b01435d | 1068 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1069 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1070 | wa_ctx_emit(batch, index, |
1071 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1072 | wa_ctx_emit(batch, index, MI_NOOP); | |
1073 | } | |
1074 | ||
b1e429fe | 1075 | /* WaClearTdlStateAckDirtyBits:bxt */ |
c033666a | 1076 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) { |
b1e429fe TG |
1077 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
1078 | ||
1079 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1080 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1081 | ||
1082 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1083 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1084 | ||
1085 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1086 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1087 | ||
1088 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1089 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1090 | wa_ctx_emit(batch, index, 0x0); | |
1091 | wa_ctx_emit(batch, index, MI_NOOP); | |
1092 | } | |
1093 | ||
9fc736e8 JN |
1094 | /* WaDisableCtxRestoreArbitration:bxt */ |
1095 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) | |
0907c8f7 AS |
1096 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1097 | ||
0504cffc AS |
1098 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1099 | ||
1100 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1101 | } | |
1102 | ||
0bc40be8 | 1103 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d | 1104 | { |
48bb74e4 CW |
1105 | struct drm_i915_gem_object *obj; |
1106 | struct i915_vma *vma; | |
1107 | int err; | |
17ee950d | 1108 | |
48bb74e4 CW |
1109 | obj = i915_gem_object_create(&engine->i915->drm, PAGE_ALIGN(size)); |
1110 | if (IS_ERR(obj)) | |
1111 | return PTR_ERR(obj); | |
17ee950d | 1112 | |
48bb74e4 CW |
1113 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1114 | if (IS_ERR(vma)) { | |
1115 | err = PTR_ERR(vma); | |
1116 | goto err; | |
17ee950d AS |
1117 | } |
1118 | ||
48bb74e4 CW |
1119 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1120 | if (err) | |
1121 | goto err; | |
1122 | ||
1123 | engine->wa_ctx.vma = vma; | |
17ee950d | 1124 | return 0; |
48bb74e4 CW |
1125 | |
1126 | err: | |
1127 | i915_gem_object_put(obj); | |
1128 | return err; | |
17ee950d AS |
1129 | } |
1130 | ||
0bc40be8 | 1131 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1132 | { |
19880c4a | 1133 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1134 | } |
1135 | ||
0bc40be8 | 1136 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1137 | { |
48bb74e4 | 1138 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d AS |
1139 | uint32_t *batch; |
1140 | uint32_t offset; | |
1141 | struct page *page; | |
48bb74e4 | 1142 | int ret; |
17ee950d | 1143 | |
0bc40be8 | 1144 | WARN_ON(engine->id != RCS); |
17ee950d | 1145 | |
5e60d790 | 1146 | /* update this when WA for higher Gen are added */ |
c033666a | 1147 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1148 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1149 | INTEL_GEN(engine->i915)); |
5e60d790 | 1150 | return 0; |
0504cffc | 1151 | } |
5e60d790 | 1152 | |
c4db7599 | 1153 | /* some WA perform writes to scratch page, ensure it is valid */ |
56c0f1a7 | 1154 | if (!engine->scratch) { |
0bc40be8 | 1155 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
c4db7599 AS |
1156 | return -EINVAL; |
1157 | } | |
1158 | ||
0bc40be8 | 1159 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1160 | if (ret) { |
1161 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1162 | return ret; | |
1163 | } | |
1164 | ||
48bb74e4 | 1165 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
17ee950d AS |
1166 | batch = kmap_atomic(page); |
1167 | offset = 0; | |
1168 | ||
c033666a | 1169 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1170 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1171 | &wa_ctx->indirect_ctx, |
1172 | batch, | |
1173 | &offset); | |
1174 | if (ret) | |
1175 | goto out; | |
1176 | ||
0bc40be8 | 1177 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1178 | &wa_ctx->per_ctx, |
1179 | batch, | |
1180 | &offset); | |
1181 | if (ret) | |
1182 | goto out; | |
c033666a | 1183 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1184 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1185 | &wa_ctx->indirect_ctx, |
1186 | batch, | |
1187 | &offset); | |
1188 | if (ret) | |
1189 | goto out; | |
1190 | ||
0bc40be8 | 1191 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1192 | &wa_ctx->per_ctx, |
1193 | batch, | |
1194 | &offset); | |
1195 | if (ret) | |
1196 | goto out; | |
17ee950d AS |
1197 | } |
1198 | ||
1199 | out: | |
1200 | kunmap_atomic(batch); | |
1201 | if (ret) | |
0bc40be8 | 1202 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1203 | |
1204 | return ret; | |
1205 | } | |
1206 | ||
04794adb TU |
1207 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1208 | { | |
c033666a | 1209 | struct drm_i915_private *dev_priv = engine->i915; |
04794adb TU |
1210 | |
1211 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
57e88531 | 1212 | engine->status_page.ggtt_offset); |
04794adb TU |
1213 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
1214 | } | |
1215 | ||
0bc40be8 | 1216 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1217 | { |
c033666a | 1218 | struct drm_i915_private *dev_priv = engine->i915; |
821ed7df CW |
1219 | int ret; |
1220 | ||
1221 | ret = intel_mocs_init_engine(engine); | |
1222 | if (ret) | |
1223 | return ret; | |
9b1136d5 | 1224 | |
04794adb | 1225 | lrc_init_hws(engine); |
e84fe803 | 1226 | |
ad07dfcd | 1227 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 1228 | |
0bc40be8 | 1229 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
73d477f6 | 1230 | |
0bc40be8 | 1231 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1232 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1233 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
dfc53c5e | 1234 | |
0bc40be8 | 1235 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1236 | |
fc0768ce | 1237 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1238 | |
c87d50cc CW |
1239 | /* After a GPU reset, we may have requests to replay */ |
1240 | if (!execlists_elsp_idle(engine)) { | |
1241 | engine->execlist_port[0].count = 0; | |
1242 | engine->execlist_port[1].count = 0; | |
821ed7df | 1243 | execlists_submit_ports(engine); |
c87d50cc | 1244 | } |
821ed7df CW |
1245 | |
1246 | return 0; | |
9b1136d5 OM |
1247 | } |
1248 | ||
0bc40be8 | 1249 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1250 | { |
c033666a | 1251 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1252 | int ret; |
1253 | ||
0bc40be8 | 1254 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1255 | if (ret) |
1256 | return ret; | |
1257 | ||
1258 | /* We need to disable the AsyncFlip performance optimisations in order | |
1259 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1260 | * programmed to '1' on all products. | |
1261 | * | |
1262 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1263 | */ | |
1264 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1265 | ||
9b1136d5 OM |
1266 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1267 | ||
0bc40be8 | 1268 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1269 | } |
1270 | ||
0bc40be8 | 1271 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1272 | { |
1273 | int ret; | |
1274 | ||
0bc40be8 | 1275 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1276 | if (ret) |
1277 | return ret; | |
1278 | ||
0bc40be8 | 1279 | return init_workarounds_ring(engine); |
82ef822e DL |
1280 | } |
1281 | ||
821ed7df CW |
1282 | static void reset_common_ring(struct intel_engine_cs *engine, |
1283 | struct drm_i915_gem_request *request) | |
1284 | { | |
1285 | struct drm_i915_private *dev_priv = engine->i915; | |
1286 | struct execlist_port *port = engine->execlist_port; | |
1287 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
1288 | ||
a3aabe86 CW |
1289 | /* We want a simple context + ring to execute the breadcrumb update. |
1290 | * We cannot rely on the context being intact across the GPU hang, | |
1291 | * so clear it and rebuild just what we need for the breadcrumb. | |
1292 | * All pending requests for this context will be zapped, and any | |
1293 | * future request will be after userspace has had the opportunity | |
1294 | * to recreate its own state. | |
1295 | */ | |
1296 | execlists_init_reg_state(ce->lrc_reg_state, | |
1297 | request->ctx, engine, ce->ring); | |
1298 | ||
821ed7df | 1299 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1300 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1301 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1302 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1303 | |
821ed7df CW |
1304 | request->ring->head = request->postfix; |
1305 | request->ring->last_retired_head = -1; | |
1306 | intel_ring_update_space(request->ring); | |
1307 | ||
1308 | if (i915.enable_guc_submission) | |
1309 | return; | |
1310 | ||
1311 | /* Catch up with any missed context-switch interrupts */ | |
1312 | I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0)); | |
1313 | if (request->ctx != port[0].request->ctx) { | |
1314 | i915_gem_request_put(port[0].request); | |
1315 | port[0] = port[1]; | |
1316 | memset(&port[1], 0, sizeof(port[1])); | |
1317 | } | |
1318 | ||
821ed7df | 1319 | GEM_BUG_ON(request->ctx != port[0].request->ctx); |
a3aabe86 CW |
1320 | |
1321 | /* Reset WaIdleLiteRestore:bdw,skl as well */ | |
1322 | request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); | |
821ed7df CW |
1323 | } |
1324 | ||
7a01a0a2 MT |
1325 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1326 | { | |
1327 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
7e37f889 | 1328 | struct intel_ring *ring = req->ring; |
4a570db5 | 1329 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1330 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
1331 | int i, ret; | |
1332 | ||
987046ad | 1333 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1334 | if (ret) |
1335 | return ret; | |
1336 | ||
b5321f30 | 1337 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
7a01a0a2 MT |
1338 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
1339 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1340 | ||
b5321f30 CW |
1341 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i)); |
1342 | intel_ring_emit(ring, upper_32_bits(pd_daddr)); | |
1343 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i)); | |
1344 | intel_ring_emit(ring, lower_32_bits(pd_daddr)); | |
7a01a0a2 MT |
1345 | } |
1346 | ||
b5321f30 CW |
1347 | intel_ring_emit(ring, MI_NOOP); |
1348 | intel_ring_advance(ring); | |
7a01a0a2 MT |
1349 | |
1350 | return 0; | |
1351 | } | |
1352 | ||
be795fc1 | 1353 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba CW |
1354 | u64 offset, u32 len, |
1355 | unsigned int dispatch_flags) | |
15648585 | 1356 | { |
7e37f889 | 1357 | struct intel_ring *ring = req->ring; |
8e004efc | 1358 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1359 | int ret; |
1360 | ||
7a01a0a2 MT |
1361 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1362 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1363 | * but we can't. Force Restore would be a second option, but | |
1364 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1365 | * not idle). PML4 is allocated during ppgtt init so this is |
1366 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1367 | if (req->ctx->ppgtt && |
666796da | 1368 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1369 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1370 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1371 | ret = intel_logical_ring_emit_pdps(req); |
1372 | if (ret) | |
1373 | return ret; | |
1374 | } | |
7a01a0a2 | 1375 | |
666796da | 1376 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1377 | } |
1378 | ||
987046ad | 1379 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1380 | if (ret) |
1381 | return ret; | |
1382 | ||
1383 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 CW |
1384 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | |
1385 | (ppgtt<<8) | | |
1386 | (dispatch_flags & I915_DISPATCH_RS ? | |
1387 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
1388 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1389 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1390 | intel_ring_emit(ring, MI_NOOP); | |
1391 | intel_ring_advance(ring); | |
15648585 OM |
1392 | |
1393 | return 0; | |
1394 | } | |
1395 | ||
31bb59cc | 1396 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1397 | { |
c033666a | 1398 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1399 | I915_WRITE_IMR(engine, |
1400 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1401 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1402 | } |
1403 | ||
31bb59cc | 1404 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1405 | { |
c033666a | 1406 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1407 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1408 | } |
1409 | ||
7c9cf4e3 | 1410 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1411 | { |
7e37f889 CW |
1412 | struct intel_ring *ring = request->ring; |
1413 | u32 cmd; | |
4712274c OM |
1414 | int ret; |
1415 | ||
987046ad | 1416 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1417 | if (ret) |
1418 | return ret; | |
1419 | ||
1420 | cmd = MI_FLUSH_DW + 1; | |
1421 | ||
f0a1fb10 CW |
1422 | /* We always require a command barrier so that subsequent |
1423 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1424 | * wrt the contents of the write cache being flushed to memory | |
1425 | * (and thus being coherent from the CPU). | |
1426 | */ | |
1427 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1428 | ||
7c9cf4e3 | 1429 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1430 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1431 | if (request->engine->id == VCS) |
f0a1fb10 | 1432 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1433 | } |
1434 | ||
b5321f30 CW |
1435 | intel_ring_emit(ring, cmd); |
1436 | intel_ring_emit(ring, | |
1437 | I915_GEM_HWS_SCRATCH_ADDR | | |
1438 | MI_FLUSH_DW_USE_GTT); | |
1439 | intel_ring_emit(ring, 0); /* upper addr */ | |
1440 | intel_ring_emit(ring, 0); /* value */ | |
1441 | intel_ring_advance(ring); | |
4712274c OM |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
7deb4d39 | 1446 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1447 | u32 mode) |
4712274c | 1448 | { |
7e37f889 | 1449 | struct intel_ring *ring = request->ring; |
b5321f30 | 1450 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1451 | u32 scratch_addr = |
1452 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1453 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1454 | u32 flags = 0; |
1455 | int ret; | |
0b2d0934 | 1456 | int len; |
4712274c OM |
1457 | |
1458 | flags |= PIPE_CONTROL_CS_STALL; | |
1459 | ||
7c9cf4e3 | 1460 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1461 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1462 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1463 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1464 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1465 | } |
1466 | ||
7c9cf4e3 | 1467 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1468 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1469 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1470 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1471 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1472 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1473 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1474 | flags |= PIPE_CONTROL_QW_WRITE; | |
1475 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1476 | |
1a5a9ce7 BW |
1477 | /* |
1478 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1479 | * pipe control. | |
1480 | */ | |
c033666a | 1481 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1482 | vf_flush_wa = true; |
0b2d0934 MK |
1483 | |
1484 | /* WaForGAMHang:kbl */ | |
1485 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1486 | dc_flush_wa = true; | |
1a5a9ce7 | 1487 | } |
9647ff36 | 1488 | |
0b2d0934 MK |
1489 | len = 6; |
1490 | ||
1491 | if (vf_flush_wa) | |
1492 | len += 6; | |
1493 | ||
1494 | if (dc_flush_wa) | |
1495 | len += 12; | |
1496 | ||
1497 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1498 | if (ret) |
1499 | return ret; | |
1500 | ||
9647ff36 | 1501 | if (vf_flush_wa) { |
b5321f30 CW |
1502 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1503 | intel_ring_emit(ring, 0); | |
1504 | intel_ring_emit(ring, 0); | |
1505 | intel_ring_emit(ring, 0); | |
1506 | intel_ring_emit(ring, 0); | |
1507 | intel_ring_emit(ring, 0); | |
9647ff36 ID |
1508 | } |
1509 | ||
0b2d0934 | 1510 | if (dc_flush_wa) { |
b5321f30 CW |
1511 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1512 | intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1513 | intel_ring_emit(ring, 0); | |
1514 | intel_ring_emit(ring, 0); | |
1515 | intel_ring_emit(ring, 0); | |
1516 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1517 | } |
1518 | ||
b5321f30 CW |
1519 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1520 | intel_ring_emit(ring, flags); | |
1521 | intel_ring_emit(ring, scratch_addr); | |
1522 | intel_ring_emit(ring, 0); | |
1523 | intel_ring_emit(ring, 0); | |
1524 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1525 | |
1526 | if (dc_flush_wa) { | |
b5321f30 CW |
1527 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1528 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); | |
1529 | intel_ring_emit(ring, 0); | |
1530 | intel_ring_emit(ring, 0); | |
1531 | intel_ring_emit(ring, 0); | |
1532 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1533 | } |
1534 | ||
b5321f30 | 1535 | intel_ring_advance(ring); |
4712274c OM |
1536 | |
1537 | return 0; | |
1538 | } | |
1539 | ||
c04e0f3b | 1540 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1541 | { |
319404df ID |
1542 | /* |
1543 | * On BXT A steppings there is a HW coherency issue whereby the | |
1544 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1545 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1546 | * clflushing the corresponding cacheline whenever the caller wants | |
1547 | * the coherency to be guaranteed. Note that this cacheline is known | |
1548 | * to be clean at this point, since we only write it in | |
1549 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1550 | * this clflush in practice becomes an invalidate operation. | |
1551 | */ | |
c04e0f3b | 1552 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1553 | } |
1554 | ||
7c17d377 CW |
1555 | /* |
1556 | * Reserve space for 2 NOOPs at the end of each request to be | |
1557 | * used as a workaround for not being allowed to do lite | |
1558 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1559 | */ | |
caddfe71 | 1560 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out) |
4da46e1e | 1561 | { |
caddfe71 CW |
1562 | *out++ = MI_NOOP; |
1563 | *out++ = MI_NOOP; | |
1564 | request->wa_tail = intel_ring_offset(request->ring, out); | |
1565 | } | |
4da46e1e | 1566 | |
caddfe71 CW |
1567 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, |
1568 | u32 *out) | |
1569 | { | |
7c17d377 CW |
1570 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1571 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1572 | |
caddfe71 CW |
1573 | *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1574 | *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1575 | *out++ = 0; | |
1576 | *out++ = request->global_seqno; | |
1577 | *out++ = MI_USER_INTERRUPT; | |
1578 | *out++ = MI_NOOP; | |
1579 | request->tail = intel_ring_offset(request->ring, out); | |
1580 | ||
1581 | gen8_emit_wa_tail(request, out); | |
7c17d377 | 1582 | } |
4da46e1e | 1583 | |
98f29e8d CW |
1584 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1585 | ||
caddfe71 CW |
1586 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
1587 | u32 *out) | |
7c17d377 | 1588 | { |
ce81a65c MW |
1589 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1590 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1591 | ||
7c17d377 CW |
1592 | /* w/a for post sync ops following a GPGPU operation we |
1593 | * need a prior CS_STALL, which is emitted by the flush | |
1594 | * following the batch. | |
1595 | */ | |
caddfe71 CW |
1596 | *out++ = GFX_OP_PIPE_CONTROL(6); |
1597 | *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1598 | PIPE_CONTROL_CS_STALL | | |
1599 | PIPE_CONTROL_QW_WRITE); | |
1600 | *out++ = intel_hws_seqno_address(request->engine); | |
1601 | *out++ = 0; | |
1602 | *out++ = request->global_seqno; | |
ce81a65c | 1603 | /* We're thrashing one dword of HWS. */ |
caddfe71 CW |
1604 | *out++ = 0; |
1605 | *out++ = MI_USER_INTERRUPT; | |
1606 | *out++ = MI_NOOP; | |
1607 | request->tail = intel_ring_offset(request->ring, out); | |
1608 | ||
1609 | gen8_emit_wa_tail(request, out); | |
4da46e1e OM |
1610 | } |
1611 | ||
98f29e8d CW |
1612 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1613 | ||
8753181e | 1614 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1615 | { |
1616 | int ret; | |
1617 | ||
e2be4faf | 1618 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1619 | if (ret) |
1620 | return ret; | |
1621 | ||
3bbaba0c PA |
1622 | ret = intel_rcs_context_init_mocs(req); |
1623 | /* | |
1624 | * Failing to program the MOCS is non-fatal.The system will not | |
1625 | * run at peak performance. So generate an error and carry on. | |
1626 | */ | |
1627 | if (ret) | |
1628 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1629 | ||
4e50f082 | 1630 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1631 | } |
1632 | ||
73e4d07f OM |
1633 | /** |
1634 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1635 | * @engine: Engine Command Streamer. |
73e4d07f | 1636 | */ |
0bc40be8 | 1637 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1638 | { |
6402c330 | 1639 | struct drm_i915_private *dev_priv; |
9832b9da | 1640 | |
27af5eea TU |
1641 | /* |
1642 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1643 | * so this is just for documentation. | |
1644 | */ | |
1645 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1646 | tasklet_kill(&engine->irq_tasklet); | |
1647 | ||
c033666a | 1648 | dev_priv = engine->i915; |
6402c330 | 1649 | |
0bc40be8 | 1650 | if (engine->buffer) { |
0bc40be8 | 1651 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1652 | } |
48d82387 | 1653 | |
0bc40be8 TU |
1654 | if (engine->cleanup) |
1655 | engine->cleanup(engine); | |
48d82387 | 1656 | |
96a945aa | 1657 | intel_engine_cleanup_common(engine); |
688e6c72 | 1658 | |
57e88531 CW |
1659 | if (engine->status_page.vma) { |
1660 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1661 | engine->status_page.vma = NULL; | |
48d82387 | 1662 | } |
24f1d3cc | 1663 | intel_lr_context_unpin(dev_priv->kernel_context, engine); |
17ee950d | 1664 | |
0bc40be8 | 1665 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1666 | engine->i915 = NULL; |
3b3f1650 AG |
1667 | dev_priv->engine[engine->id] = NULL; |
1668 | kfree(engine); | |
454afebd OM |
1669 | } |
1670 | ||
ddd66c51 CW |
1671 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) |
1672 | { | |
1673 | struct intel_engine_cs *engine; | |
3b3f1650 | 1674 | enum intel_engine_id id; |
ddd66c51 | 1675 | |
3b3f1650 | 1676 | for_each_engine(engine, dev_priv, id) |
f4ea6bdd | 1677 | engine->submit_request = execlists_submit_request; |
ddd66c51 CW |
1678 | } |
1679 | ||
c9cacf93 | 1680 | static void |
e1382efb | 1681 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1682 | { |
1683 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1684 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1685 | engine->reset_hw = reset_common_ring; |
0bc40be8 | 1686 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1687 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1688 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
f4ea6bdd | 1689 | engine->submit_request = execlists_submit_request; |
ddd66c51 | 1690 | |
31bb59cc CW |
1691 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1692 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1693 | engine->emit_bb_start = gen8_emit_bb_start; |
1b7744e7 | 1694 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) |
c04e0f3b | 1695 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
c9cacf93 TU |
1696 | } |
1697 | ||
d9f3af96 | 1698 | static inline void |
c2c7f240 | 1699 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1700 | { |
c2c7f240 | 1701 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1702 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1703 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1704 | } |
1705 | ||
7d774cac | 1706 | static int |
bf3783e5 | 1707 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1708 | { |
57e88531 | 1709 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1710 | void *hws; |
04794adb TU |
1711 | |
1712 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1713 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1714 | if (IS_ERR(hws)) |
1715 | return PTR_ERR(hws); | |
57e88531 CW |
1716 | |
1717 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1718 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1719 | engine->status_page.vma = vma; |
7d774cac TU |
1720 | |
1721 | return 0; | |
04794adb TU |
1722 | } |
1723 | ||
bb45438f TU |
1724 | static void |
1725 | logical_ring_setup(struct intel_engine_cs *engine) | |
1726 | { | |
1727 | struct drm_i915_private *dev_priv = engine->i915; | |
1728 | enum forcewake_domains fw_domains; | |
1729 | ||
019bf277 TU |
1730 | intel_engine_setup_common(engine); |
1731 | ||
bb45438f TU |
1732 | /* Intentionally left blank. */ |
1733 | engine->buffer = NULL; | |
1734 | ||
1735 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1736 | RING_ELSP(engine), | |
1737 | FW_REG_WRITE); | |
1738 | ||
1739 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1740 | RING_CONTEXT_STATUS_PTR(engine), | |
1741 | FW_REG_READ | FW_REG_WRITE); | |
1742 | ||
1743 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1744 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1745 | FW_REG_READ); | |
1746 | ||
1747 | engine->fw_domains = fw_domains; | |
1748 | ||
bb45438f TU |
1749 | tasklet_init(&engine->irq_tasklet, |
1750 | intel_lrc_irq_handler, (unsigned long)engine); | |
1751 | ||
1752 | logical_ring_init_platform_invariants(engine); | |
1753 | logical_ring_default_vfuncs(engine); | |
1754 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1755 | } |
1756 | ||
a19d6ff2 TU |
1757 | static int |
1758 | logical_ring_init(struct intel_engine_cs *engine) | |
1759 | { | |
1760 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1761 | int ret; | |
1762 | ||
019bf277 | 1763 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1764 | if (ret) |
1765 | goto error; | |
1766 | ||
1767 | ret = execlists_context_deferred_alloc(dctx, engine); | |
1768 | if (ret) | |
1769 | goto error; | |
1770 | ||
1771 | /* As this is the default context, always pin it */ | |
1772 | ret = intel_lr_context_pin(dctx, engine); | |
1773 | if (ret) { | |
1774 | DRM_ERROR("Failed to pin context for %s: %d\n", | |
1775 | engine->name, ret); | |
1776 | goto error; | |
1777 | } | |
1778 | ||
1779 | /* And setup the hardware status page. */ | |
1780 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1781 | if (ret) { | |
1782 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1783 | goto error; | |
1784 | } | |
1785 | ||
1786 | return 0; | |
1787 | ||
1788 | error: | |
1789 | intel_logical_ring_cleanup(engine); | |
1790 | return ret; | |
1791 | } | |
1792 | ||
88d2ba2e | 1793 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1794 | { |
1795 | struct drm_i915_private *dev_priv = engine->i915; | |
1796 | int ret; | |
1797 | ||
bb45438f TU |
1798 | logical_ring_setup(engine); |
1799 | ||
a19d6ff2 TU |
1800 | if (HAS_L3_DPF(dev_priv)) |
1801 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1802 | ||
1803 | /* Override some for render ring. */ | |
1804 | if (INTEL_GEN(dev_priv) >= 9) | |
1805 | engine->init_hw = gen9_init_render_ring; | |
1806 | else | |
1807 | engine->init_hw = gen8_init_render_ring; | |
1808 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1809 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1810 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1811 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1812 | |
56c0f1a7 | 1813 | ret = intel_engine_create_scratch(engine, 4096); |
a19d6ff2 TU |
1814 | if (ret) |
1815 | return ret; | |
1816 | ||
1817 | ret = intel_init_workaround_bb(engine); | |
1818 | if (ret) { | |
1819 | /* | |
1820 | * We continue even if we fail to initialize WA batch | |
1821 | * because we only expect rare glitches but nothing | |
1822 | * critical to prevent us from using GPU | |
1823 | */ | |
1824 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1825 | ret); | |
1826 | } | |
1827 | ||
1828 | ret = logical_ring_init(engine); | |
1829 | if (ret) { | |
1830 | lrc_destroy_wa_ctx_obj(engine); | |
1831 | } | |
1832 | ||
1833 | return ret; | |
1834 | } | |
1835 | ||
88d2ba2e | 1836 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1837 | { |
1838 | logical_ring_setup(engine); | |
1839 | ||
1840 | return logical_ring_init(engine); | |
454afebd OM |
1841 | } |
1842 | ||
0cea6502 | 1843 | static u32 |
c033666a | 1844 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1845 | { |
1846 | u32 rpcs = 0; | |
1847 | ||
1848 | /* | |
1849 | * No explicit RPCS request is needed to ensure full | |
1850 | * slice/subslice/EU enablement prior to Gen9. | |
1851 | */ | |
c033666a | 1852 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1853 | return 0; |
1854 | ||
1855 | /* | |
1856 | * Starting in Gen9, render power gating can leave | |
1857 | * slice/subslice/EU in a partially enabled state. We | |
1858 | * must make an explicit request through RPCS for full | |
1859 | * enablement. | |
1860 | */ | |
43b67998 | 1861 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1862 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1863 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1864 | GEN8_RPCS_S_CNT_SHIFT; |
1865 | rpcs |= GEN8_RPCS_ENABLE; | |
1866 | } | |
1867 | ||
43b67998 | 1868 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1869 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1870 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1871 | GEN8_RPCS_SS_CNT_SHIFT; |
1872 | rpcs |= GEN8_RPCS_ENABLE; | |
1873 | } | |
1874 | ||
43b67998 ID |
1875 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1876 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1877 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1878 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1879 | GEN8_RPCS_EU_MAX_SHIFT; |
1880 | rpcs |= GEN8_RPCS_ENABLE; | |
1881 | } | |
1882 | ||
1883 | return rpcs; | |
1884 | } | |
1885 | ||
0bc40be8 | 1886 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1887 | { |
1888 | u32 indirect_ctx_offset; | |
1889 | ||
c033666a | 1890 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1891 | default: |
c033666a | 1892 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1893 | /* fall through */ |
1894 | case 9: | |
1895 | indirect_ctx_offset = | |
1896 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1897 | break; | |
1898 | case 8: | |
1899 | indirect_ctx_offset = | |
1900 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1901 | break; | |
1902 | } | |
1903 | ||
1904 | return indirect_ctx_offset; | |
1905 | } | |
1906 | ||
a3aabe86 CW |
1907 | static void execlists_init_reg_state(u32 *reg_state, |
1908 | struct i915_gem_context *ctx, | |
1909 | struct intel_engine_cs *engine, | |
1910 | struct intel_ring *ring) | |
8670d6f9 | 1911 | { |
a3aabe86 CW |
1912 | struct drm_i915_private *dev_priv = engine->i915; |
1913 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
8670d6f9 OM |
1914 | |
1915 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1916 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1917 | * only for the first context restore: on a subsequent save, the GPU will | |
1918 | * recreate this batchbuffer with new values (including all the missing | |
1919 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 1920 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
1921 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
1922 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
1923 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
1924 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1925 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 1926 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
a3aabe86 | 1927 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
1928 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
1929 | 0); | |
1930 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
1931 | 0); | |
0bc40be8 TU |
1932 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
1933 | RING_START(engine->mmio_base), 0); | |
1934 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
1935 | RING_CTL(engine->mmio_base), | |
62ae14b1 | 1936 | RING_CTL_SIZE(ring->size) | RING_VALID); |
0bc40be8 TU |
1937 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
1938 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
1939 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
1940 | RING_BBADDR(engine->mmio_base), 0); | |
1941 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
1942 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 1943 | RING_BB_PPGTT); |
0bc40be8 TU |
1944 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
1945 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
1946 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
1947 | RING_SBBADDR(engine->mmio_base), 0); | |
1948 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
1949 | RING_SBBSTATE(engine->mmio_base), 0); | |
1950 | if (engine->id == RCS) { | |
1951 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
1952 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
1953 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
1954 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
1955 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1956 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
48bb74e4 | 1957 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1958 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1959 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d AS |
1960 | |
1961 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
1962 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
1963 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
1964 | ||
1965 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 1966 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
1967 | |
1968 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
1969 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
1970 | 0x01; | |
1971 | } | |
8670d6f9 | 1972 | } |
0d925ea0 | 1973 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
1974 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
1975 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 1976 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
1977 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
1978 | 0); | |
1979 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
1980 | 0); | |
1981 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
1982 | 0); | |
1983 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
1984 | 0); | |
1985 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
1986 | 0); | |
1987 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
1988 | 0); | |
1989 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
1990 | 0); | |
1991 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
1992 | 0); | |
d7b2633d | 1993 | |
2dba3239 MT |
1994 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1995 | /* 64b PPGTT (48bit canonical) | |
1996 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
1997 | * other PDP Descriptors are ignored. | |
1998 | */ | |
1999 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2000 | } else { | |
2001 | /* 32b PPGTT | |
2002 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2003 | * With dynamic page allocation, PDPs may not be allocated at | |
2004 | * this point. Point the unallocated PDPs to the scratch page | |
2005 | */ | |
c6a2ac71 | 2006 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2007 | } |
2008 | ||
0bc40be8 | 2009 | if (engine->id == RCS) { |
8670d6f9 | 2010 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2011 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2012 | make_rpcs(dev_priv)); |
8670d6f9 | 2013 | } |
a3aabe86 CW |
2014 | } |
2015 | ||
2016 | static int | |
2017 | populate_lr_context(struct i915_gem_context *ctx, | |
2018 | struct drm_i915_gem_object *ctx_obj, | |
2019 | struct intel_engine_cs *engine, | |
2020 | struct intel_ring *ring) | |
2021 | { | |
2022 | void *vaddr; | |
2023 | int ret; | |
2024 | ||
2025 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2026 | if (ret) { | |
2027 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2028 | return ret; | |
2029 | } | |
2030 | ||
2031 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2032 | if (IS_ERR(vaddr)) { | |
2033 | ret = PTR_ERR(vaddr); | |
2034 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2035 | return ret; | |
2036 | } | |
a4f5ea64 | 2037 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2038 | |
2039 | /* The second page of the context object contains some fields which must | |
2040 | * be set up prior to the first execution. */ | |
2041 | ||
2042 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2043 | ctx, engine, ring); | |
8670d6f9 | 2044 | |
7d774cac | 2045 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2046 | |
2047 | return 0; | |
2048 | } | |
2049 | ||
c5d46ee2 DG |
2050 | /** |
2051 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2052 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2053 | * |
2054 | * Each engine may require a different amount of space for a context image, | |
2055 | * so when allocating (or copying) an image, this function can be used to | |
2056 | * find the right size for the specific engine. | |
2057 | * | |
2058 | * Return: size (in bytes) of an engine-specific context image | |
2059 | * | |
2060 | * Note: this size includes the HWSP, which is part of the context image | |
2061 | * in LRC mode, but does not include the "shared data page" used with | |
2062 | * GuC submission. The caller should account for this if using the GuC. | |
2063 | */ | |
0bc40be8 | 2064 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2065 | { |
2066 | int ret = 0; | |
2067 | ||
c033666a | 2068 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2069 | |
0bc40be8 | 2070 | switch (engine->id) { |
8c857917 | 2071 | case RCS: |
c033666a | 2072 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2073 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2074 | else | |
2075 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2076 | break; |
2077 | case VCS: | |
2078 | case BCS: | |
2079 | case VECS: | |
2080 | case VCS2: | |
2081 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2082 | break; | |
2083 | } | |
2084 | ||
2085 | return ret; | |
ede7d42b OM |
2086 | } |
2087 | ||
e2efd130 | 2088 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2089 | struct intel_engine_cs *engine) |
ede7d42b | 2090 | { |
8c857917 | 2091 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2092 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2093 | struct i915_vma *vma; |
8c857917 | 2094 | uint32_t context_size; |
7e37f889 | 2095 | struct intel_ring *ring; |
8c857917 OM |
2096 | int ret; |
2097 | ||
9021ad03 | 2098 | WARN_ON(ce->state); |
ede7d42b | 2099 | |
0bc40be8 | 2100 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2101 | |
d1675198 AD |
2102 | /* One extra page as the sharing data between driver and GuC */ |
2103 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2104 | ||
91c8a326 | 2105 | ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size); |
fe3db79b | 2106 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2107 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2108 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2109 | } |
2110 | ||
bf3783e5 CW |
2111 | vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL); |
2112 | if (IS_ERR(vma)) { | |
2113 | ret = PTR_ERR(vma); | |
2114 | goto error_deref_obj; | |
2115 | } | |
2116 | ||
7e37f889 | 2117 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2118 | if (IS_ERR(ring)) { |
2119 | ret = PTR_ERR(ring); | |
e84fe803 | 2120 | goto error_deref_obj; |
8670d6f9 OM |
2121 | } |
2122 | ||
dca33ecc | 2123 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2124 | if (ret) { |
2125 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2126 | goto error_ring_free; |
84c2377f OM |
2127 | } |
2128 | ||
dca33ecc | 2129 | ce->ring = ring; |
bf3783e5 | 2130 | ce->state = vma; |
9021ad03 | 2131 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2132 | |
2133 | return 0; | |
8670d6f9 | 2134 | |
dca33ecc | 2135 | error_ring_free: |
7e37f889 | 2136 | intel_ring_free(ring); |
e84fe803 | 2137 | error_deref_obj: |
f8c417cd | 2138 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2139 | return ret; |
ede7d42b | 2140 | } |
3e5b6f05 | 2141 | |
821ed7df | 2142 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2143 | { |
e2f80391 | 2144 | struct intel_engine_cs *engine; |
bafb2f7d | 2145 | struct i915_gem_context *ctx; |
3b3f1650 | 2146 | enum intel_engine_id id; |
bafb2f7d CW |
2147 | |
2148 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2149 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2150 | * that stored in context. As we only write new commands from | |
2151 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2152 | * starts reading from its RING_HEAD from the context, it may try to | |
2153 | * execute that junk and die. | |
2154 | * | |
2155 | * So to avoid that we reset the context images upon resume. For | |
2156 | * simplicity, we just zero everything out. | |
2157 | */ | |
2158 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
3b3f1650 | 2159 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2160 | struct intel_context *ce = &ctx->engine[engine->id]; |
2161 | u32 *reg; | |
3e5b6f05 | 2162 | |
bafb2f7d CW |
2163 | if (!ce->state) |
2164 | continue; | |
7d774cac | 2165 | |
bafb2f7d CW |
2166 | reg = i915_gem_object_pin_map(ce->state->obj, |
2167 | I915_MAP_WB); | |
2168 | if (WARN_ON(IS_ERR(reg))) | |
2169 | continue; | |
3e5b6f05 | 2170 | |
bafb2f7d CW |
2171 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2172 | reg[CTX_RING_HEAD+1] = 0; | |
2173 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2174 | |
a4f5ea64 | 2175 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2176 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2177 | |
bafb2f7d CW |
2178 | ce->ring->head = ce->ring->tail = 0; |
2179 | ce->ring->last_retired_head = -1; | |
2180 | intel_ring_update_space(ce->ring); | |
2181 | } | |
3e5b6f05 TD |
2182 | } |
2183 | } |