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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
e981e7b1 TD |
141 | #define RING_EXECLIST_QFULL (1 << 0x2) |
142 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
143 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
144 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
145 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
146 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
147 | ||
148 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
149 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
150 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
151 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
152 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
153 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 154 | |
70c2a24d CW |
155 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
156 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
157 | GEN8_CTX_STATUS_PREEMPTED | \ | |
158 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
159 | ||
8670d6f9 OM |
160 | #define CTX_LRI_HEADER_0 0x01 |
161 | #define CTX_CONTEXT_CONTROL 0x02 | |
162 | #define CTX_RING_HEAD 0x04 | |
163 | #define CTX_RING_TAIL 0x06 | |
164 | #define CTX_RING_BUFFER_START 0x08 | |
165 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
166 | #define CTX_BB_HEAD_U 0x0c | |
167 | #define CTX_BB_HEAD_L 0x0e | |
168 | #define CTX_BB_STATE 0x10 | |
169 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
170 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
171 | #define CTX_SECOND_BB_STATE 0x16 | |
172 | #define CTX_BB_PER_CTX_PTR 0x18 | |
173 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
174 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
175 | #define CTX_LRI_HEADER_1 0x21 | |
176 | #define CTX_CTX_TIMESTAMP 0x22 | |
177 | #define CTX_PDP3_UDW 0x24 | |
178 | #define CTX_PDP3_LDW 0x26 | |
179 | #define CTX_PDP2_UDW 0x28 | |
180 | #define CTX_PDP2_LDW 0x2a | |
181 | #define CTX_PDP1_UDW 0x2c | |
182 | #define CTX_PDP1_LDW 0x2e | |
183 | #define CTX_PDP0_UDW 0x30 | |
184 | #define CTX_PDP0_LDW 0x32 | |
185 | #define CTX_LRI_HEADER_2 0x41 | |
186 | #define CTX_R_PWR_CLK_STATE 0x42 | |
187 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
188 | ||
56e51bf0 | 189 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 190 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
191 | (reg_state)[(pos)+1] = (val); \ |
192 | } while (0) | |
193 | ||
194 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 195 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 198 | } while (0) |
e5815a2e | 199 | |
9244a817 | 200 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
201 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
202 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 203 | } while (0) |
2dba3239 | 204 | |
71562919 MT |
205 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
206 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
7bd0a2c6 | 207 | #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 |
84b790f8 | 208 | |
0e93cdd4 CW |
209 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
210 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
211 | ||
a3aabe86 | 212 | #define WA_TAIL_DWORDS 2 |
7e4992ac | 213 | #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) |
a3aabe86 | 214 | |
e2efd130 | 215 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 216 | struct intel_engine_cs *engine); |
a3aabe86 CW |
217 | static void execlists_init_reg_state(u32 *reg_state, |
218 | struct i915_gem_context *ctx, | |
219 | struct intel_engine_cs *engine, | |
220 | struct intel_ring *ring); | |
7ba717cf | 221 | |
73e4d07f OM |
222 | /** |
223 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 224 | * @dev_priv: i915 device private |
73e4d07f OM |
225 | * @enable_execlists: value of i915.enable_execlists module parameter. |
226 | * | |
227 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 228 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
229 | * |
230 | * Return: 1 if Execlists is supported and has to be enabled. | |
231 | */ | |
c033666a | 232 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 233 | { |
a0bd6c31 ZL |
234 | /* On platforms with execlist available, vGPU will only |
235 | * support execlist mode, no ring buffer mode. | |
236 | */ | |
c033666a | 237 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
238 | return 1; |
239 | ||
c033666a | 240 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
241 | return 1; |
242 | ||
127f1003 OM |
243 | if (enable_execlists == 0) |
244 | return 0; | |
245 | ||
5a21b665 | 246 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
8279aaf5 | 247 | USES_PPGTT(dev_priv)) |
127f1003 OM |
248 | return 1; |
249 | ||
250 | return 0; | |
251 | } | |
ede7d42b | 252 | |
73e4d07f | 253 | /** |
ca82580c TU |
254 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
255 | * descriptor for a pinned context | |
ca82580c | 256 | * @ctx: Context to work on |
9021ad03 | 257 | * @engine: Engine the descriptor will be used with |
73e4d07f | 258 | * |
ca82580c TU |
259 | * The context descriptor encodes various attributes of a context, |
260 | * including its GTT address and some flags. Because it's fairly | |
261 | * expensive to calculate, we'll just do it once and cache the result, | |
262 | * which remains valid until the context is unpinned. | |
263 | * | |
6e5248b5 DV |
264 | * This is what a descriptor looks like, from LSB to MSB:: |
265 | * | |
2355cf08 | 266 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
267 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
268 | * bits 32-52: ctx ID, a globally unique tag | |
269 | * bits 53-54: mbz, reserved for use by hardware | |
270 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 271 | */ |
ca82580c | 272 | static void |
e2efd130 | 273 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 274 | struct intel_engine_cs *engine) |
84b790f8 | 275 | { |
9021ad03 | 276 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 277 | u64 desc; |
84b790f8 | 278 | |
7069b144 | 279 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 280 | |
2355cf08 | 281 | desc = ctx->desc_template; /* bits 0-11 */ |
0b29c75a | 282 | desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; |
9021ad03 | 283 | /* bits 12-31 */ |
7069b144 | 284 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 285 | |
9021ad03 | 286 | ce->lrc_desc = desc; |
5af05fef MT |
287 | } |
288 | ||
27606fd8 CW |
289 | static struct i915_priolist * |
290 | lookup_priolist(struct intel_engine_cs *engine, | |
291 | struct i915_priotree *pt, | |
292 | int prio) | |
08dd3e1a | 293 | { |
b620e870 | 294 | struct intel_engine_execlists * const execlists = &engine->execlists; |
08dd3e1a CW |
295 | struct i915_priolist *p; |
296 | struct rb_node **parent, *rb; | |
297 | bool first = true; | |
298 | ||
b620e870 | 299 | if (unlikely(execlists->no_priolist)) |
08dd3e1a CW |
300 | prio = I915_PRIORITY_NORMAL; |
301 | ||
302 | find_priolist: | |
303 | /* most positive priority is scheduled first, equal priorities fifo */ | |
304 | rb = NULL; | |
b620e870 | 305 | parent = &execlists->queue.rb_node; |
08dd3e1a CW |
306 | while (*parent) { |
307 | rb = *parent; | |
308 | p = rb_entry(rb, typeof(*p), node); | |
309 | if (prio > p->priority) { | |
310 | parent = &rb->rb_left; | |
311 | } else if (prio < p->priority) { | |
312 | parent = &rb->rb_right; | |
313 | first = false; | |
314 | } else { | |
27606fd8 | 315 | return p; |
08dd3e1a CW |
316 | } |
317 | } | |
318 | ||
319 | if (prio == I915_PRIORITY_NORMAL) { | |
b620e870 | 320 | p = &execlists->default_priolist; |
08dd3e1a CW |
321 | } else { |
322 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); | |
323 | /* Convert an allocation failure to a priority bump */ | |
324 | if (unlikely(!p)) { | |
325 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
326 | ||
327 | /* To maintain ordering with all rendering, after an | |
328 | * allocation failure we have to disable all scheduling. | |
329 | * Requests will then be executed in fifo, and schedule | |
330 | * will ensure that dependencies are emitted in fifo. | |
331 | * There will be still some reordering with existing | |
332 | * requests, so if userspace lied about their | |
333 | * dependencies that reordering may be visible. | |
334 | */ | |
b620e870 | 335 | execlists->no_priolist = true; |
08dd3e1a CW |
336 | goto find_priolist; |
337 | } | |
338 | } | |
339 | ||
340 | p->priority = prio; | |
27606fd8 | 341 | INIT_LIST_HEAD(&p->requests); |
08dd3e1a | 342 | rb_link_node(&p->node, rb, parent); |
b620e870 | 343 | rb_insert_color(&p->node, &execlists->queue); |
08dd3e1a | 344 | |
08dd3e1a | 345 | if (first) |
b620e870 | 346 | execlists->first = &p->node; |
08dd3e1a | 347 | |
27606fd8 | 348 | return ptr_pack_bits(p, first, 1); |
08dd3e1a CW |
349 | } |
350 | ||
7e4992ac CW |
351 | static void unwind_wa_tail(struct drm_i915_gem_request *rq) |
352 | { | |
353 | rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); | |
354 | assert_ring_tail_valid(rq->ring, rq->tail); | |
355 | } | |
356 | ||
357 | static void unwind_incomplete_requests(struct intel_engine_cs *engine) | |
358 | { | |
359 | struct drm_i915_gem_request *rq, *rn; | |
097a9481 MW |
360 | struct i915_priolist *uninitialized_var(p); |
361 | int last_prio = I915_PRIORITY_INVALID; | |
7e4992ac CW |
362 | |
363 | lockdep_assert_held(&engine->timeline->lock); | |
364 | ||
365 | list_for_each_entry_safe_reverse(rq, rn, | |
366 | &engine->timeline->requests, | |
367 | link) { | |
7e4992ac CW |
368 | if (i915_gem_request_completed(rq)) |
369 | return; | |
370 | ||
371 | __i915_gem_request_unsubmit(rq); | |
372 | unwind_wa_tail(rq); | |
373 | ||
097a9481 MW |
374 | GEM_BUG_ON(rq->priotree.priority == I915_PRIORITY_INVALID); |
375 | if (rq->priotree.priority != last_prio) { | |
376 | p = lookup_priolist(engine, | |
377 | &rq->priotree, | |
378 | rq->priotree.priority); | |
379 | p = ptr_mask_bits(p, 1); | |
380 | ||
381 | last_prio = rq->priotree.priority; | |
382 | } | |
383 | ||
384 | list_add(&rq->priotree.link, &p->requests); | |
7e4992ac CW |
385 | } |
386 | } | |
387 | ||
bbd6c47e CW |
388 | static inline void |
389 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
390 | unsigned long status) | |
84b790f8 | 391 | { |
bbd6c47e CW |
392 | /* |
393 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
394 | * The compiler should eliminate this function as dead-code. | |
395 | */ | |
396 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
397 | return; | |
6daccb0b | 398 | |
3fc03069 CD |
399 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
400 | status, rq); | |
84b790f8 BW |
401 | } |
402 | ||
c6a2ac71 TU |
403 | static void |
404 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
405 | { | |
406 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
407 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
408 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
409 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
410 | } | |
411 | ||
70c2a24d | 412 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 413 | { |
70c2a24d | 414 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
415 | struct i915_hw_ppgtt *ppgtt = |
416 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 417 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 418 | |
e6ba9992 | 419 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 420 | |
c6a2ac71 TU |
421 | /* True 32b PPGTT with dynamic page allocation: update PDP |
422 | * registers and point the unallocated PDPs to scratch page. | |
423 | * PML4 is allocated during ppgtt init, so this is not needed | |
424 | * in 48-bit mode. | |
425 | */ | |
949e8ab3 | 426 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 427 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
428 | |
429 | return ce->lrc_desc; | |
ae1250b9 OM |
430 | } |
431 | ||
70c2a24d | 432 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 433 | { |
b620e870 | 434 | struct execlist_port *port = engine->execlists.port; |
bbd6c47e | 435 | u32 __iomem *elsp = |
77f0d0e9 CW |
436 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); |
437 | unsigned int n; | |
bbd6c47e | 438 | |
76e70087 | 439 | for (n = execlists_num_ports(&engine->execlists); n--; ) { |
77f0d0e9 CW |
440 | struct drm_i915_gem_request *rq; |
441 | unsigned int count; | |
442 | u64 desc; | |
443 | ||
444 | rq = port_unpack(&port[n], &count); | |
445 | if (rq) { | |
446 | GEM_BUG_ON(count > !n); | |
447 | if (!count++) | |
448 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
449 | port_set(&port[n], port_pack(rq, count)); | |
450 | desc = execlists_update_context(rq); | |
451 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
452 | } else { | |
453 | GEM_BUG_ON(!n); | |
454 | desc = 0; | |
455 | } | |
bbd6c47e | 456 | |
77f0d0e9 CW |
457 | writel(upper_32_bits(desc), elsp); |
458 | writel(lower_32_bits(desc), elsp); | |
459 | } | |
bbd6c47e CW |
460 | } |
461 | ||
70c2a24d | 462 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 463 | { |
70c2a24d | 464 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 465 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 466 | } |
84b790f8 | 467 | |
70c2a24d CW |
468 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
469 | const struct i915_gem_context *next) | |
470 | { | |
471 | if (prev != next) | |
472 | return false; | |
26720ab9 | 473 | |
70c2a24d CW |
474 | if (ctx_single_port_submission(prev)) |
475 | return false; | |
26720ab9 | 476 | |
70c2a24d | 477 | return true; |
84b790f8 BW |
478 | } |
479 | ||
77f0d0e9 CW |
480 | static void port_assign(struct execlist_port *port, |
481 | struct drm_i915_gem_request *rq) | |
482 | { | |
483 | GEM_BUG_ON(rq == port_request(port)); | |
484 | ||
485 | if (port_isset(port)) | |
486 | i915_gem_request_put(port_request(port)); | |
487 | ||
488 | port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); | |
489 | } | |
490 | ||
70c2a24d | 491 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 492 | { |
20311bd3 | 493 | struct drm_i915_gem_request *last; |
7a62cc61 MK |
494 | struct intel_engine_execlists * const execlists = &engine->execlists; |
495 | struct execlist_port *port = execlists->port; | |
76e70087 MK |
496 | const struct execlist_port * const last_port = |
497 | &execlists->port[execlists->port_mask]; | |
20311bd3 | 498 | struct rb_node *rb; |
70c2a24d CW |
499 | bool submit = false; |
500 | ||
77f0d0e9 | 501 | last = port_request(port); |
70c2a24d CW |
502 | if (last) |
503 | /* WaIdleLiteRestore:bdw,skl | |
504 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 505 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
506 | * for where we prepare the padding after the end of the |
507 | * request. | |
508 | */ | |
509 | last->tail = last->wa_tail; | |
e981e7b1 | 510 | |
70c2a24d CW |
511 | /* Hardware submission is through 2 ports. Conceptually each port |
512 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
513 | * static for a context, and unique to each, so we only execute | |
514 | * requests belonging to a single context from each ring. RING_HEAD | |
515 | * is maintained by the CS in the context image, it marks the place | |
516 | * where it got up to last time, and through RING_TAIL we tell the CS | |
517 | * where we want to execute up to this time. | |
518 | * | |
519 | * In this list the requests are in order of execution. Consecutive | |
520 | * requests from the same context are adjacent in the ringbuffer. We | |
521 | * can combine these requests into a single RING_TAIL update: | |
522 | * | |
523 | * RING_HEAD...req1...req2 | |
524 | * ^- RING_TAIL | |
525 | * since to execute req2 the CS must first execute req1. | |
526 | * | |
527 | * Our goal then is to point each port to the end of a consecutive | |
528 | * sequence of requests as being the most optimal (fewest wake ups | |
529 | * and context switches) submission. | |
779949f4 | 530 | */ |
acdd884a | 531 | |
9f7886d0 | 532 | spin_lock_irq(&engine->timeline->lock); |
7a62cc61 MK |
533 | rb = execlists->first; |
534 | GEM_BUG_ON(rb_first(&execlists->queue) != rb); | |
20311bd3 | 535 | while (rb) { |
6c067579 CW |
536 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); |
537 | struct drm_i915_gem_request *rq, *rn; | |
538 | ||
539 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
540 | /* | |
541 | * Can we combine this request with the current port? | |
542 | * It has to be the same context/ringbuffer and not | |
543 | * have any exceptions (e.g. GVT saying never to | |
544 | * combine contexts). | |
545 | * | |
546 | * If we can combine the requests, we can execute both | |
547 | * by updating the RING_TAIL to point to the end of the | |
548 | * second request, and so we never need to tell the | |
549 | * hardware about the first. | |
70c2a24d | 550 | */ |
6c067579 CW |
551 | if (last && !can_merge_ctx(rq->ctx, last->ctx)) { |
552 | /* | |
553 | * If we are on the second port and cannot | |
554 | * combine this request with the last, then we | |
555 | * are done. | |
556 | */ | |
76e70087 | 557 | if (port == last_port) { |
6c067579 CW |
558 | __list_del_many(&p->requests, |
559 | &rq->priotree.link); | |
560 | goto done; | |
561 | } | |
562 | ||
563 | /* | |
564 | * If GVT overrides us we only ever submit | |
565 | * port[0], leaving port[1] empty. Note that we | |
566 | * also have to be careful that we don't queue | |
567 | * the same context (even though a different | |
568 | * request) to the second port. | |
569 | */ | |
570 | if (ctx_single_port_submission(last->ctx) || | |
571 | ctx_single_port_submission(rq->ctx)) { | |
572 | __list_del_many(&p->requests, | |
573 | &rq->priotree.link); | |
574 | goto done; | |
575 | } | |
576 | ||
577 | GEM_BUG_ON(last->ctx == rq->ctx); | |
578 | ||
579 | if (submit) | |
580 | port_assign(port, last); | |
581 | port++; | |
7a62cc61 MK |
582 | |
583 | GEM_BUG_ON(port_isset(port)); | |
6c067579 | 584 | } |
70c2a24d | 585 | |
6c067579 | 586 | INIT_LIST_HEAD(&rq->priotree.link); |
6c067579 | 587 | __i915_gem_request_submit(rq); |
7a62cc61 | 588 | trace_i915_gem_request_in(rq, port_index(port, execlists)); |
6c067579 CW |
589 | last = rq; |
590 | submit = true; | |
70c2a24d | 591 | } |
d55ac5bf | 592 | |
20311bd3 | 593 | rb = rb_next(rb); |
7a62cc61 | 594 | rb_erase(&p->node, &execlists->queue); |
6c067579 CW |
595 | INIT_LIST_HEAD(&p->requests); |
596 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 597 | kmem_cache_free(engine->i915->priorities, p); |
70c2a24d | 598 | } |
6c067579 | 599 | done: |
7a62cc61 | 600 | execlists->first = rb; |
6c067579 | 601 | if (submit) |
77f0d0e9 | 602 | port_assign(port, last); |
9f7886d0 | 603 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 604 | |
70c2a24d CW |
605 | if (submit) |
606 | execlists_submit_ports(engine); | |
acdd884a MT |
607 | } |
608 | ||
3f9e6cd8 CW |
609 | static void |
610 | execlist_cancel_port_requests(struct intel_engine_execlists *execlists) | |
cf4591d1 | 611 | { |
3f9e6cd8 CW |
612 | struct execlist_port *port = execlists->port; |
613 | unsigned int num_ports = ARRAY_SIZE(execlists->port); | |
cf4591d1 | 614 | |
3f9e6cd8 | 615 | while (num_ports-- && port_isset(port)) { |
7e44fc28 CW |
616 | struct drm_i915_gem_request *rq = port_request(port); |
617 | ||
d6c05113 | 618 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED); |
7e44fc28 CW |
619 | i915_gem_request_put(rq); |
620 | ||
3f9e6cd8 CW |
621 | memset(port, 0, sizeof(*port)); |
622 | port++; | |
623 | } | |
cf4591d1 MK |
624 | } |
625 | ||
27a5f61b CW |
626 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
627 | { | |
b620e870 | 628 | struct intel_engine_execlists * const execlists = &engine->execlists; |
27a5f61b CW |
629 | struct drm_i915_gem_request *rq, *rn; |
630 | struct rb_node *rb; | |
631 | unsigned long flags; | |
27a5f61b CW |
632 | |
633 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
634 | ||
635 | /* Cancel the requests on the HW and clear the ELSP tracker. */ | |
cf4591d1 | 636 | execlist_cancel_port_requests(execlists); |
27a5f61b CW |
637 | |
638 | /* Mark all executing requests as skipped. */ | |
639 | list_for_each_entry(rq, &engine->timeline->requests, link) { | |
640 | GEM_BUG_ON(!rq->global_seqno); | |
641 | if (!i915_gem_request_completed(rq)) | |
642 | dma_fence_set_error(&rq->fence, -EIO); | |
643 | } | |
644 | ||
645 | /* Flush the queued requests to the timeline list (for retiring). */ | |
b620e870 | 646 | rb = execlists->first; |
27a5f61b CW |
647 | while (rb) { |
648 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); | |
649 | ||
650 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
651 | INIT_LIST_HEAD(&rq->priotree.link); | |
652 | rq->priotree.priority = INT_MAX; | |
653 | ||
654 | dma_fence_set_error(&rq->fence, -EIO); | |
655 | __i915_gem_request_submit(rq); | |
656 | } | |
657 | ||
658 | rb = rb_next(rb); | |
b620e870 | 659 | rb_erase(&p->node, &execlists->queue); |
27a5f61b CW |
660 | INIT_LIST_HEAD(&p->requests); |
661 | if (p->priority != I915_PRIORITY_NORMAL) | |
662 | kmem_cache_free(engine->i915->priorities, p); | |
663 | } | |
664 | ||
665 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
666 | ||
cf4591d1 | 667 | |
b620e870 MK |
668 | execlists->queue = RB_ROOT; |
669 | execlists->first = NULL; | |
3f9e6cd8 | 670 | GEM_BUG_ON(port_isset(execlists->port)); |
27a5f61b CW |
671 | |
672 | /* | |
673 | * The port is checked prior to scheduling a tasklet, but | |
674 | * just in case we have suspended the tasklet to do the | |
675 | * wedging make sure that when it wakes, it decides there | |
676 | * is no work to do by clearing the irq_posted bit. | |
677 | */ | |
678 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
679 | ||
680 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
681 | } | |
682 | ||
816ee798 | 683 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 684 | { |
b620e870 | 685 | const struct execlist_port *port = engine->execlists.port; |
91a41032 | 686 | |
77f0d0e9 | 687 | return port_count(&port[0]) + port_count(&port[1]) < 2; |
91a41032 BW |
688 | } |
689 | ||
6e5248b5 | 690 | /* |
73e4d07f OM |
691 | * Check the unread Context Status Buffers and manage the submission of new |
692 | * contexts to the ELSP accordingly. | |
693 | */ | |
27af5eea | 694 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 695 | { |
b620e870 MK |
696 | struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; |
697 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
698 | struct execlist_port *port = execlists->port; | |
c033666a | 699 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 700 | |
48921260 CW |
701 | /* We can skip acquiring intel_runtime_pm_get() here as it was taken |
702 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
703 | * not be relinquished until the device is idle (see | |
704 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
705 | * that all ELSP are drained i.e. we have processed the CSB, | |
706 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
707 | */ | |
708 | GEM_BUG_ON(!dev_priv->gt.awake); | |
709 | ||
b620e870 | 710 | intel_uncore_forcewake_get(dev_priv, execlists->fw_domains); |
c6a2ac71 | 711 | |
899f6204 CW |
712 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
713 | * imposing the cost of a locked atomic transaction when submitting a | |
714 | * new request (outside of the context-switch interrupt). | |
715 | */ | |
716 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
6d2cb5aa CW |
717 | /* The HWSP contains a (cacheable) mirror of the CSB */ |
718 | const u32 *buf = | |
719 | &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; | |
4af0d727 | 720 | unsigned int head, tail; |
70c2a24d | 721 | |
6d2cb5aa | 722 | /* However GVT emulation depends upon intercepting CSB mmio */ |
b620e870 | 723 | if (unlikely(execlists->csb_use_mmio)) { |
6d2cb5aa CW |
724 | buf = (u32 * __force) |
725 | (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); | |
b620e870 | 726 | execlists->csb_head = -1; /* force mmio read of CSB ptrs */ |
6d2cb5aa CW |
727 | } |
728 | ||
2e70b8c6 CW |
729 | /* The write will be ordered by the uncached read (itself |
730 | * a memory barrier), so we do not need another in the form | |
731 | * of a locked instruction. The race between the interrupt | |
732 | * handler and the split test/clear is harmless as we order | |
733 | * our clear before the CSB read. If the interrupt arrived | |
734 | * first between the test and the clear, we read the updated | |
735 | * CSB and clear the bit. If the interrupt arrives as we read | |
736 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
737 | * is set and we do a new loop. | |
738 | */ | |
739 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
b620e870 | 740 | if (unlikely(execlists->csb_head == -1)) { /* following a reset */ |
767a983a CW |
741 | head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); |
742 | tail = GEN8_CSB_WRITE_PTR(head); | |
743 | head = GEN8_CSB_READ_PTR(head); | |
b620e870 | 744 | execlists->csb_head = head; |
767a983a CW |
745 | } else { |
746 | const int write_idx = | |
747 | intel_hws_csb_write_index(dev_priv) - | |
748 | I915_HWS_CSB_BUF0_INDEX; | |
749 | ||
b620e870 | 750 | head = execlists->csb_head; |
767a983a CW |
751 | tail = READ_ONCE(buf[write_idx]); |
752 | } | |
b620e870 | 753 | |
4af0d727 | 754 | while (head != tail) { |
77f0d0e9 | 755 | struct drm_i915_gem_request *rq; |
4af0d727 | 756 | unsigned int status; |
77f0d0e9 | 757 | unsigned int count; |
4af0d727 CW |
758 | |
759 | if (++head == GEN8_CSB_ENTRIES) | |
760 | head = 0; | |
70c2a24d | 761 | |
2ffe80aa CW |
762 | /* We are flying near dragons again. |
763 | * | |
764 | * We hold a reference to the request in execlist_port[] | |
765 | * but no more than that. We are operating in softirq | |
766 | * context and so cannot hold any mutex or sleep. That | |
767 | * prevents us stopping the requests we are processing | |
768 | * in port[] from being retired simultaneously (the | |
769 | * breadcrumb will be complete before we see the | |
770 | * context-switch). As we only hold the reference to the | |
771 | * request, any pointer chasing underneath the request | |
772 | * is subject to a potential use-after-free. Thus we | |
773 | * store all of the bookkeeping within port[] as | |
774 | * required, and avoid using unguarded pointers beneath | |
775 | * request itself. The same applies to the atomic | |
776 | * status notifier. | |
777 | */ | |
778 | ||
6d2cb5aa | 779 | status = READ_ONCE(buf[2 * head]); /* maybe mmio! */ |
70c2a24d CW |
780 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
781 | continue; | |
782 | ||
86aa7e76 | 783 | /* Check the context/desc id for this event matches */ |
6d2cb5aa | 784 | GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); |
86aa7e76 | 785 | |
77f0d0e9 CW |
786 | rq = port_unpack(port, &count); |
787 | GEM_BUG_ON(count == 0); | |
788 | if (--count == 0) { | |
70c2a24d | 789 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
77f0d0e9 CW |
790 | GEM_BUG_ON(!i915_gem_request_completed(rq)); |
791 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); | |
792 | ||
793 | trace_i915_gem_request_out(rq); | |
1f181225 | 794 | rq->priotree.priority = INT_MAX; |
77f0d0e9 | 795 | i915_gem_request_put(rq); |
70c2a24d | 796 | |
7a62cc61 | 797 | execlists_port_complete(execlists, port); |
77f0d0e9 CW |
798 | } else { |
799 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 800 | } |
26720ab9 | 801 | |
77f0d0e9 CW |
802 | /* After the final element, the hw should be idle */ |
803 | GEM_BUG_ON(port_count(port) == 0 && | |
70c2a24d | 804 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); |
4af0d727 | 805 | } |
e1fee72c | 806 | |
b620e870 MK |
807 | if (head != execlists->csb_head) { |
808 | execlists->csb_head = head; | |
767a983a CW |
809 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
810 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); | |
811 | } | |
e981e7b1 TD |
812 | } |
813 | ||
70c2a24d CW |
814 | if (execlists_elsp_ready(engine)) |
815 | execlists_dequeue(engine); | |
c6a2ac71 | 816 | |
b620e870 | 817 | intel_uncore_forcewake_put(dev_priv, execlists->fw_domains); |
e981e7b1 TD |
818 | } |
819 | ||
27606fd8 CW |
820 | static void insert_request(struct intel_engine_cs *engine, |
821 | struct i915_priotree *pt, | |
822 | int prio) | |
823 | { | |
824 | struct i915_priolist *p = lookup_priolist(engine, pt, prio); | |
825 | ||
826 | list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests); | |
827 | if (ptr_unmask_bits(p, 1) && execlists_elsp_ready(engine)) | |
b620e870 | 828 | tasklet_hi_schedule(&engine->execlists.irq_tasklet); |
27606fd8 CW |
829 | } |
830 | ||
f4ea6bdd | 831 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 832 | { |
4a570db5 | 833 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 834 | unsigned long flags; |
acdd884a | 835 | |
663f71e7 CW |
836 | /* Will be called from irq-context when using foreign fences. */ |
837 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 838 | |
27606fd8 | 839 | insert_request(engine, &request->priotree, request->priotree.priority); |
acdd884a | 840 | |
b620e870 | 841 | GEM_BUG_ON(!engine->execlists.first); |
6c067579 CW |
842 | GEM_BUG_ON(list_empty(&request->priotree.link)); |
843 | ||
663f71e7 | 844 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
845 | } |
846 | ||
1f181225 CW |
847 | static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt) |
848 | { | |
849 | return container_of(pt, struct drm_i915_gem_request, priotree); | |
850 | } | |
851 | ||
20311bd3 CW |
852 | static struct intel_engine_cs * |
853 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
854 | { | |
1f181225 | 855 | struct intel_engine_cs *engine = pt_to_request(pt)->engine; |
a79a524e CW |
856 | |
857 | GEM_BUG_ON(!locked); | |
20311bd3 | 858 | |
20311bd3 | 859 | if (engine != locked) { |
a79a524e CW |
860 | spin_unlock(&locked->timeline->lock); |
861 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
862 | } |
863 | ||
864 | return engine; | |
865 | } | |
866 | ||
867 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
868 | { | |
a79a524e | 869 | struct intel_engine_cs *engine; |
20311bd3 CW |
870 | struct i915_dependency *dep, *p; |
871 | struct i915_dependency stack; | |
872 | LIST_HEAD(dfs); | |
873 | ||
7d1ea609 CW |
874 | GEM_BUG_ON(prio == I915_PRIORITY_INVALID); |
875 | ||
20311bd3 CW |
876 | if (prio <= READ_ONCE(request->priotree.priority)) |
877 | return; | |
878 | ||
70cd1476 CW |
879 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
880 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
881 | |
882 | stack.signaler = &request->priotree; | |
883 | list_add(&stack.dfs_link, &dfs); | |
884 | ||
885 | /* Recursively bump all dependent priorities to match the new request. | |
886 | * | |
887 | * A naive approach would be to use recursion: | |
888 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
889 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
890 | * update_priorities(dep->signal, prio) | |
891 | * insert_request(pt); | |
892 | * } | |
893 | * but that may have unlimited recursion depth and so runs a very | |
894 | * real risk of overunning the kernel stack. Instead, we build | |
895 | * a flat list of all dependencies starting with the current request. | |
896 | * As we walk the list of dependencies, we add all of its dependencies | |
897 | * to the end of the list (this may include an already visited | |
898 | * request) and continue to walk onwards onto the new dependencies. The | |
899 | * end result is a topological list of requests in reverse order, the | |
900 | * last element in the list is the request we must execute first. | |
901 | */ | |
902 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
903 | struct i915_priotree *pt = dep->signaler; | |
904 | ||
a79a524e CW |
905 | /* Within an engine, there can be no cycle, but we may |
906 | * refer to the same dependency chain multiple times | |
907 | * (redundant dependencies are not eliminated) and across | |
908 | * engines. | |
909 | */ | |
910 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
1f181225 CW |
911 | if (i915_gem_request_completed(pt_to_request(p->signaler))) |
912 | continue; | |
913 | ||
a79a524e | 914 | GEM_BUG_ON(p->signaler->priority < pt->priority); |
20311bd3 CW |
915 | if (prio > READ_ONCE(p->signaler->priority)) |
916 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 917 | } |
20311bd3 | 918 | |
0798cff4 | 919 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
920 | } |
921 | ||
349bdb68 CW |
922 | /* If we didn't need to bump any existing priorities, and we haven't |
923 | * yet submitted this request (i.e. there is no potential race with | |
924 | * execlists_submit_request()), we can set our own priority and skip | |
925 | * acquiring the engine locks. | |
926 | */ | |
7d1ea609 | 927 | if (request->priotree.priority == I915_PRIORITY_INVALID) { |
349bdb68 CW |
928 | GEM_BUG_ON(!list_empty(&request->priotree.link)); |
929 | request->priotree.priority = prio; | |
930 | if (stack.dfs_link.next == stack.dfs_link.prev) | |
931 | return; | |
932 | __list_del_entry(&stack.dfs_link); | |
933 | } | |
934 | ||
a79a524e CW |
935 | engine = request->engine; |
936 | spin_lock_irq(&engine->timeline->lock); | |
937 | ||
20311bd3 CW |
938 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
939 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
940 | struct i915_priotree *pt = dep->signaler; | |
941 | ||
942 | INIT_LIST_HEAD(&dep->dfs_link); | |
943 | ||
944 | engine = pt_lock_engine(pt, engine); | |
945 | ||
946 | if (prio <= pt->priority) | |
947 | continue; | |
948 | ||
20311bd3 | 949 | pt->priority = prio; |
6c067579 CW |
950 | if (!list_empty(&pt->link)) { |
951 | __list_del_entry(&pt->link); | |
952 | insert_request(engine, pt, prio); | |
a79a524e | 953 | } |
20311bd3 CW |
954 | } |
955 | ||
a79a524e | 956 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
957 | |
958 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
959 | } | |
960 | ||
266a240b CW |
961 | static struct intel_ring * |
962 | execlists_context_pin(struct intel_engine_cs *engine, | |
963 | struct i915_gem_context *ctx) | |
dcb4c12a | 964 | { |
9021ad03 | 965 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 966 | unsigned int flags; |
7d774cac | 967 | void *vaddr; |
ca82580c | 968 | int ret; |
dcb4c12a | 969 | |
91c8a326 | 970 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 971 | |
266a240b CW |
972 | if (likely(ce->pin_count++)) |
973 | goto out; | |
a533b4ba | 974 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 975 | |
e8a9c58f CW |
976 | if (!ce->state) { |
977 | ret = execlists_context_deferred_alloc(ctx, engine); | |
978 | if (ret) | |
979 | goto err; | |
980 | } | |
56f6e0a7 | 981 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 982 | |
72b72ae4 | 983 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
984 | if (ctx->ggtt_offset_bias) |
985 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
986 | |
987 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 988 | if (ret) |
24f1d3cc | 989 | goto err; |
7ba717cf | 990 | |
bf3783e5 | 991 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
992 | if (IS_ERR(vaddr)) { |
993 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 994 | goto unpin_vma; |
82352e90 TU |
995 | } |
996 | ||
d822bb18 | 997 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 998 | if (ret) |
7d774cac | 999 | goto unpin_map; |
d1675198 | 1000 | |
0bc40be8 | 1001 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 1002 | |
a3aabe86 CW |
1003 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
1004 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 1005 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 1006 | |
a4f5ea64 | 1007 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 1008 | |
9a6feaf0 | 1009 | i915_gem_context_get(ctx); |
266a240b CW |
1010 | out: |
1011 | return ce->ring; | |
7ba717cf | 1012 | |
7d774cac | 1013 | unpin_map: |
bf3783e5 CW |
1014 | i915_gem_object_unpin_map(ce->state->obj); |
1015 | unpin_vma: | |
1016 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 1017 | err: |
9021ad03 | 1018 | ce->pin_count = 0; |
266a240b | 1019 | return ERR_PTR(ret); |
e84fe803 NH |
1020 | } |
1021 | ||
e8a9c58f CW |
1022 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
1023 | struct i915_gem_context *ctx) | |
e84fe803 | 1024 | { |
9021ad03 | 1025 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 1026 | |
91c8a326 | 1027 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 1028 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 1029 | |
9021ad03 | 1030 | if (--ce->pin_count) |
24f1d3cc | 1031 | return; |
e84fe803 | 1032 | |
aad29fbb | 1033 | intel_ring_unpin(ce->ring); |
dcb4c12a | 1034 | |
bf3783e5 CW |
1035 | i915_gem_object_unpin_map(ce->state->obj); |
1036 | i915_vma_unpin(ce->state); | |
321fe304 | 1037 | |
9a6feaf0 | 1038 | i915_gem_context_put(ctx); |
dcb4c12a OM |
1039 | } |
1040 | ||
f73e7399 | 1041 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
1042 | { |
1043 | struct intel_engine_cs *engine = request->engine; | |
1044 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 1045 | u32 *cs; |
ef11c01d CW |
1046 | int ret; |
1047 | ||
e8a9c58f CW |
1048 | GEM_BUG_ON(!ce->pin_count); |
1049 | ||
ef11c01d CW |
1050 | /* Flush enough space to reduce the likelihood of waiting after |
1051 | * we start building the request - in which case we will just | |
1052 | * have to repeat work. | |
1053 | */ | |
1054 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
1055 | ||
73dec95e | 1056 | cs = intel_ring_begin(request, 0); |
85e2fe67 MW |
1057 | if (IS_ERR(cs)) |
1058 | return PTR_ERR(cs); | |
ef11c01d CW |
1059 | |
1060 | if (!ce->initialised) { | |
1061 | ret = engine->init_context(request); | |
1062 | if (ret) | |
85e2fe67 | 1063 | return ret; |
ef11c01d CW |
1064 | |
1065 | ce->initialised = true; | |
1066 | } | |
1067 | ||
1068 | /* Note that after this point, we have committed to using | |
1069 | * this request as it is being used to both track the | |
1070 | * state of engine initialisation and liveness of the | |
1071 | * golden renderstate above. Think twice before you try | |
1072 | * to cancel/unwind this request now. | |
1073 | */ | |
1074 | ||
1075 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
1076 | return 0; | |
ef11c01d CW |
1077 | } |
1078 | ||
9e000847 AS |
1079 | /* |
1080 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1081 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1082 | * but there is a slight complication as this is applied in WA batch where the | |
1083 | * values are only initialized once so we cannot take register value at the | |
1084 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1085 | * constant value with bit21 set and then we restore it back with the saved value. | |
1086 | * To simplify the WA, a constant value is formed by using the default value | |
1087 | * of this register. This shouldn't be a problem because we are only modifying | |
1088 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1089 | * use additional instructions that read the actual value of the register | |
1090 | * at that time and set our bit of interest but it makes the WA complicated. | |
1091 | * | |
1092 | * This WA is also required for Gen9 so extracting as a function avoids | |
1093 | * code duplication. | |
1094 | */ | |
097d4f1c TU |
1095 | static u32 * |
1096 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 1097 | { |
097d4f1c TU |
1098 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
1099 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1100 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1101 | *batch++ = 0; | |
1102 | ||
1103 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
1104 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1105 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
1106 | ||
9f235dfa TU |
1107 | batch = gen8_emit_pipe_control(batch, |
1108 | PIPE_CONTROL_CS_STALL | | |
1109 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1110 | 0); | |
097d4f1c TU |
1111 | |
1112 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
1113 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1114 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1115 | *batch++ = 0; | |
1116 | ||
1117 | return batch; | |
17ee950d AS |
1118 | } |
1119 | ||
6e5248b5 DV |
1120 | /* |
1121 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1122 | * initialized at the beginning and shared across all contexts but this field | |
1123 | * helps us to have multiple batches at different offsets and select them based | |
1124 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1125 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1126 | * |
6e5248b5 DV |
1127 | * The number of WA applied are not known at the beginning; we use this field |
1128 | * to return the no of DWORDS written. | |
17ee950d | 1129 | * |
6e5248b5 DV |
1130 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1131 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1132 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1133 | * makes a complete batch buffer. | |
17ee950d | 1134 | */ |
097d4f1c | 1135 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1136 | { |
7ad00d1a | 1137 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1138 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1139 | |
c82435bb | 1140 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1141 | if (IS_BROADWELL(engine->i915)) |
1142 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1143 | |
0160f055 AS |
1144 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1145 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1146 | batch = gen8_emit_pipe_control(batch, |
1147 | PIPE_CONTROL_FLUSH_L3 | | |
1148 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1149 | PIPE_CONTROL_CS_STALL | | |
1150 | PIPE_CONTROL_QW_WRITE, | |
1151 | i915_ggtt_offset(engine->scratch) + | |
1152 | 2 * CACHELINE_BYTES); | |
0160f055 | 1153 | |
17ee950d | 1154 | /* Pad to end of cacheline */ |
097d4f1c TU |
1155 | while ((unsigned long)batch % CACHELINE_BYTES) |
1156 | *batch++ = MI_NOOP; | |
17ee950d AS |
1157 | |
1158 | /* | |
1159 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1160 | * execution depends on the length specified in terms of cache lines | |
1161 | * in the register CTX_RCS_INDIRECT_CTX | |
1162 | */ | |
1163 | ||
097d4f1c | 1164 | return batch; |
17ee950d AS |
1165 | } |
1166 | ||
097d4f1c | 1167 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1168 | { |
9fb5026f | 1169 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 1170 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 1171 | |
9fb5026f | 1172 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1173 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1174 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1175 | *batch++ = _MASKED_BIT_DISABLE( | |
1176 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1177 | *batch++ = MI_NOOP; | |
873e8171 | 1178 | |
066d4628 MK |
1179 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1180 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1181 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1182 | batch = gen8_emit_pipe_control(batch, |
1183 | PIPE_CONTROL_FLUSH_L3 | | |
1184 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1185 | PIPE_CONTROL_CS_STALL | | |
1186 | PIPE_CONTROL_QW_WRITE, | |
1187 | i915_ggtt_offset(engine->scratch) | |
1188 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1189 | } |
3485d99e | 1190 | |
9fb5026f | 1191 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1192 | if (HAS_POOLED_EU(engine->i915)) { |
1193 | /* | |
1194 | * EU pool configuration is setup along with golden context | |
1195 | * during context initialization. This value depends on | |
1196 | * device type (2x6 or 3x6) and needs to be updated based | |
1197 | * on which subslice is disabled especially for 2x6 | |
1198 | * devices, however it is safe to load default | |
1199 | * configuration of 3x6 device instead of masking off | |
1200 | * corresponding bits because HW ignores bits of a disabled | |
1201 | * subslice and drops down to appropriate config. Please | |
1202 | * see render_state_setup() in i915_gem_render_state.c for | |
1203 | * possible configurations, to avoid duplication they are | |
1204 | * not shown here again. | |
1205 | */ | |
097d4f1c TU |
1206 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1207 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1208 | *batch++ = 0x00777000; | |
1209 | *batch++ = 0; | |
1210 | *batch++ = 0; | |
1211 | *batch++ = 0; | |
3485d99e TG |
1212 | } |
1213 | ||
0504cffc | 1214 | /* Pad to end of cacheline */ |
097d4f1c TU |
1215 | while ((unsigned long)batch % CACHELINE_BYTES) |
1216 | *batch++ = MI_NOOP; | |
0504cffc | 1217 | |
097d4f1c | 1218 | return batch; |
0504cffc AS |
1219 | } |
1220 | ||
097d4f1c TU |
1221 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1222 | ||
1223 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1224 | { |
48bb74e4 CW |
1225 | struct drm_i915_gem_object *obj; |
1226 | struct i915_vma *vma; | |
1227 | int err; | |
17ee950d | 1228 | |
097d4f1c | 1229 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1230 | if (IS_ERR(obj)) |
1231 | return PTR_ERR(obj); | |
17ee950d | 1232 | |
a01cb37a | 1233 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1234 | if (IS_ERR(vma)) { |
1235 | err = PTR_ERR(vma); | |
1236 | goto err; | |
17ee950d AS |
1237 | } |
1238 | ||
48bb74e4 CW |
1239 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1240 | if (err) | |
1241 | goto err; | |
1242 | ||
1243 | engine->wa_ctx.vma = vma; | |
17ee950d | 1244 | return 0; |
48bb74e4 CW |
1245 | |
1246 | err: | |
1247 | i915_gem_object_put(obj); | |
1248 | return err; | |
17ee950d AS |
1249 | } |
1250 | ||
097d4f1c | 1251 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1252 | { |
19880c4a | 1253 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1254 | } |
1255 | ||
097d4f1c TU |
1256 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1257 | ||
0bc40be8 | 1258 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1259 | { |
48bb74e4 | 1260 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1261 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1262 | &wa_ctx->per_ctx }; | |
1263 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1264 | struct page *page; |
097d4f1c TU |
1265 | void *batch, *batch_ptr; |
1266 | unsigned int i; | |
48bb74e4 | 1267 | int ret; |
17ee950d | 1268 | |
097d4f1c TU |
1269 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1270 | return -EINVAL; | |
17ee950d | 1271 | |
097d4f1c | 1272 | switch (INTEL_GEN(engine->i915)) { |
90007bca RV |
1273 | case 10: |
1274 | return 0; | |
097d4f1c TU |
1275 | case 9: |
1276 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
b8aa2233 | 1277 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1278 | break; |
1279 | case 8: | |
1280 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
3ad7b52d | 1281 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1282 | break; |
1283 | default: | |
1284 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1285 | return 0; |
0504cffc | 1286 | } |
5e60d790 | 1287 | |
097d4f1c | 1288 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1289 | if (ret) { |
1290 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1291 | return ret; | |
1292 | } | |
1293 | ||
48bb74e4 | 1294 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1295 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1296 | |
097d4f1c TU |
1297 | /* |
1298 | * Emit the two workaround batch buffers, recording the offset from the | |
1299 | * start of the workaround batch buffer object for each and their | |
1300 | * respective sizes. | |
1301 | */ | |
1302 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1303 | wa_bb[i]->offset = batch_ptr - batch; | |
1304 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1305 | ret = -EINVAL; | |
1306 | break; | |
1307 | } | |
604a8f6f CW |
1308 | if (wa_bb_fn[i]) |
1309 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
097d4f1c | 1310 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); |
17ee950d AS |
1311 | } |
1312 | ||
097d4f1c TU |
1313 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1314 | ||
17ee950d AS |
1315 | kunmap_atomic(batch); |
1316 | if (ret) | |
097d4f1c | 1317 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1318 | |
1319 | return ret; | |
1320 | } | |
1321 | ||
64f09f00 CW |
1322 | static u8 gtiir[] = { |
1323 | [RCS] = 0, | |
1324 | [BCS] = 0, | |
1325 | [VCS] = 1, | |
1326 | [VCS2] = 1, | |
1327 | [VECS] = 3, | |
1328 | }; | |
1329 | ||
0bc40be8 | 1330 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1331 | { |
c033666a | 1332 | struct drm_i915_private *dev_priv = engine->i915; |
b620e870 | 1333 | struct intel_engine_execlists * const execlists = &engine->execlists; |
821ed7df CW |
1334 | int ret; |
1335 | ||
1336 | ret = intel_mocs_init_engine(engine); | |
1337 | if (ret) | |
1338 | return ret; | |
9b1136d5 | 1339 | |
ad07dfcd | 1340 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1341 | intel_engine_init_hangcheck(engine); |
821ed7df | 1342 | |
0bc40be8 | 1343 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1344 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1345 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1346 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1347 | engine->status_page.ggtt_offset); | |
1348 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1349 | |
0bc40be8 | 1350 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1351 | |
64f09f00 CW |
1352 | GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); |
1353 | ||
1354 | /* | |
1355 | * Clear any pending interrupt state. | |
1356 | * | |
1357 | * We do it twice out of paranoia that some of the IIR are double | |
1358 | * buffered, and if we only reset it once there may still be | |
1359 | * an interrupt pending. | |
1360 | */ | |
1361 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1362 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
1363 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1364 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
f747026c | 1365 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
b620e870 | 1366 | execlists->csb_head = -1; |
6b764a59 | 1367 | |
64f09f00 | 1368 | /* After a GPU reset, we may have requests to replay */ |
b620e870 MK |
1369 | if (!i915_modparams.enable_guc_submission && execlists->first) |
1370 | tasklet_schedule(&execlists->irq_tasklet); | |
6b764a59 | 1371 | |
821ed7df | 1372 | return 0; |
9b1136d5 OM |
1373 | } |
1374 | ||
0bc40be8 | 1375 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1376 | { |
c033666a | 1377 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1378 | int ret; |
1379 | ||
0bc40be8 | 1380 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1381 | if (ret) |
1382 | return ret; | |
1383 | ||
1384 | /* We need to disable the AsyncFlip performance optimisations in order | |
1385 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1386 | * programmed to '1' on all products. | |
1387 | * | |
1388 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1389 | */ | |
1390 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1391 | ||
9b1136d5 OM |
1392 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1393 | ||
0bc40be8 | 1394 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1395 | } |
1396 | ||
0bc40be8 | 1397 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1398 | { |
1399 | int ret; | |
1400 | ||
0bc40be8 | 1401 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1402 | if (ret) |
1403 | return ret; | |
1404 | ||
0bc40be8 | 1405 | return init_workarounds_ring(engine); |
82ef822e DL |
1406 | } |
1407 | ||
821ed7df CW |
1408 | static void reset_common_ring(struct intel_engine_cs *engine, |
1409 | struct drm_i915_gem_request *request) | |
1410 | { | |
b620e870 | 1411 | struct intel_engine_execlists * const execlists = &engine->execlists; |
c0dcb203 | 1412 | struct intel_context *ce; |
221ab971 | 1413 | unsigned long flags; |
cdb6ded4 | 1414 | |
221ab971 CW |
1415 | spin_lock_irqsave(&engine->timeline->lock, flags); |
1416 | ||
cdb6ded4 CW |
1417 | /* |
1418 | * Catch up with any missed context-switch interrupts. | |
1419 | * | |
1420 | * Ideally we would just read the remaining CSB entries now that we | |
1421 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1422 | * often trashed across a GPU reset! Instead we have to rely on | |
1423 | * guessing the missed context-switch events by looking at what | |
1424 | * requests were completed. | |
1425 | */ | |
cf4591d1 | 1426 | execlist_cancel_port_requests(execlists); |
cdb6ded4 | 1427 | |
221ab971 | 1428 | /* Push back any incomplete requests for replay after the reset. */ |
7e4992ac | 1429 | unwind_incomplete_requests(engine); |
cdb6ded4 | 1430 | |
221ab971 | 1431 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
c0dcb203 CW |
1432 | |
1433 | /* If the request was innocent, we leave the request in the ELSP | |
1434 | * and will try to replay it on restarting. The context image may | |
1435 | * have been corrupted by the reset, in which case we may have | |
1436 | * to service a new GPU hang, but more likely we can continue on | |
1437 | * without impact. | |
1438 | * | |
1439 | * If the request was guilty, we presume the context is corrupt | |
1440 | * and have to at least restore the RING register in the context | |
1441 | * image back to the expected values to skip over the guilty request. | |
1442 | */ | |
221ab971 | 1443 | if (!request || request->fence.error != -EIO) |
c0dcb203 | 1444 | return; |
821ed7df | 1445 | |
a3aabe86 CW |
1446 | /* We want a simple context + ring to execute the breadcrumb update. |
1447 | * We cannot rely on the context being intact across the GPU hang, | |
1448 | * so clear it and rebuild just what we need for the breadcrumb. | |
1449 | * All pending requests for this context will be zapped, and any | |
1450 | * future request will be after userspace has had the opportunity | |
1451 | * to recreate its own state. | |
1452 | */ | |
c0dcb203 | 1453 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1454 | execlists_init_reg_state(ce->lrc_reg_state, |
1455 | request->ctx, engine, ce->ring); | |
1456 | ||
821ed7df | 1457 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1458 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1459 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1460 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1461 | |
821ed7df | 1462 | request->ring->head = request->postfix; |
821ed7df CW |
1463 | intel_ring_update_space(request->ring); |
1464 | ||
a3aabe86 | 1465 | /* Reset WaIdleLiteRestore:bdw,skl as well */ |
7e4992ac | 1466 | unwind_wa_tail(request); |
821ed7df CW |
1467 | } |
1468 | ||
7a01a0a2 MT |
1469 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1470 | { | |
1471 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1472 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1473 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1474 | u32 *cs; |
1475 | int i; | |
7a01a0a2 | 1476 | |
73dec95e TU |
1477 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1478 | if (IS_ERR(cs)) | |
1479 | return PTR_ERR(cs); | |
7a01a0a2 | 1480 | |
73dec95e | 1481 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1482 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1483 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1484 | ||
73dec95e TU |
1485 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1486 | *cs++ = upper_32_bits(pd_daddr); | |
1487 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1488 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1489 | } |
1490 | ||
73dec95e TU |
1491 | *cs++ = MI_NOOP; |
1492 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1493 | |
1494 | return 0; | |
1495 | } | |
1496 | ||
be795fc1 | 1497 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1498 | u64 offset, u32 len, |
54af56db | 1499 | const unsigned int flags) |
15648585 | 1500 | { |
73dec95e | 1501 | u32 *cs; |
15648585 OM |
1502 | int ret; |
1503 | ||
7a01a0a2 MT |
1504 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1505 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1506 | * but we can't. Force Restore would be a second option, but | |
1507 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1508 | * not idle). PML4 is allocated during ppgtt init so this is |
1509 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1510 | if (req->ctx->ppgtt && |
54af56db MK |
1511 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1512 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1513 | !intel_vgpu_active(req->i915)) { | |
1514 | ret = intel_logical_ring_emit_pdps(req); | |
1515 | if (ret) | |
1516 | return ret; | |
7a01a0a2 | 1517 | |
666796da | 1518 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1519 | } |
1520 | ||
73dec95e TU |
1521 | cs = intel_ring_begin(req, 4); |
1522 | if (IS_ERR(cs)) | |
1523 | return PTR_ERR(cs); | |
15648585 | 1524 | |
3ad7b52d CW |
1525 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1526 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1527 | ||
15648585 | 1528 | /* FIXME(BDW): Address space and security selectors. */ |
54af56db MK |
1529 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1530 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1531 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1532 | *cs++ = lower_32_bits(offset); |
1533 | *cs++ = upper_32_bits(offset); | |
73dec95e | 1534 | intel_ring_advance(req, cs); |
15648585 OM |
1535 | |
1536 | return 0; | |
1537 | } | |
1538 | ||
31bb59cc | 1539 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1540 | { |
c033666a | 1541 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1542 | I915_WRITE_IMR(engine, |
1543 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1544 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1545 | } |
1546 | ||
31bb59cc | 1547 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1548 | { |
c033666a | 1549 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1550 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1551 | } |
1552 | ||
7c9cf4e3 | 1553 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1554 | { |
73dec95e | 1555 | u32 cmd, *cs; |
4712274c | 1556 | |
73dec95e TU |
1557 | cs = intel_ring_begin(request, 4); |
1558 | if (IS_ERR(cs)) | |
1559 | return PTR_ERR(cs); | |
4712274c OM |
1560 | |
1561 | cmd = MI_FLUSH_DW + 1; | |
1562 | ||
f0a1fb10 CW |
1563 | /* We always require a command barrier so that subsequent |
1564 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1565 | * wrt the contents of the write cache being flushed to memory | |
1566 | * (and thus being coherent from the CPU). | |
1567 | */ | |
1568 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1569 | ||
7c9cf4e3 | 1570 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1571 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1572 | if (request->engine->id == VCS) |
f0a1fb10 | 1573 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1574 | } |
1575 | ||
73dec95e TU |
1576 | *cs++ = cmd; |
1577 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1578 | *cs++ = 0; /* upper addr */ | |
1579 | *cs++ = 0; /* value */ | |
1580 | intel_ring_advance(request, cs); | |
4712274c OM |
1581 | |
1582 | return 0; | |
1583 | } | |
1584 | ||
7deb4d39 | 1585 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1586 | u32 mode) |
4712274c | 1587 | { |
b5321f30 | 1588 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1589 | u32 scratch_addr = |
1590 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1591 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1592 | u32 *cs, flags = 0; |
0b2d0934 | 1593 | int len; |
4712274c OM |
1594 | |
1595 | flags |= PIPE_CONTROL_CS_STALL; | |
1596 | ||
7c9cf4e3 | 1597 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1598 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1599 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1600 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1601 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1602 | } |
1603 | ||
7c9cf4e3 | 1604 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1605 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1606 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1607 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1608 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1609 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1610 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1611 | flags |= PIPE_CONTROL_QW_WRITE; | |
1612 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1613 | |
1a5a9ce7 BW |
1614 | /* |
1615 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1616 | * pipe control. | |
1617 | */ | |
c033666a | 1618 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1619 | vf_flush_wa = true; |
0b2d0934 MK |
1620 | |
1621 | /* WaForGAMHang:kbl */ | |
1622 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1623 | dc_flush_wa = true; | |
1a5a9ce7 | 1624 | } |
9647ff36 | 1625 | |
0b2d0934 MK |
1626 | len = 6; |
1627 | ||
1628 | if (vf_flush_wa) | |
1629 | len += 6; | |
1630 | ||
1631 | if (dc_flush_wa) | |
1632 | len += 12; | |
1633 | ||
73dec95e TU |
1634 | cs = intel_ring_begin(request, len); |
1635 | if (IS_ERR(cs)) | |
1636 | return PTR_ERR(cs); | |
4712274c | 1637 | |
9f235dfa TU |
1638 | if (vf_flush_wa) |
1639 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1640 | |
9f235dfa TU |
1641 | if (dc_flush_wa) |
1642 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1643 | 0); | |
0b2d0934 | 1644 | |
9f235dfa | 1645 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1646 | |
9f235dfa TU |
1647 | if (dc_flush_wa) |
1648 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1649 | |
73dec95e | 1650 | intel_ring_advance(request, cs); |
4712274c OM |
1651 | |
1652 | return 0; | |
1653 | } | |
1654 | ||
7c17d377 CW |
1655 | /* |
1656 | * Reserve space for 2 NOOPs at the end of each request to be | |
1657 | * used as a workaround for not being allowed to do lite | |
1658 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1659 | */ | |
73dec95e | 1660 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1661 | { |
73dec95e TU |
1662 | *cs++ = MI_NOOP; |
1663 | *cs++ = MI_NOOP; | |
1664 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1665 | } |
4da46e1e | 1666 | |
73dec95e | 1667 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1668 | { |
7c17d377 CW |
1669 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1670 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1671 | |
73dec95e TU |
1672 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1673 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1674 | *cs++ = 0; | |
1675 | *cs++ = request->global_seqno; | |
1676 | *cs++ = MI_USER_INTERRUPT; | |
1677 | *cs++ = MI_NOOP; | |
1678 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1679 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1680 | |
73dec95e | 1681 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1682 | } |
4da46e1e | 1683 | |
98f29e8d CW |
1684 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1685 | ||
caddfe71 | 1686 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1687 | u32 *cs) |
7c17d377 | 1688 | { |
ce81a65c MW |
1689 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1690 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1691 | ||
7c17d377 CW |
1692 | /* w/a for post sync ops following a GPGPU operation we |
1693 | * need a prior CS_STALL, which is emitted by the flush | |
1694 | * following the batch. | |
1695 | */ | |
73dec95e TU |
1696 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1697 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1698 | PIPE_CONTROL_QW_WRITE; | |
1699 | *cs++ = intel_hws_seqno_address(request->engine); | |
1700 | *cs++ = 0; | |
1701 | *cs++ = request->global_seqno; | |
ce81a65c | 1702 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1703 | *cs++ = 0; |
1704 | *cs++ = MI_USER_INTERRUPT; | |
1705 | *cs++ = MI_NOOP; | |
1706 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1707 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1708 | |
73dec95e | 1709 | gen8_emit_wa_tail(request, cs); |
4da46e1e OM |
1710 | } |
1711 | ||
98f29e8d CW |
1712 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1713 | ||
8753181e | 1714 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1715 | { |
1716 | int ret; | |
1717 | ||
4ac9659e | 1718 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1719 | if (ret) |
1720 | return ret; | |
1721 | ||
3bbaba0c PA |
1722 | ret = intel_rcs_context_init_mocs(req); |
1723 | /* | |
1724 | * Failing to program the MOCS is non-fatal.The system will not | |
1725 | * run at peak performance. So generate an error and carry on. | |
1726 | */ | |
1727 | if (ret) | |
1728 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1729 | ||
4e50f082 | 1730 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1731 | } |
1732 | ||
73e4d07f OM |
1733 | /** |
1734 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1735 | * @engine: Engine Command Streamer. |
73e4d07f | 1736 | */ |
0bc40be8 | 1737 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1738 | { |
6402c330 | 1739 | struct drm_i915_private *dev_priv; |
9832b9da | 1740 | |
27af5eea TU |
1741 | /* |
1742 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1743 | * so this is just for documentation. | |
1744 | */ | |
b620e870 MK |
1745 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state))) |
1746 | tasklet_kill(&engine->execlists.irq_tasklet); | |
27af5eea | 1747 | |
c033666a | 1748 | dev_priv = engine->i915; |
6402c330 | 1749 | |
0bc40be8 | 1750 | if (engine->buffer) { |
0bc40be8 | 1751 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1752 | } |
48d82387 | 1753 | |
0bc40be8 TU |
1754 | if (engine->cleanup) |
1755 | engine->cleanup(engine); | |
48d82387 | 1756 | |
e8a9c58f | 1757 | intel_engine_cleanup_common(engine); |
17ee950d | 1758 | |
097d4f1c | 1759 | lrc_destroy_wa_ctx(engine); |
c033666a | 1760 | engine->i915 = NULL; |
3b3f1650 AG |
1761 | dev_priv->engine[engine->id] = NULL; |
1762 | kfree(engine); | |
454afebd OM |
1763 | } |
1764 | ||
ff44ad51 | 1765 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1766 | { |
ff44ad51 | 1767 | engine->submit_request = execlists_submit_request; |
27a5f61b | 1768 | engine->cancel_requests = execlists_cancel_requests; |
ff44ad51 | 1769 | engine->schedule = execlists_schedule; |
b620e870 | 1770 | engine->execlists.irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1771 | } |
1772 | ||
c9cacf93 | 1773 | static void |
e1382efb | 1774 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1775 | { |
1776 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1777 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1778 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1779 | |
1780 | engine->context_pin = execlists_context_pin; | |
1781 | engine->context_unpin = execlists_context_unpin; | |
1782 | ||
f73e7399 CW |
1783 | engine->request_alloc = execlists_request_alloc; |
1784 | ||
0bc40be8 | 1785 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1786 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1787 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1788 | |
1789 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1790 | |
31bb59cc CW |
1791 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1792 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1793 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1794 | } |
1795 | ||
d9f3af96 | 1796 | static inline void |
c2c7f240 | 1797 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1798 | { |
c2c7f240 | 1799 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1800 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1801 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1802 | } |
1803 | ||
bb45438f TU |
1804 | static void |
1805 | logical_ring_setup(struct intel_engine_cs *engine) | |
1806 | { | |
1807 | struct drm_i915_private *dev_priv = engine->i915; | |
1808 | enum forcewake_domains fw_domains; | |
1809 | ||
019bf277 TU |
1810 | intel_engine_setup_common(engine); |
1811 | ||
bb45438f TU |
1812 | /* Intentionally left blank. */ |
1813 | engine->buffer = NULL; | |
1814 | ||
1815 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1816 | RING_ELSP(engine), | |
1817 | FW_REG_WRITE); | |
1818 | ||
1819 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1820 | RING_CONTEXT_STATUS_PTR(engine), | |
1821 | FW_REG_READ | FW_REG_WRITE); | |
1822 | ||
1823 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1824 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1825 | FW_REG_READ); | |
1826 | ||
b620e870 | 1827 | engine->execlists.fw_domains = fw_domains; |
bb45438f | 1828 | |
b620e870 | 1829 | tasklet_init(&engine->execlists.irq_tasklet, |
bb45438f TU |
1830 | intel_lrc_irq_handler, (unsigned long)engine); |
1831 | ||
bb45438f TU |
1832 | logical_ring_default_vfuncs(engine); |
1833 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1834 | } |
1835 | ||
486e93f7 | 1836 | static int logical_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 1837 | { |
a19d6ff2 TU |
1838 | int ret; |
1839 | ||
019bf277 | 1840 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1841 | if (ret) |
1842 | goto error; | |
1843 | ||
a19d6ff2 TU |
1844 | return 0; |
1845 | ||
1846 | error: | |
1847 | intel_logical_ring_cleanup(engine); | |
1848 | return ret; | |
1849 | } | |
1850 | ||
88d2ba2e | 1851 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1852 | { |
1853 | struct drm_i915_private *dev_priv = engine->i915; | |
1854 | int ret; | |
1855 | ||
bb45438f TU |
1856 | logical_ring_setup(engine); |
1857 | ||
a19d6ff2 TU |
1858 | if (HAS_L3_DPF(dev_priv)) |
1859 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1860 | ||
1861 | /* Override some for render ring. */ | |
1862 | if (INTEL_GEN(dev_priv) >= 9) | |
1863 | engine->init_hw = gen9_init_render_ring; | |
1864 | else | |
1865 | engine->init_hw = gen8_init_render_ring; | |
1866 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1867 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1868 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1869 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1870 | |
f51455d4 | 1871 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1872 | if (ret) |
1873 | return ret; | |
1874 | ||
1875 | ret = intel_init_workaround_bb(engine); | |
1876 | if (ret) { | |
1877 | /* | |
1878 | * We continue even if we fail to initialize WA batch | |
1879 | * because we only expect rare glitches but nothing | |
1880 | * critical to prevent us from using GPU | |
1881 | */ | |
1882 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1883 | ret); | |
1884 | } | |
1885 | ||
d038fc7e | 1886 | return logical_ring_init(engine); |
a19d6ff2 TU |
1887 | } |
1888 | ||
88d2ba2e | 1889 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1890 | { |
1891 | logical_ring_setup(engine); | |
1892 | ||
1893 | return logical_ring_init(engine); | |
454afebd OM |
1894 | } |
1895 | ||
0cea6502 | 1896 | static u32 |
c033666a | 1897 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1898 | { |
1899 | u32 rpcs = 0; | |
1900 | ||
1901 | /* | |
1902 | * No explicit RPCS request is needed to ensure full | |
1903 | * slice/subslice/EU enablement prior to Gen9. | |
1904 | */ | |
c033666a | 1905 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1906 | return 0; |
1907 | ||
1908 | /* | |
1909 | * Starting in Gen9, render power gating can leave | |
1910 | * slice/subslice/EU in a partially enabled state. We | |
1911 | * must make an explicit request through RPCS for full | |
1912 | * enablement. | |
1913 | */ | |
43b67998 | 1914 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1915 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1916 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1917 | GEN8_RPCS_S_CNT_SHIFT; |
1918 | rpcs |= GEN8_RPCS_ENABLE; | |
1919 | } | |
1920 | ||
43b67998 | 1921 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1922 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1923 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1924 | GEN8_RPCS_SS_CNT_SHIFT; |
1925 | rpcs |= GEN8_RPCS_ENABLE; | |
1926 | } | |
1927 | ||
43b67998 ID |
1928 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1929 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1930 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1931 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1932 | GEN8_RPCS_EU_MAX_SHIFT; |
1933 | rpcs |= GEN8_RPCS_ENABLE; | |
1934 | } | |
1935 | ||
1936 | return rpcs; | |
1937 | } | |
1938 | ||
0bc40be8 | 1939 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1940 | { |
1941 | u32 indirect_ctx_offset; | |
1942 | ||
c033666a | 1943 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1944 | default: |
c033666a | 1945 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 1946 | /* fall through */ |
7bd0a2c6 MT |
1947 | case 10: |
1948 | indirect_ctx_offset = | |
1949 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1950 | break; | |
71562919 MT |
1951 | case 9: |
1952 | indirect_ctx_offset = | |
1953 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1954 | break; | |
1955 | case 8: | |
1956 | indirect_ctx_offset = | |
1957 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1958 | break; | |
1959 | } | |
1960 | ||
1961 | return indirect_ctx_offset; | |
1962 | } | |
1963 | ||
56e51bf0 | 1964 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
1965 | struct i915_gem_context *ctx, |
1966 | struct intel_engine_cs *engine, | |
1967 | struct intel_ring *ring) | |
8670d6f9 | 1968 | { |
a3aabe86 CW |
1969 | struct drm_i915_private *dev_priv = engine->i915; |
1970 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
1971 | u32 base = engine->mmio_base; |
1972 | bool rcs = engine->id == RCS; | |
1973 | ||
1974 | /* A context is actually a big batch buffer with several | |
1975 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
1976 | * values we are setting here are only for the first context restore: | |
1977 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
1978 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
1979 | * we are not initializing here). | |
1980 | */ | |
1981 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
1982 | MI_LRI_FORCE_POSTED; | |
1983 | ||
1984 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
1985 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
1986 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
1987 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
1988 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
1989 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
1990 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
1991 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
1992 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
1993 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
1994 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
1995 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
1996 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
1997 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
1998 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
1999 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
2000 | if (rcs) { | |
604a8f6f CW |
2001 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
2002 | ||
56e51bf0 TU |
2003 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); |
2004 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2005 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
604a8f6f | 2006 | if (wa_ctx->indirect_ctx.size) { |
bde13ebd | 2007 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 2008 | |
56e51bf0 | 2009 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
2010 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
2011 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 2012 | |
56e51bf0 | 2013 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 2014 | intel_lr_indirect_ctx_offset(engine) << 6; |
604a8f6f CW |
2015 | } |
2016 | ||
2017 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
2018 | if (wa_ctx->per_ctx.size) { | |
2019 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); | |
17ee950d | 2020 | |
56e51bf0 | 2021 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 2022 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 2023 | } |
8670d6f9 | 2024 | } |
56e51bf0 TU |
2025 | |
2026 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
2027 | ||
2028 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 2029 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
2030 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
2031 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
2032 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
2033 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
2034 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
2035 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
2036 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
2037 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 2038 | |
949e8ab3 | 2039 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
2040 | /* 64b PPGTT (48bit canonical) |
2041 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2042 | * other PDP Descriptors are ignored. | |
2043 | */ | |
56e51bf0 | 2044 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
2045 | } |
2046 | ||
56e51bf0 TU |
2047 | if (rcs) { |
2048 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
2049 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
2050 | make_rpcs(dev_priv)); | |
19f81df2 RB |
2051 | |
2052 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 2053 | } |
a3aabe86 CW |
2054 | } |
2055 | ||
2056 | static int | |
2057 | populate_lr_context(struct i915_gem_context *ctx, | |
2058 | struct drm_i915_gem_object *ctx_obj, | |
2059 | struct intel_engine_cs *engine, | |
2060 | struct intel_ring *ring) | |
2061 | { | |
2062 | void *vaddr; | |
2063 | int ret; | |
2064 | ||
2065 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2066 | if (ret) { | |
2067 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2068 | return ret; | |
2069 | } | |
2070 | ||
2071 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2072 | if (IS_ERR(vaddr)) { | |
2073 | ret = PTR_ERR(vaddr); | |
2074 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2075 | return ret; | |
2076 | } | |
a4f5ea64 | 2077 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2078 | |
2079 | /* The second page of the context object contains some fields which must | |
2080 | * be set up prior to the first execution. */ | |
2081 | ||
2082 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2083 | ctx, engine, ring); | |
8670d6f9 | 2084 | |
7d774cac | 2085 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2086 | |
2087 | return 0; | |
2088 | } | |
2089 | ||
e2efd130 | 2090 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2091 | struct intel_engine_cs *engine) |
ede7d42b | 2092 | { |
8c857917 | 2093 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2094 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2095 | struct i915_vma *vma; |
8c857917 | 2096 | uint32_t context_size; |
7e37f889 | 2097 | struct intel_ring *ring; |
8c857917 OM |
2098 | int ret; |
2099 | ||
9021ad03 | 2100 | WARN_ON(ce->state); |
ede7d42b | 2101 | |
63ffbcda | 2102 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2103 | |
0b29c75a MT |
2104 | /* |
2105 | * Before the actual start of the context image, we insert a few pages | |
2106 | * for our own use and for sharing with the GuC. | |
2107 | */ | |
2108 | context_size += LRC_HEADER_PAGES * PAGE_SIZE; | |
d1675198 | 2109 | |
12d79d78 | 2110 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2111 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2112 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2113 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2114 | } |
2115 | ||
a01cb37a | 2116 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2117 | if (IS_ERR(vma)) { |
2118 | ret = PTR_ERR(vma); | |
2119 | goto error_deref_obj; | |
2120 | } | |
2121 | ||
7e37f889 | 2122 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2123 | if (IS_ERR(ring)) { |
2124 | ret = PTR_ERR(ring); | |
e84fe803 | 2125 | goto error_deref_obj; |
8670d6f9 OM |
2126 | } |
2127 | ||
dca33ecc | 2128 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2129 | if (ret) { |
2130 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2131 | goto error_ring_free; |
84c2377f OM |
2132 | } |
2133 | ||
dca33ecc | 2134 | ce->ring = ring; |
bf3783e5 | 2135 | ce->state = vma; |
0d402a24 | 2136 | ce->initialised |= engine->init_context == NULL; |
ede7d42b OM |
2137 | |
2138 | return 0; | |
8670d6f9 | 2139 | |
dca33ecc | 2140 | error_ring_free: |
7e37f889 | 2141 | intel_ring_free(ring); |
e84fe803 | 2142 | error_deref_obj: |
f8c417cd | 2143 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2144 | return ret; |
ede7d42b | 2145 | } |
3e5b6f05 | 2146 | |
821ed7df | 2147 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2148 | { |
e2f80391 | 2149 | struct intel_engine_cs *engine; |
bafb2f7d | 2150 | struct i915_gem_context *ctx; |
3b3f1650 | 2151 | enum intel_engine_id id; |
bafb2f7d CW |
2152 | |
2153 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2154 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2155 | * that stored in context. As we only write new commands from | |
2156 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2157 | * starts reading from its RING_HEAD from the context, it may try to | |
2158 | * execute that junk and die. | |
2159 | * | |
2160 | * So to avoid that we reset the context images upon resume. For | |
2161 | * simplicity, we just zero everything out. | |
2162 | */ | |
829a0af2 | 2163 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
3b3f1650 | 2164 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2165 | struct intel_context *ce = &ctx->engine[engine->id]; |
2166 | u32 *reg; | |
3e5b6f05 | 2167 | |
bafb2f7d CW |
2168 | if (!ce->state) |
2169 | continue; | |
7d774cac | 2170 | |
bafb2f7d CW |
2171 | reg = i915_gem_object_pin_map(ce->state->obj, |
2172 | I915_MAP_WB); | |
2173 | if (WARN_ON(IS_ERR(reg))) | |
2174 | continue; | |
3e5b6f05 | 2175 | |
bafb2f7d CW |
2176 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2177 | reg[CTX_RING_HEAD+1] = 0; | |
2178 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2179 | |
a4f5ea64 | 2180 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2181 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2182 | |
e6ba9992 | 2183 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2184 | } |
3e5b6f05 TD |
2185 | } |
2186 | } |