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Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm...
[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW		 1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP		 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
f766093e 33#include <linux/kernel.h>
7bd90909 34#include <linux/moduleparam.h>
b029e66f 35#include <linux/pwm.h>
1d8e1c75
CW		 36#include "intel_drv.h"
37
b029e66f
SK		 38#define CRC_PMIC_PWM_PERIOD_NS 21333
39
1d8e1c75 40void
4c6df4b4 41intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW		 42 struct drm_display_mode *adjusted_mode)
43{
4c6df4b4 44 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID		 45
46 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW		 47}
48
525997e0
JN		 49/**
50 * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID
a318b4c4 51 * @dev_priv: i915 device instance
525997e0
JN		 52 * @fixed_mode : panel native mode
53 * @connector: LVDS/eDP connector
54 *
55 * Return downclock_avail
56 * Find the reduced downclock for LVDS/eDP in EDID.
57 */
58struct drm_display_mode *
a318b4c4 59intel_find_panel_downclock(struct drm_i915_private *dev_priv,
525997e0
JN		 60 struct drm_display_mode *fixed_mode,
61 struct drm_connector *connector)
62{
63 struct drm_display_mode *scan, *tmp_mode;
64 int temp_downclock;
65
66 temp_downclock = fixed_mode->clock;
67 tmp_mode = NULL;
68
69 list_for_each_entry(scan, &connector->probed_modes, head) {
70 /*
71 * If one mode has the same resolution with the fixed_panel
72 * mode while they have the different refresh rate, it means
73 * that the reduced downclock is found. In such
74 * case we can set the different FPx0/1 to dynamically select
75 * between low and high frequency.
76 */
77 if (scan->hdisplay == fixed_mode->hdisplay &&
78 scan->hsync_start == fixed_mode->hsync_start &&
79 scan->hsync_end == fixed_mode->hsync_end &&
80 scan->htotal == fixed_mode->htotal &&
81 scan->vdisplay == fixed_mode->vdisplay &&
82 scan->vsync_start == fixed_mode->vsync_start &&
83 scan->vsync_end == fixed_mode->vsync_end &&
84 scan->vtotal == fixed_mode->vtotal) {
85 if (scan->clock < temp_downclock) {
86 /*
87 * The downclock is already found. But we
88 * expect to find the lower downclock.
89 */
90 temp_downclock = scan->clock;
91 tmp_mode = scan;
92 }
93 }
94 }
95
96 if (temp_downclock < fixed_mode->clock)
a318b4c4 97 return drm_mode_duplicate(&dev_priv->drm, tmp_mode);
525997e0
JN		 98 else
99 return NULL;
100}
101
1d8e1c75
CW		 102/* adjusted_mode has been preset to be the panel's fixed mode */
103void
b074cec8 104intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 105 struct intel_crtc_state *pipe_config,
b074cec8 106 int fitting_mode)
1d8e1c75 107{
7c5f93b0
VS		 108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
109 int x = 0, y = 0, width = 0, height = 0;
1d8e1c75
CW		 110
111 /* Native modes don't need fitting */
aad941d5 112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
e5c05931 113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
33b7f3ee 114 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
1d8e1c75
CW		 115 goto done;
116
117 switch (fitting_mode) {
118 case DRM_MODE_SCALE_CENTER:
37327abd
VS		 119 width = pipe_config->pipe_src_w;
120 height = pipe_config->pipe_src_h;
aad941d5
VS		 121 x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
122 y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
1d8e1c75
CW		 123 break;
124
125 case DRM_MODE_SCALE_ASPECT:
126 /* Scale but preserve the aspect ratio */
127 {
aad941d5 128 u32 scaled_width = adjusted_mode->crtc_hdisplay
9084e7d2
SV		 129 * pipe_config->pipe_src_h;
130 u32 scaled_height = pipe_config->pipe_src_w
aad941d5 131 * adjusted_mode->crtc_vdisplay;
1d8e1c75 132 if (scaled_width > scaled_height) { /* pillar */
37327abd 133 width = scaled_height / pipe_config->pipe_src_h;
302983e9 134 if (width & 1)
0206e353 135 width++;
aad941d5 136 x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
1d8e1c75 137 y = 0;
aad941d5 138 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 139 } else if (scaled_width < scaled_height) { /* letter */
37327abd 140 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ		 141 if (height & 1)
142 height++;
aad941d5 143 y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
1d8e1c75 144 x = 0;
aad941d5 145 width = adjusted_mode->crtc_hdisplay;
1d8e1c75
CW		 146 } else {
147 x = y = 0;
aad941d5
VS		 148 width = adjusted_mode->crtc_hdisplay;
149 height = adjusted_mode->crtc_vdisplay;
1d8e1c75
CW		 150 }
151 }
152 break;
153
1d8e1c75
CW		 154 case DRM_MODE_SCALE_FULLSCREEN:
155 x = y = 0;
aad941d5
VS		 156 width = adjusted_mode->crtc_hdisplay;
157 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 158 break;
ab3e67f4
JB		 159
160 default:
161 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
162 return;
1d8e1c75
CW		 163 }
164
165done:
b074cec8
JB		 166 pipe_config->pch_pfit.pos = (x << 16) | y;
167 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 168 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 169}
a9573556 170
2dd24552 171static void
5e7234c9 172centre_horizontally(struct drm_display_mode *adjusted_mode,
2dd24552
JB		 173 int width)
174{
175 u32 border, sync_pos, blank_width, sync_width;
176
177 /* keep the hsync and hblank widths constant */
5e7234c9
VS		 178 sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
179 blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
2dd24552
JB		 180 sync_pos = (blank_width - sync_width + 1) / 2;
181
aad941d5 182 border = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
2dd24552
JB		 183 border += border & 1; /* make the border even */
184
5e7234c9
VS		 185 adjusted_mode->crtc_hdisplay = width;
186 adjusted_mode->crtc_hblank_start = width + border;
187 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width;
2dd24552 188
5e7234c9
VS		 189 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos;
190 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width;
2dd24552
JB		 191}
192
193static void
5e7234c9 194centre_vertically(struct drm_display_mode *adjusted_mode,
2dd24552
JB		 195 int height)
196{
197 u32 border, sync_pos, blank_width, sync_width;
198
199 /* keep the vsync and vblank widths constant */
5e7234c9
VS		 200 sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
201 blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
2dd24552
JB		 202 sync_pos = (blank_width - sync_width + 1) / 2;
203
aad941d5 204 border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
2dd24552 205
5e7234c9
VS		 206 adjusted_mode->crtc_vdisplay = height;
207 adjusted_mode->crtc_vblank_start = height + border;
208 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width;
2dd24552 209
5e7234c9
VS		 210 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos;
211 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width;
2dd24552
JB		 212}
213
214static inline u32 panel_fitter_scaling(u32 source, u32 target)
215{
216 /*
217 * Floating point operation is not supported. So the FACTOR
218 * is defined, which can avoid the floating point computation
219 * when calculating the panel ratio.
220 */
221#define ACCURACY 12
222#define FACTOR (1 << ACCURACY)
223 u32 ratio = source * FACTOR / target;
224 return (FACTOR * ratio + FACTOR/2) / FACTOR;
225}
226
5cec258b 227static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
SV		 228 u32 *pfit_control)
229{
7c5f93b0 230 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 231 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
SV		 232 pipe_config->pipe_src_h;
233 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 234 adjusted_mode->crtc_vdisplay;
9084e7d2
SV		 235
236 /* 965+ is easy, it does everything in hw */
237 if (scaled_width > scaled_height)
238 *pfit_control |= PFIT_ENABLE |
239 PFIT_SCALING_PILLAR;
240 else if (scaled_width < scaled_height)
241 *pfit_control |= PFIT_ENABLE |
242 PFIT_SCALING_LETTER;
aad941d5 243 else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w)
9084e7d2
SV		 244 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
245}
246
5cec258b 247static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
SV		 248 u32 *pfit_control, u32 *pfit_pgm_ratios,
249 u32 *border)
250{
2d112de7 251 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 252 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
SV		 253 pipe_config->pipe_src_h;
254 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 255 adjusted_mode->crtc_vdisplay;
9084e7d2
SV		 256 u32 bits;
257
258 /*
259 * For earlier chips we have to calculate the scaling
260 * ratio by hand and program it into the
261 * PFIT_PGM_RATIO register
262 */
263 if (scaled_width > scaled_height) { /* pillar */
264 centre_horizontally(adjusted_mode,
265 scaled_height /
266 pipe_config->pipe_src_h);
267
268 *border = LVDS_BORDER_ENABLE;
aad941d5 269 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) {
9084e7d2 270 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
aad941d5 271 adjusted_mode->crtc_vdisplay);
9084e7d2
SV		 272
273 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
274 bits << PFIT_VERT_SCALE_SHIFT);
275 *pfit_control |= (PFIT_ENABLE |
276 VERT_INTERP_BILINEAR |
277 HORIZ_INTERP_BILINEAR);
278 }
279 } else if (scaled_width < scaled_height) { /* letter */
280 centre_vertically(adjusted_mode,
281 scaled_width /
282 pipe_config->pipe_src_w);
283
284 *border = LVDS_BORDER_ENABLE;
aad941d5 285 if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
9084e7d2 286 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
aad941d5 287 adjusted_mode->crtc_hdisplay);
9084e7d2
SV		 288
289 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
290 bits << PFIT_VERT_SCALE_SHIFT);
291 *pfit_control |= (PFIT_ENABLE |
292 VERT_INTERP_BILINEAR |
293 HORIZ_INTERP_BILINEAR);
294 }
295 } else {
296 /* Aspects match, Let hw scale both directions */
297 *pfit_control |= (PFIT_ENABLE |
298 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
299 VERT_INTERP_BILINEAR |
300 HORIZ_INTERP_BILINEAR);
301 }
302}
303
2dd24552 304void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 305 struct intel_crtc_state *pipe_config,
2dd24552
JB		 306 int fitting_mode)
307{
66478475 308 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2dd24552 309 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
7c5f93b0 310 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2dd24552
JB		 311
312 /* Native modes don't need fitting */
aad941d5
VS		 313 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
314 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
2dd24552
JB		 315 goto out;
316
317 switch (fitting_mode) {
318 case DRM_MODE_SCALE_CENTER:
319 /*
320 * For centered modes, we have to calculate border widths &
321 * heights and modify the values programmed into the CRTC.
322 */
37327abd
VS		 323 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
324 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB		 325 border = LVDS_BORDER_ENABLE;
326 break;
327 case DRM_MODE_SCALE_ASPECT:
328 /* Scale but preserve the aspect ratio */
66478475 329 if (INTEL_GEN(dev_priv) >= 4)
9084e7d2
SV		 330 i965_scale_aspect(pipe_config, &pfit_control);
331 else
332 i9xx_scale_aspect(pipe_config, &pfit_control,
333 &pfit_pgm_ratios, &border);
2dd24552 334 break;
2dd24552
JB		 335 case DRM_MODE_SCALE_FULLSCREEN:
336 /*
337 * Full scaling, even if it changes the aspect ratio.
338 * Fortunately this is all done for us in hw.
339 */
aad941d5
VS		 340 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
341 pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
2dd24552 342 pfit_control |= PFIT_ENABLE;
66478475 343 if (INTEL_GEN(dev_priv) >= 4)
2dd24552
JB		 344 pfit_control |= PFIT_SCALING_AUTO;
345 else
346 pfit_control |= (VERT_AUTO_SCALE |
347 VERT_INTERP_BILINEAR |
348 HORIZ_AUTO_SCALE |
349 HORIZ_INTERP_BILINEAR);
350 }
351 break;
ab3e67f4
JB		 352 default:
353 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
354 return;
2dd24552
JB		 355 }
356
357 /* 965+ wants fuzzy fitting */
358 /* FIXME: handle multiple panels by failing gracefully */
66478475 359 if (INTEL_GEN(dev_priv) >= 4)
2dd24552
JB		 360 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
361 PFIT_FILTER_FUZZY);
362
363out:
364 if ((pfit_control & PFIT_ENABLE) == 0) {
365 pfit_control = 0;
366 pfit_pgm_ratios = 0;
367 }
368
6b89cdde 369 /* Make sure pre-965 set dither correctly for 18bpp panels. */
66478475 370 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
6b89cdde
SV		 371 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
372
2deefda5
SV		 373 pipe_config->gmch_pfit.control = pfit_control;
374 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 375 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB		 376}
377
6dda730e
JN		 378/**
379 * scale - scale values from one range to another
6dda730e 380 * @source_val: value in range [@source_min..@source_max]
e9a744fa
CW		 381 * @source_min: minimum legal value for @source_val
382 * @source_max: maximum legal value for @source_val
383 * @target_min: corresponding target value for @source_min
384 * @target_max: corresponding target value for @source_max
6dda730e
JN		 385 *
386 * Return @source_val in range [@source_min..@source_max] scaled to range
387 * [@target_min..@target_max].
388 */
fd620bf9
JN		 389static u32 scale(u32 source_val,
390 u32 source_min, u32 source_max,
391 u32 target_min, u32 target_max)
6dda730e 392{
fd620bf9 393 u64 target_val;
6dda730e
JN		 394
395 WARN_ON(source_min > source_max);
396 WARN_ON(target_min > target_max);
397
398 /* defensive */
399 source_val = clamp(source_val, source_min, source_max);
400
401 /* avoid overflows */
5af4ce7d
CW		 402 target_val = mul_u32_u32(source_val - source_min,
403 target_max - target_min);
404 target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min);
6dda730e
JN		 405 target_val += target_min;
406
407 return target_val;
408}
409
410/* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */
411static inline u32 scale_user_to_hw(struct intel_connector *connector,
412 u32 user_level, u32 user_max)
413{
414 struct intel_panel *panel = &connector->panel;
415
416 return scale(user_level, 0, user_max,
417 panel->backlight.min, panel->backlight.max);
418}
419
420/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result
421 * to [hw_min..hw_max]. */
422static inline u32 clamp_user_to_hw(struct intel_connector *connector,
423 u32 user_level, u32 user_max)
424{
425 struct intel_panel *panel = &connector->panel;
426 u32 hw_level;
427
428 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max);
429 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max);
430
431 return hw_level;
432}
433
434/* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */
435static inline u32 scale_hw_to_user(struct intel_connector *connector,
436 u32 hw_level, u32 user_max)
437{
438 struct intel_panel *panel = &connector->panel;
439
440 return scale(hw_level, panel->backlight.min, panel->backlight.max,
441 0, user_max);
442}
443
7bd688cd
JN		 444static u32 intel_panel_compute_brightness(struct intel_connector *connector,
445 u32 val)
7bd90909 446{
e6cb3727 447 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
f91c15e0
JN		 448 struct intel_panel *panel = &connector->panel;
449
450 WARN_ON(panel->backlight.max == 0);
4dca20ef 451
4f044a88 452 if (i915_modparams.invert_brightness < 0)
4dca20ef
CE		 453 return val;
454
4f044a88 455 if (i915_modparams.invert_brightness > 0 ||
d6540632 456 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
e9d7486e 457 return panel->backlight.max - val + panel->backlight.min;
d6540632 458 }
7bd90909
CE		 459
460 return val;
461}
462
437b15b8 463static u32 lpt_get_backlight(struct intel_connector *connector)
0b0b053a 464{
e6cb3727 465 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0b0b053a 466
96ab4c70
SV		 467 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
468}
07bf139b 469
7bd688cd 470static u32 pch_get_backlight(struct intel_connector *connector)
a9573556 471{
e6cb3727 472 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8ba2d185 473
7bd688cd
JN		 474 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
475}
a9573556 476
7bd688cd
JN		 477static u32 i9xx_get_backlight(struct intel_connector *connector)
478{
e6cb3727 479 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
636baebf 480 struct intel_panel *panel = &connector->panel;
7bd688cd 481 u32 val;
07bf139b 482
7bd688cd 483 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
c56b89f1 484 if (INTEL_GEN(dev_priv) < 4)
7bd688cd 485 val >>= 1;
ba3820ad 486
636baebf 487 if (panel->backlight.combination_mode) {
7bd688cd 488 u8 lbpc;
ba3820ad 489
91c8a326 490 pci_read_config_byte(dev_priv->drm.pdev, LBPC, &lbpc);
7bd688cd 491 val *= lbpc;
a9573556
CW		 492 }
493
7bd688cd
JN		 494 return val;
495}
496
e6cb3727 497static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe)
7bd688cd 498{
23ec0a88
VS		 499 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
500 return 0;
501
7bd688cd
JN		 502 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
503}
504
505static u32 vlv_get_backlight(struct intel_connector *connector)
506{
e6cb3727 507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
046c9bca 508 enum pipe pipe = intel_connector_get_pipe(connector);
7bd688cd 509
e6cb3727 510 return _vlv_get_backlight(dev_priv, pipe);
7bd688cd
JN		 511}
512
0fb890c0
VK		 513static u32 bxt_get_backlight(struct intel_connector *connector)
514{
e6cb3727 515 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52 516 struct intel_panel *panel = &connector->panel;
0fb890c0 517
022e4e52 518 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
0fb890c0
VK		 519}
520
b029e66f
SK		 521static u32 pwm_get_backlight(struct intel_connector *connector)
522{
523 struct intel_panel *panel = &connector->panel;
524 int duty_ns;
525
526 duty_ns = pwm_get_duty_cycle(panel->backlight.pwm);
527 return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS);
528}
529
7d025e08 530static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level)
f8e10062 531{
7d025e08 532 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 533 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 534
f8e10062
BW		 535 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
536 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
537}
538
7d025e08 539static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level)
a9573556 540{
7d025e08 541 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 542 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd
JN		 543 u32 tmp;
544
545 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
546 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
a9573556
CW		 547}
548
7d025e08 549static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level)
a9573556 550{
7d025e08 551 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 552 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
f91c15e0 553 struct intel_panel *panel = &connector->panel;
b329b328 554 u32 tmp, mask;
ba3820ad 555
f91c15e0
JN		 556 WARN_ON(panel->backlight.max == 0);
557
636baebf 558 if (panel->backlight.combination_mode) {
ba3820ad
TI		 559 u8 lbpc;
560
f91c15e0 561 lbpc = level * 0xfe / panel->backlight.max + 1;
ba3820ad 562 level /= lbpc;
91c8a326 563 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc);
ba3820ad
TI		 564 }
565
cf819eff 566 if (IS_GEN(dev_priv, 4)) {
b329b328
JN		 567 mask = BACKLIGHT_DUTY_CYCLE_MASK;
568 } else {
a9573556 569 level <<= 1;
b329b328
JN		 570 mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
571 }
7bd688cd 572
b329b328 573 tmp = I915_READ(BLC_PWM_CTL) & ~mask;
7bd688cd
JN		 574 I915_WRITE(BLC_PWM_CTL, tmp | level);
575}
576
7d025e08 577static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level)
7bd688cd 578{
7d025e08 579 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 580 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 581 enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;
7bd688cd
JN		 582 u32 tmp;
583
584 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
585 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
586}
587
7d025e08 588static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level)
0fb890c0 589{
7d025e08 590 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 591 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52 592 struct intel_panel *panel = &connector->panel;
0fb890c0 593
022e4e52 594 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
0fb890c0
VK		 595}
596
7d025e08 597static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level)
b029e66f 598{
7d025e08 599 struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel;
b029e66f
SK		 600 int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100);
601
602 pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS);
603}
604
7bd688cd 605static void
7d025e08 606intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, u32 level)
7bd688cd 607{
7d025e08 608 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5507faeb 609 struct intel_panel *panel = &connector->panel;
7bd688cd
JN		 610
611 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
612
613 level = intel_panel_compute_brightness(connector, level);
7d025e08 614 panel->backlight.set(conn_state, level);
a9573556 615}
47356eb6 616
6dda730e
JN		 617/* set backlight brightness to level in range [0..max], assuming hw min is
618 * respected.
619 */
90d7cd24 620void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
6dda730e
JN		 621 u32 user_level, u32 user_max)
622{
90d7cd24 623 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 624 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6dda730e 625 struct intel_panel *panel = &connector->panel;
6dda730e 626 u32 hw_level;
6dda730e 627
260d8f98 628 /*
90d7cd24 629 * Lack of crtc may occur during driver init because
260d8f98
VS		 630 * connection_mutex isn't held across the entire backlight
631 * setup + modeset readout, and the BIOS can issue the
632 * requests at any time.
633 */
90d7cd24 634 if (!panel->backlight.present || !conn_state->crtc)
6dda730e
JN		 635 return;
636
07f11d49 637 mutex_lock(&dev_priv->backlight_lock);
6dda730e
JN		 638
639 WARN_ON(panel->backlight.max == 0);
640
641 hw_level = clamp_user_to_hw(connector, user_level, user_max);
642 panel->backlight.level = hw_level;
47356eb6 643
58c68779 644 if (panel->backlight.device)
6dda730e
JN		 645 panel->backlight.device->props.brightness =
646 scale_hw_to_user(connector,
647 panel->backlight.level,
648 panel->backlight.device->props.max_brightness);
b6b3ba5b 649
58c68779 650 if (panel->backlight.enabled)
7d025e08 651 intel_panel_actually_set_backlight(conn_state, hw_level);
f91c15e0 652
07f11d49 653 mutex_unlock(&dev_priv->backlight_lock);
f52c619a
TI		 654}
655
7d025e08 656static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state)
437b15b8 657{
7d025e08 658 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 659 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
437b15b8
JN		 660 u32 tmp;
661
7d025e08 662 intel_panel_actually_set_backlight(old_conn_state, 0);
437b15b8 663
6675bce2
JN		 664 /*
665 * Although we don't support or enable CPU PWM with LPT/SPT based
666 * systems, it may have been enabled prior to loading the
667 * driver. Disable to avoid warnings on LCPLL disable.
668 *
669 * This needs rework if we need to add support for CPU PWM on PCH split
670 * platforms.
671 */
672 tmp = I915_READ(BLC_PWM_CPU_CTL2);
673 if (tmp & BLM_PWM_ENABLE) {
674 DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");
675 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
676 }
677
437b15b8
JN		 678 tmp = I915_READ(BLC_PWM_PCH_CTL1);
679 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
680}
681
7d025e08 682static void pch_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 683{
7d025e08 684 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 685 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd
JN		 686 u32 tmp;
687
7d025e08 688 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 689
7bd688cd
JN		 690 tmp = I915_READ(BLC_PWM_CPU_CTL2);
691 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
692
693 tmp = I915_READ(BLC_PWM_PCH_CTL1);
694 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
695}
696
7d025e08 697static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state)
3bd712e5 698{
7d025e08 699 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5
JN		 700}
701
7d025e08 702static void i965_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 703{
7d025e08 704 struct drm_i915_private *dev_priv = to_i915(old_conn_state->connector->dev);
7bd688cd
JN		 705 u32 tmp;
706
7d025e08 707 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 708
7bd688cd
JN		 709 tmp = I915_READ(BLC_PWM_CTL2);
710 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
711}
712
7d025e08 713static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 714{
7d025e08 715 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 716 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 717 enum pipe pipe = to_intel_crtc(old_conn_state->crtc)->pipe;
7bd688cd
JN		 718 u32 tmp;
719
7d025e08 720 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 721
7bd688cd
JN		 722 tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
723 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);
724}
725
7d025e08 726static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state)
0fb890c0 727{
7d025e08 728 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 729 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52
SK		 730 struct intel_panel *panel = &connector->panel;
731 u32 tmp, val;
0fb890c0 732
7d025e08 733 intel_panel_actually_set_backlight(old_conn_state, 0);
0fb890c0 734
022e4e52
SK		 735 tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
736 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
737 tmp & ~BXT_BLC_PWM_ENABLE);
738
739 if (panel->backlight.controller == 1) {
740 val = I915_READ(UTIL_PIN_CTL);
741 val &= ~UTIL_PIN_ENABLE;
742 I915_WRITE(UTIL_PIN_CTL, val);
743 }
0fb890c0
VK		 744}
745
7d025e08 746static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state)
4c9f7086 747{
7d025e08 748 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
4c9f7086
RV		 749 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
750 struct intel_panel *panel = &connector->panel;
751 u32 tmp;
752
7d025e08 753 intel_panel_actually_set_backlight(old_conn_state, 0);
4c9f7086
RV		 754
755 tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
756 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
757 tmp & ~BXT_BLC_PWM_ENABLE);
758}
759
7d025e08 760static void pwm_disable_backlight(const struct drm_connector_state *old_conn_state)
b029e66f 761{
7d025e08 762 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
b029e66f
SK		 763 struct intel_panel *panel = &connector->panel;
764
765 /* Disable the backlight */
328f75bb 766 intel_panel_actually_set_backlight(old_conn_state, 0);
b029e66f
SK		 767 usleep_range(2000, 3000);
768 pwm_disable(panel->backlight.pwm);
769}
770
b037d58f 771void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state)
f52c619a 772{
b037d58f 773 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 774 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
58c68779 775 struct intel_panel *panel = &connector->panel;
8ba2d185 776
260d8f98 777 if (!panel->backlight.present)
752aa88a
JB		 778 return;
779
3f577573 780 /*
5389e916 781 * Do not disable backlight on the vga_switcheroo path. When switching
3f577573
JN		 782 * away from i915, the other client may depend on i915 to handle the
783 * backlight. This will leave the backlight on unnecessarily when
784 * another client is not activated.
785 */
91c8a326 786 if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) {
3f577573
JN		 787 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
788 return;
789 }
790
07f11d49 791 mutex_lock(&dev_priv->backlight_lock);
47356eb6 792
ab656bb9
JN		 793 if (panel->backlight.device)
794 panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
58c68779 795 panel->backlight.enabled = false;
7d025e08 796 panel->backlight.disable(old_conn_state);
24ded204 797
07f11d49 798 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd 799}
24ded204 800
7d025e08
ML		 801static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
802 const struct drm_connector_state *conn_state)
96ab4c70 803{
7d025e08 804 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 805 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
96ab4c70 806 struct intel_panel *panel = &connector->panel;
e29aff05 807 u32 pch_ctl1, pch_ctl2, schicken;
96ab4c70
SV		 808
809 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
810 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
811 DRM_DEBUG_KMS("pch backlight already enabled\n");
812 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
813 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
814 }
24ded204 815
e29aff05
SL		 816 if (HAS_PCH_LPT(dev_priv)) {
817 schicken = I915_READ(SOUTH_CHICKEN2);
818 if (panel->backlight.alternate_pwm_increment)
819 schicken |= LPT_PWM_GRANULARITY;
820 else
821 schicken &= ~LPT_PWM_GRANULARITY;
822 I915_WRITE(SOUTH_CHICKEN2, schicken);
823 } else {
824 schicken = I915_READ(SOUTH_CHICKEN1);
825 if (panel->backlight.alternate_pwm_increment)
826 schicken |= SPT_PWM_GRANULARITY;
827 else
828 schicken &= ~SPT_PWM_GRANULARITY;
829 I915_WRITE(SOUTH_CHICKEN1, schicken);
830 }
831
96ab4c70
SV		 832 pch_ctl2 = panel->backlight.max << 16;
833 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
a4f32fc3 834
96ab4c70
SV		 835 pch_ctl1 = 0;
836 if (panel->backlight.active_low_pwm)
837 pch_ctl1 |= BLM_PCH_POLARITY;
8ba2d185 838
e6b2627c
JN		 839 /* After LPT, override is the default. */
840 if (HAS_PCH_LPT(dev_priv))
841 pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE;
96ab4c70
SV		 842
843 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
844 POSTING_READ(BLC_PWM_PCH_CTL1);
845 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
846
847 /* This won't stick until the above enable. */
7d025e08 848 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
47356eb6
CW		 849}
850
7d025e08
ML		 851static void pch_enable_backlight(const struct intel_crtc_state *crtc_state,
852 const struct drm_connector_state *conn_state)
7bd688cd 853{
7d025e08 854 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 855 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 856 struct intel_panel *panel = &connector->panel;
7d025e08 857 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
b35684b8 858 u32 cpu_ctl2, pch_ctl1, pch_ctl2;
7bd688cd 859
b35684b8
JN		 860 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
861 if (cpu_ctl2 & BLM_PWM_ENABLE) {
813008cd 862 DRM_DEBUG_KMS("cpu backlight already enabled\n");
b35684b8
JN		 863 cpu_ctl2 &= ~BLM_PWM_ENABLE;
864 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
865 }
7bd688cd 866
b35684b8
JN		 867 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
868 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
869 DRM_DEBUG_KMS("pch backlight already enabled\n");
870 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
871 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
872 }
7bd688cd
JN		 873
874 if (cpu_transcoder == TRANSCODER_EDP)
b35684b8 875 cpu_ctl2 = BLM_TRANSCODER_EDP;
7bd688cd 876 else
b35684b8
JN		 877 cpu_ctl2 = BLM_PIPE(cpu_transcoder);
878 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
7bd688cd 879 POSTING_READ(BLC_PWM_CPU_CTL2);
b35684b8 880 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);
3bd712e5 881
b35684b8 882 /* This won't stick until the above enable. */
7d025e08 883 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
b35684b8
JN		 884
885 pch_ctl2 = panel->backlight.max << 16;
886 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
887
b35684b8
JN		 888 pch_ctl1 = 0;
889 if (panel->backlight.active_low_pwm)
890 pch_ctl1 |= BLM_PCH_POLARITY;
96ab4c70 891
b35684b8
JN		 892 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
893 POSTING_READ(BLC_PWM_PCH_CTL1);
894 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
3bd712e5
JN		 895}
896
7d025e08
ML		 897static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
898 const struct drm_connector_state *conn_state)
3bd712e5 899{
7d025e08 900 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 901 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 902 struct intel_panel *panel = &connector->panel;
b35684b8
JN		 903 u32 ctl, freq;
904
905 ctl = I915_READ(BLC_PWM_CTL);
906 if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
813008cd 907 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 908 I915_WRITE(BLC_PWM_CTL, 0);
909 }
3bd712e5 910
b35684b8
JN		 911 freq = panel->backlight.max;
912 if (panel->backlight.combination_mode)
913 freq /= 0xff;
914
915 ctl = freq << 17;
b6ab66aa 916 if (panel->backlight.combination_mode)
b35684b8 917 ctl |= BLM_LEGACY_MODE;
e6cb3727 918 if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm)
b35684b8
JN		 919 ctl |= BLM_POLARITY_PNV;
920
921 I915_WRITE(BLC_PWM_CTL, ctl);
922 POSTING_READ(BLC_PWM_CTL);
923
924 /* XXX: combine this into above write? */
7d025e08 925 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
2059ac3b
JN		 926
927 /*
928 * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
929 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
930 * that has backlight.
931 */
cf819eff 932 if (IS_GEN(dev_priv, 2))
2059ac3b 933 I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
7bd688cd 934}
8ba2d185 935
7d025e08
ML		 936static void i965_enable_backlight(const struct intel_crtc_state *crtc_state,
937 const struct drm_connector_state *conn_state)
7bd688cd 938{
7d025e08 939 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 940 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 941 struct intel_panel *panel = &connector->panel;
7d025e08 942 enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;
b35684b8 943 u32 ctl, ctl2, freq;
7bd688cd 944
b35684b8
JN		 945 ctl2 = I915_READ(BLC_PWM_CTL2);
946 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 947 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 948 ctl2 &= ~BLM_PWM_ENABLE;
949 I915_WRITE(BLC_PWM_CTL2, ctl2);
950 }
7bd688cd 951
b35684b8
JN		 952 freq = panel->backlight.max;
953 if (panel->backlight.combination_mode)
954 freq /= 0xff;
7bd688cd 955
b35684b8
JN		 956 ctl = freq << 16;
957 I915_WRITE(BLC_PWM_CTL, ctl);
3bd712e5 958
b35684b8
JN		 959 ctl2 = BLM_PIPE(pipe);
960 if (panel->backlight.combination_mode)
961 ctl2 |= BLM_COMBINATION_MODE;
962 if (panel->backlight.active_low_pwm)
963 ctl2 |= BLM_POLARITY_I965;
964 I915_WRITE(BLC_PWM_CTL2, ctl2);
965 POSTING_READ(BLC_PWM_CTL2);
966 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
2e7eeeb5 967
7d025e08 968 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
7bd688cd
JN		 969}
970
7d025e08
ML		 971static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
972 const struct drm_connector_state *conn_state)
7bd688cd 973{
7d025e08 974 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 975 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 976 struct intel_panel *panel = &connector->panel;
7d025e08 977 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
b35684b8 978 u32 ctl, ctl2;
7bd688cd 979
b35684b8
JN		 980 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
981 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 982 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 983 ctl2 &= ~BLM_PWM_ENABLE;
984 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
985 }
7bd688cd 986
b35684b8
JN		 987 ctl = panel->backlight.max << 16;
988 I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl);
7bd688cd 989
b35684b8 990 /* XXX: combine this into above write? */
7d025e08 991 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
7bd688cd 992
b35684b8
JN		 993 ctl2 = 0;
994 if (panel->backlight.active_low_pwm)
995 ctl2 |= BLM_POLARITY_I965;
996 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
7bd688cd 997 POSTING_READ(VLV_BLC_PWM_CTL2(pipe));
b35684b8 998 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
47356eb6
CW		 999}
1000
7d025e08
ML		 1001static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
1002 const struct drm_connector_state *conn_state)
0fb890c0 1003{
7d025e08 1004 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 1005 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0fb890c0 1006 struct intel_panel *panel = &connector->panel;
7d025e08 1007 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
022e4e52
SK		 1008 u32 pwm_ctl, val;
1009
add03379 1010 /* Controller 1 uses the utility pin. */
022e4e52
SK		 1011 if (panel->backlight.controller == 1) {
1012 val = I915_READ(UTIL_PIN_CTL);
1013 if (val & UTIL_PIN_ENABLE) {
1014 DRM_DEBUG_KMS("util pin already enabled\n");
1015 val &= ~UTIL_PIN_ENABLE;
1016 I915_WRITE(UTIL_PIN_CTL, val);
1017 }
0fb890c0 1018
022e4e52
SK		 1019 val = 0;
1020 if (panel->backlight.util_pin_active_low)
1021 val |= UTIL_PIN_POLARITY;
1022 I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
1023 UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
1024 }
1025
1026 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
0fb890c0
VK		 1027 if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
1028 DRM_DEBUG_KMS("backlight already enabled\n");
1029 pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
022e4e52
SK		 1030 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1031 pwm_ctl);
0fb890c0
VK		 1032 }
1033
022e4e52
SK		 1034 I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
1035 panel->backlight.max);
0fb890c0 1036
7d025e08 1037 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
0fb890c0
VK		 1038
1039 pwm_ctl = 0;
1040 if (panel->backlight.active_low_pwm)
1041 pwm_ctl |= BXT_BLC_PWM_POLARITY;
1042
022e4e52
SK		 1043 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
1044 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1045 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1046 pwm_ctl | BXT_BLC_PWM_ENABLE);
0fb890c0
VK		 1047}
1048
7d025e08
ML		 1049static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state,
1050 const struct drm_connector_state *conn_state)
4c9f7086 1051{
7d025e08 1052 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4c9f7086
RV		 1053 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1054 struct intel_panel *panel = &connector->panel;
1055 u32 pwm_ctl;
1056
1057 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1058 if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
1059 DRM_DEBUG_KMS("backlight already enabled\n");
1060 pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
1061 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1062 pwm_ctl);
1063 }
1064
1065 I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
1066 panel->backlight.max);
1067
7d025e08 1068 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
4c9f7086
RV		 1069
1070 pwm_ctl = 0;
1071 if (panel->backlight.active_low_pwm)
1072 pwm_ctl |= BXT_BLC_PWM_POLARITY;
1073
1074 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
1075 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1076 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1077 pwm_ctl | BXT_BLC_PWM_ENABLE);
1078}
1079
7d025e08
ML		 1080static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
1081 const struct drm_connector_state *conn_state)
b029e66f 1082{
7d025e08 1083 struct intel_connector *connector = to_intel_connector(conn_state->connector);
b029e66f
SK		 1084 struct intel_panel *panel = &connector->panel;
1085
1086 pwm_enable(panel->backlight.pwm);
7d025e08 1087 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
b029e66f
SK		 1088}
1089
63a23d24
ML		 1090static void __intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1091 const struct drm_connector_state *conn_state)
47356eb6 1092{
b037d58f 1093 struct intel_connector *connector = to_intel_connector(conn_state->connector);
58c68779 1094 struct intel_panel *panel = &connector->panel;
47356eb6 1095
f91c15e0
JN		 1096 WARN_ON(panel->backlight.max == 0);
1097
13f3fbe8 1098 if (panel->backlight.level <= panel->backlight.min) {
f91c15e0 1099 panel->backlight.level = panel->backlight.max;
58c68779
JN		 1100 if (panel->backlight.device)
1101 panel->backlight.device->props.brightness =
6dda730e
JN		 1102 scale_hw_to_user(connector,
1103 panel->backlight.level,
1104 panel->backlight.device->props.max_brightness);
b6b3ba5b 1105 }
47356eb6 1106
7d025e08 1107 panel->backlight.enable(crtc_state, conn_state);
58c68779 1108 panel->backlight.enabled = true;
ab656bb9
JN		 1109 if (panel->backlight.device)
1110 panel->backlight.device->props.power = FB_BLANK_UNBLANK;
63a23d24
ML		 1111}
1112
1113void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1114 const struct drm_connector_state *conn_state)
1115{
1116 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1117 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1118 struct intel_panel *panel = &connector->panel;
1119 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
1120
1121 if (!panel->backlight.present)
1122 return;
1123
1124 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
1125
1126 mutex_lock(&dev_priv->backlight_lock);
1127
1128 __intel_panel_enable_backlight(crtc_state, conn_state);
8ba2d185 1129
07f11d49 1130 mutex_unlock(&dev_priv->backlight_lock);
47356eb6
CW		 1131}
1132
912e8b12 1133#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
fd94d53e
AB		 1134static u32 intel_panel_get_backlight(struct intel_connector *connector)
1135{
1136 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1137 struct intel_panel *panel = &connector->panel;
1138 u32 val = 0;
1139
1140 mutex_lock(&dev_priv->backlight_lock);
1141
1142 if (panel->backlight.enabled) {
1143 val = panel->backlight.get(connector);
1144 val = intel_panel_compute_brightness(connector, val);
1145 }
1146
1147 mutex_unlock(&dev_priv->backlight_lock);
1148
1149 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
1150 return val;
1151}
1152
1153/* set backlight brightness to level in range [0..max], scaling wrt hw min */
1154static void intel_panel_set_backlight(const struct drm_connector_state *conn_state,
1155 u32 user_level, u32 user_max)
1156{
1157 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1158 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1159 struct intel_panel *panel = &connector->panel;
1160 u32 hw_level;
1161
1162 if (!panel->backlight.present)
1163 return;
1164
1165 mutex_lock(&dev_priv->backlight_lock);
1166
1167 WARN_ON(panel->backlight.max == 0);
1168
1169 hw_level = scale_user_to_hw(connector, user_level, user_max);
1170 panel->backlight.level = hw_level;
1171
1172 if (panel->backlight.enabled)
1173 intel_panel_actually_set_backlight(conn_state, hw_level);
1174
1175 mutex_unlock(&dev_priv->backlight_lock);
1176}
1177
db31af1d 1178static int intel_backlight_device_update_status(struct backlight_device *bd)
aaa6fd2a 1179{
752aa88a 1180 struct intel_connector *connector = bl_get_data(bd);
ab656bb9 1181 struct intel_panel *panel = &connector->panel;
752aa88a
JB		 1182 struct drm_device *dev = connector->base.dev;
1183
51fd371b 1184 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
540b5d02
CW		 1185 DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
1186 bd->props.brightness, bd->props.max_brightness);
7d025e08 1187 intel_panel_set_backlight(connector->base.state, bd->props.brightness,
d6540632 1188 bd->props.max_brightness);
ab656bb9
JN		 1189
1190 /*
1191 * Allow flipping bl_power as a sub-state of enabled. Sadly the
1192 * backlight class device does not make it easy to to differentiate
1193 * between callbacks for brightness and bl_power, so our backlight_power
1194 * callback needs to take this into account.
1195 */
1196 if (panel->backlight.enabled) {
5507faeb 1197 if (panel->backlight.power) {
e6755fb7
JN		 1198 bool enable = bd->props.power == FB_BLANK_UNBLANK &&
1199 bd->props.brightness != 0;
5507faeb 1200 panel->backlight.power(connector, enable);
ab656bb9
JN		 1201 }
1202 } else {
1203 bd->props.power = FB_BLANK_POWERDOWN;
1204 }
1205
51fd371b 1206 drm_modeset_unlock(&dev->mode_config.connection_mutex);
aaa6fd2a
MG		 1207 return 0;
1208}
1209
db31af1d 1210static int intel_backlight_device_get_brightness(struct backlight_device *bd)
aaa6fd2a 1211{
752aa88a
JB		 1212 struct intel_connector *connector = bl_get_data(bd);
1213 struct drm_device *dev = connector->base.dev;
fac5e23e 1214 struct drm_i915_private *dev_priv = to_i915(dev);
2cb2cb5f 1215 intel_wakeref_t wakeref;
d4225a53 1216 int ret = 0;
752aa88a 1217
d4225a53
CW		 1218 with_intel_runtime_pm(dev_priv, wakeref) {
1219 u32 hw_level;
6dda730e 1220
d4225a53 1221 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
6dda730e 1222
d4225a53
CW		 1223 hw_level = intel_panel_get_backlight(connector);
1224 ret = scale_hw_to_user(connector,
1225 hw_level, bd->props.max_brightness);
1226
1227 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1228 }
752aa88a 1229
7bd688cd 1230 return ret;
aaa6fd2a
MG		 1231}
1232
db31af1d
JN		 1233static const struct backlight_ops intel_backlight_device_ops = {
1234 .update_status = intel_backlight_device_update_status,
1235 .get_brightness = intel_backlight_device_get_brightness,
aaa6fd2a
MG		 1236};
1237
1ebaa0b9 1238int intel_backlight_device_register(struct intel_connector *connector)
aaa6fd2a 1239{
58c68779 1240 struct intel_panel *panel = &connector->panel;
aaa6fd2a 1241 struct backlight_properties props;
aaa6fd2a 1242
58c68779 1243 if (WARN_ON(panel->backlight.device))
dc652f90
JN		 1244 return -ENODEV;
1245
0962c3c9
VS		 1246 if (!panel->backlight.present)
1247 return 0;
1248
6dda730e 1249 WARN_ON(panel->backlight.max == 0);
7bd688cd 1250
af437cfd 1251 memset(&props, 0, sizeof(props));
aaa6fd2a 1252 props.type = BACKLIGHT_RAW;
6dda730e
JN		 1253
1254 /*
1255 * Note: Everything should work even if the backlight device max
1256 * presented to the userspace is arbitrarily chosen.
1257 */
7bd688cd 1258 props.max_brightness = panel->backlight.max;
6dda730e
JN		 1259 props.brightness = scale_hw_to_user(connector,
1260 panel->backlight.level,
1261 props.max_brightness);
58c68779 1262
ab656bb9
JN		 1263 if (panel->backlight.enabled)
1264 props.power = FB_BLANK_UNBLANK;
1265 else
1266 props.power = FB_BLANK_POWERDOWN;
1267
58c68779
JN		 1268 /*
1269 * Note: using the same name independent of the connector prevents
1270 * registration of multiple backlight devices in the driver.
1271 */
1272 panel->backlight.device =
aaa6fd2a 1273 backlight_device_register("intel_backlight",
db31af1d
JN		 1274 connector->base.kdev,
1275 connector,
1276 &intel_backlight_device_ops, &props);
aaa6fd2a 1277
58c68779 1278 if (IS_ERR(panel->backlight.device)) {
aaa6fd2a 1279 DRM_ERROR("Failed to register backlight: %ld\n",
58c68779
JN		 1280 PTR_ERR(panel->backlight.device));
1281 panel->backlight.device = NULL;
aaa6fd2a
MG		 1282 return -ENODEV;
1283 }
0962c3c9
VS		 1284
1285 DRM_DEBUG_KMS("Connector %s backlight sysfs interface registered\n",
1286 connector->base.name);
1287
aaa6fd2a
MG		 1288 return 0;
1289}
1290
e63d87c0 1291void intel_backlight_device_unregister(struct intel_connector *connector)
aaa6fd2a 1292{
58c68779
JN		 1293 struct intel_panel *panel = &connector->panel;
1294
1295 if (panel->backlight.device) {
1296 backlight_device_unregister(panel->backlight.device);
1297 panel->backlight.device = NULL;
dc652f90 1298 }
aaa6fd2a 1299}
db31af1d
JN		 1300#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1301
4c9f7086
RV		 1302/*
1303 * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
1304 * PWM increment = 1
1305 */
1306static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1307{
1308 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1309
1310 return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
1311}
1312
2dd6982e
JN		 1313/*
1314 * BXT: PWM clock frequency = 19.2 MHz.
1315 */
1316static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1317{
37f2248e 1318 return DIV_ROUND_CLOSEST(KHz(19200), pwm_freq_hz);
2dd6982e
JN		 1319}
1320
f91c15e0 1321/*
aa17cdb4
JN		 1322 * SPT: This value represents the period of the PWM stream in clock periods
1323 * multiplied by 16 (default increment) or 128 (alternate increment selected in
1324 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1325 */
1326static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1327{
32b421e7 1328 struct intel_panel *panel = &connector->panel;
e7dc33f3 1329 u32 mul;
aa17cdb4 1330
32b421e7 1331 if (panel->backlight.alternate_pwm_increment)
aa17cdb4
JN		 1332 mul = 128;
1333 else
1334 mul = 16;
1335
37f2248e 1336 return DIV_ROUND_CLOSEST(MHz(24), pwm_freq_hz * mul);
aa17cdb4
JN		 1337}
1338
1339/*
1340 * LPT: This value represents the period of the PWM stream in clock periods
1341 * multiplied by 128 (default increment) or 16 (alternate increment, selected in
1342 * LPT SOUTH_CHICKEN2 register bit 5).
1343 */
1344static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1345{
e6cb3727 1346 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
32b421e7 1347 struct intel_panel *panel = &connector->panel;
aa17cdb4
JN		 1348 u32 mul, clock;
1349
32b421e7 1350 if (panel->backlight.alternate_pwm_increment)
aa17cdb4
JN		 1351 mul = 16;
1352 else
1353 mul = 128;
1354
56f5f700 1355 if (HAS_PCH_LPT_H(dev_priv))
aa17cdb4
JN		 1356 clock = MHz(135); /* LPT:H */
1357 else
1358 clock = MHz(24); /* LPT:LP */
1359
37f2248e 1360 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
aa17cdb4
JN		 1361}
1362
1363/*
1364 * ILK/SNB/IVB: This value represents the period of the PWM stream in PCH
1365 * display raw clocks multiplied by 128.
1366 */
1367static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1368{
e7dc33f3 1369 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
aa17cdb4 1370
37f2248e 1371 return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128);
aa17cdb4
JN		 1372}
1373
1374/*
1375 * Gen2: This field determines the number of time base events (display core
1376 * clock frequency/32) in total for a complete cycle of modulated backlight
1377 * control.
f91c15e0 1378 *
aa17cdb4
JN		 1379 * Gen3: A time base event equals the display core clock ([DevPNV] HRAW clock)
1380 * divided by 32.
1381 */
1382static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1383{
e7dc33f3 1384 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
aa17cdb4
JN		 1385 int clock;
1386
e7dc33f3
VS		 1387 if (IS_PINEVIEW(dev_priv))
1388 clock = KHz(dev_priv->rawclk_freq);
aa17cdb4 1389 else
49cd97a3 1390 clock = KHz(dev_priv->cdclk.hw.cdclk);
aa17cdb4 1391
37f2248e 1392 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
aa17cdb4
JN		 1393}
1394
1395/*
1396 * Gen4: This value represents the period of the PWM stream in display core
83d83392
VS		 1397 * clocks ([DevCTG] HRAW clocks) multiplied by 128.
1398 *
aa17cdb4
JN		 1399 */
1400static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1401{
3bed7f4d 1402 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
83d83392
VS		 1403 int clock;
1404
1405 if (IS_G4X(dev_priv))
e7dc33f3 1406 clock = KHz(dev_priv->rawclk_freq);
83d83392 1407 else
49cd97a3 1408 clock = KHz(dev_priv->cdclk.hw.cdclk);
aa17cdb4 1409
37f2248e 1410 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
aa17cdb4
JN		 1411}
1412
1413/*
1414 * VLV: This value represents the period of the PWM stream in display core
1415 * clocks ([DevCTG] 200MHz HRAW clocks) multiplied by 128 or 25MHz S0IX clocks
1416 * multiplied by 16. CHV uses a 19.2MHz S0IX clock.
1417 */
1418static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1419{
e7dc33f3
VS		 1420 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1421 int mul, clock;
aa17cdb4
JN		 1422
1423 if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
e7dc33f3
VS		 1424 if (IS_CHERRYVIEW(dev_priv))
1425 clock = KHz(19200);
aa17cdb4 1426 else
e7dc33f3
VS		 1427 clock = MHz(25);
1428 mul = 16;
aa17cdb4 1429 } else {
e7dc33f3
VS		 1430 clock = KHz(dev_priv->rawclk_freq);
1431 mul = 128;
aa17cdb4 1432 }
e7dc33f3 1433
37f2248e 1434 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
aa17cdb4
JN		 1435}
1436
1437static u32 get_backlight_max_vbt(struct intel_connector *connector)
1438{
e6cb3727 1439 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5507faeb 1440 struct intel_panel *panel = &connector->panel;
aa17cdb4
JN		 1441 u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
1442 u32 pwm;
1443
5075222b
JN		 1444 if (!panel->backlight.hz_to_pwm) {
1445 DRM_DEBUG_KMS("backlight frequency conversion not supported\n");
aa17cdb4
JN		 1446 return 0;
1447 }
1448
5075222b
JN		 1449 if (pwm_freq_hz) {
1450 DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n",
1451 pwm_freq_hz);
1452 } else {
1453 pwm_freq_hz = 200;
1454 DRM_DEBUG_KMS("default backlight frequency %u Hz\n",
1455 pwm_freq_hz);
aa17cdb4
JN		 1456 }
1457
5507faeb 1458 pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz);
aa17cdb4
JN		 1459 if (!pwm) {
1460 DRM_DEBUG_KMS("backlight frequency conversion failed\n");
1461 return 0;
1462 }
1463
aa17cdb4
JN		 1464 return pwm;
1465}
1466
1467/*
1468 * Note: The setup hooks can't assume pipe is set!
f91c15e0 1469 */
6dda730e
JN		 1470static u32 get_backlight_min_vbt(struct intel_connector *connector)
1471{
e6cb3727 1472 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6dda730e 1473 struct intel_panel *panel = &connector->panel;
e1c412e7 1474 int min;
6dda730e
JN		 1475
1476 WARN_ON(panel->backlight.max == 0);
1477
e1c412e7
JN		 1478 /*
1479 * XXX: If the vbt value is 255, it makes min equal to max, which leads
1480 * to problems. There are such machines out there. Either our
1481 * interpretation is wrong or the vbt has bogus data. Or both. Safeguard
1482 * against this by letting the minimum be at most (arbitrarily chosen)
1483 * 25% of the max.
1484 */
1485 min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
1486 if (min != dev_priv->vbt.backlight.min_brightness) {
1487 DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
1488 dev_priv->vbt.backlight.min_brightness, min);
1489 }
1490
6dda730e 1491 /* vbt value is a coefficient in range [0..255] */
e1c412e7 1492 return scale(min, 0, 255, 0, panel->backlight.max);
6dda730e
JN		 1493}
1494
437b15b8 1495static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused)
aaa6fd2a 1496{
e6cb3727 1497 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
96ab4c70 1498 struct intel_panel *panel = &connector->panel;
5b1ec9ac
ML		 1499 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
1500 bool alt, cpu_mode;
32b421e7
JN		 1501
1502 if (HAS_PCH_LPT(dev_priv))
1503 alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
1504 else
1505 alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
1506 panel->backlight.alternate_pwm_increment = alt;
96ab4c70
SV		 1507
1508 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1509 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1510
1511 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1512 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4 1513
5b1ec9ac
ML		 1514 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
1515
aa17cdb4
JN		 1516 if (!panel->backlight.max)
1517 panel->backlight.max = get_backlight_max_vbt(connector);
1518
96ab4c70
SV		 1519 if (!panel->backlight.max)
1520 return -ENODEV;
1521
6dda730e
JN		 1522 panel->backlight.min = get_backlight_min_vbt(connector);
1523
5b1ec9ac
ML		 1524 panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
1525
1526 cpu_mode = panel->backlight.enabled && HAS_PCH_LPT(dev_priv) &&
1527 !(pch_ctl1 & BLM_PCH_OVERRIDE_ENABLE) &&
1528 (cpu_ctl2 & BLM_PWM_ENABLE);
1529 if (cpu_mode)
1530 val = pch_get_backlight(connector);
1531 else
1532 val = lpt_get_backlight(connector);
46e69f39
JN		 1533 val = intel_panel_compute_brightness(connector, val);
1534 panel->backlight.level = clamp(val, panel->backlight.min,
1535 panel->backlight.max);
96ab4c70 1536
5b1ec9ac
ML		 1537 if (cpu_mode) {
1538 DRM_DEBUG_KMS("CPU backlight register was enabled, switching to PCH override\n");
1539
1540 /* Write converted CPU PWM value to PCH override register */
1541 lpt_set_backlight(connector->base.state, panel->backlight.level);
1542 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
1543
1544 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 & ~BLM_PWM_ENABLE);
1545 }
96ab4c70
SV		 1546
1547 return 0;
1548}
1549
6517d273 1550static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1551{
e6cb3727 1552 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1553 struct intel_panel *panel = &connector->panel;
636baebf 1554 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
7bd688cd 1555
636baebf
JN		 1556 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1557 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1558
1559 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1560 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4
JN		 1561
1562 if (!panel->backlight.max)
1563 panel->backlight.max = get_backlight_max_vbt(connector);
1564
7bd688cd
JN		 1565 if (!panel->backlight.max)
1566 return -ENODEV;
1567
6dda730e
JN		 1568 panel->backlight.min = get_backlight_min_vbt(connector);
1569
7bd688cd 1570 val = pch_get_backlight(connector);
46e69f39
JN		 1571 val = intel_panel_compute_brightness(connector, val);
1572 panel->backlight.level = clamp(val, panel->backlight.min,
1573 panel->backlight.max);
7bd688cd 1574
636baebf
JN		 1575 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
1576 panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) &&
46e69f39 1577 (pch_ctl1 & BLM_PCH_PWM_ENABLE);
636baebf 1578
7bd688cd
JN		 1579 return 0;
1580}
1581
6517d273 1582static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1583{
e6cb3727 1584 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1585 struct intel_panel *panel = &connector->panel;
636baebf
JN		 1586 u32 ctl, val;
1587
1588 ctl = I915_READ(BLC_PWM_CTL);
1589
cf819eff 1590 if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
636baebf
JN		 1591 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
1592
e6cb3727 1593 if (IS_PINEVIEW(dev_priv))
636baebf
JN		 1594 panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV;
1595
1596 panel->backlight.max = ctl >> 17;
aa17cdb4
JN		 1597
1598 if (!panel->backlight.max) {
1599 panel->backlight.max = get_backlight_max_vbt(connector);
1600 panel->backlight.max >>= 1;
1601 }
7bd688cd 1602
7bd688cd
JN		 1603 if (!panel->backlight.max)
1604 return -ENODEV;
1605
aa17cdb4
JN		 1606 if (panel->backlight.combination_mode)
1607 panel->backlight.max *= 0xff;
1608
6dda730e
JN		 1609 panel->backlight.min = get_backlight_min_vbt(connector);
1610
7bd688cd 1611 val = i9xx_get_backlight(connector);
46e69f39
JN		 1612 val = intel_panel_compute_brightness(connector, val);
1613 panel->backlight.level = clamp(val, panel->backlight.min,
1614 panel->backlight.max);
7bd688cd 1615
46e69f39 1616 panel->backlight.enabled = val != 0;
636baebf 1617
7bd688cd
JN		 1618 return 0;
1619}
1620
6517d273 1621static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1622{
e6cb3727 1623 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1624 struct intel_panel *panel = &connector->panel;
636baebf
JN		 1625 u32 ctl, ctl2, val;
1626
1627 ctl2 = I915_READ(BLC_PWM_CTL2);
1628 panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE;
1629 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1630
1631 ctl = I915_READ(BLC_PWM_CTL);
1632 panel->backlight.max = ctl >> 16;
aa17cdb4
JN		 1633
1634 if (!panel->backlight.max)
1635 panel->backlight.max = get_backlight_max_vbt(connector);
7bd688cd 1636
7bd688cd
JN		 1637 if (!panel->backlight.max)
1638 return -ENODEV;
1639
aa17cdb4
JN		 1640 if (panel->backlight.combination_mode)
1641 panel->backlight.max *= 0xff;
1642
6dda730e
JN		 1643 panel->backlight.min = get_backlight_min_vbt(connector);
1644
7bd688cd 1645 val = i9xx_get_backlight(connector);
46e69f39
JN		 1646 val = intel_panel_compute_brightness(connector, val);
1647 panel->backlight.level = clamp(val, panel->backlight.min,
1648 panel->backlight.max);
7bd688cd 1649
46e69f39 1650 panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE;
636baebf 1651
7bd688cd
JN		 1652 return 0;
1653}
1654
6517d273 1655static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe)
7bd688cd 1656{
e6cb3727 1657 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1658 struct intel_panel *panel = &connector->panel;
636baebf 1659 u32 ctl, ctl2, val;
7bd688cd 1660
6517d273
VS		 1661 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
1662 return -ENODEV;
1663
1664 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
636baebf
JN		 1665 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1666
6517d273 1667 ctl = I915_READ(VLV_BLC_PWM_CTL(pipe));
636baebf 1668 panel->backlight.max = ctl >> 16;
aa17cdb4
JN		 1669
1670 if (!panel->backlight.max)
1671 panel->backlight.max = get_backlight_max_vbt(connector);
1672
7bd688cd
JN		 1673 if (!panel->backlight.max)
1674 return -ENODEV;
1675
6dda730e
JN		 1676 panel->backlight.min = get_backlight_min_vbt(connector);
1677
e6cb3727 1678 val = _vlv_get_backlight(dev_priv, pipe);
46e69f39
JN		 1679 val = intel_panel_compute_brightness(connector, val);
1680 panel->backlight.level = clamp(val, panel->backlight.min,
1681 panel->backlight.max);
7bd688cd 1682
46e69f39 1683 panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE;
636baebf 1684
7bd688cd
JN		 1685 return 0;
1686}
1687
0fb890c0
VK		 1688static int
1689bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
1690{
e6cb3727 1691 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0fb890c0
VK		 1692 struct intel_panel *panel = &connector->panel;
1693 u32 pwm_ctl, val;
1694
add03379 1695 panel->backlight.controller = dev_priv->vbt.backlight.controller;
0fb890c0 1696
022e4e52
SK		 1697 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1698
add03379 1699 /* Controller 1 uses the utility pin. */
022e4e52
SK		 1700 if (panel->backlight.controller == 1) {
1701 val = I915_READ(UTIL_PIN_CTL);
1702 panel->backlight.util_pin_active_low =
1703 val & UTIL_PIN_POLARITY;
1704 }
1705
1706 panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
1707 panel->backlight.max =
1708 I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
aa17cdb4
JN		 1709
1710 if (!panel->backlight.max)
1711 panel->backlight.max = get_backlight_max_vbt(connector);
1712
0fb890c0
VK		 1713 if (!panel->backlight.max)
1714 return -ENODEV;
1715
c3881128
LS		 1716 panel->backlight.min = get_backlight_min_vbt(connector);
1717
0fb890c0 1718 val = bxt_get_backlight(connector);
46e69f39
JN		 1719 val = intel_panel_compute_brightness(connector, val);
1720 panel->backlight.level = clamp(val, panel->backlight.min,
1721 panel->backlight.max);
0fb890c0 1722
46e69f39 1723 panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
0fb890c0
VK		 1724
1725 return 0;
1726}
1727
4c9f7086
RV		 1728static int
1729cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
1730{
1731 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1732 struct intel_panel *panel = &connector->panel;
1733 u32 pwm_ctl, val;
1734
1735 /*
ccf6e0d9
AS		 1736 * CNP has the BXT implementation of backlight, but with only one
1737 * controller. TODO: ICP has multiple controllers but we only use
1738 * controller 0 for now.
4c9f7086
RV		 1739 */
1740 panel->backlight.controller = 0;
1741
1742 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1743
1744 panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
1745 panel->backlight.max =
1746 I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
1747
1748 if (!panel->backlight.max)
1749 panel->backlight.max = get_backlight_max_vbt(connector);
1750
1751 if (!panel->backlight.max)
1752 return -ENODEV;
1753
f44e354f
LS		 1754 panel->backlight.min = get_backlight_min_vbt(connector);
1755
4c9f7086
RV		 1756 val = bxt_get_backlight(connector);
1757 val = intel_panel_compute_brightness(connector, val);
1758 panel->backlight.level = clamp(val, panel->backlight.min,
1759 panel->backlight.max);
1760
1761 panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
1762
1763 return 0;
1764}
1765
b029e66f
SK		 1766static int pwm_setup_backlight(struct intel_connector *connector,
1767 enum pipe pipe)
1768{
1769 struct drm_device *dev = connector->base.dev;
1770 struct intel_panel *panel = &connector->panel;
1771 int retval;
1772
1773 /* Get the PWM chip for backlight control */
1774 panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
1775 if (IS_ERR(panel->backlight.pwm)) {
1776 DRM_ERROR("Failed to own the pwm chip\n");
1777 panel->backlight.pwm = NULL;
1778 return -ENODEV;
1779 }
1780
2347aa7c
BB		 1781 /*
1782 * FIXME: pwm_apply_args() should be removed when switching to
1783 * the atomic PWM API.
1784 */
1785 pwm_apply_args(panel->backlight.pwm);
1786
b029e66f
SK		 1787 retval = pwm_config(panel->backlight.pwm, CRC_PMIC_PWM_PERIOD_NS,
1788 CRC_PMIC_PWM_PERIOD_NS);
1789 if (retval < 0) {
1790 DRM_ERROR("Failed to configure the pwm chip\n");
1791 pwm_put(panel->backlight.pwm);
1792 panel->backlight.pwm = NULL;
1793 return retval;
1794 }
1795
1796 panel->backlight.min = 0; /* 0% */
1797 panel->backlight.max = 100; /* 100% */
1798 panel->backlight.level = DIV_ROUND_UP(
1799 pwm_get_duty_cycle(panel->backlight.pwm) * 100,
1800 CRC_PMIC_PWM_PERIOD_NS);
1801 panel->backlight.enabled = panel->backlight.level != 0;
1802
1803 return 0;
1804}
1805
63a23d24
ML		 1806void intel_panel_update_backlight(struct intel_encoder *encoder,
1807 const struct intel_crtc_state *crtc_state,
1808 const struct drm_connector_state *conn_state)
1809{
1810 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1811 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1812 struct intel_panel *panel = &connector->panel;
1813
1814 if (!panel->backlight.present)
1815 return;
1816
1817 mutex_lock(&dev_priv->backlight_lock);
1818 if (!panel->backlight.enabled)
1819 __intel_panel_enable_backlight(crtc_state, conn_state);
1820
1821 mutex_unlock(&dev_priv->backlight_lock);
1822}
1823
6517d273 1824int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe)
aaa6fd2a 1825{
e6cb3727 1826 struct drm_i915_private *dev_priv = to_i915(connector->dev);
db31af1d 1827 struct intel_connector *intel_connector = to_intel_connector(connector);
58c68779 1828 struct intel_panel *panel = &intel_connector->panel;
7bd688cd 1829 int ret;
db31af1d 1830
c675949e 1831 if (!dev_priv->vbt.backlight.present) {
9c72cc6f
SD		 1832 if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
1833 DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
1834 } else {
1835 DRM_DEBUG_KMS("no backlight present per VBT\n");
1836 return 0;
1837 }
c675949e
JN		 1838 }
1839
5507faeb
JN		 1840 /* ensure intel_panel has been initialized first */
1841 if (WARN_ON(!panel->backlight.setup))
1842 return -ENODEV;
1843
7bd688cd 1844 /* set level and max in panel struct */
07f11d49 1845 mutex_lock(&dev_priv->backlight_lock);
5507faeb 1846 ret = panel->backlight.setup(intel_connector, pipe);
07f11d49 1847 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd
JN		 1848
1849 if (ret) {
1850 DRM_DEBUG_KMS("failed to setup backlight for connector %s\n",
c23cc417 1851 connector->name);
7bd688cd
JN		 1852 return ret;
1853 }
db31af1d 1854
c91c9f32
JN		 1855 panel->backlight.present = true;
1856
0962c3c9
VS		 1857 DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n",
1858 connector->name,
08c4d7fc 1859 enableddisabled(panel->backlight.enabled),
0962c3c9 1860 panel->backlight.level, panel->backlight.max);
c445b3b1 1861
aaa6fd2a
MG		 1862 return 0;
1863}
1864
19dfe572 1865static void intel_panel_destroy_backlight(struct intel_panel *panel)
aaa6fd2a 1866{
b029e66f
SK		 1867 /* dispose of the pwm */
1868 if (panel->backlight.pwm)
1869 pwm_put(panel->backlight.pwm);
1870
c91c9f32 1871 panel->backlight.present = false;
aaa6fd2a 1872}
1d508706 1873
7bd688cd 1874/* Set up chip specific backlight functions */
5507faeb
JN		 1875static void
1876intel_panel_init_backlight_funcs(struct intel_panel *panel)
7bd688cd 1877{
e6cb3727 1878 struct intel_connector *connector =
5507faeb 1879 container_of(panel, struct intel_connector, panel);
e6cb3727 1880 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1881
e7156c83
YA		 1882 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1883 intel_dp_aux_init_backlight_funcs(connector) == 0)
1884 return;
1885
90198355
JN		 1886 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
1887 intel_dsi_dcs_init_backlight_funcs(connector) == 0)
1888 return;
1889
cc3f90f0 1890 if (IS_GEN9_LP(dev_priv)) {
5507faeb
JN		 1891 panel->backlight.setup = bxt_setup_backlight;
1892 panel->backlight.enable = bxt_enable_backlight;
1893 panel->backlight.disable = bxt_disable_backlight;
1894 panel->backlight.set = bxt_set_backlight;
1895 panel->backlight.get = bxt_get_backlight;
2dd6982e 1896 panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
ccf6e0d9 1897 } else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {
4c9f7086
RV		 1898 panel->backlight.setup = cnp_setup_backlight;
1899 panel->backlight.enable = cnp_enable_backlight;
1900 panel->backlight.disable = cnp_disable_backlight;
1901 panel->backlight.set = bxt_set_backlight;
1902 panel->backlight.get = bxt_get_backlight;
1903 panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
22dea0be
RV		 1904 } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
1905 HAS_PCH_KBP(dev_priv)) {
5507faeb
JN		 1906 panel->backlight.setup = lpt_setup_backlight;
1907 panel->backlight.enable = lpt_enable_backlight;
1908 panel->backlight.disable = lpt_disable_backlight;
1909 panel->backlight.set = lpt_set_backlight;
1910 panel->backlight.get = lpt_get_backlight;
e6cb3727 1911 if (HAS_PCH_LPT(dev_priv))
5507faeb 1912 panel->backlight.hz_to_pwm = lpt_hz_to_pwm;
aa17cdb4 1913 else
5507faeb 1914 panel->backlight.hz_to_pwm = spt_hz_to_pwm;
e6cb3727 1915 } else if (HAS_PCH_SPLIT(dev_priv)) {
5507faeb
JN		 1916 panel->backlight.setup = pch_setup_backlight;
1917 panel->backlight.enable = pch_enable_backlight;
1918 panel->backlight.disable = pch_disable_backlight;
1919 panel->backlight.set = pch_set_backlight;
1920 panel->backlight.get = pch_get_backlight;
1921 panel->backlight.hz_to_pwm = pch_hz_to_pwm;
e6cb3727 1922 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
92c4565e 1923 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
5507faeb
JN		 1924 panel->backlight.setup = pwm_setup_backlight;
1925 panel->backlight.enable = pwm_enable_backlight;
1926 panel->backlight.disable = pwm_disable_backlight;
1927 panel->backlight.set = pwm_set_backlight;
1928 panel->backlight.get = pwm_get_backlight;
b029e66f 1929 } else {
5507faeb
JN		 1930 panel->backlight.setup = vlv_setup_backlight;
1931 panel->backlight.enable = vlv_enable_backlight;
1932 panel->backlight.disable = vlv_disable_backlight;
1933 panel->backlight.set = vlv_set_backlight;
1934 panel->backlight.get = vlv_get_backlight;
1935 panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
b029e66f 1936 }
cf819eff 1937 } else if (IS_GEN(dev_priv, 4)) {
5507faeb
JN		 1938 panel->backlight.setup = i965_setup_backlight;
1939 panel->backlight.enable = i965_enable_backlight;
1940 panel->backlight.disable = i965_disable_backlight;
1941 panel->backlight.set = i9xx_set_backlight;
1942 panel->backlight.get = i9xx_get_backlight;
1943 panel->backlight.hz_to_pwm = i965_hz_to_pwm;
7bd688cd 1944 } else {
5507faeb
JN		 1945 panel->backlight.setup = i9xx_setup_backlight;
1946 panel->backlight.enable = i9xx_enable_backlight;
1947 panel->backlight.disable = i9xx_disable_backlight;
1948 panel->backlight.set = i9xx_set_backlight;
1949 panel->backlight.get = i9xx_get_backlight;
1950 panel->backlight.hz_to_pwm = i9xx_hz_to_pwm;
7bd688cd
JN		 1951 }
1952}
1953
dd06f90e 1954int intel_panel_init(struct intel_panel *panel,
4b6ed685
VK		 1955 struct drm_display_mode *fixed_mode,
1956 struct drm_display_mode *downclock_mode)
1d508706 1957{
5507faeb
JN		 1958 intel_panel_init_backlight_funcs(panel);
1959
dd06f90e 1960 panel->fixed_mode = fixed_mode;
4b6ed685 1961 panel->downclock_mode = downclock_mode;
dd06f90e 1962
1d508706
JN		 1963 return 0;
1964}
1965
1966void intel_panel_fini(struct intel_panel *panel)
1967{
dd06f90e
JN		 1968 struct intel_connector *intel_connector =
1969 container_of(panel, struct intel_connector, panel);
1970
19dfe572
VS		 1971 intel_panel_destroy_backlight(panel);
1972
dd06f90e
JN		 1973 if (panel->fixed_mode)
1974 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
ec9ed197
VK		 1975
1976 if (panel->downclock_mode)
1977 drm_mode_destroy(intel_connector->base.dev,
1978 panel->downclock_mode);
1d508706 1979}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git