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696173b0 JN |
1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright © 2019 Intel Corporation | |
4 | */ | |
5 | ||
6 | #ifndef __INTEL_PM_H__ | |
7 | #define __INTEL_PM_H__ | |
8 | ||
9 | #include <linux/types.h> | |
10 | ||
11 | struct drm_atomic_state; | |
12 | struct drm_device; | |
13 | struct drm_i915_private; | |
14 | struct i915_request; | |
15 | struct intel_crtc; | |
16 | struct intel_crtc_state; | |
17 | struct intel_plane; | |
18 | struct skl_ddb_allocation; | |
19 | struct skl_ddb_entry; | |
20 | struct skl_pipe_wm; | |
21 | struct skl_wm_level; | |
22 | ||
23 | void intel_init_clock_gating(struct drm_i915_private *dev_priv); | |
24 | void intel_suspend_hw(struct drm_i915_private *dev_priv); | |
25 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv); | |
26 | void intel_update_watermarks(struct intel_crtc *crtc); | |
27 | void intel_init_pm(struct drm_i915_private *dev_priv); | |
28 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); | |
29 | void intel_pm_setup(struct drm_i915_private *dev_priv); | |
30 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
31 | void intel_gpu_ips_teardown(void); | |
32 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); | |
33 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); | |
34 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); | |
35 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); | |
36 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); | |
37 | void gen6_rps_busy(struct drm_i915_private *dev_priv); | |
38 | void gen6_rps_idle(struct drm_i915_private *dev_priv); | |
39 | void gen6_rps_boost(struct i915_request *rq); | |
40 | void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
41 | void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
42 | void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
43 | void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); | |
44 | void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, | |
45 | struct skl_ddb_entry *ddb_y, | |
46 | struct skl_ddb_entry *ddb_uv); | |
47 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, | |
48 | struct skl_ddb_allocation *ddb /* out */); | |
49 | void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, | |
50 | struct skl_pipe_wm *out); | |
51 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv); | |
52 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv); | |
53 | bool intel_can_enable_sagv(struct drm_atomic_state *state); | |
54 | int intel_enable_sagv(struct drm_i915_private *dev_priv); | |
55 | int intel_disable_sagv(struct drm_i915_private *dev_priv); | |
56 | bool skl_wm_level_equals(const struct skl_wm_level *l1, | |
57 | const struct skl_wm_level *l2); | |
58 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, | |
59 | const struct skl_ddb_entry *entries, | |
60 | int num_entries, int ignore_idx); | |
61 | void skl_write_plane_wm(struct intel_plane *plane, | |
62 | const struct intel_crtc_state *crtc_state); | |
63 | void skl_write_cursor_wm(struct intel_plane *plane, | |
64 | const struct intel_crtc_state *crtc_state); | |
65 | bool ilk_disable_lp_wm(struct drm_device *dev); | |
66 | int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, | |
67 | struct intel_crtc_state *cstate); | |
68 | void intel_init_ipc(struct drm_i915_private *dev_priv); | |
69 | void intel_enable_ipc(struct drm_i915_private *dev_priv); | |
70 | ||
71 | #endif /* __INTEL_PM_H__ */ |