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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
55367a27 JN |
24 | #include <drm/drm_atomic_helper.h> |
25 | ||
26 | #include "i915_drv.h" | |
27fec1f9 | 27 | #include "intel_dp.h" |
55367a27 JN |
28 | #include "intel_drv.h" |
29 | #include "intel_psr.h" | |
f9a79f9a | 30 | #include "intel_sprite.h" |
55367a27 | 31 | |
b2b89f55 RV |
32 | /** |
33 | * DOC: Panel Self Refresh (PSR/SRD) | |
34 | * | |
35 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
36 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
37 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
38 | * when system is idle but display is on as it eliminates display refresh | |
39 | * request to DDR memory completely as long as the frame buffer for that | |
40 | * display is unchanged. | |
41 | * | |
42 | * Panel Self Refresh must be supported by both Hardware (source) and | |
43 | * Panel (sink). | |
44 | * | |
45 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
46 | * to power down the link and memory controller. For DSI panels the same idea | |
47 | * is called "manual mode". | |
48 | * | |
49 | * The implementation uses the hardware-based PSR support which automatically | |
50 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
51 | * required DP aux message and could even retrain the link (that part isn't | |
52 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
53 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
54 | * part doesn't work too well, hence why the i915 PSR support uses the | |
55 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
56 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
57 | * get called by the frontbuffer tracking code. Note that because of locking | |
58 | * issues the self-refresh re-enable code is done from a work queue, which | |
59 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
60 | */ | |
61 | ||
c44301fc ML |
62 | static bool psr_global_enabled(u32 debug) |
63 | { | |
64 | switch (debug & I915_PSR_DEBUG_MODE_MASK) { | |
65 | case I915_PSR_DEBUG_DEFAULT: | |
66 | return i915_modparams.enable_psr; | |
67 | case I915_PSR_DEBUG_DISABLE: | |
68 | return false; | |
69 | default: | |
70 | return true; | |
71 | } | |
72 | } | |
73 | ||
2ac45bdd ML |
74 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
75 | const struct intel_crtc_state *crtc_state) | |
76 | { | |
8228c42f MN |
77 | /* Cannot enable DSC and PSR2 simultaneously */ |
78 | WARN_ON(crtc_state->dsc_params.compression_enable && | |
79 | crtc_state->has_psr2); | |
80 | ||
2ac45bdd | 81 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
235ca26f | 82 | case I915_PSR_DEBUG_DISABLE: |
2ac45bdd ML |
83 | case I915_PSR_DEBUG_FORCE_PSR1: |
84 | return false; | |
85 | default: | |
86 | return crtc_state->has_psr2; | |
87 | } | |
88 | } | |
89 | ||
c0871805 ID |
90 | static int edp_psr_shift(enum transcoder cpu_transcoder) |
91 | { | |
92 | switch (cpu_transcoder) { | |
93 | case TRANSCODER_A: | |
94 | return EDP_PSR_TRANSCODER_A_SHIFT; | |
95 | case TRANSCODER_B: | |
96 | return EDP_PSR_TRANSCODER_B_SHIFT; | |
97 | case TRANSCODER_C: | |
98 | return EDP_PSR_TRANSCODER_C_SHIFT; | |
99 | default: | |
100 | MISSING_CASE(cpu_transcoder); | |
101 | /* fallthrough */ | |
102 | case TRANSCODER_EDP: | |
103 | return EDP_PSR_TRANSCODER_EDP_SHIFT; | |
104 | } | |
105 | } | |
106 | ||
1aeb1b5f | 107 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) |
54fd3149 DP |
108 | { |
109 | u32 debug_mask, mask; | |
c0871805 ID |
110 | enum transcoder cpu_transcoder; |
111 | u32 transcoders = BIT(TRANSCODER_EDP); | |
54fd3149 | 112 | |
c0871805 ID |
113 | if (INTEL_GEN(dev_priv) >= 8) |
114 | transcoders |= BIT(TRANSCODER_A) | | |
115 | BIT(TRANSCODER_B) | | |
116 | BIT(TRANSCODER_C); | |
117 | ||
118 | debug_mask = 0; | |
119 | mask = 0; | |
120 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
121 | int shift = edp_psr_shift(cpu_transcoder); | |
122 | ||
123 | mask |= EDP_PSR_ERROR(shift); | |
124 | debug_mask |= EDP_PSR_POST_EXIT(shift) | | |
125 | EDP_PSR_PRE_ENTRY(shift); | |
54fd3149 DP |
126 | } |
127 | ||
1aeb1b5f | 128 | if (debug & I915_PSR_DEBUG_IRQ) |
54fd3149 DP |
129 | mask |= debug_mask; |
130 | ||
54fd3149 DP |
131 | I915_WRITE(EDP_PSR_IMR, ~mask); |
132 | } | |
133 | ||
bc18b4df JRS |
134 | static void psr_event_print(u32 val, bool psr2_enabled) |
135 | { | |
136 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
137 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
138 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
139 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
140 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
141 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
142 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
143 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
144 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
145 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
146 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
147 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
148 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
149 | if (val & PSR_EVENT_MEMORY_UP) | |
150 | DRM_DEBUG_KMS("\tMemory up\n"); | |
151 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
152 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
153 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
154 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
155 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
156 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
157 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
158 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
159 | if (val & PSR_EVENT_HDCP_ENABLE) | |
160 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
161 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
162 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
163 | if (val & PSR_EVENT_VBI_ENABLE) | |
164 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
165 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
166 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
167 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
168 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
169 | } | |
170 | ||
54fd3149 DP |
171 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
172 | { | |
173 | u32 transcoders = BIT(TRANSCODER_EDP); | |
174 | enum transcoder cpu_transcoder; | |
3f983e54 | 175 | ktime_t time_ns = ktime_get(); |
183b8e67 | 176 | u32 mask = 0; |
54fd3149 DP |
177 | |
178 | if (INTEL_GEN(dev_priv) >= 8) | |
179 | transcoders |= BIT(TRANSCODER_A) | | |
180 | BIT(TRANSCODER_B) | | |
181 | BIT(TRANSCODER_C); | |
182 | ||
183 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
c0871805 ID |
184 | int shift = edp_psr_shift(cpu_transcoder); |
185 | ||
183b8e67 JRS |
186 | if (psr_iir & EDP_PSR_ERROR(shift)) { |
187 | DRM_WARN("[transcoder %s] PSR aux error\n", | |
188 | transcoder_name(cpu_transcoder)); | |
189 | ||
190 | dev_priv->psr.irq_aux_error = true; | |
191 | ||
192 | /* | |
193 | * If this interruption is not masked it will keep | |
194 | * interrupting so fast that it prevents the scheduled | |
195 | * work to run. | |
196 | * Also after a PSR error, we don't want to arm PSR | |
197 | * again so we don't care about unmask the interruption | |
198 | * or unset irq_aux_error. | |
199 | */ | |
200 | mask |= EDP_PSR_ERROR(shift); | |
201 | } | |
54fd3149 | 202 | |
c0871805 | 203 | if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) { |
3f983e54 | 204 | dev_priv->psr.last_entry_attempt = time_ns; |
54fd3149 DP |
205 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", |
206 | transcoder_name(cpu_transcoder)); | |
3f983e54 | 207 | } |
54fd3149 | 208 | |
c0871805 | 209 | if (psr_iir & EDP_PSR_POST_EXIT(shift)) { |
3f983e54 | 210 | dev_priv->psr.last_exit = time_ns; |
54fd3149 DP |
211 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", |
212 | transcoder_name(cpu_transcoder)); | |
bc18b4df JRS |
213 | |
214 | if (INTEL_GEN(dev_priv) >= 9) { | |
215 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
216 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
217 | ||
218 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); | |
219 | psr_event_print(val, psr2_enabled); | |
220 | } | |
3f983e54 | 221 | } |
54fd3149 | 222 | } |
183b8e67 JRS |
223 | |
224 | if (mask) { | |
225 | mask |= I915_READ(EDP_PSR_IMR); | |
226 | I915_WRITE(EDP_PSR_IMR, mask); | |
227 | ||
228 | schedule_work(&dev_priv->psr.work); | |
229 | } | |
54fd3149 DP |
230 | } |
231 | ||
77fe36ff DP |
232 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
233 | { | |
739f3abd | 234 | u8 dprx = 0; |
77fe36ff DP |
235 | |
236 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
237 | &dprx) != 1) | |
238 | return false; | |
239 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
240 | } | |
241 | ||
242 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) | |
243 | { | |
739f3abd | 244 | u8 alpm_caps = 0; |
77fe36ff DP |
245 | |
246 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
247 | &alpm_caps) != 1) | |
248 | return false; | |
249 | return alpm_caps & DP_ALPM_CAP; | |
250 | } | |
251 | ||
26e5378d JRS |
252 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
253 | { | |
264ff016 | 254 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
255 | |
256 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
257 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
258 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
259 | else | |
264ff016 | 260 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
261 | return val; |
262 | } | |
263 | ||
8c0d2c29 JRS |
264 | static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) |
265 | { | |
266 | u16 val; | |
267 | ssize_t r; | |
268 | ||
269 | /* | |
270 | * Returning the default X granularity if granularity not required or | |
271 | * if DPCD read fails | |
272 | */ | |
273 | if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) | |
274 | return 4; | |
275 | ||
276 | r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); | |
277 | if (r != 2) | |
278 | DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n"); | |
279 | ||
280 | /* | |
281 | * Spec says that if the value read is 0 the default granularity should | |
282 | * be used instead. | |
283 | */ | |
284 | if (r != 2 || val == 0) | |
285 | val = 4; | |
286 | ||
287 | return val; | |
288 | } | |
289 | ||
77fe36ff DP |
290 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
291 | { | |
292 | struct drm_i915_private *dev_priv = | |
293 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
294 | ||
295 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, | |
296 | sizeof(intel_dp->psr_dpcd)); | |
297 | ||
8cf6da7e DP |
298 | if (!intel_dp->psr_dpcd[0]) |
299 | return; | |
8cf6da7e DP |
300 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
301 | intel_dp->psr_dpcd[0]); | |
84bb2916 | 302 | |
7c5c641a JRS |
303 | if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { |
304 | DRM_DEBUG_KMS("PSR support not currently available for this panel\n"); | |
305 | return; | |
306 | } | |
307 | ||
84bb2916 DP |
308 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
309 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
310 | return; | |
311 | } | |
7c5c641a | 312 | |
8cf6da7e | 313 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
314 | dev_priv->psr.sink_sync_latency = |
315 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 316 | |
c44301fc ML |
317 | WARN_ON(dev_priv->psr.dp); |
318 | dev_priv->psr.dp = intel_dp; | |
319 | ||
77fe36ff | 320 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 321 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
322 | bool y_req = intel_dp->psr_dpcd[1] & |
323 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
324 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
325 | ||
aee3bac0 JRS |
326 | /* |
327 | * All panels that supports PSR version 03h (PSR2 + | |
328 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
329 | * only sure that it is going to be used when required by the | |
330 | * panel. This way panel is capable to do selective update | |
331 | * without a aux frame sync. | |
332 | * | |
333 | * To support PSR version 02h and PSR version 03h without | |
334 | * Y-coordinate requirement panels we would need to enable | |
335 | * GTC first. | |
336 | */ | |
97c9de66 | 337 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
338 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
339 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 340 | |
95f28d2e | 341 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
342 | dev_priv->psr.colorimetry_support = |
343 | intel_dp_get_colorimetry_status(intel_dp); | |
8c0d2c29 JRS |
344 | dev_priv->psr.su_x_granularity = |
345 | intel_dp_get_su_x_granulartiy(intel_dp); | |
77fe36ff DP |
346 | } |
347 | } | |
348 | } | |
349 | ||
cf5d862d RV |
350 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
351 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 352 | { |
97da2ef4 | 353 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 354 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d2419ffc | 355 | struct edp_vsc_psr psr_vsc; |
474d1ec4 | 356 | |
95f28d2e | 357 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
358 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
359 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
360 | psr_vsc.sdp_header.HB0 = 0; | |
361 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 362 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
363 | psr_vsc.sdp_header.HB2 = 0x5; |
364 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 365 | } else { |
2ce4df87 RV |
366 | psr_vsc.sdp_header.HB2 = 0x4; |
367 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 368 | } |
97da2ef4 | 369 | } else { |
2ce4df87 RV |
370 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
371 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
372 | psr_vsc.sdp_header.HB0 = 0; | |
373 | psr_vsc.sdp_header.HB1 = 0x7; | |
374 | psr_vsc.sdp_header.HB2 = 0x2; | |
375 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
376 | } |
377 | ||
790ea70c VS |
378 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
379 | crtc_state, | |
1d776538 | 380 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
381 | } |
382 | ||
b90eed08 | 383 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 384 | { |
1895759e | 385 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
386 | u32 aux_clock_divider, aux_ctl; |
387 | int i; | |
739f3abd | 388 | static const u8 aux_msg[] = { |
0bc12bcb RV |
389 | [0] = DP_AUX_NATIVE_WRITE << 4, |
390 | [1] = DP_SET_POWER >> 8, | |
391 | [2] = DP_SET_POWER & 0xff, | |
392 | [3] = 1 - 1, | |
393 | [4] = DP_SET_POWER_D0, | |
394 | }; | |
d544e918 DP |
395 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
396 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
397 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
398 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
399 | |
400 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 401 | for (i = 0; i < sizeof(aux_msg); i += 4) |
d544e918 | 402 | I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), |
b90eed08 DP |
403 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
404 | ||
d544e918 DP |
405 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
406 | ||
407 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 408 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 409 | aux_clock_divider); |
d544e918 DP |
410 | |
411 | /* Select only valid bits for SRD_AUX_CTL */ | |
412 | aux_ctl &= psr_aux_mask; | |
413 | I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); | |
b90eed08 DP |
414 | } |
415 | ||
cf5d862d | 416 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 417 | { |
1895759e | 418 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 419 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 420 | |
340c93c0 | 421 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
422 | if (dev_priv->psr.psr2_enabled) { |
423 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
424 | DP_ALPM_ENABLE); | |
98751b8c | 425 | dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; |
60cae442 JRS |
426 | } else { |
427 | if (dev_priv->psr.link_standby) | |
428 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; | |
de570946 JRS |
429 | |
430 | if (INTEL_GEN(dev_priv) >= 8) | |
431 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
97c9de66 DP |
432 | } |
433 | ||
4df4925b | 434 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 435 | |
d544e918 | 436 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
437 | } |
438 | ||
1e0c05c0 | 439 | static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) |
0bc12bcb | 440 | { |
1895759e | 441 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1e0c05c0 | 442 | u32 val = 0; |
60e5ffe3 | 443 | |
8a9a5608 JRS |
444 | if (INTEL_GEN(dev_priv) >= 11) |
445 | val |= EDP_PSR_TP4_TIME_0US; | |
446 | ||
77312ae8 | 447 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
1e0c05c0 | 448 | val |= EDP_PSR_TP1_TIME_0us; |
77312ae8 | 449 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) |
50db1390 | 450 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
451 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
452 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 453 | else |
77312ae8 | 454 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 455 | |
77312ae8 | 456 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
1e0c05c0 | 457 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
77312ae8 | 458 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) |
50db1390 | 459 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
460 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
461 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 462 | else |
77312ae8 | 463 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 SV |
464 | |
465 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
466 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
467 | val |= EDP_PSR_TP1_TP3_SEL; | |
468 | else | |
469 | val |= EDP_PSR_TP1_TP2_SEL; | |
470 | ||
1e0c05c0 JRS |
471 | return val; |
472 | } | |
473 | ||
474 | static void hsw_activate_psr1(struct intel_dp *intel_dp) | |
475 | { | |
476 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
477 | u32 max_sleep_time = 0x1f; | |
478 | u32 val = EDP_PSR_ENABLE; | |
479 | ||
480 | /* Let's use 6 as the minimum to cover all known cases including the | |
481 | * off-by-one issue that HW has in some cases. | |
482 | */ | |
483 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
484 | ||
485 | /* sink_sync_latency of 8 means source has to wait for more than 8 | |
486 | * frames, we'll go with 9 frames for now | |
487 | */ | |
488 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
489 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
490 | ||
491 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
492 | if (IS_HASWELL(dev_priv)) | |
493 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
494 | ||
495 | if (dev_priv->psr.link_standby) | |
496 | val |= EDP_PSR_LINK_STANDBY; | |
497 | ||
498 | val |= intel_psr1_get_tp_time(intel_dp); | |
499 | ||
00c8f194 JRS |
500 | if (INTEL_GEN(dev_priv) >= 8) |
501 | val |= EDP_PSR_CRC_ENABLE; | |
502 | ||
912d6412 | 503 | val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; |
50db1390 | 504 | I915_WRITE(EDP_PSR_CTL, val); |
3fcb0ca1 | 505 | } |
50db1390 | 506 | |
ed63d24b | 507 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 508 | { |
1895759e | 509 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
510 | u32 val; |
511 | ||
512 | /* Let's use 6 as the minimum to cover all known cases including the | |
513 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 514 | */ |
a3db1428 DP |
515 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
516 | ||
517 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
518 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 | 519 | |
5e87325f | 520 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
521 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
522 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 523 | |
26e5378d | 524 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 525 | |
88a0d960 JRS |
526 | if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && |
527 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) | |
77312ae8 | 528 | val |= EDP_PSR2_TP2_TIME_50us; |
88a0d960 | 529 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) |
77312ae8 | 530 | val |= EDP_PSR2_TP2_TIME_100us; |
88a0d960 | 531 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) |
77312ae8 | 532 | val |= EDP_PSR2_TP2_TIME_500us; |
50db1390 | 533 | else |
77312ae8 | 534 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 535 | |
06dd94cc | 536 | /* |
15b7dae0 JRS |
537 | * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is |
538 | * recommending keep this bit unset while PSR2 is enabled. | |
06dd94cc JRS |
539 | */ |
540 | I915_WRITE(EDP_PSR_CTL, 0); | |
541 | ||
50db1390 | 542 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
543 | } |
544 | ||
c4932d79 RV |
545 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
546 | struct intel_crtc_state *crtc_state) | |
547 | { | |
1895759e | 548 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c90c275c DP |
549 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
550 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
551 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 | 552 | |
95f28d2e | 553 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
554 | return false; |
555 | ||
8228c42f MN |
556 | /* |
557 | * DSC and PSR2 cannot be enabled simultaneously. If a requested | |
558 | * resolution requires DSC to be enabled, priority is given to DSC | |
559 | * over PSR2. | |
560 | */ | |
561 | if (crtc_state->dsc_params.compression_enable) { | |
562 | DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); | |
563 | return false; | |
564 | } | |
565 | ||
c90c275c DP |
566 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
567 | psr_max_h = 4096; | |
568 | psr_max_v = 2304; | |
cf819eff | 569 | } else if (IS_GEN(dev_priv, 9)) { |
c90c275c DP |
570 | psr_max_h = 3640; |
571 | psr_max_v = 2304; | |
572 | } | |
573 | ||
574 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
575 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
576 | crtc_hdisplay, crtc_vdisplay, | |
577 | psr_max_h, psr_max_v); | |
c4932d79 RV |
578 | return false; |
579 | } | |
580 | ||
bef5e5b3 JRS |
581 | /* |
582 | * HW sends SU blocks of size four scan lines, which means the starting | |
583 | * X coordinate and Y granularity requirements will always be met. We | |
8c0d2c29 JRS |
584 | * only need to validate the SU block width is a multiple of |
585 | * x granularity. | |
bef5e5b3 | 586 | */ |
8c0d2c29 JRS |
587 | if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { |
588 | DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", | |
589 | crtc_hdisplay, dev_priv->psr.su_x_granularity); | |
bef5e5b3 JRS |
590 | return false; |
591 | } | |
592 | ||
618cf883 JRS |
593 | if (crtc_state->crc_enabled) { |
594 | DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n"); | |
595 | return false; | |
596 | } | |
597 | ||
c4932d79 RV |
598 | return true; |
599 | } | |
600 | ||
4d90f2d5 VS |
601 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
602 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
603 | { |
604 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 605 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 606 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 607 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 608 | int psr_setup_time; |
0bc12bcb | 609 | |
4371d896 | 610 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
611 | return; |
612 | ||
c44301fc | 613 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 614 | return; |
0bc12bcb | 615 | |
dc9b5a0c RV |
616 | /* |
617 | * HSW spec explicitly says PSR is tied to port A. | |
618 | * BDW+ platforms with DDI implementation of PSR have different | |
619 | * PSR registers per transcoder and we only implement transcoder EDP | |
620 | * ones. Since by Display design transcoder EDP is tied to port A | |
621 | * we can safely escape based on the port A. | |
622 | */ | |
ce3508fd | 623 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 624 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 625 | return; |
0bc12bcb RV |
626 | } |
627 | ||
50a12d8f JRS |
628 | if (dev_priv->psr.sink_not_reliable) { |
629 | DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); | |
630 | return; | |
631 | } | |
632 | ||
7ae6ad6f JRS |
633 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
634 | DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n"); | |
4d90f2d5 | 635 | return; |
0bc12bcb RV |
636 | } |
637 | ||
dfd2e9ab VS |
638 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
639 | if (psr_setup_time < 0) { | |
640 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
641 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 642 | return; |
dfd2e9ab VS |
643 | } |
644 | ||
645 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
646 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
647 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
648 | psr_setup_time); | |
4d90f2d5 VS |
649 | return; |
650 | } | |
651 | ||
4d90f2d5 | 652 | crtc_state->has_psr = true; |
c4932d79 | 653 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
654 | } |
655 | ||
e2bbc343 | 656 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 657 | { |
1895759e | 658 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 659 | |
bcc233b2 | 660 | if (INTEL_GEN(dev_priv) >= 9) |
3fcb0ca1 | 661 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
bcc233b2 | 662 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); |
0bc12bcb RV |
663 | WARN_ON(dev_priv->psr.active); |
664 | lockdep_assert_held(&dev_priv->psr.lock); | |
665 | ||
cf5d862d RV |
666 | /* psr1 and psr2 are mutually exclusive.*/ |
667 | if (dev_priv->psr.psr2_enabled) | |
668 | hsw_activate_psr2(intel_dp); | |
669 | else | |
670 | hsw_activate_psr1(intel_dp); | |
671 | ||
0bc12bcb RV |
672 | dev_priv->psr.active = true; |
673 | } | |
674 | ||
8f19b401 ID |
675 | static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv, |
676 | enum transcoder cpu_transcoder) | |
677 | { | |
678 | static const i915_reg_t regs[] = { | |
679 | [TRANSCODER_A] = CHICKEN_TRANS_A, | |
680 | [TRANSCODER_B] = CHICKEN_TRANS_B, | |
681 | [TRANSCODER_C] = CHICKEN_TRANS_C, | |
682 | [TRANSCODER_EDP] = CHICKEN_TRANS_EDP, | |
683 | }; | |
684 | ||
685 | WARN_ON(INTEL_GEN(dev_priv) < 9); | |
686 | ||
687 | if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) || | |
688 | !regs[cpu_transcoder].reg)) | |
689 | cpu_transcoder = TRANSCODER_A; | |
690 | ||
691 | return regs[cpu_transcoder]; | |
692 | } | |
693 | ||
cf5d862d RV |
694 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
695 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 696 | { |
1895759e | 697 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 698 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 699 | u32 mask; |
4d1fa22f | 700 | |
d544e918 DP |
701 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
702 | * use hardcoded values PSR AUX transactions | |
703 | */ | |
704 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
705 | hsw_psr_setup_aux(intel_dp); | |
706 | ||
cf819eff | 707 | if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && |
d15f9cdd | 708 | !IS_GEMINILAKE(dev_priv))) { |
8f19b401 ID |
709 | i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, |
710 | cpu_transcoder); | |
711 | u32 chicken = I915_READ(reg); | |
5e87325f | 712 | |
d15f9cdd JRS |
713 | chicken |= PSR2_VSC_ENABLE_PROG_HEADER | |
714 | PSR2_ADD_VERTICAL_LINE_COUNT; | |
8f19b401 | 715 | I915_WRITE(reg, chicken); |
4d1fa22f | 716 | } |
bf80928f JRS |
717 | |
718 | /* | |
719 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
720 | * mask LPSP to avoid dependency on other drivers that might block | |
721 | * runtime_pm besides preventing other hw tracking issues now we | |
722 | * can rely on frontbuffer tracking. | |
723 | */ | |
fc6ff9dc JRS |
724 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
725 | EDP_PSR_DEBUG_MASK_HPD | | |
726 | EDP_PSR_DEBUG_MASK_LPSP | | |
727 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
728 | ||
729 | if (INTEL_GEN(dev_priv) < 11) | |
730 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
731 | ||
732 | I915_WRITE(EDP_PSR_DEBUG, mask); | |
4d1fa22f RV |
733 | } |
734 | ||
c44301fc ML |
735 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
736 | const struct intel_crtc_state *crtc_state) | |
737 | { | |
738 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
739 | ||
23ec9f52 JRS |
740 | WARN_ON(dev_priv->psr.enabled); |
741 | ||
742 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
743 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
744 | dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; | |
c44301fc ML |
745 | |
746 | DRM_DEBUG_KMS("Enabling PSR%s\n", | |
747 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
748 | intel_psr_setup_vsc(intel_dp, crtc_state); | |
749 | intel_psr_enable_sink(intel_dp); | |
750 | intel_psr_enable_source(intel_dp, crtc_state); | |
751 | dev_priv->psr.enabled = true; | |
752 | ||
753 | intel_psr_activate(intel_dp); | |
754 | } | |
755 | ||
b2b89f55 RV |
756 | /** |
757 | * intel_psr_enable - Enable PSR | |
758 | * @intel_dp: Intel DP | |
d2419ffc | 759 | * @crtc_state: new CRTC state |
b2b89f55 RV |
760 | * |
761 | * This function can only be called after the pipe is fully trained and enabled. | |
762 | */ | |
d2419ffc VS |
763 | void intel_psr_enable(struct intel_dp *intel_dp, |
764 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 765 | { |
1895759e | 766 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 767 | |
4d90f2d5 | 768 | if (!crtc_state->has_psr) |
0bc12bcb | 769 | return; |
0bc12bcb | 770 | |
c9ef291a DP |
771 | if (WARN_ON(!CAN_PSR(dev_priv))) |
772 | return; | |
773 | ||
da83ef85 | 774 | WARN_ON(dev_priv->drrs.dp); |
c44301fc | 775 | |
0bc12bcb | 776 | mutex_lock(&dev_priv->psr.lock); |
23ec9f52 JRS |
777 | |
778 | if (!psr_global_enabled(dev_priv->psr.debug)) { | |
779 | DRM_DEBUG_KMS("PSR disabled by flag\n"); | |
0bc12bcb RV |
780 | goto unlock; |
781 | } | |
782 | ||
23ec9f52 | 783 | intel_psr_enable_locked(dev_priv, crtc_state); |
d0ac896a | 784 | |
0bc12bcb RV |
785 | unlock: |
786 | mutex_unlock(&dev_priv->psr.lock); | |
787 | } | |
788 | ||
26f9ec9a JRS |
789 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
790 | { | |
791 | u32 val; | |
792 | ||
b2fc2252 JRS |
793 | if (!dev_priv->psr.active) { |
794 | if (INTEL_GEN(dev_priv) >= 9) | |
795 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
796 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
26f9ec9a | 797 | return; |
b2fc2252 | 798 | } |
26f9ec9a JRS |
799 | |
800 | if (dev_priv->psr.psr2_enabled) { | |
801 | val = I915_READ(EDP_PSR2_CTL); | |
802 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
803 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
804 | } else { | |
805 | val = I915_READ(EDP_PSR_CTL); | |
806 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
807 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
808 | } | |
809 | dev_priv->psr.active = false; | |
810 | } | |
811 | ||
2ee936e3 | 812 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 813 | { |
1895759e | 814 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
815 | i915_reg_t psr_status; |
816 | u32 psr_status_mask; | |
0bc12bcb | 817 | |
2ee936e3 JRS |
818 | lockdep_assert_held(&dev_priv->psr.lock); |
819 | ||
820 | if (!dev_priv->psr.enabled) | |
821 | return; | |
822 | ||
823 | DRM_DEBUG_KMS("Disabling PSR%s\n", | |
824 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
825 | ||
b2fc2252 | 826 | intel_psr_exit(dev_priv); |
77affa31 | 827 | |
b2fc2252 JRS |
828 | if (dev_priv->psr.psr2_enabled) { |
829 | psr_status = EDP_PSR2_STATUS; | |
830 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; | |
0bc12bcb | 831 | } else { |
b2fc2252 JRS |
832 | psr_status = EDP_PSR_STATUS; |
833 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 834 | } |
b2fc2252 JRS |
835 | |
836 | /* Wait till PSR is idle */ | |
97a04e0d DCS |
837 | if (intel_wait_for_register(&dev_priv->uncore, |
838 | psr_status, psr_status_mask, 0, 2000)) | |
b2fc2252 | 839 | DRM_ERROR("Timed out waiting PSR idle state\n"); |
cc3054ff JRS |
840 | |
841 | /* Disable PSR on Sink */ | |
842 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
843 | ||
c44301fc | 844 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
845 | } |
846 | ||
e2bbc343 RV |
847 | /** |
848 | * intel_psr_disable - Disable PSR | |
849 | * @intel_dp: Intel DP | |
d2419ffc | 850 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
851 | * |
852 | * This function needs to be called before disabling pipe. | |
853 | */ | |
d2419ffc VS |
854 | void intel_psr_disable(struct intel_dp *intel_dp, |
855 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 856 | { |
1895759e | 857 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 858 | |
4d90f2d5 | 859 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
860 | return; |
861 | ||
c9ef291a DP |
862 | if (WARN_ON(!CAN_PSR(dev_priv))) |
863 | return; | |
864 | ||
e2bbc343 | 865 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 866 | |
cc3054ff | 867 | intel_psr_disable_locked(intel_dp); |
c44301fc | 868 | |
0bc12bcb | 869 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 870 | cancel_work_sync(&dev_priv->psr.work); |
0bc12bcb RV |
871 | } |
872 | ||
88e05aff JRS |
873 | static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) |
874 | { | |
875 | /* | |
876 | * Display WA #0884: all | |
877 | * This documented WA for bxt can be safely applied | |
878 | * broadly so we can force HW tracking to exit PSR | |
879 | * instead of disabling and re-enabling. | |
880 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
881 | * but it makes more sense write to the current active | |
882 | * pipe. | |
883 | */ | |
884 | I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); | |
885 | } | |
886 | ||
23ec9f52 JRS |
887 | /** |
888 | * intel_psr_update - Update PSR state | |
889 | * @intel_dp: Intel DP | |
890 | * @crtc_state: new CRTC state | |
891 | * | |
892 | * This functions will update PSR states, disabling, enabling or switching PSR | |
893 | * version when executing fastsets. For full modeset, intel_psr_disable() and | |
894 | * intel_psr_enable() should be called instead. | |
895 | */ | |
896 | void intel_psr_update(struct intel_dp *intel_dp, | |
897 | const struct intel_crtc_state *crtc_state) | |
898 | { | |
899 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
900 | struct i915_psr *psr = &dev_priv->psr; | |
901 | bool enable, psr2_enable; | |
902 | ||
903 | if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) | |
904 | return; | |
905 | ||
906 | mutex_lock(&dev_priv->psr.lock); | |
907 | ||
908 | enable = crtc_state->has_psr && psr_global_enabled(psr->debug); | |
909 | psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); | |
910 | ||
88e05aff JRS |
911 | if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { |
912 | /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ | |
913 | if (crtc_state->crc_enabled && psr->enabled) | |
914 | psr_force_hw_tracking_exit(dev_priv); | |
915 | ||
23ec9f52 | 916 | goto unlock; |
88e05aff | 917 | } |
23ec9f52 | 918 | |
9f952664 JRS |
919 | if (psr->enabled) |
920 | intel_psr_disable_locked(intel_dp); | |
23ec9f52 | 921 | |
9f952664 JRS |
922 | if (enable) |
923 | intel_psr_enable_locked(dev_priv, crtc_state); | |
23ec9f52 JRS |
924 | |
925 | unlock: | |
926 | mutex_unlock(&dev_priv->psr.lock); | |
927 | } | |
928 | ||
65df9c79 DP |
929 | /** |
930 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
931 | * @new_crtc_state: new CRTC state | |
932 | * @out_value: PSR status in case of failure | |
933 | * | |
934 | * This function is expected to be called from pipe_update_start() where it is | |
935 | * not expected to race with PSR enable or disable. | |
936 | * | |
937 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
938 | */ | |
63ec132d DP |
939 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
940 | u32 *out_value) | |
c43dbcbb | 941 | { |
c3d43361 TV |
942 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
943 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
c43dbcbb | 944 | |
c44301fc | 945 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
946 | return 0; |
947 | ||
fd255f6e DP |
948 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
949 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
950 | return 0; | |
c43dbcbb TV |
951 | |
952 | /* | |
65df9c79 DP |
953 | * From bspec: Panel Self Refresh (BDW+) |
954 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
955 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
956 | * defensive enough to cover everything. | |
c43dbcbb | 957 | */ |
63ec132d | 958 | |
97a04e0d | 959 | return __intel_wait_for_register(&dev_priv->uncore, EDP_PSR_STATUS, |
fd255f6e | 960 | EDP_PSR_STATUS_STATE_MASK, |
63ec132d DP |
961 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
962 | out_value); | |
c43dbcbb TV |
963 | } |
964 | ||
965 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 966 | { |
daeb725e CW |
967 | i915_reg_t reg; |
968 | u32 mask; | |
969 | int err; | |
970 | ||
c44301fc | 971 | if (!dev_priv->psr.enabled) |
daeb725e | 972 | return false; |
0bc12bcb | 973 | |
ce3508fd DP |
974 | if (dev_priv->psr.psr2_enabled) { |
975 | reg = EDP_PSR2_STATUS; | |
976 | mask = EDP_PSR2_STATUS_STATE_MASK; | |
995d3047 | 977 | } else { |
ce3508fd DP |
978 | reg = EDP_PSR_STATUS; |
979 | mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 980 | } |
daeb725e CW |
981 | |
982 | mutex_unlock(&dev_priv->psr.lock); | |
983 | ||
97a04e0d | 984 | err = intel_wait_for_register(&dev_priv->uncore, reg, mask, 0, 50); |
daeb725e CW |
985 | if (err) |
986 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
987 | ||
988 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 989 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
990 | return err == 0 && dev_priv->psr.enabled; |
991 | } | |
0bc12bcb | 992 | |
23ec9f52 | 993 | static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) |
2ac45bdd | 994 | { |
23ec9f52 JRS |
995 | struct drm_device *dev = &dev_priv->drm; |
996 | struct drm_modeset_acquire_ctx ctx; | |
997 | struct drm_atomic_state *state; | |
998 | struct drm_crtc *crtc; | |
999 | int err; | |
2ac45bdd | 1000 | |
23ec9f52 JRS |
1001 | state = drm_atomic_state_alloc(dev); |
1002 | if (!state) | |
1003 | return -ENOMEM; | |
2ac45bdd | 1004 | |
23ec9f52 JRS |
1005 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
1006 | state->acquire_ctx = &ctx; | |
1007 | ||
1008 | retry: | |
1009 | drm_for_each_crtc(crtc, dev) { | |
1010 | struct drm_crtc_state *crtc_state; | |
1011 | struct intel_crtc_state *intel_crtc_state; | |
1012 | ||
1013 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
1014 | if (IS_ERR(crtc_state)) { | |
1015 | err = PTR_ERR(crtc_state); | |
1016 | goto error; | |
1017 | } | |
1018 | ||
1019 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
1020 | ||
458e0977 | 1021 | if (crtc_state->active && intel_crtc_state->has_psr) { |
23ec9f52 JRS |
1022 | /* Mark mode as changed to trigger a pipe->update() */ |
1023 | crtc_state->mode_changed = true; | |
1024 | break; | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | err = drm_atomic_commit(state); | |
2ac45bdd | 1029 | |
23ec9f52 JRS |
1030 | error: |
1031 | if (err == -EDEADLK) { | |
1032 | drm_atomic_state_clear(state); | |
1033 | err = drm_modeset_backoff(&ctx); | |
1034 | if (!err) | |
1035 | goto retry; | |
1036 | } | |
1037 | ||
1038 | drm_modeset_drop_locks(&ctx); | |
1039 | drm_modeset_acquire_fini(&ctx); | |
1040 | drm_atomic_state_put(state); | |
1041 | ||
1042 | return err; | |
2ac45bdd ML |
1043 | } |
1044 | ||
23ec9f52 | 1045 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) |
c44301fc | 1046 | { |
23ec9f52 JRS |
1047 | const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
1048 | u32 old_mode; | |
c44301fc | 1049 | int ret; |
c44301fc ML |
1050 | |
1051 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 1052 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
c44301fc ML |
1053 | DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); |
1054 | return -EINVAL; | |
1055 | } | |
1056 | ||
c44301fc ML |
1057 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); |
1058 | if (ret) | |
1059 | return ret; | |
1060 | ||
23ec9f52 | 1061 | old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; |
c44301fc | 1062 | dev_priv->psr.debug = val; |
1aeb1b5f | 1063 | intel_psr_irq_control(dev_priv, dev_priv->psr.debug); |
c44301fc | 1064 | |
c44301fc | 1065 | mutex_unlock(&dev_priv->psr.lock); |
23ec9f52 JRS |
1066 | |
1067 | if (old_mode != mode) | |
1068 | ret = intel_psr_fastset_force(dev_priv); | |
1069 | ||
c44301fc ML |
1070 | return ret; |
1071 | } | |
1072 | ||
183b8e67 JRS |
1073 | static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) |
1074 | { | |
1075 | struct i915_psr *psr = &dev_priv->psr; | |
1076 | ||
1077 | intel_psr_disable_locked(psr->dp); | |
1078 | psr->sink_not_reliable = true; | |
1079 | /* let's make sure that sink is awaken */ | |
1080 | drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); | |
1081 | } | |
1082 | ||
daeb725e CW |
1083 | static void intel_psr_work(struct work_struct *work) |
1084 | { | |
1085 | struct drm_i915_private *dev_priv = | |
5422b37c | 1086 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
1087 | |
1088 | mutex_lock(&dev_priv->psr.lock); | |
1089 | ||
5422b37c RV |
1090 | if (!dev_priv->psr.enabled) |
1091 | goto unlock; | |
1092 | ||
183b8e67 JRS |
1093 | if (READ_ONCE(dev_priv->psr.irq_aux_error)) |
1094 | intel_psr_handle_irq(dev_priv); | |
1095 | ||
daeb725e CW |
1096 | /* |
1097 | * We have to make sure PSR is ready for re-enable | |
1098 | * otherwise it keeps disabled until next full enable/disable cycle. | |
1099 | * PSR might take some time to get fully disabled | |
1100 | * and be ready for re-enable. | |
1101 | */ | |
c43dbcbb | 1102 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
1103 | goto unlock; |
1104 | ||
1105 | /* | |
1106 | * The delayed work can race with an invalidate hence we need to | |
1107 | * recheck. Since psr_flush first clears this and then reschedules we | |
1108 | * won't ever miss a flush when bailing out here. | |
1109 | */ | |
c12e0643 | 1110 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
1111 | goto unlock; |
1112 | ||
c44301fc | 1113 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
1114 | unlock: |
1115 | mutex_unlock(&dev_priv->psr.lock); | |
1116 | } | |
1117 | ||
b2b89f55 RV |
1118 | /** |
1119 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 1120 | * @dev_priv: i915 device |
b2b89f55 | 1121 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 1122 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
1123 | * |
1124 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1125 | * with the software frontbuffer tracking. This function gets called every | |
1126 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
1127 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
1128 | * | |
1129 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
1130 | */ | |
5748b6a1 | 1131 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 1132 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1133 | { |
4371d896 | 1134 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1135 | return; |
1136 | ||
ce3508fd | 1137 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1138 | return; |
1139 | ||
0bc12bcb RV |
1140 | mutex_lock(&dev_priv->psr.lock); |
1141 | if (!dev_priv->psr.enabled) { | |
1142 | mutex_unlock(&dev_priv->psr.lock); | |
1143 | return; | |
1144 | } | |
1145 | ||
f0ad62a6 | 1146 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb | 1147 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 SV |
1148 | |
1149 | if (frontbuffer_bits) | |
5748b6a1 | 1150 | intel_psr_exit(dev_priv); |
ec76d629 | 1151 | |
0bc12bcb RV |
1152 | mutex_unlock(&dev_priv->psr.lock); |
1153 | } | |
1154 | ||
b2b89f55 RV |
1155 | /** |
1156 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 1157 | * @dev_priv: i915 device |
b2b89f55 | 1158 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 1159 | * @origin: which operation caused the flush |
b2b89f55 RV |
1160 | * |
1161 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1162 | * with the software frontbuffer tracking. This function gets called every | |
1163 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
1164 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
1165 | * | |
1166 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
1167 | */ | |
5748b6a1 | 1168 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 1169 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1170 | { |
4371d896 | 1171 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1172 | return; |
1173 | ||
ce3508fd | 1174 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1175 | return; |
1176 | ||
0bc12bcb RV |
1177 | mutex_lock(&dev_priv->psr.lock); |
1178 | if (!dev_priv->psr.enabled) { | |
1179 | mutex_unlock(&dev_priv->psr.lock); | |
1180 | return; | |
1181 | } | |
1182 | ||
f0ad62a6 | 1183 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb RV |
1184 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1185 | ||
921ec285 | 1186 | /* By definition flush = invalidate + flush */ |
88e05aff JRS |
1187 | if (frontbuffer_bits) |
1188 | psr_force_hw_tracking_exit(dev_priv); | |
995d3047 | 1189 | |
0bc12bcb | 1190 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1191 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1192 | mutex_unlock(&dev_priv->psr.lock); |
1193 | } | |
1194 | ||
b2b89f55 RV |
1195 | /** |
1196 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1197 | * @dev_priv: i915 device private |
b2b89f55 RV |
1198 | * |
1199 | * This function is called only once at driver load to initialize basic | |
1200 | * PSR stuff. | |
1201 | */ | |
c39055b0 | 1202 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1203 | { |
888bf84d JRS |
1204 | u32 val; |
1205 | ||
0f328da6 RV |
1206 | if (!HAS_PSR(dev_priv)) |
1207 | return; | |
1208 | ||
443a389f VS |
1209 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
1210 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
1211 | ||
c9ef291a DP |
1212 | if (!dev_priv->psr.sink_support) |
1213 | return; | |
1214 | ||
598c6cfe DP |
1215 | if (i915_modparams.enable_psr == -1) |
1216 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1217 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1218 | |
888bf84d JRS |
1219 | /* |
1220 | * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR | |
1221 | * will still keep the error set even after the reset done in the | |
1222 | * irq_preinstall and irq_uninstall hooks. | |
1223 | * And enabling in this situation cause the screen to freeze in the | |
1224 | * first time that PSR HW tries to activate so lets keep PSR disabled | |
1225 | * to avoid any rendering problems. | |
1226 | */ | |
1227 | val = I915_READ(EDP_PSR_IIR); | |
1228 | val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP)); | |
1229 | if (val) { | |
1230 | DRM_DEBUG_KMS("PSR interruption error set\n"); | |
1231 | dev_priv->psr.sink_not_reliable = true; | |
888bf84d JRS |
1232 | } |
1233 | ||
65f61b42 | 1234 | /* Set link_standby x link_off defaults */ |
8652744b | 1235 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1236 | /* HSW and BDW require workarounds that we don't implement. */ |
1237 | dev_priv->psr.link_standby = false; | |
60e5ffe3 RV |
1238 | else |
1239 | /* For new platforms let's respect VBT back again */ | |
1240 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
1241 | ||
5422b37c | 1242 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
0bc12bcb RV |
1243 | mutex_init(&dev_priv->psr.lock); |
1244 | } | |
cc3054ff JRS |
1245 | |
1246 | void intel_psr_short_pulse(struct intel_dp *intel_dp) | |
1247 | { | |
1895759e | 1248 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff JRS |
1249 | struct i915_psr *psr = &dev_priv->psr; |
1250 | u8 val; | |
93bf76ed | 1251 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1252 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1253 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1254 | |
1255 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1256 | return; | |
1257 | ||
1258 | mutex_lock(&psr->lock); | |
1259 | ||
c44301fc | 1260 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1261 | goto exit; |
1262 | ||
1263 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { | |
1264 | DRM_ERROR("PSR_STATUS dpcd read failed\n"); | |
1265 | goto exit; | |
1266 | } | |
1267 | ||
1268 | if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { | |
1269 | DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); | |
1270 | intel_psr_disable_locked(intel_dp); | |
50a12d8f | 1271 | psr->sink_not_reliable = true; |
cc3054ff JRS |
1272 | } |
1273 | ||
93bf76ed JRS |
1274 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { |
1275 | DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n"); | |
1276 | goto exit; | |
1277 | } | |
1278 | ||
1279 | if (val & DP_PSR_RFB_STORAGE_ERROR) | |
1280 | DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); | |
1281 | if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) | |
1282 | DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
00c8f194 JRS |
1283 | if (val & DP_PSR_LINK_CRC_ERROR) |
1284 | DRM_ERROR("PSR Link CRC error, disabling PSR\n"); | |
93bf76ed JRS |
1285 | |
1286 | if (val & ~errors) | |
1287 | DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", | |
1288 | val & ~errors); | |
50a12d8f | 1289 | if (val & errors) { |
93bf76ed | 1290 | intel_psr_disable_locked(intel_dp); |
50a12d8f JRS |
1291 | psr->sink_not_reliable = true; |
1292 | } | |
93bf76ed JRS |
1293 | /* clear status register */ |
1294 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); | |
cc3054ff JRS |
1295 | exit: |
1296 | mutex_unlock(&psr->lock); | |
1297 | } | |
2f8e7ea9 JRS |
1298 | |
1299 | bool intel_psr_enabled(struct intel_dp *intel_dp) | |
1300 | { | |
1301 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1302 | bool ret; | |
1303 | ||
1304 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1305 | return false; | |
1306 | ||
1307 | mutex_lock(&dev_priv->psr.lock); | |
1308 | ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); | |
1309 | mutex_unlock(&dev_priv->psr.lock); | |
1310 | ||
1311 | return ret; | |
1312 | } |