[thirdparty/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>
#include "i915_gem_batch_pool.h"

#define I915_CMD_HASH_ORDER 9

/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
#define gen8_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SEMAPHORE_OFFSET(__from, __to)			     \
	(((__from) * I915_NUM_ENGINES  + (__to)) * gen8_semaphore_seqno_size)
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
#define GEN8_WAIT_OFFSET(__ring, from)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))

#define GEN8_RING_SEMAPHORE_INIT(e) do { \
	if (!dev_priv->semaphore_obj) { \
		break; \
	} \
	(e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \
	(e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \
	(e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \
	(e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \
	(e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \
	(e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \
	} while(0)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u32 seqno;
	unsigned user_interrupts;
	int score;
	enum intel_ring_hangcheck_action action;
	int deadlock;
	u32 instdone[I915_NUM_INSTDONE_REG];
};

struct intel_ringbuffer {
	struct drm_i915_gem_object *obj;
	void __iomem *virtual_start;
	struct i915_vma *vma;

	struct intel_engine_cs *engine;
	struct list_head link;

	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

struct	intel_context;
struct drm_i915_reg_table;

/*
 * we use a single page to load ctx workarounds so all of these
 * values are referred in terms of dwords
 *
 * struct i915_wa_ctx_bb:
 *  offset: specifies batch starting position, also helpful in case
 *    if we want to have multiple batches at different offsets based on
 *    some criteria. It is not a requirement at the moment but provides
 *    an option for future use.
 *  size: size of the batch in DWORDS
 */
struct  i915_ctx_workarounds {
	struct i915_wa_ctx_bb {
		u32 offset;
		u32 size;
	} indirect_ctx, per_ctx;
	struct drm_i915_gem_object *obj;
};

struct  intel_engine_cs {
	const char	*name;
	enum intel_engine_id {
		RCS = 0,
		BCS,
		VCS,
		VCS2,	/* Keep instances of the same type engine together. */
		VECS
	} id;
#define I915_NUM_ENGINES 5
#define _VCS(n) (VCS + (n))
	unsigned int exec_id;
	unsigned int guc_id;
	u32		mmio_base;
	struct		drm_device *dev;
	struct intel_ringbuffer *buffer;
	struct list_head buffers;

	/*
	 * A pool of objects to use as shadow copies of client batch buffers
	 * when the command parser is enabled. Prevents the client from
	 * modifying the batch contents after software parsing.
	 */
	struct i915_gem_batch_pool batch_pool;

	struct intel_hw_status_page status_page;
	struct i915_ctx_workarounds wa_ctx;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	struct drm_i915_gem_request *trace_irq_req;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init_hw)(struct intel_engine_cs *ring);

	int		(*init_context)(struct drm_i915_gem_request *req);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct drm_i915_gem_request *req,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct drm_i915_gem_request *req);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	void		(*irq_seqno_barrier)(struct intel_engine_cs *ring);
	u32		(*get_seqno)(struct intel_engine_cs *ring);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct drm_i915_gem_request *req,
					       u64 offset, u32 length,
					       unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
#define I915_DISPATCH_RS     0x4
	void		(*cleanup)(struct intel_engine_cs *ring);

	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
	struct {
		u32	sync_seqno[I915_NUM_ENGINES-1];

		union {
			struct {
				/* our mbox written by others */
				u32		wait[I915_NUM_ENGINES];
				/* mboxes this ring signals to */
				i915_reg_t	signal[I915_NUM_ENGINES];
			} mbox;
			u64		signal_ggtt[I915_NUM_ENGINES];
		};

		/* AKA wait() */
		int	(*sync_to)(struct drm_i915_gem_request *to_req,
				   struct intel_engine_cs *from,
				   u32 seqno);
		int	(*signal)(struct drm_i915_gem_request *signaller_req,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/* Execlists */
	struct tasklet_struct irq_tasklet;
	spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
	struct list_head execlist_queue;
	unsigned int fw_domains;
	unsigned int next_context_status_buffer;
	unsigned int idle_lite_restore_wa;
	bool disable_lite_restore_wa;
	u32 ctx_desc_template;
	u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
	int		(*emit_request)(struct drm_i915_gem_request *request);
	int		(*emit_flush)(struct drm_i915_gem_request *request,
				      u32 invalidate_domains,
				      u32 flush_domains);
	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
					 u64 offset, unsigned dispatch_flags);

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_read_req
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Seqno of request most recently submitted to request_list.
	 * Used exclusively by hang checker to avoid grabbing lock while
	 * inspecting request list.
	 */
	u32 last_submitted_seqno;
	unsigned user_interrupts;

	bool gpu_caches_dirty;

	wait_queue_head_t irq_queue;

	struct intel_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const struct drm_i915_reg_table *reg_tables;
	int reg_table_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

static inline bool
intel_engine_initialized(struct intel_engine_cs *engine)
{
	return engine->dev != NULL;
}

static inline unsigned
intel_engine_flag(struct intel_engine_cs *engine)
{
	return 1 << engine->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *engine,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - engine) - 1;
	if (idx < 0)
		idx += I915_NUM_ENGINES;

	return idx;
}

static inline void
intel_flush_status_page(struct intel_engine_cs *engine, int reg)
{
	mb();
	clflush(&engine->status_page.page_addr[reg]);
	mb();
}

static inline u32
intel_read_status_page(struct intel_engine_cs *engine, int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	return READ_ONCE(engine->status_page.page_addr[reg]);
}

static inline void
intel_write_status_page(struct intel_engine_cs *engine,
			int reg, u32 value)
{
	engine->status_page.page_addr[reg] = value;
}

/*
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 * 0x20-0x2f: Reserved (Gen6+)
 *
 * The area from dword 0x30 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x30
#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
#define I915_GEM_HWS_SCRATCH_INDEX	0x40
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

struct intel_ringbuffer *
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
				     struct intel_ringbuffer *ringbuf);
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
void intel_ringbuffer_free(struct intel_ringbuffer *ring);

void intel_stop_engine(struct intel_engine_cs *engine);
void intel_cleanup_engine(struct intel_engine_cs *engine);

int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);

int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
static inline void intel_ring_emit(struct intel_engine_cs *engine,
				   u32 data)
{
	struct intel_ringbuffer *ringbuf = engine->buffer;
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
				       i915_reg_t reg)
{
	intel_ring_emit(engine, i915_mmio_reg_offset(reg));
}
static inline void intel_ring_advance(struct intel_engine_cs *engine)
{
	struct intel_ringbuffer *ringbuf = engine->buffer;
	ringbuf->tail &= ringbuf->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
bool intel_engine_stopped(struct intel_engine_cs *engine);

int __must_check intel_engine_idle(struct intel_engine_cs *engine);
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);

void intel_fini_pipe_control(struct intel_engine_cs *engine);
int intel_init_pipe_control(struct intel_engine_cs *engine);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *engine);

int init_workarounds_ring(struct intel_engine_cs *engine);

static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{
	return ringbuf->tail;
}

/*
 * Arbitrary size for largest possible 'add request' sequence. The code paths
 * are complex and variable. Empirical measurement shows that the worst case
 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
 * we need to allocate double the largest single packet within that emission
 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
 */
#define MIN_SPACE_FOR_ADD_REQUEST 336

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8	4	#include <linux/hashtable.h>
06fbca71	5	#include "i915_gem_batch_pool.h"
44e895a8 BV	6
	7	#define I915_CMD_HASH_ORDER 9
	8
4712274c OM	9	/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
	10	* but keeps the logic simple. Indeed, the whole purpose of this macro is just
	11	* to give some inclination as to some of the magic values used in the various
	12	* workarounds!
	13	*/
	14	#define CACHELINE_BYTES 64
17ee950d	15	#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
4712274c	16
633cf8f5 VS	17	/*
	18	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	19	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	20	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	21	*
	22	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	23	* cacheline, the Head Pointer must not be greater than the Tail
	24	* Pointer."
	25	*/
	26	#define I915_RING_FREE_SPACE 64
	27
8187a2b7	28	struct intel_hw_status_page {
4225d0f2	29	u32 *page_addr;
8187a2b7	30	unsigned int gfx_addr;
05394f39	31	struct drm_i915_gem_object *obj;
8187a2b7 ZN	32	};
8187a2b7 ZN	33
b7287d80 BW	34	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	35	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	36
b7287d80 BW	37	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	38	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	39
b7287d80 BW	40	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	41	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	42
b7287d80 BW	43	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	44	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	45
b7287d80 BW	46	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	47	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	48
e9fea574	49	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	50	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	51
3e78998a BW	52	/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
	53	* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
	54	*/
8c12672e CW	55	#define gen8_semaphore_seqno_size sizeof(uint64_t)
	56	#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
	57	(((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
3e78998a BW	58	#define GEN8_SIGNAL_OFFSET(__ring, to) \
3e78998a BW	59	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
8c12672e	60	GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
3e78998a BW	61	#define GEN8_WAIT_OFFSET(__ring, from) \
3e78998a BW	62	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
8c12672e	63	GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
3e78998a	64
e2f80391	65	#define GEN8_RING_SEMAPHORE_INIT(e) do { \
3e78998a BW	66	if (!dev_priv->semaphore_obj) { \
	67	break; \
	68	} \
e2f80391 TU	69	(e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \
	70	(e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \
	71	(e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \
	72	(e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \
	73	(e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \
	74	(e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \
3e78998a BW	75	} while(0)
3e78998a BW	76
f2f4d82f	77	enum intel_ring_hangcheck_action {
da661464	78	HANGCHECK_IDLE = 0,
f2f4d82f JN	79	HANGCHECK_WAIT,
	80	HANGCHECK_ACTIVE,
	81	HANGCHECK_KICK,
	82	HANGCHECK_HUNG,
	83	};
ad8beaea	84
b6b0fac0 MK	85	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	86
92cab734	87	struct intel_ring_hangcheck {
50877445	88	u64 acthd;
92cab734	89	u32 seqno;
12471ba8	90	unsigned user_interrupts;
05407ff8	91	int score;
ad8beaea	92	enum intel_ring_hangcheck_action action;
4be17381	93	int deadlock;
61642ff0	94	u32 instdone[I915_NUM_INSTDONE_REG];
92cab734 MK	95	};
92cab734 MK	96
8ee14975 OM	97	struct intel_ringbuffer {
	98	struct drm_i915_gem_object *obj;
	99	void __iomem *virtual_start;
0eb973d3	100	struct i915_vma *vma;
8ee14975	101
4a570db5	102	struct intel_engine_cs *engine;
608c1a52	103	struct list_head link;
0c7dd53b	104
8ee14975 OM	105	u32 head;
	106	u32 tail;
	107	int space;
	108	int size;
	109	int effective_size;
	110
	111	/** We track the position of the requests in the ring buffer, and
	112	* when each is retired we increment last_retired_head as the GPU
	113	* must have finished processing the request and so we know we
	114	* can advance the ringbuffer up to that position.
	115	*
	116	* last_retired_head is set to -1 after the value is consumed so
	117	* we can detect new retirements.
	118	*/
	119	u32 last_retired_head;
	120	};
	121
21076372	122	struct intel_context;
361b027b	123	struct drm_i915_reg_table;
21076372	124
17ee950d AS	125	/*
	126	* we use a single page to load ctx workarounds so all of these
	127	* values are referred in terms of dwords
	128	*
	129	* struct i915_wa_ctx_bb:
	130	* offset: specifies batch starting position, also helpful in case
	131	* if we want to have multiple batches at different offsets based on
	132	* some criteria. It is not a requirement at the moment but provides
	133	* an option for future use.
	134	* size: size of the batch in DWORDS
	135	*/
	136	struct i915_ctx_workarounds {
	137	struct i915_wa_ctx_bb {
	138	u32 offset;
	139	u32 size;
	140	} indirect_ctx, per_ctx;
	141	struct drm_i915_gem_object *obj;
	142	};
	143
a4872ba6	144	struct intel_engine_cs {
8187a2b7	145	const char *name;
117897f4	146	enum intel_engine_id {
de1add36	147	RCS = 0,
96154f2f	148	BCS,
de1add36 TU	149	VCS,
	150	VCS2, /* Keep instances of the same type engine together. */
	151	VECS
9220434a	152	} id;
666796da	153	#define I915_NUM_ENGINES 5
de1add36	154	#define _VCS(n) (VCS + (n))
426960be	155	unsigned int exec_id;
397097b0	156	unsigned int guc_id;
333e9fe9	157	u32 mmio_base;
8187a2b7	158	struct drm_device *dev;
8ee14975	159	struct intel_ringbuffer *buffer;
608c1a52	160	struct list_head buffers;
8187a2b7	161
06fbca71 CW	162	/*
	163	* A pool of objects to use as shadow copies of client batch buffers
	164	* when the command parser is enabled. Prevents the client from
	165	* modifying the batch contents after software parsing.
	166	*/
	167	struct i915_gem_batch_pool batch_pool;
	168
8187a2b7	169	struct intel_hw_status_page status_page;
17ee950d	170	struct i915_ctx_workarounds wa_ctx;
8187a2b7	171
c7113cc3	172	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	173	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
581c26e8	174	struct drm_i915_gem_request *trace_irq_req;
a4872ba6 OM	175	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	176	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	177
ecfe00d8	178	int (init_hw)(struct intel_engine_cs ring);
8187a2b7	179
8753181e	180	int (init_context)(struct drm_i915_gem_request req);
86d7f238	181
a4872ba6	182	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	183	u32 value);
a84c3ae1	184	int __must_check (flush)(struct drm_i915_gem_request req,
b72f3acb CW	185	u32 invalidate_domains,
b72f3acb CW	186	u32 flush_domains);
ee044a88	187	int (add_request)(struct drm_i915_gem_request req);
b2eadbc8 CW	188	/* Some chipsets are not quite as coherent as advertised and need
	189	* an expensive kick to force a true read of the up-to-date seqno.
	190	* However, the up-to-date seqno is not always required and the last
	191	* seen value is good enough. Note that the seqno will always be
	192	* monotonic, even if not coherent.
	193	*/
c04e0f3b CW	194	void (irq_seqno_barrier)(struct intel_engine_cs ring);
c04e0f3b CW	195	u32 (get_seqno)(struct intel_engine_cs ring);
a4872ba6	196	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	197	u32 seqno);
53fddaf7	198	int (dispatch_execbuffer)(struct drm_i915_gem_request req,
9bcb144c	199	u64 offset, u32 length,
8e004efc	200	unsigned dispatch_flags);
d7d4eedd	201	#define I915_DISPATCH_SECURE 0x1
b45305fc	202	#define I915_DISPATCH_PINNED 0x2
919032ec	203	#define I915_DISPATCH_RS 0x4
a4872ba6	204	void (cleanup)(struct intel_engine_cs ring);
ebc348b2	205
3e78998a BW	206	/* GEN8 signal/wait table - never trust comments!
	207	* signal to signal to signal to signal to signal to
	208	* RCS VCS BCS VECS VCS2
	209	* --------------------------------------------------------------------
	210	* RCS \| NOP (0x00) \| VCS (0x08) \| BCS (0x10) \| VECS (0x18) \| VCS2 (0x20) \|
	211	* \|-------------------------------------------------------------------
	212	* VCS \| RCS (0x28) \| NOP (0x30) \| BCS (0x38) \| VECS (0x40) \| VCS2 (0x48) \|
	213	* \|-------------------------------------------------------------------
	214	* BCS \| RCS (0x50) \| VCS (0x58) \| NOP (0x60) \| VECS (0x68) \| VCS2 (0x70) \|
	215	* \|-------------------------------------------------------------------
	216	* VECS \| RCS (0x78) \| VCS (0x80) \| BCS (0x88) \| NOP (0x90) \| VCS2 (0x98) \|
	217	* \|-------------------------------------------------------------------
	218	* VCS2 \| RCS (0xa0) \| VCS (0xa8) \| BCS (0xb0) \| VECS (0xb8) \| NOP (0xc0) \|
	219	* \|-------------------------------------------------------------------
	220	*
	221	* Generalization:
	222	* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	223	* ie. transpose of g(x, y)
	224	*
	225	* sync from sync from sync from sync from sync from
	226	* RCS VCS BCS VECS VCS2
	227	* --------------------------------------------------------------------
	228	* RCS \| NOP (0x00) \| VCS (0x28) \| BCS (0x50) \| VECS (0x78) \| VCS2 (0xa0) \|
	229	* \|-------------------------------------------------------------------
	230	* VCS \| RCS (0x08) \| NOP (0x30) \| BCS (0x58) \| VECS (0x80) \| VCS2 (0xa8) \|
	231	* \|-------------------------------------------------------------------
	232	* BCS \| RCS (0x10) \| VCS (0x38) \| NOP (0x60) \| VECS (0x88) \| VCS2 (0xb0) \|
	233	* \|-------------------------------------------------------------------
	234	* VECS \| RCS (0x18) \| VCS (0x40) \| BCS (0x68) \| NOP (0x90) \| VCS2 (0xb8) \|
	235	* \|-------------------------------------------------------------------
	236	* VCS2 \| RCS (0x20) \| VCS (0x48) \| BCS (0x70) \| VECS (0x98) \| NOP (0xc0) \|
	237	* \|-------------------------------------------------------------------
	238	*
	239	* Generalization:
	240	* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	241	* ie. transpose of f(x, y)
	242	*/
ebc348b2	243	struct {
666796da	244	u32 sync_seqno[I915_NUM_ENGINES-1];
78325f2d	245
3e78998a BW	246	union {
	247	struct {
	248	/* our mbox written by others */
666796da	249	u32 wait[I915_NUM_ENGINES];
3e78998a	250	/* mboxes this ring signals to */
666796da	251	i915_reg_t signal[I915_NUM_ENGINES];
3e78998a	252	} mbox;
666796da	253	u64 signal_ggtt[I915_NUM_ENGINES];
3e78998a	254	};
78325f2d BW	255
78325f2d BW	256	/* AKA wait() */
599d924c JH	257	int (sync_to)(struct drm_i915_gem_request to_req,
599d924c JH	258	struct intel_engine_cs *from,
78325f2d	259	u32 seqno);
f7169687	260	int (signal)(struct drm_i915_gem_request signaller_req,
024a43e1 BW	261	/* num_dwords needed by caller */
024a43e1 BW	262	unsigned int num_dwords);
ebc348b2	263	} semaphore;
ad776f8b	264
4da46e1e	265	/* Execlists */
27af5eea TU	266	struct tasklet_struct irq_tasklet;
27af5eea TU	267	spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
acdd884a	268	struct list_head execlist_queue;
3756685a	269	unsigned int fw_domains;
c6a2ac71 TU	270	unsigned int next_context_status_buffer;
c6a2ac71 TU	271	unsigned int idle_lite_restore_wa;
ca82580c TU	272	bool disable_lite_restore_wa;
ca82580c TU	273	u32 ctx_desc_template;
73d477f6	274	u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
c4e76638	275	int (emit_request)(struct drm_i915_gem_request request);
7deb4d39	276	int (emit_flush)(struct drm_i915_gem_request request,
4712274c OM	277	u32 invalidate_domains,
4712274c OM	278	u32 flush_domains);
be795fc1	279	int (emit_bb_start)(struct drm_i915_gem_request req,
8e004efc	280	u64 offset, unsigned dispatch_flags);
4da46e1e	281
8187a2b7 ZN	282	/**
	283	* List of objects currently involved in rendering from the
	284	* ringbuffer.
	285	*
	286	* Includes buffers having the contents of their GPU caches
97b2a6a1	287	* flushed, not necessarily primitives. last_read_req
8187a2b7 ZN	288	* represents when the rendering involved will be completed.
	289	*
	290	* A reference is held on the buffer while on this list.
	291	*/
	292	struct list_head active_list;
	293
	294	/**
	295	* List of breadcrumbs associated with GPU requests currently
	296	* outstanding.
	297	*/
	298	struct list_head request_list;
	299
94f7bbe1 TE	300	/**
	301	* Seqno of request most recently submitted to request_list.
	302	* Used exclusively by hang checker to avoid grabbing lock while
	303	* inspecting request list.
	304	*/
	305	u32 last_submitted_seqno;
12471ba8	306	unsigned user_interrupts;
94f7bbe1	307
cc889e0f	308	bool gpu_caches_dirty;
a56ba56c	309
8187a2b7	310	wait_queue_head_t irq_queue;
8d19215b	311
273497e5	312	struct intel_context *last_context;
40521054	313
92cab734 MK	314	struct intel_ring_hangcheck hangcheck;
92cab734 MK	315
0d1aacac CW	316	struct {
	317	struct drm_i915_gem_object *obj;
	318	u32 gtt_offset;
	319	volatile u32 *cpu_page;
	320	} scratch;
351e3db2	321
44e895a8 BV	322	bool needs_cmd_parser;
44e895a8 BV	323
351e3db2	324	/*
44e895a8	325	* Table of commands the command parser needs to know about
351e3db2 BV	326	* for this ring.
351e3db2 BV	327	*/
44e895a8	328	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	329
	330	/*
	331	* Table of registers allowed in commands that read/write registers.
	332	*/
361b027b JJ	333	const struct drm_i915_reg_table *reg_tables;
361b027b JJ	334	int reg_table_count;
351e3db2 BV	335
	336	/*
	337	* Returns the bitmask for the length field of the specified command.
	338	* Return 0 for an unrecognized/invalid command.
	339	*
	340	* If the command parser finds an entry for a command in the ring's
	341	* cmd_tables, it gets the command's length based on the table entry.
	342	* If not, it calls this function to determine the per-ring length field
	343	* encoding for the command (i.e. certain opcode ranges use certain bits
	344	* to encode the command length in the header).
	345	*/
	346	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	347	};
8187a2b7 ZN	348
b0366a54	349	static inline bool
117897f4	350	intel_engine_initialized(struct intel_engine_cs *engine)
b0366a54	351	{
0bc40be8	352	return engine->dev != NULL;
b0366a54	353	}
b4519513	354
96154f2f	355	static inline unsigned
666796da	356	intel_engine_flag(struct intel_engine_cs *engine)
96154f2f	357	{
0bc40be8	358	return 1 << engine->id;
96154f2f DV	359	}
96154f2f DV	360
1ec14ad3	361	static inline u32
0bc40be8	362	intel_ring_sync_index(struct intel_engine_cs *engine,
a4872ba6	363	struct intel_engine_cs *other)
1ec14ad3 CW	364	{
	365	int idx;
	366
	367	/*
ddd4dbc6 RV	368	* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	369	* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	370	* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	371	* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	372	* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1ec14ad3 CW	373	*/
1ec14ad3 CW	374
0bc40be8	375	idx = (other - engine) - 1;
1ec14ad3	376	if (idx < 0)
666796da	377	idx += I915_NUM_ENGINES;
1ec14ad3 CW	378
	379	return idx;
	380	}
	381
319404df	382	static inline void
0bc40be8	383	intel_flush_status_page(struct intel_engine_cs *engine, int reg)
319404df	384	{
0d317ce9 CW	385	mb();
	386	clflush(&engine->status_page.page_addr[reg]);
	387	mb();
319404df ID	388	}
319404df ID	389
8187a2b7	390	static inline u32
5dd8e50c	391	intel_read_status_page(struct intel_engine_cs *engine, int reg)
8187a2b7	392	{
4225d0f2	393	/* Ensure that the compiler doesn't optimize away the load. */
5dd8e50c	394	return READ_ONCE(engine->status_page.page_addr[reg]);
8187a2b7 ZN	395	}
8187a2b7 ZN	396
b70ec5bf	397	static inline void
0bc40be8	398	intel_write_status_page(struct intel_engine_cs *engine,
b70ec5bf MK	399	int reg, u32 value)
b70ec5bf MK	400	{
0bc40be8	401	engine->status_page.page_addr[reg] = value;
b70ec5bf MK	402	}
b70ec5bf MK	403
e2828914	404	/*
311bd68e CW	405	* Reads a dword out of the status page, which is written to from the command
	406	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	407	* MI_STORE_DATA_IMM.
	408	*
	409	* The following dwords have a reserved meaning:
	410	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	411	* 0x04: ring 0 head pointer
	412	* 0x05: ring 1 head pointer (915-class)
	413	* 0x06: ring 2 head pointer (915-class)
	414	* 0x10-0x1b: Context status DWords (GM45)
	415	* 0x1f: Last written status offset. (GM45)
b07da53c	416	* 0x20-0x2f: Reserved (Gen6+)
311bd68e	417	*
b07da53c	418	* The area from dword 0x30 to 0x3ff is available for driver usage.
311bd68e	419	*/
b07da53c	420	#define I915_GEM_HWS_INDEX 0x30
7c17d377	421	#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
b07da53c	422	#define I915_GEM_HWS_SCRATCH_INDEX 0x40
9a289771	423	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	424
01101fa7 CW	425	struct intel_ringbuffer *
01101fa7 CW	426	intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
7ba717cf TD	427	int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
7ba717cf TD	428	struct intel_ringbuffer *ringbuf);
01101fa7 CW	429	void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
01101fa7 CW	430	void intel_ringbuffer_free(struct intel_ringbuffer *ring);
84c2377f	431
117897f4 TU	432	void intel_stop_engine(struct intel_engine_cs *engine);
117897f4 TU	433	void intel_cleanup_engine(struct intel_engine_cs *engine);
96f298aa	434
6689cb2b JH	435	int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
6689cb2b JH	436
5fb9de1a	437	int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
bba09b12	438	int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
0bc40be8	439	static inline void intel_ring_emit(struct intel_engine_cs *engine,
78501eac	440	u32 data)
e898cd22	441	{
0bc40be8	442	struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 OM	443	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
93b0a4e0 OM	444	ringbuf->tail += 4;
e898cd22	445	}
0bc40be8	446	static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
f0f59a00	447	i915_reg_t reg)
f92a9162	448	{
0bc40be8	449	intel_ring_emit(engine, i915_mmio_reg_offset(reg));
f92a9162	450	}
0bc40be8	451	static inline void intel_ring_advance(struct intel_engine_cs *engine)
09246732	452	{
0bc40be8	453	struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0	454	ringbuf->tail &= ringbuf->size - 1;
09246732	455	}
82e104cc	456	int __intel_ring_space(int head, int tail, int size);
ebd0fd4b	457	void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
117897f4	458	bool intel_engine_stopped(struct intel_engine_cs *engine);
09246732	459
666796da	460	int __must_check intel_engine_idle(struct intel_engine_cs *engine);
0bc40be8	461	void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
4866d729	462	int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
2f20055d	463	int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
8187a2b7	464
0bc40be8 TU	465	void intel_fini_pipe_control(struct intel_engine_cs *engine);
0bc40be8 TU	466	int intel_init_pipe_control(struct intel_engine_cs *engine);
9b1136d5	467
5c1143bb XH	468	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	469	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	470	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	471	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	472	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	473
0bc40be8	474	u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
79f321b7	475
0bc40be8	476	int init_workarounds_ring(struct intel_engine_cs *engine);
771b9a53	477
1b5d063f	478	static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
a71d8d94	479	{
1b5d063f	480	return ringbuf->tail;
a71d8d94 CW	481	}
a71d8d94 CW	482
29b1b415 JH	483	/*
	484	* Arbitrary size for largest possible 'add request' sequence. The code paths
	485	* are complex and variable. Empirical measurement shows that the worst case
596e5efc CW	486	* is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
	487	* we need to allocate double the largest single packet within that emission
	488	* to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
29b1b415	489	*/
596e5efc	490	#define MIN_SPACE_FOR_ADD_REQUEST 336
29b1b415	491
8187a2b7	492	#endif /* _INTEL_RINGBUFFER_H_ */