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9c065a7d SV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f SV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
9c065a7d SV |
52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
53 | for (i = 0; \ | |
54 | i < (power_domains)->power_well_count && \ | |
55 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
56 | i++) \ | |
57 | if ((power_well)->domains & (domain_mask)) | |
58 | ||
59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
60 | for (i = (power_domains)->power_well_count - 1; \ | |
61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
62 | i--) \ | |
63 | if ((power_well)->domains & (domain_mask)) | |
64 | ||
e4e7684f | 65 | /* |
9c065a7d SV |
66 | * We should only use the power well if we explicitly asked the hardware to |
67 | * enable it, so check if it's enabled and also check if we've requested it to | |
68 | * be enabled. | |
69 | */ | |
70 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
71 | struct i915_power_well *power_well) | |
72 | { | |
73 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
74 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
75 | } | |
76 | ||
e4e7684f SV |
77 | /** |
78 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
79 | * @dev_priv: i915 device instance | |
80 | * @domain: power domain to check | |
81 | * | |
82 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
83 | * only be used from error capture and recovery code where deadlocks are | |
84 | * possible. | |
85 | * | |
86 | * Returns: | |
87 | * True when the power domain is enabled, false otherwise. | |
88 | */ | |
f458ebbc SV |
89 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
90 | enum intel_display_power_domain domain) | |
9c065a7d SV |
91 | { |
92 | struct i915_power_domains *power_domains; | |
93 | struct i915_power_well *power_well; | |
94 | bool is_enabled; | |
95 | int i; | |
96 | ||
97 | if (dev_priv->pm.suspended) | |
98 | return false; | |
99 | ||
100 | power_domains = &dev_priv->power_domains; | |
101 | ||
102 | is_enabled = true; | |
103 | ||
104 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
105 | if (power_well->always_on) | |
106 | continue; | |
107 | ||
108 | if (!power_well->hw_enabled) { | |
109 | is_enabled = false; | |
110 | break; | |
111 | } | |
112 | } | |
113 | ||
114 | return is_enabled; | |
115 | } | |
116 | ||
e4e7684f | 117 | /** |
f61ccae3 | 118 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f SV |
119 | * @dev_priv: i915 device instance |
120 | * @domain: power domain to check | |
121 | * | |
122 | * This function can be used to check the hw power domain state. It is mostly | |
123 | * used in hardware state readout functions. Everywhere else code should rely | |
124 | * upon explicit power domain reference counting to ensure that the hardware | |
125 | * block is powered up before accessing it. | |
126 | * | |
127 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
128 | * threads can't disable the power well while the caller tries to read a few | |
129 | * registers. | |
130 | * | |
131 | * Returns: | |
132 | * True when the power domain is enabled, false otherwise. | |
133 | */ | |
f458ebbc SV |
134 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
135 | enum intel_display_power_domain domain) | |
9c065a7d SV |
136 | { |
137 | struct i915_power_domains *power_domains; | |
138 | bool ret; | |
139 | ||
140 | power_domains = &dev_priv->power_domains; | |
141 | ||
142 | mutex_lock(&power_domains->lock); | |
f458ebbc | 143 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d SV |
144 | mutex_unlock(&power_domains->lock); |
145 | ||
146 | return ret; | |
147 | } | |
148 | ||
e4e7684f SV |
149 | /** |
150 | * intel_display_set_init_power - set the initial power domain state | |
151 | * @dev_priv: i915 device instance | |
152 | * @enable: whether to enable or disable the initial power domain state | |
153 | * | |
154 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
155 | * that all power domains are always enabled. This functions controls the state | |
156 | * of this little hack. While the initial power domain state is enabled runtime | |
157 | * pm is effectively disabled. | |
158 | */ | |
d9bc89d9 SV |
159 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
160 | bool enable) | |
161 | { | |
162 | if (dev_priv->power_domains.init_power_on == enable) | |
163 | return; | |
164 | ||
165 | if (enable) | |
166 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
167 | else | |
168 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
169 | ||
170 | dev_priv->power_domains.init_power_on = enable; | |
171 | } | |
172 | ||
9c065a7d SV |
173 | /* |
174 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
175 | * when not needed anymore. We have 4 registers that can request the power well | |
176 | * to be enabled, and it will only be disabled if none of the registers is | |
177 | * requesting it to be enabled. | |
178 | */ | |
179 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
180 | { | |
181 | struct drm_device *dev = dev_priv->dev; | |
182 | ||
183 | /* | |
184 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
185 | * we'll get unclaimed register interrupts. This stops after we write | |
186 | * anything to the VGA MSR register. The vgacon module uses this | |
187 | * register all the time, so if we unbind our driver and, as a | |
188 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
189 | * console_unlock(). So make here we touch the VGA MSR register, making | |
190 | * sure vgacon can keep working normally without triggering interrupts | |
191 | * and error messages. | |
192 | */ | |
193 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
194 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
195 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
196 | ||
25400392 | 197 | if (IS_BROADWELL(dev)) |
4c6c03be DL |
198 | gen8_irq_power_well_post_enable(dev_priv, |
199 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d SV |
200 | } |
201 | ||
d14c0343 DL |
202 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
203 | struct i915_power_well *power_well) | |
204 | { | |
205 | struct drm_device *dev = dev_priv->dev; | |
206 | ||
207 | /* | |
208 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
209 | * we'll get unclaimed register interrupts. This stops after we write | |
210 | * anything to the VGA MSR register. The vgacon module uses this | |
211 | * register all the time, so if we unbind our driver and, as a | |
212 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
213 | * console_unlock(). So make here we touch the VGA MSR register, making | |
214 | * sure vgacon can keep working normally without triggering interrupts | |
215 | * and error messages. | |
216 | */ | |
217 | if (power_well->data == SKL_DISP_PW_2) { | |
218 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
219 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
220 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
221 | ||
222 | gen8_irq_power_well_post_enable(dev_priv, | |
223 | 1 << PIPE_C | 1 << PIPE_B); | |
224 | } | |
225 | ||
1d2b9526 DL |
226 | if (power_well->data == SKL_DISP_PW_1) { |
227 | intel_prepare_ddi(dev); | |
d14c0343 | 228 | gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); |
1d2b9526 | 229 | } |
d14c0343 DL |
230 | } |
231 | ||
9c065a7d SV |
232 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
233 | struct i915_power_well *power_well, bool enable) | |
234 | { | |
235 | bool is_enabled, enable_requested; | |
236 | uint32_t tmp; | |
237 | ||
238 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
239 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
240 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
241 | ||
242 | if (enable) { | |
243 | if (!enable_requested) | |
244 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
245 | HSW_PWR_WELL_ENABLE_REQUEST); | |
246 | ||
247 | if (!is_enabled) { | |
248 | DRM_DEBUG_KMS("Enabling power well\n"); | |
249 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
250 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
251 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 252 | hsw_power_well_post_enable(dev_priv); |
9c065a7d SV |
253 | } |
254 | ||
9c065a7d SV |
255 | } else { |
256 | if (enable_requested) { | |
257 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
258 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
259 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
260 | } | |
261 | } | |
262 | } | |
263 | ||
94dd5138 S |
264 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
265 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
266 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
267 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
268 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
269 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
270 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
271 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
272 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
273 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
274 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
275 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
276 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
277 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
278 | BIT(POWER_DOMAIN_AUX_B) | \ | |
279 | BIT(POWER_DOMAIN_AUX_C) | \ | |
280 | BIT(POWER_DOMAIN_AUX_D) | \ | |
281 | BIT(POWER_DOMAIN_AUDIO) | \ | |
282 | BIT(POWER_DOMAIN_VGA) | \ | |
283 | BIT(POWER_DOMAIN_INIT)) | |
284 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
285 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
286 | BIT(POWER_DOMAIN_PLLS) | \ | |
287 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
288 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
289 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
290 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
291 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
292 | BIT(POWER_DOMAIN_AUX_A) | \ | |
293 | BIT(POWER_DOMAIN_INIT)) | |
294 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ | |
295 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
296 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
297 | BIT(POWER_DOMAIN_INIT)) | |
298 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
299 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
300 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
301 | BIT(POWER_DOMAIN_INIT)) | |
302 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
303 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
304 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
305 | BIT(POWER_DOMAIN_INIT)) | |
306 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
307 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
308 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
309 | BIT(POWER_DOMAIN_INIT)) | |
310 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ | |
311 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS) | |
312 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ | |
313 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
314 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
315 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ | |
316 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ | |
317 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ | |
318 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ | |
319 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ | |
320 | BIT(POWER_DOMAIN_INIT)) | |
321 | ||
0b4a2a36 S |
322 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
323 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
324 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
325 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
326 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
327 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
328 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
329 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
330 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
331 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
332 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
333 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
334 | BIT(POWER_DOMAIN_AUX_B) | \ | |
335 | BIT(POWER_DOMAIN_AUX_C) | \ | |
336 | BIT(POWER_DOMAIN_AUDIO) | \ | |
337 | BIT(POWER_DOMAIN_VGA) | \ | |
338 | BIT(POWER_DOMAIN_INIT)) | |
339 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
340 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
341 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
342 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
343 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
344 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
345 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
346 | BIT(POWER_DOMAIN_AUX_A) | \ | |
347 | BIT(POWER_DOMAIN_PLLS) | \ | |
348 | BIT(POWER_DOMAIN_INIT)) | |
349 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ | |
350 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
351 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ | |
352 | BIT(POWER_DOMAIN_INIT)) | |
353 | ||
664326f8 SK |
354 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
355 | { | |
356 | struct drm_device *dev = dev_priv->dev; | |
357 | ||
358 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); | |
359 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
360 | "DC9 already programmed to be enabled.\n"); | |
361 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
362 | "DC5 still not disabled to enable DC9.\n"); | |
363 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); | |
364 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
365 | ||
366 | /* | |
367 | * TODO: check for the following to verify the conditions to enter DC9 | |
368 | * state are satisfied: | |
369 | * 1] Check relevant display engine registers to verify if mode set | |
370 | * disable sequence was followed. | |
371 | * 2] Check if display uninitialize sequence is initialized. | |
372 | */ | |
373 | } | |
374 | ||
375 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) | |
376 | { | |
377 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
378 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
379 | "DC9 already programmed to be disabled.\n"); | |
380 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
381 | "DC5 still not disabled.\n"); | |
382 | ||
383 | /* | |
384 | * TODO: check for the following to verify DC9 state was indeed | |
385 | * entered before programming to disable it: | |
386 | * 1] Check relevant display engine registers to verify if mode | |
387 | * set disable sequence was followed. | |
388 | * 2] Check if display uninitialize sequence is initialized. | |
389 | */ | |
390 | } | |
391 | ||
392 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) | |
393 | { | |
394 | uint32_t val; | |
395 | ||
396 | assert_can_enable_dc9(dev_priv); | |
397 | ||
398 | DRM_DEBUG_KMS("Enabling DC9\n"); | |
399 | ||
400 | val = I915_READ(DC_STATE_EN); | |
401 | val |= DC_STATE_EN_DC9; | |
402 | I915_WRITE(DC_STATE_EN, val); | |
403 | POSTING_READ(DC_STATE_EN); | |
404 | } | |
405 | ||
406 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) | |
407 | { | |
408 | uint32_t val; | |
409 | ||
410 | assert_can_disable_dc9(dev_priv); | |
411 | ||
412 | DRM_DEBUG_KMS("Disabling DC9\n"); | |
413 | ||
414 | val = I915_READ(DC_STATE_EN); | |
415 | val &= ~DC_STATE_EN_DC9; | |
416 | I915_WRITE(DC_STATE_EN, val); | |
417 | POSTING_READ(DC_STATE_EN); | |
418 | } | |
419 | ||
94dd5138 S |
420 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
421 | struct i915_power_well *power_well, bool enable) | |
422 | { | |
423 | uint32_t tmp, fuse_status; | |
424 | uint32_t req_mask, state_mask; | |
2a51835f | 425 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
426 | |
427 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
428 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
429 | ||
430 | switch (power_well->data) { | |
431 | case SKL_DISP_PW_1: | |
432 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
433 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
434 | DRM_ERROR("PG0 not enabled\n"); | |
435 | return; | |
436 | } | |
437 | break; | |
438 | case SKL_DISP_PW_2: | |
439 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
440 | DRM_ERROR("PG1 in disabled state\n"); | |
441 | return; | |
442 | } | |
443 | break; | |
444 | case SKL_DISP_PW_DDI_A_E: | |
445 | case SKL_DISP_PW_DDI_B: | |
446 | case SKL_DISP_PW_DDI_C: | |
447 | case SKL_DISP_PW_DDI_D: | |
448 | case SKL_DISP_PW_MISC_IO: | |
449 | break; | |
450 | default: | |
451 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
452 | return; | |
453 | } | |
454 | ||
455 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 456 | enable_requested = tmp & req_mask; |
94dd5138 | 457 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 458 | is_enabled = tmp & state_mask; |
94dd5138 S |
459 | |
460 | if (enable) { | |
2a51835f | 461 | if (!enable_requested) { |
94dd5138 | 462 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
463 | } |
464 | ||
2a51835f | 465 | if (!is_enabled) { |
510e6fdd | 466 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
467 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
468 | state_mask), 1)) | |
469 | DRM_ERROR("%s enable timeout\n", | |
470 | power_well->name); | |
471 | check_fuse_status = true; | |
472 | } | |
473 | } else { | |
2a51835f | 474 | if (enable_requested) { |
94dd5138 S |
475 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
476 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
477 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
478 | } | |
479 | } | |
480 | ||
481 | if (check_fuse_status) { | |
482 | if (power_well->data == SKL_DISP_PW_1) { | |
483 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
484 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
485 | DRM_ERROR("PG1 distributing status timeout\n"); | |
486 | } else if (power_well->data == SKL_DISP_PW_2) { | |
487 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
488 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
489 | DRM_ERROR("PG2 distributing status timeout\n"); | |
490 | } | |
491 | } | |
d14c0343 DL |
492 | |
493 | if (enable && !is_enabled) | |
494 | skl_power_well_post_enable(dev_priv, power_well); | |
94dd5138 S |
495 | } |
496 | ||
9c065a7d SV |
497 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
498 | struct i915_power_well *power_well) | |
499 | { | |
500 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
501 | ||
502 | /* | |
503 | * We're taking over the BIOS, so clear any requests made by it since | |
504 | * the driver is in charge now. | |
505 | */ | |
506 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
507 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
508 | } | |
509 | ||
510 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
511 | struct i915_power_well *power_well) | |
512 | { | |
513 | hsw_set_power_well(dev_priv, power_well, true); | |
514 | } | |
515 | ||
516 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
517 | struct i915_power_well *power_well) | |
518 | { | |
519 | hsw_set_power_well(dev_priv, power_well, false); | |
520 | } | |
521 | ||
94dd5138 S |
522 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
523 | struct i915_power_well *power_well) | |
524 | { | |
525 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
526 | SKL_POWER_WELL_STATE(power_well->data); | |
527 | ||
528 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
529 | } | |
530 | ||
531 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
532 | struct i915_power_well *power_well) | |
533 | { | |
534 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
535 | ||
536 | /* Clear any request made by BIOS as driver is taking over */ | |
537 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
538 | } | |
539 | ||
540 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
541 | struct i915_power_well *power_well) | |
542 | { | |
543 | skl_set_power_well(dev_priv, power_well, true); | |
544 | } | |
545 | ||
546 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
547 | struct i915_power_well *power_well) | |
548 | { | |
549 | skl_set_power_well(dev_priv, power_well, false); | |
550 | } | |
551 | ||
9c065a7d SV |
552 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
553 | struct i915_power_well *power_well) | |
554 | { | |
555 | } | |
556 | ||
557 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
558 | struct i915_power_well *power_well) | |
559 | { | |
560 | return true; | |
561 | } | |
562 | ||
563 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
564 | struct i915_power_well *power_well, bool enable) | |
565 | { | |
566 | enum punit_power_well power_well_id = power_well->data; | |
567 | u32 mask; | |
568 | u32 state; | |
569 | u32 ctrl; | |
570 | ||
571 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
572 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
573 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
574 | ||
575 | mutex_lock(&dev_priv->rps.hw_lock); | |
576 | ||
577 | #define COND \ | |
578 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
579 | ||
580 | if (COND) | |
581 | goto out; | |
582 | ||
583 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
584 | ctrl &= ~mask; | |
585 | ctrl |= state; | |
586 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
587 | ||
588 | if (wait_for(COND, 100)) | |
589 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
590 | state, | |
591 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
592 | ||
593 | #undef COND | |
594 | ||
595 | out: | |
596 | mutex_unlock(&dev_priv->rps.hw_lock); | |
597 | } | |
598 | ||
599 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
600 | struct i915_power_well *power_well) | |
601 | { | |
602 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
603 | } | |
604 | ||
605 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
606 | struct i915_power_well *power_well) | |
607 | { | |
608 | vlv_set_power_well(dev_priv, power_well, true); | |
609 | } | |
610 | ||
611 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
612 | struct i915_power_well *power_well) | |
613 | { | |
614 | vlv_set_power_well(dev_priv, power_well, false); | |
615 | } | |
616 | ||
617 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
618 | struct i915_power_well *power_well) | |
619 | { | |
620 | int power_well_id = power_well->data; | |
621 | bool enabled = false; | |
622 | u32 mask; | |
623 | u32 state; | |
624 | u32 ctrl; | |
625 | ||
626 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
627 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
628 | ||
629 | mutex_lock(&dev_priv->rps.hw_lock); | |
630 | ||
631 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
632 | /* | |
633 | * We only ever set the power-on and power-gate states, anything | |
634 | * else is unexpected. | |
635 | */ | |
636 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
637 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
638 | if (state == ctrl) | |
639 | enabled = true; | |
640 | ||
641 | /* | |
642 | * A transient state at this point would mean some unexpected party | |
643 | * is poking at the power controls too. | |
644 | */ | |
645 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
646 | WARN_ON(ctrl != state); | |
647 | ||
648 | mutex_unlock(&dev_priv->rps.hw_lock); | |
649 | ||
650 | return enabled; | |
651 | } | |
652 | ||
653 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
654 | struct i915_power_well *power_well) | |
655 | { | |
656 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
657 | ||
658 | vlv_set_power_well(dev_priv, power_well, true); | |
659 | ||
660 | spin_lock_irq(&dev_priv->irq_lock); | |
661 | valleyview_enable_display_irqs(dev_priv); | |
662 | spin_unlock_irq(&dev_priv->irq_lock); | |
663 | ||
664 | /* | |
665 | * During driver initialization/resume we can avoid restoring the | |
666 | * part of the HW/SW state that will be inited anyway explicitly. | |
667 | */ | |
668 | if (dev_priv->power_domains.initializing) | |
669 | return; | |
670 | ||
b963291c | 671 | intel_hpd_init(dev_priv); |
9c065a7d SV |
672 | |
673 | i915_redisable_vga_power_on(dev_priv->dev); | |
674 | } | |
675 | ||
676 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, | |
677 | struct i915_power_well *power_well) | |
678 | { | |
679 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
680 | ||
681 | spin_lock_irq(&dev_priv->irq_lock); | |
682 | valleyview_disable_display_irqs(dev_priv); | |
683 | spin_unlock_irq(&dev_priv->irq_lock); | |
684 | ||
685 | vlv_set_power_well(dev_priv, power_well, false); | |
686 | ||
687 | vlv_power_sequencer_reset(dev_priv); | |
688 | } | |
689 | ||
690 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
691 | struct i915_power_well *power_well) | |
692 | { | |
693 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
694 | ||
695 | /* | |
696 | * Enable the CRI clock source so we can get at the | |
697 | * display and the reference clock for VGA | |
698 | * hotplug / manual detection. | |
699 | */ | |
700 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
701 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
702 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
703 | ||
704 | vlv_set_power_well(dev_priv, power_well, true); | |
705 | ||
706 | /* | |
707 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
708 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
709 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
710 | * b. The other bits such as sfr settings / modesel may all | |
711 | * be set to 0. | |
712 | * | |
713 | * This should only be done on init and resume from S3 with | |
714 | * both PLLs disabled, or we risk losing DPIO and PLL | |
715 | * synchronization. | |
716 | */ | |
717 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
718 | } | |
719 | ||
720 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
721 | struct i915_power_well *power_well) | |
722 | { | |
723 | enum pipe pipe; | |
724 | ||
725 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
726 | ||
727 | for_each_pipe(dev_priv, pipe) | |
728 | assert_pll_disabled(dev_priv, pipe); | |
729 | ||
730 | /* Assert common reset */ | |
731 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
732 | ||
733 | vlv_set_power_well(dev_priv, power_well, false); | |
734 | } | |
735 | ||
736 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
737 | struct i915_power_well *power_well) | |
738 | { | |
739 | enum dpio_phy phy; | |
740 | ||
741 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
742 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
743 | ||
744 | /* | |
745 | * Enable the CRI clock source so we can get at the | |
746 | * display and the reference clock for VGA | |
747 | * hotplug / manual detection. | |
748 | */ | |
749 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
750 | phy = DPIO_PHY0; | |
751 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
752 | DPLL_REFA_CLK_ENABLE_VLV); | |
753 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
754 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
755 | } else { | |
756 | phy = DPIO_PHY1; | |
757 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | | |
758 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
759 | } | |
760 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
761 | vlv_set_power_well(dev_priv, power_well, true); | |
762 | ||
763 | /* Poll for phypwrgood signal */ | |
764 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
765 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
766 | ||
767 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | | |
768 | PHY_COM_LANE_RESET_DEASSERT(phy)); | |
769 | } | |
770 | ||
771 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
772 | struct i915_power_well *power_well) | |
773 | { | |
774 | enum dpio_phy phy; | |
775 | ||
776 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
777 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
778 | ||
779 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
780 | phy = DPIO_PHY0; | |
781 | assert_pll_disabled(dev_priv, PIPE_A); | |
782 | assert_pll_disabled(dev_priv, PIPE_B); | |
783 | } else { | |
784 | phy = DPIO_PHY1; | |
785 | assert_pll_disabled(dev_priv, PIPE_C); | |
786 | } | |
787 | ||
788 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & | |
789 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); | |
790 | ||
791 | vlv_set_power_well(dev_priv, power_well, false); | |
792 | } | |
793 | ||
794 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
795 | struct i915_power_well *power_well) | |
796 | { | |
797 | enum pipe pipe = power_well->data; | |
798 | bool enabled; | |
799 | u32 state, ctrl; | |
800 | ||
801 | mutex_lock(&dev_priv->rps.hw_lock); | |
802 | ||
803 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
804 | /* | |
805 | * We only ever set the power-on and power-gate states, anything | |
806 | * else is unexpected. | |
807 | */ | |
808 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
809 | enabled = state == DP_SSS_PWR_ON(pipe); | |
810 | ||
811 | /* | |
812 | * A transient state at this point would mean some unexpected party | |
813 | * is poking at the power controls too. | |
814 | */ | |
815 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
816 | WARN_ON(ctrl << 16 != state); | |
817 | ||
818 | mutex_unlock(&dev_priv->rps.hw_lock); | |
819 | ||
820 | return enabled; | |
821 | } | |
822 | ||
823 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
824 | struct i915_power_well *power_well, | |
825 | bool enable) | |
826 | { | |
827 | enum pipe pipe = power_well->data; | |
828 | u32 state; | |
829 | u32 ctrl; | |
830 | ||
831 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
832 | ||
833 | mutex_lock(&dev_priv->rps.hw_lock); | |
834 | ||
835 | #define COND \ | |
836 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
837 | ||
838 | if (COND) | |
839 | goto out; | |
840 | ||
841 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
842 | ctrl &= ~DP_SSC_MASK(pipe); | |
843 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
844 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
845 | ||
846 | if (wait_for(COND, 100)) | |
847 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
848 | state, | |
849 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
850 | ||
851 | #undef COND | |
852 | ||
853 | out: | |
854 | mutex_unlock(&dev_priv->rps.hw_lock); | |
855 | } | |
856 | ||
857 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
858 | struct i915_power_well *power_well) | |
859 | { | |
860 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); | |
861 | } | |
862 | ||
863 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
864 | struct i915_power_well *power_well) | |
865 | { | |
866 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
867 | power_well->data != PIPE_B && | |
868 | power_well->data != PIPE_C); | |
869 | ||
870 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d VS |
871 | |
872 | if (power_well->data == PIPE_A) { | |
873 | spin_lock_irq(&dev_priv->irq_lock); | |
874 | valleyview_enable_display_irqs(dev_priv); | |
875 | spin_unlock_irq(&dev_priv->irq_lock); | |
876 | ||
877 | /* | |
878 | * During driver initialization/resume we can avoid restoring the | |
879 | * part of the HW/SW state that will be inited anyway explicitly. | |
880 | */ | |
881 | if (dev_priv->power_domains.initializing) | |
882 | return; | |
883 | ||
884 | intel_hpd_init(dev_priv); | |
885 | ||
886 | i915_redisable_vga_power_on(dev_priv->dev); | |
887 | } | |
9c065a7d SV |
888 | } |
889 | ||
890 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
891 | struct i915_power_well *power_well) | |
892 | { | |
893 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
894 | power_well->data != PIPE_B && | |
895 | power_well->data != PIPE_C); | |
896 | ||
afd6275d VS |
897 | if (power_well->data == PIPE_A) { |
898 | spin_lock_irq(&dev_priv->irq_lock); | |
899 | valleyview_disable_display_irqs(dev_priv); | |
900 | spin_unlock_irq(&dev_priv->irq_lock); | |
901 | } | |
902 | ||
9c065a7d | 903 | chv_set_pipe_power_well(dev_priv, power_well, false); |
baa4e575 VS |
904 | |
905 | if (power_well->data == PIPE_A) | |
906 | vlv_power_sequencer_reset(dev_priv); | |
9c065a7d SV |
907 | } |
908 | ||
e4e7684f SV |
909 | /** |
910 | * intel_display_power_get - grab a power domain reference | |
911 | * @dev_priv: i915 device instance | |
912 | * @domain: power domain to reference | |
913 | * | |
914 | * This function grabs a power domain reference for @domain and ensures that the | |
915 | * power domain and all its parents are powered up. Therefore users should only | |
916 | * grab a reference to the innermost power domain they need. | |
917 | * | |
918 | * Any power domain reference obtained by this function must have a symmetric | |
919 | * call to intel_display_power_put() to release the reference again. | |
920 | */ | |
9c065a7d SV |
921 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
922 | enum intel_display_power_domain domain) | |
923 | { | |
924 | struct i915_power_domains *power_domains; | |
925 | struct i915_power_well *power_well; | |
926 | int i; | |
927 | ||
928 | intel_runtime_pm_get(dev_priv); | |
929 | ||
930 | power_domains = &dev_priv->power_domains; | |
931 | ||
932 | mutex_lock(&power_domains->lock); | |
933 | ||
934 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
935 | if (!power_well->count++) { | |
936 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
937 | power_well->ops->enable(dev_priv, power_well); | |
938 | power_well->hw_enabled = true; | |
939 | } | |
9c065a7d SV |
940 | } |
941 | ||
942 | power_domains->domain_use_count[domain]++; | |
943 | ||
944 | mutex_unlock(&power_domains->lock); | |
945 | } | |
946 | ||
e4e7684f SV |
947 | /** |
948 | * intel_display_power_put - release a power domain reference | |
949 | * @dev_priv: i915 device instance | |
950 | * @domain: power domain to reference | |
951 | * | |
952 | * This function drops the power domain reference obtained by | |
953 | * intel_display_power_get() and might power down the corresponding hardware | |
954 | * block right away if this is the last reference. | |
955 | */ | |
9c065a7d SV |
956 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
957 | enum intel_display_power_domain domain) | |
958 | { | |
959 | struct i915_power_domains *power_domains; | |
960 | struct i915_power_well *power_well; | |
961 | int i; | |
962 | ||
963 | power_domains = &dev_priv->power_domains; | |
964 | ||
965 | mutex_lock(&power_domains->lock); | |
966 | ||
967 | WARN_ON(!power_domains->domain_use_count[domain]); | |
968 | power_domains->domain_use_count[domain]--; | |
969 | ||
970 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
971 | WARN_ON(!power_well->count); | |
972 | ||
973 | if (!--power_well->count && i915.disable_power_well) { | |
974 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
975 | power_well->hw_enabled = false; | |
976 | power_well->ops->disable(dev_priv, power_well); | |
977 | } | |
9c065a7d SV |
978 | } |
979 | ||
980 | mutex_unlock(&power_domains->lock); | |
981 | ||
982 | intel_runtime_pm_put(dev_priv); | |
983 | } | |
984 | ||
985 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) | |
986 | ||
987 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
988 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
989 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
990 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
991 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
992 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
993 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
994 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
995 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
996 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
997 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
998 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
999 | BIT(POWER_DOMAIN_PLLS) | \ | |
1407121a S |
1000 | BIT(POWER_DOMAIN_AUX_A) | \ |
1001 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1002 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1003 | BIT(POWER_DOMAIN_AUX_D) | \ | |
9c065a7d SV |
1004 | BIT(POWER_DOMAIN_INIT)) |
1005 | #define HSW_DISPLAY_POWER_DOMAINS ( \ | |
1006 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1007 | BIT(POWER_DOMAIN_INIT)) | |
1008 | ||
1009 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1010 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
1011 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
1012 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
1013 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1014 | BIT(POWER_DOMAIN_INIT)) | |
1015 | ||
1016 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) | |
1017 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
1018 | ||
1019 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
1020 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1021 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1022 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1023 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1024 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1407121a S |
1025 | BIT(POWER_DOMAIN_AUX_B) | \ |
1026 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d SV |
1027 | BIT(POWER_DOMAIN_INIT)) |
1028 | ||
1029 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
1030 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1031 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1032 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d SV |
1033 | BIT(POWER_DOMAIN_INIT)) |
1034 | ||
1035 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
1036 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1037 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d SV |
1038 | BIT(POWER_DOMAIN_INIT)) |
1039 | ||
1040 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
1041 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1042 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1043 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d SV |
1044 | BIT(POWER_DOMAIN_INIT)) |
1045 | ||
1046 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
1047 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1048 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d SV |
1049 | BIT(POWER_DOMAIN_INIT)) |
1050 | ||
1051 | #define CHV_PIPE_A_POWER_DOMAINS ( \ | |
1052 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1053 | BIT(POWER_DOMAIN_INIT)) | |
1054 | ||
1055 | #define CHV_PIPE_B_POWER_DOMAINS ( \ | |
1056 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
1057 | BIT(POWER_DOMAIN_INIT)) | |
1058 | ||
1059 | #define CHV_PIPE_C_POWER_DOMAINS ( \ | |
1060 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
1061 | BIT(POWER_DOMAIN_INIT)) | |
1062 | ||
1063 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
1064 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1065 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1066 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1067 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a S |
1068 | BIT(POWER_DOMAIN_AUX_B) | \ |
1069 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d SV |
1070 | BIT(POWER_DOMAIN_INIT)) |
1071 | ||
1072 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
1073 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1074 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 1075 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d SV |
1076 | BIT(POWER_DOMAIN_INIT)) |
1077 | ||
1078 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ | |
1079 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1080 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 1081 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d SV |
1082 | BIT(POWER_DOMAIN_INIT)) |
1083 | ||
1084 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ | |
1085 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 1086 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d SV |
1087 | BIT(POWER_DOMAIN_INIT)) |
1088 | ||
1089 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { | |
1090 | .sync_hw = i9xx_always_on_power_well_noop, | |
1091 | .enable = i9xx_always_on_power_well_noop, | |
1092 | .disable = i9xx_always_on_power_well_noop, | |
1093 | .is_enabled = i9xx_always_on_power_well_enabled, | |
1094 | }; | |
1095 | ||
1096 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
1097 | .sync_hw = chv_pipe_power_well_sync_hw, | |
1098 | .enable = chv_pipe_power_well_enable, | |
1099 | .disable = chv_pipe_power_well_disable, | |
1100 | .is_enabled = chv_pipe_power_well_enabled, | |
1101 | }; | |
1102 | ||
1103 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
1104 | .sync_hw = vlv_power_well_sync_hw, | |
1105 | .enable = chv_dpio_cmn_power_well_enable, | |
1106 | .disable = chv_dpio_cmn_power_well_disable, | |
1107 | .is_enabled = vlv_power_well_enabled, | |
1108 | }; | |
1109 | ||
1110 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
1111 | { | |
1112 | .name = "always-on", | |
1113 | .always_on = 1, | |
1114 | .domains = POWER_DOMAIN_MASK, | |
1115 | .ops = &i9xx_always_on_power_well_ops, | |
1116 | }, | |
1117 | }; | |
1118 | ||
1119 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
1120 | .sync_hw = hsw_power_well_sync_hw, | |
1121 | .enable = hsw_power_well_enable, | |
1122 | .disable = hsw_power_well_disable, | |
1123 | .is_enabled = hsw_power_well_enabled, | |
1124 | }; | |
1125 | ||
94dd5138 S |
1126 | static const struct i915_power_well_ops skl_power_well_ops = { |
1127 | .sync_hw = skl_power_well_sync_hw, | |
1128 | .enable = skl_power_well_enable, | |
1129 | .disable = skl_power_well_disable, | |
1130 | .is_enabled = skl_power_well_enabled, | |
1131 | }; | |
1132 | ||
9c065a7d SV |
1133 | static struct i915_power_well hsw_power_wells[] = { |
1134 | { | |
1135 | .name = "always-on", | |
1136 | .always_on = 1, | |
1137 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
1138 | .ops = &i9xx_always_on_power_well_ops, | |
1139 | }, | |
1140 | { | |
1141 | .name = "display", | |
1142 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1143 | .ops = &hsw_power_well_ops, | |
1144 | }, | |
1145 | }; | |
1146 | ||
1147 | static struct i915_power_well bdw_power_wells[] = { | |
1148 | { | |
1149 | .name = "always-on", | |
1150 | .always_on = 1, | |
1151 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
1152 | .ops = &i9xx_always_on_power_well_ops, | |
1153 | }, | |
1154 | { | |
1155 | .name = "display", | |
1156 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1157 | .ops = &hsw_power_well_ops, | |
1158 | }, | |
1159 | }; | |
1160 | ||
1161 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1162 | .sync_hw = vlv_power_well_sync_hw, | |
1163 | .enable = vlv_display_power_well_enable, | |
1164 | .disable = vlv_display_power_well_disable, | |
1165 | .is_enabled = vlv_power_well_enabled, | |
1166 | }; | |
1167 | ||
1168 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1169 | .sync_hw = vlv_power_well_sync_hw, | |
1170 | .enable = vlv_dpio_cmn_power_well_enable, | |
1171 | .disable = vlv_dpio_cmn_power_well_disable, | |
1172 | .is_enabled = vlv_power_well_enabled, | |
1173 | }; | |
1174 | ||
1175 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1176 | .sync_hw = vlv_power_well_sync_hw, | |
1177 | .enable = vlv_power_well_enable, | |
1178 | .disable = vlv_power_well_disable, | |
1179 | .is_enabled = vlv_power_well_enabled, | |
1180 | }; | |
1181 | ||
1182 | static struct i915_power_well vlv_power_wells[] = { | |
1183 | { | |
1184 | .name = "always-on", | |
1185 | .always_on = 1, | |
1186 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1187 | .ops = &i9xx_always_on_power_well_ops, | |
1188 | }, | |
1189 | { | |
1190 | .name = "display", | |
1191 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1192 | .data = PUNIT_POWER_WELL_DISP2D, | |
1193 | .ops = &vlv_display_power_well_ops, | |
1194 | }, | |
1195 | { | |
1196 | .name = "dpio-tx-b-01", | |
1197 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1198 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1199 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1200 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1201 | .ops = &vlv_dpio_power_well_ops, | |
1202 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1203 | }, | |
1204 | { | |
1205 | .name = "dpio-tx-b-23", | |
1206 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1207 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1208 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1209 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1210 | .ops = &vlv_dpio_power_well_ops, | |
1211 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1212 | }, | |
1213 | { | |
1214 | .name = "dpio-tx-c-01", | |
1215 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1216 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1217 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1218 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1219 | .ops = &vlv_dpio_power_well_ops, | |
1220 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1221 | }, | |
1222 | { | |
1223 | .name = "dpio-tx-c-23", | |
1224 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1225 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1226 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1227 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1228 | .ops = &vlv_dpio_power_well_ops, | |
1229 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1230 | }, | |
1231 | { | |
1232 | .name = "dpio-common", | |
1233 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1234 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1235 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1236 | }, | |
1237 | }; | |
1238 | ||
1239 | static struct i915_power_well chv_power_wells[] = { | |
1240 | { | |
1241 | .name = "always-on", | |
1242 | .always_on = 1, | |
1243 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1244 | .ops = &i9xx_always_on_power_well_ops, | |
1245 | }, | |
1246 | #if 0 | |
1247 | { | |
1248 | .name = "display", | |
1249 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1250 | .data = PUNIT_POWER_WELL_DISP2D, | |
1251 | .ops = &vlv_display_power_well_ops, | |
1252 | }, | |
baa4e575 | 1253 | #endif |
9c065a7d SV |
1254 | { |
1255 | .name = "pipe-a", | |
baa4e575 VS |
1256 | /* |
1257 | * FIXME: pipe A power well seems to be the new disp2d well. | |
1258 | * At least all registers seem to be housed there. Figure | |
1259 | * out if this a a temporary situation in pre-production | |
1260 | * hardware or a permanent state of affairs. | |
1261 | */ | |
1262 | .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, | |
9c065a7d SV |
1263 | .data = PIPE_A, |
1264 | .ops = &chv_pipe_power_well_ops, | |
1265 | }, | |
baa4e575 | 1266 | #if 0 |
9c065a7d SV |
1267 | { |
1268 | .name = "pipe-b", | |
1269 | .domains = CHV_PIPE_B_POWER_DOMAINS, | |
1270 | .data = PIPE_B, | |
1271 | .ops = &chv_pipe_power_well_ops, | |
1272 | }, | |
1273 | { | |
1274 | .name = "pipe-c", | |
1275 | .domains = CHV_PIPE_C_POWER_DOMAINS, | |
1276 | .data = PIPE_C, | |
1277 | .ops = &chv_pipe_power_well_ops, | |
1278 | }, | |
1279 | #endif | |
1280 | { | |
1281 | .name = "dpio-common-bc", | |
1282 | /* | |
1283 | * XXX: cmnreset for one PHY seems to disturb the other. | |
1284 | * As a workaround keep both powered on at the same | |
1285 | * time for now. | |
1286 | */ | |
1287 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
1288 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1289 | .ops = &chv_dpio_cmn_power_well_ops, | |
1290 | }, | |
1291 | { | |
1292 | .name = "dpio-common-d", | |
1293 | /* | |
1294 | * XXX: cmnreset for one PHY seems to disturb the other. | |
1295 | * As a workaround keep both powered on at the same | |
1296 | * time for now. | |
1297 | */ | |
1298 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
1299 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, | |
1300 | .ops = &chv_dpio_cmn_power_well_ops, | |
1301 | }, | |
1302 | #if 0 | |
1303 | { | |
1304 | .name = "dpio-tx-b-01", | |
1305 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1306 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
1307 | .ops = &vlv_dpio_power_well_ops, | |
1308 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1309 | }, | |
1310 | { | |
1311 | .name = "dpio-tx-b-23", | |
1312 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1313 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
1314 | .ops = &vlv_dpio_power_well_ops, | |
1315 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1316 | }, | |
1317 | { | |
1318 | .name = "dpio-tx-c-01", | |
1319 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1320 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1321 | .ops = &vlv_dpio_power_well_ops, | |
1322 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1323 | }, | |
1324 | { | |
1325 | .name = "dpio-tx-c-23", | |
1326 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1327 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1328 | .ops = &vlv_dpio_power_well_ops, | |
1329 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1330 | }, | |
1331 | { | |
1332 | .name = "dpio-tx-d-01", | |
1333 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
1334 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
1335 | .ops = &vlv_dpio_power_well_ops, | |
1336 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, | |
1337 | }, | |
1338 | { | |
1339 | .name = "dpio-tx-d-23", | |
1340 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
1341 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
1342 | .ops = &vlv_dpio_power_well_ops, | |
1343 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, | |
1344 | }, | |
1345 | #endif | |
1346 | }; | |
1347 | ||
1348 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
1349 | enum punit_power_well power_well_id) | |
1350 | { | |
1351 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1352 | struct i915_power_well *power_well; | |
1353 | int i; | |
1354 | ||
1355 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1356 | if (power_well->data == power_well_id) | |
1357 | return power_well; | |
1358 | } | |
1359 | ||
1360 | return NULL; | |
1361 | } | |
1362 | ||
94dd5138 S |
1363 | static struct i915_power_well skl_power_wells[] = { |
1364 | { | |
1365 | .name = "always-on", | |
1366 | .always_on = 1, | |
1367 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1368 | .ops = &i9xx_always_on_power_well_ops, | |
1369 | }, | |
1370 | { | |
1371 | .name = "power well 1", | |
1372 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1373 | .ops = &skl_power_well_ops, | |
1374 | .data = SKL_DISP_PW_1, | |
1375 | }, | |
1376 | { | |
1377 | .name = "MISC IO power well", | |
1378 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, | |
1379 | .ops = &skl_power_well_ops, | |
1380 | .data = SKL_DISP_PW_MISC_IO, | |
1381 | }, | |
1382 | { | |
1383 | .name = "power well 2", | |
1384 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1385 | .ops = &skl_power_well_ops, | |
1386 | .data = SKL_DISP_PW_2, | |
1387 | }, | |
1388 | { | |
1389 | .name = "DDI A/E power well", | |
1390 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1391 | .ops = &skl_power_well_ops, | |
1392 | .data = SKL_DISP_PW_DDI_A_E, | |
1393 | }, | |
1394 | { | |
1395 | .name = "DDI B power well", | |
1396 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1397 | .ops = &skl_power_well_ops, | |
1398 | .data = SKL_DISP_PW_DDI_B, | |
1399 | }, | |
1400 | { | |
1401 | .name = "DDI C power well", | |
1402 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1403 | .ops = &skl_power_well_ops, | |
1404 | .data = SKL_DISP_PW_DDI_C, | |
1405 | }, | |
1406 | { | |
1407 | .name = "DDI D power well", | |
1408 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1409 | .ops = &skl_power_well_ops, | |
1410 | .data = SKL_DISP_PW_DDI_D, | |
1411 | }, | |
1412 | }; | |
1413 | ||
0b4a2a36 S |
1414 | static struct i915_power_well bxt_power_wells[] = { |
1415 | { | |
1416 | .name = "always-on", | |
1417 | .always_on = 1, | |
1418 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1419 | .ops = &i9xx_always_on_power_well_ops, | |
1420 | }, | |
1421 | { | |
1422 | .name = "power well 1", | |
1423 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1424 | .ops = &skl_power_well_ops, | |
1425 | .data = SKL_DISP_PW_1, | |
1426 | }, | |
1427 | { | |
1428 | .name = "power well 2", | |
1429 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1430 | .ops = &skl_power_well_ops, | |
1431 | .data = SKL_DISP_PW_2, | |
1432 | } | |
1433 | }; | |
1434 | ||
9c065a7d SV |
1435 | #define set_power_wells(power_domains, __power_wells) ({ \ |
1436 | (power_domains)->power_wells = (__power_wells); \ | |
1437 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
1438 | }) | |
1439 | ||
e4e7684f SV |
1440 | /** |
1441 | * intel_power_domains_init - initializes the power domain structures | |
1442 | * @dev_priv: i915 device instance | |
1443 | * | |
1444 | * Initializes the power domain structures for @dev_priv depending upon the | |
1445 | * supported platform. | |
1446 | */ | |
9c065a7d SV |
1447 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1448 | { | |
1449 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1450 | ||
1451 | mutex_init(&power_domains->lock); | |
1452 | ||
1453 | /* | |
1454 | * The enabling order will be from lower to higher indexed wells, | |
1455 | * the disabling order is reversed. | |
1456 | */ | |
1457 | if (IS_HASWELL(dev_priv->dev)) { | |
1458 | set_power_wells(power_domains, hsw_power_wells); | |
9c065a7d SV |
1459 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1460 | set_power_wells(power_domains, bdw_power_wells); | |
94dd5138 S |
1461 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
1462 | set_power_wells(power_domains, skl_power_wells); | |
0b4a2a36 S |
1463 | } else if (IS_BROXTON(dev_priv->dev)) { |
1464 | set_power_wells(power_domains, bxt_power_wells); | |
9c065a7d SV |
1465 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1466 | set_power_wells(power_domains, chv_power_wells); | |
1467 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { | |
1468 | set_power_wells(power_domains, vlv_power_wells); | |
1469 | } else { | |
1470 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
1471 | } | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
41373cd5 SV |
1476 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
1477 | { | |
1478 | struct drm_device *dev = dev_priv->dev; | |
1479 | struct device *device = &dev->pdev->dev; | |
1480 | ||
1481 | if (!HAS_RUNTIME_PM(dev)) | |
1482 | return; | |
1483 | ||
1484 | if (!intel_enable_rc6(dev)) | |
1485 | return; | |
1486 | ||
1487 | /* Make sure we're not suspended first. */ | |
1488 | pm_runtime_get_sync(device); | |
1489 | pm_runtime_disable(device); | |
1490 | } | |
1491 | ||
e4e7684f SV |
1492 | /** |
1493 | * intel_power_domains_fini - finalizes the power domain structures | |
1494 | * @dev_priv: i915 device instance | |
1495 | * | |
1496 | * Finalizes the power domain structures for @dev_priv depending upon the | |
1497 | * supported platform. This function also disables runtime pm and ensures that | |
1498 | * the device stays powered up so that the driver can be reloaded. | |
1499 | */ | |
f458ebbc | 1500 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 1501 | { |
41373cd5 SV |
1502 | intel_runtime_pm_disable(dev_priv); |
1503 | ||
f458ebbc SV |
1504 | /* The i915.ko module is still not prepared to be loaded when |
1505 | * the power well is not enabled, so just enable it in case | |
1506 | * we're going to unload/reload. */ | |
1507 | intel_display_set_init_power(dev_priv, true); | |
9c065a7d SV |
1508 | } |
1509 | ||
1510 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) | |
1511 | { | |
1512 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1513 | struct i915_power_well *power_well; | |
1514 | int i; | |
1515 | ||
1516 | mutex_lock(&power_domains->lock); | |
1517 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1518 | power_well->ops->sync_hw(dev_priv, power_well); | |
1519 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
1520 | power_well); | |
1521 | } | |
1522 | mutex_unlock(&power_domains->lock); | |
1523 | } | |
1524 | ||
1525 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) | |
1526 | { | |
1527 | struct i915_power_well *cmn = | |
1528 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1529 | struct i915_power_well *disp2d = | |
1530 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
1531 | ||
9c065a7d | 1532 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
1533 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
1534 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d SV |
1535 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1536 | return; | |
1537 | ||
1538 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
1539 | ||
1540 | /* cmnlane needs DPLL registers */ | |
1541 | disp2d->ops->enable(dev_priv, disp2d); | |
1542 | ||
1543 | /* | |
1544 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1545 | * Need to assert and de-assert PHY SB reset by gating the | |
1546 | * common lane power, then un-gating it. | |
1547 | * Simply ungating isn't enough to reset the PHY enough to get | |
1548 | * ports and lanes running. | |
1549 | */ | |
1550 | cmn->ops->disable(dev_priv, cmn); | |
1551 | } | |
1552 | ||
e4e7684f SV |
1553 | /** |
1554 | * intel_power_domains_init_hw - initialize hardware power domain state | |
1555 | * @dev_priv: i915 device instance | |
1556 | * | |
1557 | * This function initializes the hardware power domain state and enables all | |
1558 | * power domains using intel_display_set_init_power(). | |
1559 | */ | |
9c065a7d SV |
1560 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
1561 | { | |
1562 | struct drm_device *dev = dev_priv->dev; | |
1563 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1564 | ||
1565 | power_domains->initializing = true; | |
1566 | ||
1567 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
1568 | mutex_lock(&power_domains->lock); | |
1569 | vlv_cmnlane_wa(dev_priv); | |
1570 | mutex_unlock(&power_domains->lock); | |
1571 | } | |
1572 | ||
1573 | /* For now, we need the power well to be always enabled. */ | |
1574 | intel_display_set_init_power(dev_priv, true); | |
1575 | intel_power_domains_resume(dev_priv); | |
1576 | power_domains->initializing = false; | |
1577 | } | |
1578 | ||
e4e7684f | 1579 | /** |
ca2b1403 | 1580 | * intel_aux_display_runtime_get - grab an auxiliary power domain reference |
e4e7684f SV |
1581 | * @dev_priv: i915 device instance |
1582 | * | |
1583 | * This function grabs a power domain reference for the auxiliary power domain | |
1584 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its | |
1585 | * parents are powered up. Therefore users should only grab a reference to the | |
1586 | * innermost power domain they need. | |
1587 | * | |
1588 | * Any power domain reference obtained by this function must have a symmetric | |
1589 | * call to intel_aux_display_runtime_put() to release the reference again. | |
1590 | */ | |
9c065a7d SV |
1591 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
1592 | { | |
1593 | intel_runtime_pm_get(dev_priv); | |
1594 | } | |
1595 | ||
e4e7684f | 1596 | /** |
ca2b1403 | 1597 | * intel_aux_display_runtime_put - release an auxiliary power domain reference |
e4e7684f SV |
1598 | * @dev_priv: i915 device instance |
1599 | * | |
ca2b1403 | 1600 | * This function drops the auxiliary power domain reference obtained by |
e4e7684f SV |
1601 | * intel_aux_display_runtime_get() and might power down the corresponding |
1602 | * hardware block right away if this is the last reference. | |
1603 | */ | |
9c065a7d SV |
1604 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
1605 | { | |
1606 | intel_runtime_pm_put(dev_priv); | |
1607 | } | |
1608 | ||
e4e7684f SV |
1609 | /** |
1610 | * intel_runtime_pm_get - grab a runtime pm reference | |
1611 | * @dev_priv: i915 device instance | |
1612 | * | |
1613 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1614 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
1615 | * | |
1616 | * Any runtime pm reference obtained by this function must have a symmetric | |
1617 | * call to intel_runtime_pm_put() to release the reference again. | |
1618 | */ | |
9c065a7d SV |
1619 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
1620 | { | |
1621 | struct drm_device *dev = dev_priv->dev; | |
1622 | struct device *device = &dev->pdev->dev; | |
1623 | ||
1624 | if (!HAS_RUNTIME_PM(dev)) | |
1625 | return; | |
1626 | ||
1627 | pm_runtime_get_sync(device); | |
1628 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
1629 | } | |
1630 | ||
e4e7684f SV |
1631 | /** |
1632 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
1633 | * @dev_priv: i915 device instance | |
1634 | * | |
1635 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1636 | * code to ensure the GTT or GT is on). | |
1637 | * | |
1638 | * It will _not_ power up the device but instead only check that it's powered | |
1639 | * on. Therefore it is only valid to call this functions from contexts where | |
1640 | * the device is known to be powered up and where trying to power it up would | |
1641 | * result in hilarity and deadlocks. That pretty much means only the system | |
1642 | * suspend/resume code where this is used to grab runtime pm references for | |
1643 | * delayed setup down in work items. | |
1644 | * | |
1645 | * Any runtime pm reference obtained by this function must have a symmetric | |
1646 | * call to intel_runtime_pm_put() to release the reference again. | |
1647 | */ | |
9c065a7d SV |
1648 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
1649 | { | |
1650 | struct drm_device *dev = dev_priv->dev; | |
1651 | struct device *device = &dev->pdev->dev; | |
1652 | ||
1653 | if (!HAS_RUNTIME_PM(dev)) | |
1654 | return; | |
1655 | ||
1656 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
1657 | pm_runtime_get_noresume(device); | |
1658 | } | |
1659 | ||
e4e7684f SV |
1660 | /** |
1661 | * intel_runtime_pm_put - release a runtime pm reference | |
1662 | * @dev_priv: i915 device instance | |
1663 | * | |
1664 | * This function drops the device-level runtime pm reference obtained by | |
1665 | * intel_runtime_pm_get() and might power down the corresponding | |
1666 | * hardware block right away if this is the last reference. | |
1667 | */ | |
9c065a7d SV |
1668 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
1669 | { | |
1670 | struct drm_device *dev = dev_priv->dev; | |
1671 | struct device *device = &dev->pdev->dev; | |
1672 | ||
1673 | if (!HAS_RUNTIME_PM(dev)) | |
1674 | return; | |
1675 | ||
1676 | pm_runtime_mark_last_busy(device); | |
1677 | pm_runtime_put_autosuspend(device); | |
1678 | } | |
1679 | ||
e4e7684f SV |
1680 | /** |
1681 | * intel_runtime_pm_enable - enable runtime pm | |
1682 | * @dev_priv: i915 device instance | |
1683 | * | |
1684 | * This function enables runtime pm at the end of the driver load sequence. | |
1685 | * | |
1686 | * Note that this function does currently not enable runtime pm for the | |
1687 | * subordinate display power domains. That is only done on the first modeset | |
1688 | * using intel_display_set_init_power(). | |
1689 | */ | |
f458ebbc | 1690 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d SV |
1691 | { |
1692 | struct drm_device *dev = dev_priv->dev; | |
1693 | struct device *device = &dev->pdev->dev; | |
1694 | ||
1695 | if (!HAS_RUNTIME_PM(dev)) | |
1696 | return; | |
1697 | ||
1698 | pm_runtime_set_active(device); | |
1699 | ||
1700 | /* | |
1701 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
1702 | * requirement. | |
1703 | */ | |
1704 | if (!intel_enable_rc6(dev)) { | |
1705 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
1706 | return; | |
1707 | } | |
1708 | ||
1709 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
1710 | pm_runtime_mark_last_busy(device); | |
1711 | pm_runtime_use_autosuspend(device); | |
1712 | ||
1713 | pm_runtime_put_autosuspend(device); | |
1714 | } | |
1715 |