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72341af4 JN |
1 | /* |
2 | * Copyright © 2006-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This information is private to VBT parsing in intel_bios.c. | |
30 | * | |
31 | * Please do NOT include anywhere else. | |
32 | */ | |
33 | #ifndef _INTEL_BIOS_PRIVATE | |
34 | #error "intel_vbt_defs.h is private to intel_bios.c" | |
35 | #endif | |
36 | ||
37 | #ifndef _INTEL_VBT_DEFS_H_ | |
38 | #define _INTEL_VBT_DEFS_H_ | |
39 | ||
40 | #include "intel_bios.h" | |
41 | ||
42 | /** | |
43 | * struct vbt_header - VBT Header structure | |
44 | * @signature: VBT signature, always starts with "$VBT" | |
45 | * @version: Version of this structure | |
46 | * @header_size: Size of this structure | |
47 | * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) | |
48 | * @vbt_checksum: Checksum | |
49 | * @reserved0: Reserved | |
50 | * @bdb_offset: Offset of &struct bdb_header from beginning of VBT | |
51 | * @aim_offset: Offsets of add-in data blocks from beginning of VBT | |
52 | */ | |
53 | struct vbt_header { | |
54 | u8 signature[20]; | |
55 | u16 version; | |
56 | u16 header_size; | |
57 | u16 vbt_size; | |
58 | u8 vbt_checksum; | |
59 | u8 reserved0; | |
60 | u32 bdb_offset; | |
61 | u32 aim_offset[4]; | |
62 | } __packed; | |
63 | ||
64 | /** | |
65 | * struct bdb_header - BDB Header structure | |
66 | * @signature: BDB signature "BIOS_DATA_BLOCK" | |
67 | * @version: Version of the data block definitions | |
68 | * @header_size: Size of this structure | |
69 | * @bdb_size: Size of BDB (BDB Header and data blocks) | |
70 | */ | |
71 | struct bdb_header { | |
72 | u8 signature[16]; | |
73 | u16 version; | |
74 | u16 header_size; | |
75 | u16 bdb_size; | |
76 | } __packed; | |
77 | ||
78 | /* strictly speaking, this is a "skip" block, but it has interesting info */ | |
79 | struct vbios_data { | |
80 | u8 type; /* 0 == desktop, 1 == mobile */ | |
81 | u8 relstage; | |
82 | u8 chipset; | |
83 | u8 lvds_present:1; | |
84 | u8 tv_present:1; | |
85 | u8 rsvd2:6; /* finish byte */ | |
86 | u8 rsvd3[4]; | |
87 | u8 signon[155]; | |
88 | u8 copyright[61]; | |
89 | u16 code_segment; | |
90 | u8 dos_boot_mode; | |
91 | u8 bandwidth_percent; | |
92 | u8 rsvd4; /* popup memory size */ | |
93 | u8 resize_pci_bios; | |
94 | u8 rsvd5; /* is crt already on ddc2 */ | |
95 | } __packed; | |
96 | ||
97 | /* | |
98 | * There are several types of BIOS data blocks (BDBs), each block has | |
99 | * an ID and size in the first 3 bytes (ID in first, size in next 2). | |
100 | * Known types are listed below. | |
101 | */ | |
102 | #define BDB_GENERAL_FEATURES 1 | |
103 | #define BDB_GENERAL_DEFINITIONS 2 | |
104 | #define BDB_OLD_TOGGLE_LIST 3 | |
105 | #define BDB_MODE_SUPPORT_LIST 4 | |
106 | #define BDB_GENERIC_MODE_TABLE 5 | |
107 | #define BDB_EXT_MMIO_REGS 6 | |
108 | #define BDB_SWF_IO 7 | |
109 | #define BDB_SWF_MMIO 8 | |
110 | #define BDB_PSR 9 | |
111 | #define BDB_MODE_REMOVAL_TABLE 10 | |
112 | #define BDB_CHILD_DEVICE_TABLE 11 | |
113 | #define BDB_DRIVER_FEATURES 12 | |
114 | #define BDB_DRIVER_PERSISTENCE 13 | |
115 | #define BDB_EXT_TABLE_PTRS 14 | |
116 | #define BDB_DOT_CLOCK_OVERRIDE 15 | |
117 | #define BDB_DISPLAY_SELECT 16 | |
118 | /* 17 rsvd */ | |
119 | #define BDB_DRIVER_ROTATION 18 | |
120 | #define BDB_DISPLAY_REMOVE 19 | |
121 | #define BDB_OEM_CUSTOM 20 | |
122 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ | |
123 | #define BDB_SDVO_LVDS_OPTIONS 22 | |
124 | #define BDB_SDVO_PANEL_DTDS 23 | |
125 | #define BDB_SDVO_LVDS_PNP_IDS 24 | |
126 | #define BDB_SDVO_LVDS_POWER_SEQ 25 | |
127 | #define BDB_TV_OPTIONS 26 | |
128 | #define BDB_EDP 27 | |
129 | #define BDB_LVDS_OPTIONS 40 | |
130 | #define BDB_LVDS_LFP_DATA_PTRS 41 | |
131 | #define BDB_LVDS_LFP_DATA 42 | |
132 | #define BDB_LVDS_BACKLIGHT 43 | |
133 | #define BDB_LVDS_POWER 44 | |
134 | #define BDB_MIPI_CONFIG 52 | |
135 | #define BDB_MIPI_SEQUENCE 53 | |
136 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ | |
137 | ||
138 | struct bdb_general_features { | |
139 | /* bits 1 */ | |
140 | u8 panel_fitting:2; | |
141 | u8 flexaim:1; | |
142 | u8 msg_enable:1; | |
143 | u8 clear_screen:3; | |
144 | u8 color_flip:1; | |
145 | ||
146 | /* bits 2 */ | |
147 | u8 download_ext_vbt:1; | |
148 | u8 enable_ssc:1; | |
149 | u8 ssc_freq:1; | |
150 | u8 enable_lfp_on_override:1; | |
151 | u8 disable_ssc_ddt:1; | |
e445dd18 | 152 | u8 underscan_vga_timings:1; |
72341af4 | 153 | u8 display_clock_mode:1; |
e445dd18 | 154 | u8 vbios_hotplug_support:1; |
72341af4 JN |
155 | |
156 | /* bits 3 */ | |
157 | u8 disable_smooth_vision:1; | |
158 | u8 single_dvi:1; | |
e445dd18 | 159 | u8 rotate_180:1; /* 181 */ |
72341af4 | 160 | u8 fdi_rx_polarity_inverted:1; |
e445dd18 JN |
161 | u8 vbios_extended_mode:1; /* 160 */ |
162 | u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ | |
163 | u8 panel_best_fit_timing:1; /* 160 */ | |
164 | u8 ignore_strap_state:1; /* 160 */ | |
72341af4 JN |
165 | |
166 | /* bits 4 */ | |
167 | u8 legacy_monitor_detect; | |
168 | ||
169 | /* bits 5 */ | |
170 | u8 int_crt_support:1; | |
171 | u8 int_tv_support:1; | |
172 | u8 int_efp_support:1; | |
e445dd18 | 173 | u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ |
72341af4 | 174 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
e445dd18 JN |
175 | u8 dp_ssc_dongle_supported:1; |
176 | u8 rsvd11:2; /* finish byte */ | |
72341af4 JN |
177 | } __packed; |
178 | ||
179 | /* pre-915 */ | |
180 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ | |
181 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ | |
182 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ | |
183 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ | |
184 | ||
185 | /* Pre 915 */ | |
186 | #define DEVICE_TYPE_NONE 0x00 | |
187 | #define DEVICE_TYPE_CRT 0x01 | |
188 | #define DEVICE_TYPE_TV 0x09 | |
189 | #define DEVICE_TYPE_EFP 0x12 | |
190 | #define DEVICE_TYPE_LFP 0x22 | |
191 | /* On 915+ */ | |
192 | #define DEVICE_TYPE_CRT_DPMS 0x6001 | |
193 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 | |
194 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 | |
195 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 | |
196 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c | |
197 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 | |
198 | #define DEVICE_TYPE_TV_SCART 0x0209 | |
199 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 | |
200 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 | |
201 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 | |
202 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 | |
203 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 | |
204 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 | |
205 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 | |
206 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 | |
207 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 | |
208 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 | |
209 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 | |
210 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 | |
211 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 | |
212 | ||
6a794c8a JN |
213 | /* Add the device class for LFP, TV, HDMI */ |
214 | #define DEVICE_TYPE_INT_LFP 0x1022 | |
215 | #define DEVICE_TYPE_INT_TV 0x1009 | |
216 | #define DEVICE_TYPE_HDMI 0x60D2 | |
217 | #define DEVICE_TYPE_DP 0x68C6 | |
218 | #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 | |
219 | #define DEVICE_TYPE_eDP 0x78C6 | |
220 | ||
221 | #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) | |
222 | #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) | |
223 | #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) | |
224 | #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) | |
225 | #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) | |
226 | #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) | |
227 | #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) | |
228 | #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) | |
229 | #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) | |
3cfd3265 | 230 | #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) |
6a794c8a JN |
231 | #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) |
232 | #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) | |
233 | #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) | |
234 | #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) | |
235 | #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) | |
236 | ||
237 | /* | |
238 | * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the | |
239 | * system, the other bits may or may not be set for eDP outputs. | |
240 | */ | |
241 | #define DEVICE_TYPE_eDP_BITS \ | |
242 | (DEVICE_TYPE_INTERNAL_CONNECTOR | \ | |
243 | DEVICE_TYPE_MIPI_OUTPUT | \ | |
244 | DEVICE_TYPE_COMPOSITE_OUTPUT | \ | |
245 | DEVICE_TYPE_DUAL_CHANNEL | \ | |
3cfd3265 | 246 | DEVICE_TYPE_LVDS_SIGNALING | \ |
6a794c8a JN |
247 | DEVICE_TYPE_TMDS_DVI_SIGNALING | \ |
248 | DEVICE_TYPE_VIDEO_SIGNALING | \ | |
249 | DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ | |
250 | DEVICE_TYPE_ANALOG_OUTPUT) | |
251 | ||
252 | #define DEVICE_TYPE_DP_DUAL_MODE_BITS \ | |
253 | (DEVICE_TYPE_INTERNAL_CONNECTOR | \ | |
254 | DEVICE_TYPE_MIPI_OUTPUT | \ | |
255 | DEVICE_TYPE_COMPOSITE_OUTPUT | \ | |
3cfd3265 | 256 | DEVICE_TYPE_LVDS_SIGNALING | \ |
6a794c8a JN |
257 | DEVICE_TYPE_TMDS_DVI_SIGNALING | \ |
258 | DEVICE_TYPE_VIDEO_SIGNALING | \ | |
259 | DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ | |
260 | DEVICE_TYPE_DIGITAL_OUTPUT | \ | |
261 | DEVICE_TYPE_ANALOG_OUTPUT) | |
262 | ||
72341af4 JN |
263 | #define DEVICE_CFG_NONE 0x00 |
264 | #define DEVICE_CFG_12BIT_DVOB 0x01 | |
265 | #define DEVICE_CFG_12BIT_DVOC 0x02 | |
266 | #define DEVICE_CFG_24BIT_DVOBC 0x09 | |
267 | #define DEVICE_CFG_24BIT_DVOCB 0x0a | |
268 | #define DEVICE_CFG_DUAL_DVOB 0x11 | |
269 | #define DEVICE_CFG_DUAL_DVOC 0x12 | |
270 | #define DEVICE_CFG_DUAL_DVOBC 0x13 | |
271 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 | |
272 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a | |
273 | ||
274 | #define DEVICE_WIRE_NONE 0x00 | |
275 | #define DEVICE_WIRE_DVOB 0x01 | |
276 | #define DEVICE_WIRE_DVOC 0x02 | |
277 | #define DEVICE_WIRE_DVOBC 0x03 | |
278 | #define DEVICE_WIRE_DVOBB 0x05 | |
279 | #define DEVICE_WIRE_DVOCC 0x06 | |
280 | #define DEVICE_WIRE_DVOB_MASTER 0x0d | |
281 | #define DEVICE_WIRE_DVOC_MASTER 0x0e | |
282 | ||
fca36df5 | 283 | /* dvo_port pre BDB 155 */ |
72341af4 JN |
284 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
285 | #define DEVICE_PORT_DVOB 0x01 | |
286 | #define DEVICE_PORT_DVOC 0x02 | |
287 | ||
fca36df5 JN |
288 | /* dvo_port BDB 155+ */ |
289 | #define DVO_PORT_HDMIA 0 | |
290 | #define DVO_PORT_HDMIB 1 | |
291 | #define DVO_PORT_HDMIC 2 | |
292 | #define DVO_PORT_HDMID 3 | |
293 | #define DVO_PORT_LVDS 4 | |
294 | #define DVO_PORT_TV 5 | |
295 | #define DVO_PORT_CRT 6 | |
296 | #define DVO_PORT_DPB 7 | |
297 | #define DVO_PORT_DPC 8 | |
298 | #define DVO_PORT_DPD 9 | |
299 | #define DVO_PORT_DPA 10 | |
300 | #define DVO_PORT_DPE 11 /* 193 */ | |
301 | #define DVO_PORT_HDMIE 12 /* 193 */ | |
841b5ed7 RV |
302 | #define DVO_PORT_DPF 13 /* N/A */ |
303 | #define DVO_PORT_HDMIF 14 /* N/A */ | |
fca36df5 JN |
304 | #define DVO_PORT_MIPIA 21 /* 171 */ |
305 | #define DVO_PORT_MIPIB 22 /* 171 */ | |
306 | #define DVO_PORT_MIPIC 23 /* 171 */ | |
307 | #define DVO_PORT_MIPID 24 /* 171 */ | |
308 | ||
d6038611 VS |
309 | #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ |
310 | #define HDMI_MAX_DATA_RATE_297 1 /* 204 */ | |
311 | #define HDMI_MAX_DATA_RATE_165 2 /* 204 */ | |
312 | ||
21907e72 | 313 | #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 |
72341af4 | 314 | |
9c3b2689 RV |
315 | /* DDC Bus DDI Type 155+ */ |
316 | enum vbt_gmbus_ddi { | |
317 | DDC_BUS_DDI_B = 0x1, | |
318 | DDC_BUS_DDI_C, | |
319 | DDC_BUS_DDI_D, | |
320 | DDC_BUS_DDI_F, | |
3937eb1a RS |
321 | ICL_DDC_BUS_DDI_A = 0x1, |
322 | ICL_DDC_BUS_DDI_B, | |
323 | ICL_DDC_BUS_PORT_1 = 0x4, | |
324 | ICL_DDC_BUS_PORT_2, | |
325 | ICL_DDC_BUS_PORT_3, | |
326 | ICL_DDC_BUS_PORT_4, | |
9c3b2689 RV |
327 | }; |
328 | ||
0a885381 JN |
329 | #define DP_AUX_A 0x40 |
330 | #define DP_AUX_B 0x10 | |
331 | #define DP_AUX_C 0x20 | |
332 | #define DP_AUX_D 0x30 | |
333 | #define DP_AUX_E 0x50 | |
334 | #define DP_AUX_F 0x60 | |
335 | ||
99b91bda JN |
336 | #define VBT_DP_MAX_LINK_RATE_HBR3 0 |
337 | #define VBT_DP_MAX_LINK_RATE_HBR2 1 | |
338 | #define VBT_DP_MAX_LINK_RATE_HBR 2 | |
339 | #define VBT_DP_MAX_LINK_RATE_LBR 3 | |
340 | ||
56f304e9 JN |
341 | /* |
342 | * The child device config, aka the display device data structure, provides a | |
343 | * description of a port and its configuration on the platform. | |
344 | * | |
345 | * The child device config size has been increased, and fields have been added | |
346 | * and their meaning has changed over time. Care must be taken when accessing | |
347 | * basically any of the fields to ensure the correct interpretation for the BDB | |
348 | * version in question. | |
349 | * | |
350 | * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve | |
351 | * space for the full structure below, and initialize the tail not actually | |
352 | * present in VBT to zeros. Accessing those fields is fine, as long as the | |
353 | * default zero is taken into account, again according to the BDB version. | |
354 | * | |
355 | * BDB versions 155 and below are considered legacy, and version 155 seems to be | |
356 | * a baseline for some of the VBT documentation. When adding new fields, please | |
357 | * include the BDB version when the field was added, if it's above that. | |
358 | */ | |
cc998589 | 359 | struct child_device_config { |
72341af4 | 360 | u16 handle; |
6a794c8a | 361 | u16 device_type; /* See DEVICE_TYPE_* above */ |
56f304e9 JN |
362 | |
363 | union { | |
364 | u8 device_id[10]; /* ascii string */ | |
365 | struct { | |
366 | u8 i2c_speed; | |
367 | u8 dp_onboard_redriver; /* 158 */ | |
368 | u8 dp_ondock_redriver; /* 158 */ | |
6e8fbf8d VS |
369 | u8 hdmi_level_shifter_value:5; /* 169 */ |
370 | u8 hdmi_max_data_rate:3; /* 204 */ | |
56f304e9 JN |
371 | u16 dtd_buf_ptr; /* 161 */ |
372 | u8 edidless_efp:1; /* 161 */ | |
373 | u8 compression_enable:1; /* 198 */ | |
374 | u8 compression_method:1; /* 198 */ | |
375 | u8 ganged_edp:1; /* 202 */ | |
376 | u8 reserved0:4; | |
377 | u8 compression_structure_index:4; /* 198 */ | |
378 | u8 reserved1:4; | |
379 | u8 slave_port; /* 202 */ | |
380 | u8 reserved2; | |
381 | } __packed; | |
382 | } __packed; | |
383 | ||
f865f7e1 | 384 | u16 addin_offset; |
fca36df5 | 385 | u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ |
f865f7e1 JN |
386 | u8 i2c_pin; |
387 | u8 slave_addr; | |
72341af4 JN |
388 | u8 ddc_pin; |
389 | u16 edid_ptr; | |
4e27bd50 | 390 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
56f304e9 JN |
391 | |
392 | union { | |
393 | struct { | |
394 | u8 dvo2_port; | |
395 | u8 i2c2_pin; | |
396 | u8 slave2_addr; | |
397 | u8 ddc2_pin; | |
398 | } __packed; | |
399 | struct { | |
400 | u8 efp_routed:1; /* 158 */ | |
401 | u8 lane_reversal:1; /* 184 */ | |
402 | u8 lspcon:1; /* 192 */ | |
403 | u8 iboost:1; /* 196 */ | |
404 | u8 hpd_invert:1; /* 196 */ | |
405 | u8 flag_reserved:3; | |
406 | u8 hdmi_support:1; /* 158 */ | |
407 | u8 dp_support:1; /* 158 */ | |
408 | u8 tmds_support:1; /* 158 */ | |
409 | u8 support_reserved:5; | |
410 | u8 aux_channel; | |
411 | u8 dongle_detect; | |
412 | } __packed; | |
413 | } __packed; | |
414 | ||
b7c7c3ea JN |
415 | u8 pipe_cap:2; |
416 | u8 sdvo_stall:1; /* 158 */ | |
417 | u8 hpd_status:2; | |
418 | u8 integrated_encoder:1; | |
419 | u8 capabilities_reserved:2; | |
f865f7e1 | 420 | u8 dvo_wiring; /* See DEVICE_WIRE_* above */ |
56f304e9 JN |
421 | |
422 | union { | |
423 | u8 dvo2_wiring; | |
424 | u8 mipi_bridge_type; /* 171 */ | |
425 | } __packed; | |
426 | ||
f865f7e1 JN |
427 | u16 extended_type; |
428 | u8 dvo_function; | |
b7c7c3ea | 429 | u8 dp_usb_type_c:1; /* 195 */ |
f677bd55 PZ |
430 | u8 tbt:1; /* 209 */ |
431 | u8 flags2_reserved:2; /* 195 */ | |
432 | u8 dp_port_trace_length:4; /* 209 */ | |
f865f7e1 JN |
433 | u8 dp_gpio_index; /* 195 */ |
434 | u16 dp_gpio_pin_num; /* 195 */ | |
f22bb358 JN |
435 | u8 dp_iboost_level:4; /* 196 */ |
436 | u8 hdmi_iboost_level:4; /* 196 */ | |
c4fb60b9 JN |
437 | u8 dp_max_link_rate:2; /* 216 CNL+ */ |
438 | u8 dp_max_link_rate_reserved:6; /* 216 */ | |
72341af4 JN |
439 | } __packed; |
440 | ||
72341af4 JN |
441 | struct bdb_general_definitions { |
442 | /* DDC GPIO */ | |
443 | u8 crt_ddc_gmbus_pin; | |
444 | ||
445 | /* DPMS bits */ | |
446 | u8 dpms_acpi:1; | |
447 | u8 skip_boot_crt_detect:1; | |
448 | u8 dpms_aim:1; | |
449 | u8 rsvd1:5; /* finish byte */ | |
450 | ||
451 | /* boot device bits */ | |
452 | u8 boot_display[2]; | |
453 | u8 child_dev_size; | |
454 | ||
455 | /* | |
456 | * Device info: | |
457 | * If TV is present, it'll be at devices[0]. | |
458 | * LVDS will be next, either devices[0] or [1], if present. | |
459 | * On some platforms the number of device is 6. But could be as few as | |
460 | * 4 if both TV and LVDS are missing. | |
461 | * And the device num is related with the size of general definition | |
462 | * block. It is obtained by using the following formula: | |
463 | * number = (block_size - sizeof(bdb_general_definitions))/ | |
464 | * defs->child_dev_size; | |
465 | */ | |
0ede0141 | 466 | u8 devices[0]; |
72341af4 JN |
467 | } __packed; |
468 | ||
469 | /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ | |
470 | #define MODE_MASK 0x3 | |
471 | ||
472 | struct bdb_lvds_options { | |
473 | u8 panel_type; | |
474 | u8 rsvd1; | |
475 | /* LVDS capabilities, stored in a dword */ | |
476 | u8 pfit_mode:2; | |
477 | u8 pfit_text_mode_enhanced:1; | |
478 | u8 pfit_gfx_mode_enhanced:1; | |
479 | u8 pfit_ratio_auto:1; | |
480 | u8 pixel_dither:1; | |
481 | u8 lvds_edid:1; | |
482 | u8 rsvd2:1; | |
483 | u8 rsvd4; | |
484 | /* LVDS Panel channel bits stored here */ | |
485 | u32 lvds_panel_channel_bits; | |
486 | /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ | |
487 | u16 ssc_bits; | |
488 | u16 ssc_freq; | |
489 | u16 ssc_ddt; | |
490 | /* Panel color depth defined here */ | |
491 | u16 panel_color_depth; | |
492 | /* LVDS panel type bits stored here */ | |
493 | u32 dps_panel_type_bits; | |
494 | /* LVDS backlight control type bits stored here */ | |
495 | u32 blt_control_type_bits; | |
496 | } __packed; | |
497 | ||
498 | /* LFP pointer table contains entries to the struct below */ | |
499 | struct bdb_lvds_lfp_data_ptr { | |
500 | u16 fp_timing_offset; /* offsets are from start of bdb */ | |
501 | u8 fp_table_size; | |
502 | u16 dvo_timing_offset; | |
503 | u8 dvo_table_size; | |
504 | u16 panel_pnp_id_offset; | |
505 | u8 pnp_table_size; | |
506 | } __packed; | |
507 | ||
508 | struct bdb_lvds_lfp_data_ptrs { | |
509 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ | |
510 | struct bdb_lvds_lfp_data_ptr ptr[16]; | |
511 | } __packed; | |
512 | ||
513 | /* LFP data has 3 blocks per entry */ | |
514 | struct lvds_fp_timing { | |
515 | u16 x_res; | |
516 | u16 y_res; | |
517 | u32 lvds_reg; | |
518 | u32 lvds_reg_val; | |
519 | u32 pp_on_reg; | |
520 | u32 pp_on_reg_val; | |
521 | u32 pp_off_reg; | |
522 | u32 pp_off_reg_val; | |
523 | u32 pp_cycle_reg; | |
524 | u32 pp_cycle_reg_val; | |
525 | u32 pfit_reg; | |
526 | u32 pfit_reg_val; | |
527 | u16 terminator; | |
528 | } __packed; | |
529 | ||
530 | struct lvds_dvo_timing { | |
531 | u16 clock; /**< In 10khz */ | |
532 | u8 hactive_lo; | |
533 | u8 hblank_lo; | |
534 | u8 hblank_hi:4; | |
535 | u8 hactive_hi:4; | |
536 | u8 vactive_lo; | |
537 | u8 vblank_lo; | |
538 | u8 vblank_hi:4; | |
539 | u8 vactive_hi:4; | |
540 | u8 hsync_off_lo; | |
ce2e87b4 VT |
541 | u8 hsync_pulse_width_lo; |
542 | u8 vsync_pulse_width_lo:4; | |
543 | u8 vsync_off_lo:4; | |
544 | u8 vsync_pulse_width_hi:2; | |
545 | u8 vsync_off_hi:2; | |
546 | u8 hsync_pulse_width_hi:2; | |
72341af4 | 547 | u8 hsync_off_hi:2; |
df457245 VS |
548 | u8 himage_lo; |
549 | u8 vimage_lo; | |
550 | u8 vimage_hi:4; | |
551 | u8 himage_hi:4; | |
72341af4 JN |
552 | u8 h_border; |
553 | u8 v_border; | |
554 | u8 rsvd1:3; | |
555 | u8 digital:2; | |
556 | u8 vsync_positive:1; | |
557 | u8 hsync_positive:1; | |
ce2e87b4 | 558 | u8 non_interlaced:1; |
72341af4 JN |
559 | } __packed; |
560 | ||
561 | struct lvds_pnp_id { | |
562 | u16 mfg_name; | |
563 | u16 product_code; | |
564 | u32 serial; | |
565 | u8 mfg_week; | |
566 | u8 mfg_year; | |
567 | } __packed; | |
568 | ||
569 | struct bdb_lvds_lfp_data_entry { | |
570 | struct lvds_fp_timing fp_timing; | |
571 | struct lvds_dvo_timing dvo_timing; | |
572 | struct lvds_pnp_id pnp_id; | |
573 | } __packed; | |
574 | ||
575 | struct bdb_lvds_lfp_data { | |
576 | struct bdb_lvds_lfp_data_entry data[16]; | |
577 | } __packed; | |
578 | ||
579 | #define BDB_BACKLIGHT_TYPE_NONE 0 | |
580 | #define BDB_BACKLIGHT_TYPE_PWM 2 | |
581 | ||
582 | struct bdb_lfp_backlight_data_entry { | |
583 | u8 type:2; | |
584 | u8 active_low_pwm:1; | |
585 | u8 obsolete1:5; | |
586 | u16 pwm_freq_hz; | |
587 | u8 min_brightness; | |
588 | u8 obsolete2; | |
589 | u8 obsolete3; | |
590 | } __packed; | |
591 | ||
9a41e17d D |
592 | struct bdb_lfp_backlight_control_method { |
593 | u8 type:4; | |
594 | u8 controller:4; | |
595 | } __packed; | |
596 | ||
72341af4 JN |
597 | struct bdb_lfp_backlight_data { |
598 | u8 entry_size; | |
599 | struct bdb_lfp_backlight_data_entry data[16]; | |
600 | u8 level[16]; | |
9a41e17d | 601 | struct bdb_lfp_backlight_control_method backlight_control[16]; |
72341af4 JN |
602 | } __packed; |
603 | ||
604 | struct aimdb_header { | |
605 | char signature[16]; | |
606 | char oem_device[20]; | |
607 | u16 aimdb_version; | |
608 | u16 aimdb_header_size; | |
609 | u16 aimdb_size; | |
610 | } __packed; | |
611 | ||
612 | struct aimdb_block { | |
613 | u8 aimdb_id; | |
614 | u16 aimdb_size; | |
615 | } __packed; | |
616 | ||
617 | struct vch_panel_data { | |
618 | u16 fp_timing_offset; | |
619 | u8 fp_timing_size; | |
620 | u16 dvo_timing_offset; | |
621 | u8 dvo_timing_size; | |
622 | u16 text_fitting_offset; | |
623 | u8 text_fitting_size; | |
624 | u16 graphics_fitting_offset; | |
625 | u8 graphics_fitting_size; | |
626 | } __packed; | |
627 | ||
628 | struct vch_bdb_22 { | |
629 | struct aimdb_block aimdb_block; | |
630 | struct vch_panel_data panels[16]; | |
631 | } __packed; | |
632 | ||
633 | struct bdb_sdvo_lvds_options { | |
634 | u8 panel_backlight; | |
635 | u8 h40_set_panel_type; | |
636 | u8 panel_type; | |
637 | u8 ssc_clk_freq; | |
638 | u16 als_low_trip; | |
639 | u16 als_high_trip; | |
640 | u8 sclalarcoeff_tab_row_num; | |
641 | u8 sclalarcoeff_tab_row_size; | |
642 | u8 coefficient[8]; | |
643 | u8 panel_misc_bits_1; | |
644 | u8 panel_misc_bits_2; | |
645 | u8 panel_misc_bits_3; | |
646 | u8 panel_misc_bits_4; | |
647 | } __packed; | |
648 | ||
649 | ||
650 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 | |
651 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 | |
652 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 | |
ca3b3fa3 | 653 | #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 |
72341af4 JN |
654 | |
655 | struct bdb_driver_features { | |
656 | u8 boot_dev_algorithm:1; | |
657 | u8 block_display_switch:1; | |
658 | u8 allow_display_switch:1; | |
659 | u8 hotplug_dvo:1; | |
660 | u8 dual_view_zoom:1; | |
661 | u8 int15h_hook:1; | |
662 | u8 sprite_in_clone:1; | |
663 | u8 primary_lfp_id:1; | |
664 | ||
665 | u16 boot_mode_x; | |
666 | u16 boot_mode_y; | |
667 | u8 boot_mode_bpp; | |
668 | u8 boot_mode_refresh; | |
669 | ||
670 | u16 enable_lfp_primary:1; | |
671 | u16 selective_mode_pruning:1; | |
672 | u16 dual_frequency:1; | |
673 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ | |
674 | u16 nt_clone_support:1; | |
675 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ | |
676 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ | |
677 | u16 cui_aspect_scaling:1; | |
678 | u16 preserve_aspect_ratio:1; | |
679 | u16 sdvo_device_power_down:1; | |
680 | u16 crt_hotplug:1; | |
681 | u16 lvds_config:2; | |
682 | u16 tv_hotplug:1; | |
683 | u16 hdmi_config:2; | |
684 | ||
685 | u8 static_display:1; | |
686 | u8 reserved2:7; | |
687 | u16 legacy_crt_max_x; | |
688 | u16 legacy_crt_max_y; | |
689 | u8 legacy_crt_max_refresh; | |
690 | ||
691 | u8 hdmi_termination; | |
692 | u8 custom_vbt_version; | |
693 | /* Driver features data block */ | |
694 | u16 rmpm_enabled:1; | |
695 | u16 s2ddt_enabled:1; | |
696 | u16 dpst_enabled:1; | |
697 | u16 bltclt_enabled:1; | |
698 | u16 adb_enabled:1; | |
699 | u16 drrs_enabled:1; | |
700 | u16 grs_enabled:1; | |
701 | u16 gpmt_enabled:1; | |
702 | u16 tbt_enabled:1; | |
703 | u16 psr_enabled:1; | |
704 | u16 ips_enabled:1; | |
705 | u16 reserved3:4; | |
706 | u16 pc_feature_valid:1; | |
707 | } __packed; | |
708 | ||
709 | #define EDP_18BPP 0 | |
710 | #define EDP_24BPP 1 | |
711 | #define EDP_30BPP 2 | |
712 | #define EDP_RATE_1_62 0 | |
713 | #define EDP_RATE_2_7 1 | |
714 | #define EDP_LANE_1 0 | |
715 | #define EDP_LANE_2 1 | |
716 | #define EDP_LANE_4 3 | |
717 | #define EDP_PREEMPHASIS_NONE 0 | |
718 | #define EDP_PREEMPHASIS_3_5dB 1 | |
719 | #define EDP_PREEMPHASIS_6dB 2 | |
720 | #define EDP_PREEMPHASIS_9_5dB 3 | |
721 | #define EDP_VSWING_0_4V 0 | |
722 | #define EDP_VSWING_0_6V 1 | |
723 | #define EDP_VSWING_0_8V 2 | |
724 | #define EDP_VSWING_1_2V 3 | |
725 | ||
726 | ||
058727ee | 727 | struct edp_fast_link_params { |
72341af4 JN |
728 | u8 rate:4; |
729 | u8 lanes:4; | |
730 | u8 preemphasis:4; | |
731 | u8 vswing:4; | |
732 | } __packed; | |
733 | ||
058727ee JN |
734 | struct edp_pwm_delays { |
735 | u16 pwm_on_to_backlight_enable; | |
736 | u16 backlight_disable_to_pwm_off; | |
737 | } __packed; | |
738 | ||
739 | struct edp_full_link_params { | |
740 | u8 preemphasis:4; | |
741 | u8 vswing:4; | |
742 | } __packed; | |
743 | ||
72341af4 JN |
744 | struct bdb_edp { |
745 | struct edp_power_seq power_seqs[16]; | |
746 | u32 color_depth; | |
058727ee | 747 | struct edp_fast_link_params fast_link_params[16]; |
72341af4 JN |
748 | u32 sdrrs_msa_timing_delay; |
749 | ||
750 | /* ith bit indicates enabled/disabled for (i+1)th panel */ | |
058727ee JN |
751 | u16 edp_s3d_feature; /* 162 */ |
752 | u16 edp_t3_optimization; /* 165 */ | |
753 | u64 edp_vswing_preemph; /* 173 */ | |
754 | u16 fast_link_training; /* 182 */ | |
755 | u16 dpcd_600h_write_required; /* 185 */ | |
756 | struct edp_pwm_delays pwm_delays[16]; /* 186 */ | |
757 | u16 full_link_params_provided; /* 199 */ | |
758 | struct edp_full_link_params full_link_params[16]; /* 199 */ | |
72341af4 JN |
759 | } __packed; |
760 | ||
761 | struct psr_table { | |
762 | /* Feature bits */ | |
763 | u8 full_link:1; | |
764 | u8 require_aux_to_wakeup:1; | |
765 | u8 feature_bits_rsvd:6; | |
766 | ||
767 | /* Wait times */ | |
768 | u8 idle_frames:4; | |
769 | u8 lines_to_wait:3; | |
770 | u8 wait_times_rsvd:1; | |
771 | ||
772 | /* TP wake up time in multiple of 100 */ | |
773 | u16 tp1_wakeup_time; | |
774 | u16 tp2_tp3_wakeup_time; | |
88a0d960 JRS |
775 | |
776 | /* PSR2 TP2/TP3 wakeup time for 16 panels */ | |
777 | u32 psr2_tp2_tp3_wakeup_time; | |
72341af4 JN |
778 | } __packed; |
779 | ||
780 | struct bdb_psr { | |
781 | struct psr_table psr_table[16]; | |
782 | } __packed; | |
783 | ||
784 | /* | |
785 | * Driver<->VBIOS interaction occurs through scratch bits in | |
786 | * GR18 & SWF*. | |
787 | */ | |
788 | ||
789 | /* GR18 bits are set on display switch and hotkey events */ | |
790 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ | |
791 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ | |
792 | #define GR18_HK_NONE (0x0<<3) | |
793 | #define GR18_HK_LFP_STRETCH (0x1<<3) | |
794 | #define GR18_HK_TOGGLE_DISP (0x2<<3) | |
795 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ | |
796 | #define GR18_HK_POPUP_DISABLED (0x6<<3) | |
797 | #define GR18_HK_POPUP_ENABLED (0x7<<3) | |
798 | #define GR18_HK_PFIT (0x8<<3) | |
799 | #define GR18_HK_APM_CHANGE (0xa<<3) | |
800 | #define GR18_HK_MULTIPLE (0xc<<3) | |
801 | #define GR18_USER_INT_EN (1<<2) | |
802 | #define GR18_A0000_FLUSH_EN (1<<1) | |
803 | #define GR18_SMM_EN (1<<0) | |
804 | ||
805 | /* Set by driver, cleared by VBIOS */ | |
806 | #define SWF00_YRES_SHIFT 16 | |
807 | #define SWF00_XRES_SHIFT 0 | |
808 | #define SWF00_RES_MASK 0xffff | |
809 | ||
810 | /* Set by VBIOS at boot time and driver at runtime */ | |
811 | #define SWF01_TV2_FORMAT_SHIFT 8 | |
812 | #define SWF01_TV1_FORMAT_SHIFT 0 | |
813 | #define SWF01_TV_FORMAT_MASK 0xffff | |
814 | ||
815 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) | |
816 | #define SWF10_GTT_OVERRIDE_EN (1<<28) | |
817 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ | |
818 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) | |
819 | #define SWF10_OLD_TOGGLE 0x0 | |
820 | #define SWF10_TOGGLE_LIST_1 0x1 | |
821 | #define SWF10_TOGGLE_LIST_2 0x2 | |
822 | #define SWF10_TOGGLE_LIST_3 0x3 | |
823 | #define SWF10_TOGGLE_LIST_4 0x4 | |
824 | #define SWF10_PANNING_EN (1<<23) | |
825 | #define SWF10_DRIVER_LOADED (1<<22) | |
826 | #define SWF10_EXTENDED_DESKTOP (1<<21) | |
827 | #define SWF10_EXCLUSIVE_MODE (1<<20) | |
828 | #define SWF10_OVERLAY_EN (1<<19) | |
829 | #define SWF10_PLANEB_HOLDOFF (1<<18) | |
830 | #define SWF10_PLANEA_HOLDOFF (1<<17) | |
831 | #define SWF10_VGA_HOLDOFF (1<<16) | |
832 | #define SWF10_ACTIVE_DISP_MASK 0xffff | |
833 | #define SWF10_PIPEB_LFP2 (1<<15) | |
834 | #define SWF10_PIPEB_EFP2 (1<<14) | |
835 | #define SWF10_PIPEB_TV2 (1<<13) | |
836 | #define SWF10_PIPEB_CRT2 (1<<12) | |
837 | #define SWF10_PIPEB_LFP (1<<11) | |
838 | #define SWF10_PIPEB_EFP (1<<10) | |
839 | #define SWF10_PIPEB_TV (1<<9) | |
840 | #define SWF10_PIPEB_CRT (1<<8) | |
841 | #define SWF10_PIPEA_LFP2 (1<<7) | |
842 | #define SWF10_PIPEA_EFP2 (1<<6) | |
843 | #define SWF10_PIPEA_TV2 (1<<5) | |
844 | #define SWF10_PIPEA_CRT2 (1<<4) | |
845 | #define SWF10_PIPEA_LFP (1<<3) | |
846 | #define SWF10_PIPEA_EFP (1<<2) | |
847 | #define SWF10_PIPEA_TV (1<<1) | |
848 | #define SWF10_PIPEA_CRT (1<<0) | |
849 | ||
850 | #define SWF11_MEMORY_SIZE_SHIFT 16 | |
851 | #define SWF11_SV_TEST_EN (1<<15) | |
852 | #define SWF11_IS_AGP (1<<14) | |
853 | #define SWF11_DISPLAY_HOLDOFF (1<<13) | |
854 | #define SWF11_DPMS_REDUCED (1<<12) | |
855 | #define SWF11_IS_VBE_MODE (1<<11) | |
856 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ | |
857 | #define SWF11_DPMS_MASK 0x07 | |
858 | #define SWF11_DPMS_OFF (1<<2) | |
859 | #define SWF11_DPMS_SUSPEND (1<<1) | |
860 | #define SWF11_DPMS_STANDBY (1<<0) | |
861 | #define SWF11_DPMS_ON 0 | |
862 | ||
863 | #define SWF14_GFX_PFIT_EN (1<<31) | |
864 | #define SWF14_TEXT_PFIT_EN (1<<30) | |
865 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ | |
866 | #define SWF14_POPUP_EN (1<<28) | |
867 | #define SWF14_DISPLAY_HOLDOFF (1<<27) | |
868 | #define SWF14_DISP_DETECT_EN (1<<26) | |
869 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ | |
870 | #define SWF14_DRIVER_STATUS (1<<24) | |
871 | #define SWF14_OS_TYPE_WIN9X (1<<23) | |
872 | #define SWF14_OS_TYPE_WINNT (1<<22) | |
873 | /* 21:19 rsvd */ | |
874 | #define SWF14_PM_TYPE_MASK 0x00070000 | |
875 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) | |
876 | #define SWF14_PM_ACPI (0x3 << 16) | |
877 | #define SWF14_PM_APM_12 (0x2 << 16) | |
878 | #define SWF14_PM_APM_11 (0x1 << 16) | |
879 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ | |
880 | /* if GR18 indicates a display switch */ | |
881 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) | |
882 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) | |
883 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) | |
884 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) | |
885 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) | |
886 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) | |
887 | #define SWF14_DS_PIPEB_TV_EN (1<<9) | |
888 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) | |
889 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) | |
890 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) | |
891 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) | |
892 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) | |
893 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) | |
894 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) | |
895 | #define SWF14_DS_PIPEA_TV_EN (1<<1) | |
896 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) | |
897 | /* if GR18 indicates a panel fitting request */ | |
898 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ | |
899 | /* if GR18 indicates an APM change request */ | |
900 | #define SWF14_APM_HIBERNATE 0x4 | |
901 | #define SWF14_APM_SUSPEND 0x3 | |
902 | #define SWF14_APM_STANDBY 0x1 | |
903 | #define SWF14_APM_RESTORE 0x0 | |
904 | ||
72341af4 JN |
905 | /* Block 52 contains MIPI configuration block |
906 | * 6 * bdb_mipi_config, followed by 6 pps data block | |
907 | * block below | |
908 | */ | |
909 | #define MAX_MIPI_CONFIGURATIONS 6 | |
910 | ||
911 | struct bdb_mipi_config { | |
912 | struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; | |
913 | struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; | |
914 | } __packed; | |
915 | ||
916 | /* Block 53 contains MIPI sequences as needed by the panel | |
917 | * for enabling it. This block can be variable in size and | |
918 | * can be maximum of 6 blocks | |
919 | */ | |
920 | struct bdb_mipi_sequence { | |
921 | u8 version; | |
922 | u8 data[0]; | |
923 | } __packed; | |
924 | ||
925 | enum mipi_gpio_pin_index { | |
926 | MIPI_GPIO_UNDEFINED = 0, | |
927 | MIPI_GPIO_PANEL_ENABLE, | |
928 | MIPI_GPIO_BL_ENABLE, | |
929 | MIPI_GPIO_PWM_ENABLE, | |
930 | MIPI_GPIO_RESET_N, | |
931 | MIPI_GPIO_PWR_DOWN_R, | |
932 | MIPI_GPIO_STDBY_RST_N, | |
933 | MIPI_GPIO_MAX | |
934 | }; | |
935 | ||
936 | #endif /* _INTEL_VBT_DEFS_H_ */ |