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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
ec7f29ff JN |
26 | #include <linux/gpio/consumer.h> |
27 | #include <linux/slab.h> | |
28 | ||
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
30 | #include <drm/drm_crtc.h> |
31 | #include <drm/drm_edid.h> | |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
ec7f29ff JN |
33 | #include <drm/i915_drm.h> |
34 | ||
4e646495 | 35 | #include "i915_drv.h" |
ec7f29ff | 36 | #include "intel_connector.h" |
4e646495 JN |
37 | #include "intel_drv.h" |
38 | #include "intel_dsi.h" | |
4e646495 | 39 | |
042ab0c3 R |
40 | /* return pixels in terms of txbyteclkhs */ |
41 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
42 | u16 burst_mode_ratio) | |
43 | { | |
44 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
45 | 8 * 100), lane_count); | |
46 | } | |
47 | ||
cefc4e18 R |
48 | /* return pixels equvalent to txbyteclkhs */ |
49 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
50 | u16 burst_mode_ratio) | |
51 | { | |
52 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
53 | (bpp * burst_mode_ratio)); | |
54 | } | |
55 | ||
43367ec9 R |
56 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
57 | { | |
58 | /* It just so happens the VBT matches register contents. */ | |
59 | switch (fmt) { | |
60 | case VID_MODE_FORMAT_RGB888: | |
61 | return MIPI_DSI_FMT_RGB888; | |
62 | case VID_MODE_FORMAT_RGB666: | |
63 | return MIPI_DSI_FMT_RGB666; | |
64 | case VID_MODE_FORMAT_RGB666_PACKED: | |
65 | return MIPI_DSI_FMT_RGB666_PACKED; | |
66 | case VID_MODE_FORMAT_RGB565: | |
67 | return MIPI_DSI_FMT_RGB565; | |
68 | default: | |
69 | MISSING_CASE(fmt); | |
70 | return MIPI_DSI_FMT_RGB666; | |
71 | } | |
72 | } | |
73 | ||
e518634b | 74 | void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
75 | { |
76 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
77 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 78 | struct drm_i915_private *dev_priv = to_i915(dev); |
3b1808bf JN |
79 | u32 mask; |
80 | ||
81 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
82 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
83 | ||
97a04e0d | 84 | if (intel_wait_for_register(&dev_priv->uncore, |
9b6a2d72 CW |
85 | MIPI_GEN_FIFO_STAT(port), mask, mask, |
86 | 100)) | |
3b1808bf JN |
87 | DRM_ERROR("DPI FIFOs are not empty\n"); |
88 | } | |
89 | ||
f0f59a00 VS |
90 | static void write_data(struct drm_i915_private *dev_priv, |
91 | i915_reg_t reg, | |
7e9804fd JN |
92 | const u8 *data, u32 len) |
93 | { | |
94 | u32 i, j; | |
95 | ||
96 | for (i = 0; i < len; i += 4) { | |
97 | u32 val = 0; | |
98 | ||
99 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
100 | val |= *data++ << 8 * j; | |
101 | ||
102 | I915_WRITE(reg, val); | |
103 | } | |
104 | } | |
105 | ||
f0f59a00 VS |
106 | static void read_data(struct drm_i915_private *dev_priv, |
107 | i915_reg_t reg, | |
7e9804fd JN |
108 | u8 *data, u32 len) |
109 | { | |
110 | u32 i, j; | |
111 | ||
112 | for (i = 0; i < len; i += 4) { | |
113 | u32 val = I915_READ(reg); | |
114 | ||
115 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
116 | *data++ = val >> 8 * j; | |
117 | } | |
118 | } | |
119 | ||
120 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
121 | const struct mipi_dsi_msg *msg) | |
122 | { | |
123 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
124 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
fac5e23e | 125 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd JN |
126 | enum port port = intel_dsi_host->port; |
127 | struct mipi_dsi_packet packet; | |
128 | ssize_t ret; | |
129 | const u8 *header, *data; | |
f0f59a00 VS |
130 | i915_reg_t data_reg, ctrl_reg; |
131 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
132 | |
133 | ret = mipi_dsi_create_packet(&packet, msg); | |
134 | if (ret < 0) | |
135 | return ret; | |
136 | ||
137 | header = packet.header; | |
138 | data = packet.payload; | |
139 | ||
140 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
141 | data_reg = MIPI_LP_GEN_DATA(port); | |
142 | data_mask = LP_DATA_FIFO_FULL; | |
143 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
144 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
145 | } else { | |
146 | data_reg = MIPI_HS_GEN_DATA(port); | |
147 | data_mask = HS_DATA_FIFO_FULL; | |
148 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
149 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
150 | } | |
151 | ||
152 | /* note: this is never true for reads */ | |
153 | if (packet.payload_length) { | |
97a04e0d | 154 | if (intel_wait_for_register(&dev_priv->uncore, |
8c6cea0b CW |
155 | MIPI_GEN_FIFO_STAT(port), |
156 | data_mask, 0, | |
157 | 50)) | |
7e9804fd JN |
158 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
159 | ||
160 | write_data(dev_priv, data_reg, packet.payload, | |
161 | packet.payload_length); | |
162 | } | |
163 | ||
164 | if (msg->rx_len) { | |
165 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
166 | } | |
167 | ||
97a04e0d | 168 | if (intel_wait_for_register(&dev_priv->uncore, |
84c2aa90 CW |
169 | MIPI_GEN_FIFO_STAT(port), |
170 | ctrl_mask, 0, | |
171 | 50)) { | |
7e9804fd JN |
172 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
173 | } | |
174 | ||
175 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
176 | ||
177 | /* ->rx_len is set only for reads */ | |
178 | if (msg->rx_len) { | |
179 | data_mask = GEN_READ_DATA_AVAIL; | |
97a04e0d | 180 | if (intel_wait_for_register(&dev_priv->uncore, |
e7615b37 CW |
181 | MIPI_INTR_STAT(port), |
182 | data_mask, data_mask, | |
183 | 50)) | |
7e9804fd JN |
184 | DRM_ERROR("Timeout waiting for read data.\n"); |
185 | ||
186 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
187 | } | |
188 | ||
189 | /* XXX: fix for reads and writes */ | |
190 | return 4 + packet.payload_length; | |
191 | } | |
192 | ||
193 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
194 | struct mipi_dsi_device *dsi) | |
195 | { | |
196 | return 0; | |
197 | } | |
198 | ||
199 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
200 | struct mipi_dsi_device *dsi) | |
201 | { | |
202 | return 0; | |
203 | } | |
204 | ||
205 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
206 | .attach = intel_dsi_host_attach, | |
207 | .detach = intel_dsi_host_detach, | |
208 | .transfer = intel_dsi_host_transfer, | |
209 | }; | |
210 | ||
a2581a9e JN |
211 | /* |
212 | * send a video mode command | |
213 | * | |
214 | * XXX: commands with data in MIPI_DPI_DATA? | |
215 | */ | |
216 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
217 | enum port port) | |
218 | { | |
219 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
220 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 221 | struct drm_i915_private *dev_priv = to_i915(dev); |
a2581a9e JN |
222 | u32 mask; |
223 | ||
224 | /* XXX: pipe, hs */ | |
225 | if (hs) | |
226 | cmd &= ~DPI_LP_MODE; | |
227 | else | |
228 | cmd |= DPI_LP_MODE; | |
229 | ||
230 | /* clear bit */ | |
231 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
232 | ||
233 | /* XXX: old code skips write if control unchanged */ | |
234 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
5b60fc09 | 235 | DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); |
a2581a9e JN |
236 | |
237 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
238 | ||
239 | mask = SPL_PKT_SENT_INTERRUPT; | |
97a04e0d | 240 | if (intel_wait_for_register(&dev_priv->uncore, |
2af05078 CW |
241 | MIPI_INTR_STAT(port), mask, mask, |
242 | 100)) | |
a2581a9e JN |
243 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
e9fe51c6 | 248 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 249 | { |
a580516d | 250 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 251 | |
e9fe51c6 SK |
252 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
253 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
254 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
255 | udelay(150); | |
256 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
257 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 258 | |
a580516d | 259 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
260 | } |
261 | ||
49965350 VS |
262 | static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) |
263 | { | |
264 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
265 | u32 tmp; | |
266 | ||
267 | tmp = I915_READ(PIPEMISC(crtc->pipe)); | |
268 | ||
269 | switch (tmp & PIPEMISC_DITHER_BPC_MASK) { | |
270 | case PIPEMISC_DITHER_6_BPC: | |
271 | return 18; | |
272 | case PIPEMISC_DITHER_8_BPC: | |
273 | return 24; | |
274 | case PIPEMISC_DITHER_10_BPC: | |
275 | return 30; | |
276 | case PIPEMISC_DITHER_12_BPC: | |
277 | return 36; | |
278 | default: | |
279 | MISSING_CASE(tmp); | |
280 | return 0; | |
281 | } | |
282 | } | |
283 | ||
204474a6 LP |
284 | static int intel_dsi_compute_config(struct intel_encoder *encoder, |
285 | struct intel_crtc_state *pipe_config, | |
286 | struct drm_connector_state *conn_state) | |
4e646495 | 287 | { |
fac5e23e | 288 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4e646495 JN |
289 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
290 | base); | |
291 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
292 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
293 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 294 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 295 | int ret; |
4e646495 JN |
296 | |
297 | DRM_DEBUG_KMS("\n"); | |
d9facae6 | 298 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
4e646495 | 299 | |
f4ee265f | 300 | if (fixed_mode) { |
4e646495 JN |
301 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
302 | ||
b2ae318a | 303 | if (HAS_GMCH(dev_priv)) |
f4ee265f | 304 | intel_gmch_panel_fitting(crtc, pipe_config, |
eead06df | 305 | conn_state->scaling_mode); |
f4ee265f VS |
306 | else |
307 | intel_pch_panel_fitting(crtc, pipe_config, | |
eead06df | 308 | conn_state->scaling_mode); |
f4ee265f VS |
309 | } |
310 | ||
e4dd27aa | 311 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 312 | return -EINVAL; |
e4dd27aa | 313 | |
f573de5a SK |
314 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
315 | adjusted_mode->flags = 0; | |
316 | ||
ca0b04db HG |
317 | if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) |
318 | pipe_config->pipe_bpp = 24; | |
319 | else | |
320 | pipe_config->pipe_bpp = 18; | |
321 | ||
cc3f90f0 | 322 | if (IS_GEN9_LP(dev_priv)) { |
aec0246f US |
323 | /* Enable Frame time stamp based scanline reporting */ |
324 | adjusted_mode->private_flags |= | |
325 | I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; | |
326 | ||
4d1de975 JN |
327 | /* Dual link goes to DSI transcoder A. */ |
328 | if (intel_dsi->ports == BIT(PORT_C)) | |
329 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
330 | else | |
331 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
4d1de975 | 332 | |
e518634b JN |
333 | ret = bxt_dsi_pll_compute(encoder, pipe_config); |
334 | if (ret) | |
204474a6 | 335 | return -EINVAL; |
e518634b JN |
336 | } else { |
337 | ret = vlv_dsi_pll_compute(encoder, pipe_config); | |
338 | if (ret) | |
204474a6 | 339 | return -EINVAL; |
e518634b | 340 | } |
47eacbab | 341 | |
cd2d34d9 VS |
342 | pipe_config->clock_set = true; |
343 | ||
204474a6 | 344 | return 0; |
4e646495 JN |
345 | } |
346 | ||
8a1deb32 | 347 | static bool glk_dsi_enable_io(struct intel_encoder *encoder) |
46448483 D |
348 | { |
349 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
350 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
351 | enum port port; | |
74e4ce6a | 352 | u32 tmp; |
8a1deb32 | 353 | bool cold_boot = false; |
46448483 D |
354 | |
355 | /* Set the MIPI mode | |
356 | * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. | |
357 | * Power ON MIPI IO first and then write into IO reset and LP wake bits | |
358 | */ | |
359 | for_each_dsi_port(port, intel_dsi->ports) { | |
360 | tmp = I915_READ(MIPI_CTRL(port)); | |
361 | I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); | |
362 | } | |
363 | ||
364 | /* Put the IO into reset */ | |
365 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
366 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
367 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
368 | ||
369 | /* Program LP Wake */ | |
370 | for_each_dsi_port(port, intel_dsi->ports) { | |
371 | tmp = I915_READ(MIPI_CTRL(port)); | |
8a1deb32 MC |
372 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) |
373 | tmp &= ~GLK_LP_WAKE; | |
374 | else | |
375 | tmp |= GLK_LP_WAKE; | |
46448483 D |
376 | I915_WRITE(MIPI_CTRL(port), tmp); |
377 | } | |
378 | ||
379 | /* Wait for Pwr ACK */ | |
380 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d DCS |
381 | if (intel_wait_for_register(&dev_priv->uncore, |
382 | MIPI_CTRL(port), | |
383 | GLK_MIPIIO_PORT_POWERED, | |
384 | GLK_MIPIIO_PORT_POWERED, | |
385 | 20)) | |
46448483 D |
386 | DRM_ERROR("MIPIO port is powergated\n"); |
387 | } | |
8a1deb32 MC |
388 | |
389 | /* Check for cold boot scenario */ | |
390 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d DCS |
391 | cold_boot |= |
392 | !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); | |
8a1deb32 MC |
393 | } |
394 | ||
395 | return cold_boot; | |
74e4ce6a MC |
396 | } |
397 | ||
398 | static void glk_dsi_device_ready(struct intel_encoder *encoder) | |
399 | { | |
400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
401 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
402 | enum port port; | |
403 | u32 val; | |
46448483 D |
404 | |
405 | /* Wait for MIPI PHY status bit to set */ | |
406 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d DCS |
407 | if (intel_wait_for_register(&dev_priv->uncore, |
408 | MIPI_CTRL(port), | |
409 | GLK_PHY_STATUS_PORT_READY, | |
410 | GLK_PHY_STATUS_PORT_READY, | |
411 | 20)) | |
46448483 D |
412 | DRM_ERROR("PHY is not ON\n"); |
413 | } | |
414 | ||
415 | /* Get IO out of reset */ | |
74e4ce6a MC |
416 | val = I915_READ(MIPI_CTRL(PORT_A)); |
417 | I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); | |
46448483 D |
418 | |
419 | /* Get IO out of Low power state*/ | |
420 | for_each_dsi_port(port, intel_dsi->ports) { | |
421 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { | |
422 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
423 | val &= ~ULPS_STATE_MASK; | |
424 | val |= DEVICE_READY; | |
425 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
426 | usleep_range(10, 15); | |
8a1deb32 MC |
427 | } else { |
428 | /* Enter ULPS */ | |
429 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
430 | val &= ~ULPS_STATE_MASK; | |
431 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
432 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 433 | |
8a1deb32 | 434 | /* Wait for ULPS active */ |
97a04e0d DCS |
435 | if (intel_wait_for_register(&dev_priv->uncore, |
436 | MIPI_CTRL(port), | |
437 | GLK_ULPS_NOT_ACTIVE, | |
438 | 0, | |
439 | 20)) | |
8a1deb32 | 440 | DRM_ERROR("ULPS not active\n"); |
46448483 | 441 | |
8a1deb32 MC |
442 | /* Exit ULPS */ |
443 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
444 | val &= ~ULPS_STATE_MASK; | |
445 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
446 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 447 | |
8a1deb32 MC |
448 | /* Enter Normal Mode */ |
449 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
450 | val &= ~ULPS_STATE_MASK; | |
451 | val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); | |
452 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 453 | |
8a1deb32 MC |
454 | val = I915_READ(MIPI_CTRL(port)); |
455 | val &= ~GLK_LP_WAKE; | |
456 | I915_WRITE(MIPI_CTRL(port), val); | |
457 | } | |
46448483 D |
458 | } |
459 | ||
460 | /* Wait for Stop state */ | |
461 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d DCS |
462 | if (intel_wait_for_register(&dev_priv->uncore, |
463 | MIPI_CTRL(port), | |
464 | GLK_DATA_LANE_STOP_STATE, | |
465 | GLK_DATA_LANE_STOP_STATE, | |
466 | 20)) | |
46448483 D |
467 | DRM_ERROR("Date lane not in STOP state\n"); |
468 | } | |
469 | ||
470 | /* Wait for AFE LATCH */ | |
471 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d DCS |
472 | if (intel_wait_for_register(&dev_priv->uncore, |
473 | BXT_MIPI_PORT_CTRL(port), | |
474 | AFE_LATCHOUT, | |
475 | AFE_LATCHOUT, | |
476 | 20)) | |
46448483 D |
477 | DRM_ERROR("D-PHY not entering LP-11 state\n"); |
478 | } | |
479 | } | |
480 | ||
37ab0810 | 481 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 482 | { |
fac5e23e | 483 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5505a244 | 484 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 485 | enum port port; |
37ab0810 | 486 | u32 val; |
5505a244 | 487 | |
37ab0810 | 488 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 489 | |
eba4daf0 | 490 | /* Enable MIPI PHY transparent latch */ |
369602d3 | 491 | for_each_dsi_port(port, intel_dsi->ports) { |
37ab0810 SS |
492 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
493 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
494 | usleep_range(2000, 2500); | |
eba4daf0 | 495 | } |
37ab0810 | 496 | |
eba4daf0 US |
497 | /* Clear ULPS and set device ready */ |
498 | for_each_dsi_port(port, intel_dsi->ports) { | |
37ab0810 SS |
499 | val = I915_READ(MIPI_DEVICE_READY(port)); |
500 | val &= ~ULPS_STATE_MASK; | |
37ab0810 | 501 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
eba4daf0 | 502 | usleep_range(2000, 2500); |
37ab0810 SS |
503 | val |= DEVICE_READY; |
504 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 505 | } |
5505a244 GS |
506 | } |
507 | ||
37ab0810 | 508 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 509 | { |
fac5e23e | 510 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24ee0e64 GS |
511 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
512 | enum port port; | |
1dbd7cb2 SK |
513 | u32 val; |
514 | ||
4e646495 | 515 | DRM_DEBUG_KMS("\n"); |
4e646495 | 516 | |
a580516d | 517 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
518 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
519 | * needed everytime after power gate */ | |
520 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 521 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
522 | |
523 | /* bandgap reset is needed after everytime we do power gate */ | |
524 | band_gap_reset(dev_priv); | |
525 | ||
24ee0e64 | 526 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 527 | |
24ee0e64 GS |
528 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
529 | usleep_range(2500, 3000); | |
aceb365c | 530 | |
bf344e80 GS |
531 | /* Enable MIPI PHY transparent latch |
532 | * Common bit for both MIPI Port A & MIPI Port C | |
533 | * No similar bit in MIPI Port C reg | |
534 | */ | |
4ba7d93a | 535 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 536 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 537 | usleep_range(1000, 1500); |
aceb365c | 538 | |
24ee0e64 GS |
539 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
540 | usleep_range(2500, 3000); | |
541 | ||
542 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
543 | usleep_range(2500, 3000); | |
544 | } | |
1dbd7cb2 | 545 | } |
1dbd7cb2 | 546 | |
37ab0810 SS |
547 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
548 | { | |
e2d214ae | 549 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
37ab0810 | 550 | |
012bf847 | 551 | if (IS_GEMINILAKE(dev_priv)) |
46448483 | 552 | glk_dsi_device_ready(encoder); |
012bf847 JN |
553 | else if (IS_GEN9_LP(dev_priv)) |
554 | bxt_dsi_device_ready(encoder); | |
555 | else | |
556 | vlv_dsi_device_ready(encoder); | |
37ab0810 SS |
557 | } |
558 | ||
46448483 D |
559 | static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) |
560 | { | |
561 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
562 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
563 | enum port port; | |
564 | u32 val; | |
565 | ||
566 | /* Enter ULPS */ | |
567 | for_each_dsi_port(port, intel_dsi->ports) { | |
568 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
569 | val &= ~ULPS_STATE_MASK; | |
570 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
571 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
572 | } | |
573 | ||
574 | /* Wait for MIPI PHY status bit to unset */ | |
575 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d | 576 | if (intel_wait_for_register(&dev_priv->uncore, |
46448483 D |
577 | MIPI_CTRL(port), |
578 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
579 | DRM_ERROR("PHY is not turning OFF\n"); | |
580 | } | |
581 | ||
582 | /* Wait for Pwr ACK bit to unset */ | |
583 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d | 584 | if (intel_wait_for_register(&dev_priv->uncore, |
46448483 D |
585 | MIPI_CTRL(port), |
586 | GLK_MIPIIO_PORT_POWERED, 0, 20)) | |
587 | DRM_ERROR("MIPI IO Port is not powergated\n"); | |
588 | } | |
589 | } | |
590 | ||
591 | static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) | |
592 | { | |
593 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
594 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
595 | enum port port; | |
596 | u32 tmp; | |
597 | ||
598 | /* Put the IO into reset */ | |
599 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
600 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
601 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
602 | ||
603 | /* Wait for MIPI PHY status bit to unset */ | |
604 | for_each_dsi_port(port, intel_dsi->ports) { | |
97a04e0d | 605 | if (intel_wait_for_register(&dev_priv->uncore, |
46448483 D |
606 | MIPI_CTRL(port), |
607 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
608 | DRM_ERROR("PHY is not turning OFF\n"); | |
609 | } | |
610 | ||
611 | /* Clear MIPI mode */ | |
612 | for_each_dsi_port(port, intel_dsi->ports) { | |
613 | tmp = I915_READ(MIPI_CTRL(port)); | |
614 | tmp &= ~GLK_MIPIIO_ENABLE; | |
615 | I915_WRITE(MIPI_CTRL(port), tmp); | |
616 | } | |
617 | } | |
618 | ||
619 | static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) | |
620 | { | |
621 | glk_dsi_enter_low_power_mode(encoder); | |
622 | glk_dsi_disable_mipi_io(encoder); | |
623 | } | |
624 | ||
625 | static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) | |
14be7a5c HG |
626 | { |
627 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
628 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
629 | enum port port; | |
630 | ||
631 | DRM_DEBUG_KMS("\n"); | |
632 | for_each_dsi_port(port, intel_dsi->ports) { | |
633 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ | |
634 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? | |
635 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
636 | u32 val; | |
637 | ||
638 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
639 | ULPS_STATE_ENTER); | |
640 | usleep_range(2000, 2500); | |
641 | ||
642 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
643 | ULPS_STATE_EXIT); | |
644 | usleep_range(2000, 2500); | |
645 | ||
646 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
647 | ULPS_STATE_ENTER); | |
648 | usleep_range(2000, 2500); | |
649 | ||
1e08a260 HG |
650 | /* |
651 | * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI | |
652 | * Port A only. MIPI Port C has no similar bit for checking. | |
14be7a5c | 653 | */ |
1e08a260 | 654 | if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && |
97a04e0d | 655 | intel_wait_for_register(&dev_priv->uncore, |
14be7a5c HG |
656 | port_ctrl, AFE_LATCHOUT, 0, |
657 | 30)) | |
658 | DRM_ERROR("DSI LP not going Low\n"); | |
659 | ||
660 | /* Disable MIPI PHY transparent latch */ | |
661 | val = I915_READ(port_ctrl); | |
662 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
663 | usleep_range(1000, 1500); | |
664 | ||
665 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
666 | usleep_range(2000, 2500); | |
667 | } | |
668 | } | |
669 | ||
3c0628f8 VS |
670 | static void intel_dsi_port_enable(struct intel_encoder *encoder, |
671 | const struct intel_crtc_state *crtc_state) | |
37ab0810 | 672 | { |
3c0628f8 VS |
673 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
674 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
37ab0810 SS |
675 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
676 | enum port port; | |
37ab0810 SS |
677 | |
678 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 | 679 | u32 temp; |
6043801f D |
680 | if (IS_GEN9_LP(dev_priv)) { |
681 | for_each_dsi_port(port, intel_dsi->ports) { | |
682 | temp = I915_READ(MIPI_CTRL(port)); | |
683 | temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | | |
684 | intel_dsi->pixel_overlap << | |
685 | BXT_PIXEL_OVERLAP_CNT_SHIFT; | |
686 | I915_WRITE(MIPI_CTRL(port), temp); | |
687 | } | |
688 | } else { | |
689 | temp = I915_READ(VLV_CHICKEN_3); | |
690 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
37ab0810 SS |
691 | intel_dsi->pixel_overlap << |
692 | PIXEL_OVERLAP_CNT_SHIFT; | |
6043801f D |
693 | I915_WRITE(VLV_CHICKEN_3, temp); |
694 | } | |
37ab0810 SS |
695 | } |
696 | ||
697 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 698 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
699 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
700 | u32 temp; | |
37ab0810 SS |
701 | |
702 | temp = I915_READ(port_ctrl); | |
703 | ||
704 | temp &= ~LANE_CONFIGURATION_MASK; | |
705 | temp &= ~DUAL_LINK_MODE_MASK; | |
706 | ||
701d25b4 | 707 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
708 | temp |= (intel_dsi->dual_link - 1) |
709 | << DUAL_LINK_MODE_SHIFT; | |
812b1d2f BP |
710 | if (IS_BROXTON(dev_priv)) |
711 | temp |= LANE_CONFIGURATION_DUAL_LINK_A; | |
712 | else | |
3c0628f8 | 713 | temp |= crtc->pipe ? |
37ab0810 SS |
714 | LANE_CONFIGURATION_DUAL_LINK_B : |
715 | LANE_CONFIGURATION_DUAL_LINK_A; | |
716 | } | |
24bf86cc HG |
717 | |
718 | if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) | |
719 | temp |= DITHERING_ENABLE; | |
720 | ||
37ab0810 SS |
721 | /* assert ip_tg_enable signal */ |
722 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
723 | POSTING_READ(port_ctrl); | |
724 | } | |
725 | } | |
726 | ||
727 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
728 | { | |
729 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 730 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
731 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
732 | enum port port; | |
37ab0810 SS |
733 | |
734 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 735 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
736 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
737 | u32 temp; | |
738 | ||
37ab0810 | 739 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
740 | temp = I915_READ(port_ctrl); |
741 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
742 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
743 | } |
744 | } | |
745 | ||
5eff0edf | 746 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
5f88a9c6 | 747 | const struct intel_crtc_state *pipe_config); |
c7991eca | 748 | static void intel_dsi_unprepare(struct intel_encoder *encoder); |
e3488e75 | 749 | |
249f6962 HG |
750 | /* |
751 | * Panel enable/disable sequences from the VBT spec. | |
752 | * | |
753 | * Note the spec has AssertReset / DeassertReset swapped from their | |
754 | * usual naming. We use the normal names to avoid confusion (so below | |
755 | * they are swapped compared to the spec). | |
756 | * | |
757 | * Steps starting with MIPI refer to VBT sequences, note that for v2 | |
758 | * VBTs several steps which have a VBT in v2 are expected to be handled | |
759 | * directly by the driver, by directly driving gpios for example. | |
760 | * | |
761 | * v2 video mode seq v3 video mode seq command mode seq | |
762 | * - power on - MIPIPanelPowerOn - power on | |
763 | * - wait t1+t2 - wait t1+t2 | |
764 | * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin | |
765 | * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 | |
766 | * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds | |
767 | * - MIPITearOn | |
768 | * - MIPIDisplayOn | |
769 | * - turn on DPI - turn on DPI - set pipe to dsr mode | |
770 | * - MIPIDisplayOn - MIPIDisplayOn | |
771 | * - wait t5 - wait t5 | |
772 | * - backlight on - MIPIBacklightOn - backlight on | |
773 | * ... ... ... issue mem cmds ... | |
774 | * - backlight off - MIPIBacklightOff - backlight off | |
775 | * - wait t6 - wait t6 | |
776 | * - MIPIDisplayOff | |
777 | * - turn off DPI - turn off DPI - disable pipe dsr mode | |
778 | * - MIPITearOff | |
779 | * - MIPIDisplayOff - MIPIDisplayOff | |
780 | * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 | |
781 | * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin | |
782 | * - wait t3 - wait t3 | |
783 | * - power off - MIPIPanelPowerOff - power off | |
784 | * - wait t4 - wait t4 | |
785 | */ | |
786 | ||
c84c6fe3 JN |
787 | /* |
788 | * DSI port enable has to be done before pipe and plane enable, so we do it in | |
789 | * the pre_enable hook instead of the enable hook. | |
790 | */ | |
fd6bbda9 | 791 | static void intel_dsi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
792 | const struct intel_crtc_state *pipe_config, |
793 | const struct drm_connector_state *conn_state) | |
2634fd7f SK |
794 | { |
795 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
364a3fe1 JN |
796 | struct drm_crtc *crtc = pipe_config->base.crtc; |
797 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
799 | int pipe = intel_crtc->pipe; | |
5a2e65e7 | 800 | enum port port; |
1881a423 | 801 | u32 val; |
8a1deb32 | 802 | bool glk_cold_boot = false; |
2634fd7f SK |
803 | |
804 | DRM_DEBUG_KMS("\n"); | |
805 | ||
364a3fe1 JN |
806 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
807 | ||
f00b5689 VS |
808 | /* |
809 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
810 | * lock. It needs to be fully powered down to fix it. | |
811 | */ | |
e518634b JN |
812 | if (IS_GEN9_LP(dev_priv)) { |
813 | bxt_dsi_pll_disable(encoder); | |
814 | bxt_dsi_pll_enable(encoder, pipe_config); | |
815 | } else { | |
816 | vlv_dsi_pll_disable(encoder); | |
817 | vlv_dsi_pll_enable(encoder, pipe_config); | |
818 | } | |
f00b5689 | 819 | |
1881a423 US |
820 | if (IS_BROXTON(dev_priv)) { |
821 | /* Add MIPI IO reset programming for modeset */ | |
822 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
823 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
824 | val | MIPIO_RST_CTRL); | |
825 | ||
826 | /* Power up DSI regulator */ | |
827 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
828 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); | |
829 | } | |
830 | ||
d1877c0f VS |
831 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
832 | u32 val; | |
833 | ||
cd2d34d9 | 834 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
835 | val = I915_READ(DSPCLK_GATE_D); |
836 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
837 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 838 | } |
2634fd7f | 839 | |
8a1deb32 MC |
840 | if (!IS_GEMINILAKE(dev_priv)) |
841 | intel_dsi_prepare(encoder, pipe_config); | |
deae2006 HG |
842 | |
843 | /* Power on, try both CRC pmic gpio and VBT */ | |
844 | if (intel_dsi->gpio_panel) | |
845 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
b0dd6887 | 846 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); |
25b4620e | 847 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); |
deae2006 | 848 | |
3e40fa8a | 849 | /* Deassert reset */ |
b0dd6887 | 850 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); |
3e40fa8a | 851 | |
8a1deb32 MC |
852 | if (IS_GEMINILAKE(dev_priv)) { |
853 | glk_cold_boot = glk_dsi_enable_io(encoder); | |
854 | ||
855 | /* Prepare port in cold boot(s3/s4) scenario */ | |
856 | if (glk_cold_boot) | |
857 | intel_dsi_prepare(encoder, pipe_config); | |
858 | } | |
74e4ce6a | 859 | |
3e40fa8a | 860 | /* Put device in ready state (LP-11) */ |
2634fd7f | 861 | intel_dsi_device_ready(encoder); |
4e646495 | 862 | |
8a1deb32 MC |
863 | /* Prepare port in normal boot scenario */ |
864 | if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) | |
865 | intel_dsi_prepare(encoder, pipe_config); | |
866 | ||
3e40fa8a | 867 | /* Send initialization commands in LP mode */ |
b0dd6887 | 868 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); |
20e5bf66 | 869 | |
2634fd7f SK |
870 | /* Enable port in pre-enable phase itself because as per hw team |
871 | * recommendation, port should be enabled befor plane & pipe */ | |
5a2e65e7 HG |
872 | if (is_cmd_mode(intel_dsi)) { |
873 | for_each_dsi_port(port, intel_dsi->ports) | |
874 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
b0dd6887 JN |
875 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); |
876 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); | |
5a2e65e7 HG |
877 | } else { |
878 | msleep(20); /* XXX */ | |
879 | for_each_dsi_port(port, intel_dsi->ports) | |
880 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); | |
25b4620e | 881 | intel_dsi_msleep(intel_dsi, 100); |
5a2e65e7 | 882 | |
b0dd6887 | 883 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); |
5a2e65e7 | 884 | |
3c0628f8 | 885 | intel_dsi_port_enable(encoder, pipe_config); |
5a2e65e7 HG |
886 | } |
887 | ||
b037d58f | 888 | intel_panel_enable_backlight(pipe_config, conn_state); |
b0dd6887 | 889 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); |
2634fd7f SK |
890 | } |
891 | ||
fefc51e8 JN |
892 | /* |
893 | * DSI port disable has to be done after pipe and plane disable, so we do it in | |
894 | * the post_disable hook. | |
895 | */ | |
896 | static void intel_dsi_disable(struct intel_encoder *encoder, | |
5f88a9c6 VS |
897 | const struct intel_crtc_state *old_crtc_state, |
898 | const struct drm_connector_state *old_conn_state) | |
c315faf8 ID |
899 | { |
900 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 901 | enum port port; |
c315faf8 ID |
902 | |
903 | DRM_DEBUG_KMS("\n"); | |
904 | ||
b0dd6887 | 905 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); |
b037d58f | 906 | intel_panel_disable_backlight(old_conn_state); |
b029e66f | 907 | |
39831451 HG |
908 | /* |
909 | * According to the spec we should send SHUTDOWN before | |
910 | * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing | |
911 | * has shown that the v3 sequence works for v2 VBTs too | |
912 | */ | |
c315faf8 ID |
913 | if (is_vid_mode(intel_dsi)) { |
914 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 915 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 916 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
917 | msleep(10); |
918 | } | |
919 | } | |
920 | ||
46448483 D |
921 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
922 | { | |
923 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
924 | ||
012bf847 | 925 | if (IS_GEMINILAKE(dev_priv)) |
46448483 | 926 | glk_dsi_clear_device_ready(encoder); |
012bf847 JN |
927 | else |
928 | vlv_dsi_clear_device_ready(encoder); | |
46448483 D |
929 | } |
930 | ||
fd6bbda9 | 931 | static void intel_dsi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
932 | const struct intel_crtc_state *pipe_config, |
933 | const struct drm_connector_state *conn_state) | |
1dbd7cb2 | 934 | { |
fac5e23e | 935 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1dbd7cb2 | 936 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5a2e65e7 | 937 | enum port port; |
1881a423 | 938 | u32 val; |
1dbd7cb2 SK |
939 | |
940 | DRM_DEBUG_KMS("\n"); | |
941 | ||
5a2e65e7 HG |
942 | if (is_vid_mode(intel_dsi)) { |
943 | for_each_dsi_port(port, intel_dsi->ports) | |
e518634b | 944 | vlv_dsi_wait_for_fifo_empty(intel_dsi, port); |
5a2e65e7 HG |
945 | |
946 | intel_dsi_port_disable(encoder); | |
947 | usleep_range(2000, 5000); | |
948 | } | |
949 | ||
c7991eca | 950 | intel_dsi_unprepare(encoder); |
5a2e65e7 HG |
951 | |
952 | /* | |
953 | * if disable packets are sent before sending shutdown packet then in | |
954 | * some next enable sequence send turn on packet error is observed | |
955 | */ | |
7108b436 | 956 | if (is_cmd_mode(intel_dsi)) |
b0dd6887 JN |
957 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); |
958 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); | |
c315faf8 | 959 | |
3e40fa8a | 960 | /* Transition to LP-00 */ |
1dbd7cb2 SK |
961 | intel_dsi_clear_device_ready(encoder); |
962 | ||
1881a423 US |
963 | if (IS_BROXTON(dev_priv)) { |
964 | /* Power down DSI regulator to save power */ | |
965 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
966 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); | |
967 | ||
968 | /* Add MIPI IO reset programming for modeset */ | |
969 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
970 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
971 | val & ~MIPIO_RST_CTRL); | |
972 | } | |
973 | ||
e518634b JN |
974 | if (IS_GEN9_LP(dev_priv)) { |
975 | bxt_dsi_pll_disable(encoder); | |
976 | } else { | |
d6e3af54 US |
977 | u32 val; |
978 | ||
e518634b JN |
979 | vlv_dsi_pll_disable(encoder); |
980 | ||
d6e3af54 US |
981 | val = I915_READ(DSPCLK_GATE_D); |
982 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
983 | I915_WRITE(DSPCLK_GATE_D, val); | |
984 | } | |
20e5bf66 | 985 | |
3e40fa8a | 986 | /* Assert reset */ |
b0dd6887 | 987 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); |
df38e655 | 988 | |
c7dc5275 | 989 | /* Power off, try both CRC pmic gpio and VBT */ |
25b4620e | 990 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); |
b0dd6887 | 991 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); |
fc45e821 SK |
992 | if (intel_dsi->gpio_panel) |
993 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
994 | |
995 | /* | |
996 | * FIXME As we do with eDP, just make a note of the time here | |
997 | * and perform the wait before the next panel power on. | |
998 | */ | |
25b4620e | 999 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); |
1dbd7cb2 | 1000 | } |
4e646495 JN |
1001 | |
1002 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
1003 | enum pipe *pipe) | |
1004 | { | |
fac5e23e | 1005 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c0beefd2 | 1006 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
0e6e0be4 | 1007 | intel_wakeref_t wakeref; |
e7d7cad0 | 1008 | enum port port; |
1dcec2f3 | 1009 | bool active = false; |
4e646495 JN |
1010 | |
1011 | DRM_DEBUG_KMS("\n"); | |
1012 | ||
0e6e0be4 CW |
1013 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1014 | encoder->power_domain); | |
1015 | if (!wakeref) | |
6d129bea ID |
1016 | return false; |
1017 | ||
db18b6a6 ID |
1018 | /* |
1019 | * On Broxton the PLL needs to be enabled with a valid divider | |
1020 | * configuration, otherwise accessing DSI registers will hang the | |
1021 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
1022 | */ | |
e518634b | 1023 | if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
1024 | goto out_put_power; |
1025 | ||
4e646495 | 1026 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 1027 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1028 | i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? |
f0f59a00 | 1029 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
1dcec2f3 | 1030 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 1031 | |
e6f57789 JN |
1032 | /* |
1033 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
1034 | * bit in port C control register does not get set. As a | |
1035 | * workaround, check pipe B conf instead. | |
c0beefd2 | 1036 | */ |
920a14b2 TU |
1037 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1038 | port == PORT_C) | |
1dcec2f3 | 1039 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 1040 | |
1dcec2f3 JN |
1041 | /* Try command mode if video mode not enabled */ |
1042 | if (!enabled) { | |
1043 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
1044 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 1045 | } |
1dcec2f3 JN |
1046 | |
1047 | if (!enabled) | |
1048 | continue; | |
1049 | ||
1050 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
1051 | continue; | |
1052 | ||
cc3f90f0 | 1053 | if (IS_GEN9_LP(dev_priv)) { |
6b93e9c8 JN |
1054 | u32 tmp = I915_READ(MIPI_CTRL(port)); |
1055 | tmp &= BXT_PIPE_SELECT_MASK; | |
1056 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
1057 | ||
1058 | if (WARN_ON(tmp > PIPE_C)) | |
1059 | continue; | |
1060 | ||
1061 | *pipe = tmp; | |
1062 | } else { | |
1063 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
1064 | } | |
1065 | ||
1dcec2f3 JN |
1066 | active = true; |
1067 | break; | |
4e646495 | 1068 | } |
1dcec2f3 | 1069 | |
db18b6a6 | 1070 | out_put_power: |
0e6e0be4 | 1071 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
4e646495 | 1072 | |
1dcec2f3 | 1073 | return active; |
4e646495 JN |
1074 | } |
1075 | ||
6f0e7535 | 1076 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
5f88a9c6 | 1077 | struct intel_crtc_state *pipe_config) |
6f0e7535 R |
1078 | { |
1079 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1080 | struct drm_i915_private *dev_priv = to_i915(dev); |
6f0e7535 R |
1081 | struct drm_display_mode *adjusted_mode = |
1082 | &pipe_config->base.adjusted_mode; | |
042ab0c3 | 1083 | struct drm_display_mode *adjusted_mode_sw; |
3c0628f8 | 1084 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
6f0e7535 | 1085 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 1086 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
1087 | unsigned int bpp, fmt; |
1088 | enum port port; | |
cefc4e18 | 1089 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
1090 | u16 hfp_sw, hsync_sw, hbp_sw; |
1091 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
1092 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
1093 | ||
5eff0edf | 1094 | /* FIXME: hw readout should not depend on SW state */ |
3c0628f8 | 1095 | adjusted_mode_sw = &crtc->config->base.adjusted_mode; |
6f0e7535 R |
1096 | |
1097 | /* | |
1098 | * Atleast one port is active as encoder->get_config called only if | |
1099 | * encoder->get_hw_state() returns true. | |
1100 | */ | |
1101 | for_each_dsi_port(port, intel_dsi->ports) { | |
1102 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
1103 | break; | |
1104 | } | |
1105 | ||
1106 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
ca0b04db HG |
1107 | bpp = mipi_dsi_pixel_format_to_bpp( |
1108 | pixel_format_from_register_bits(fmt)); | |
6f0e7535 | 1109 | |
49965350 VS |
1110 | pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); |
1111 | ||
aec0246f US |
1112 | /* Enable Frame time stamo based scanline reporting */ |
1113 | adjusted_mode->private_flags |= | |
1114 | I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; | |
1115 | ||
6f0e7535 R |
1116 | /* In terms of pixels */ |
1117 | adjusted_mode->crtc_hdisplay = | |
1118 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
1119 | adjusted_mode->crtc_vdisplay = | |
1120 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
1121 | adjusted_mode->crtc_vtotal = | |
1122 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
1123 | ||
cefc4e18 R |
1124 | hactive = adjusted_mode->crtc_hdisplay; |
1125 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
1126 | ||
6f0e7535 | 1127 | /* |
cefc4e18 R |
1128 | * Meaningful for video mode non-burst sync pulse mode only, |
1129 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 1130 | */ |
cefc4e18 R |
1131 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
1132 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
1133 | ||
1134 | /* harizontal values are in terms of high speed byte clock */ | |
1135 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
1136 | intel_dsi->burst_mode_ratio); | |
1137 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
1138 | intel_dsi->burst_mode_ratio); | |
1139 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
1140 | intel_dsi->burst_mode_ratio); | |
1141 | ||
1142 | if (intel_dsi->dual_link) { | |
1143 | hfp *= 2; | |
1144 | hsync *= 2; | |
1145 | hbp *= 2; | |
1146 | } | |
6f0e7535 R |
1147 | |
1148 | /* vertical values are in terms of lines */ | |
1149 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
1150 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
1151 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
1152 | ||
cefc4e18 R |
1153 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
1154 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
1155 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 1156 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 1157 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 1158 | |
cefc4e18 R |
1159 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
1160 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
1161 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
1162 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 1163 | |
042ab0c3 R |
1164 | /* |
1165 | * In BXT DSI there is no regs programmed with few horizontal timings | |
1166 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
1167 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
1168 | * Actually here for the given adjusted_mode, we are calculating the | |
1169 | * value programmed to the port and then back to the horizontal timing | |
1170 | * param in pixels. This is the expected value, including roundup errors | |
1171 | * And if that is same as retrieved value from port, then | |
1172 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
1173 | * match with SW state to nullify the errors. | |
1174 | */ | |
1175 | /* Calculating the value programmed to the Port register */ | |
1176 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
1177 | adjusted_mode_sw->crtc_hdisplay; | |
1178 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
1179 | adjusted_mode_sw->crtc_hsync_start; | |
1180 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
1181 | adjusted_mode_sw->crtc_hsync_end; | |
1182 | ||
1183 | if (intel_dsi->dual_link) { | |
1184 | hfp_sw /= 2; | |
1185 | hsync_sw /= 2; | |
1186 | hbp_sw /= 2; | |
1187 | } | |
1188 | ||
1189 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
1190 | intel_dsi->burst_mode_ratio); | |
1191 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
1192 | intel_dsi->burst_mode_ratio); | |
1193 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
1194 | intel_dsi->burst_mode_ratio); | |
1195 | ||
1196 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
1197 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
1198 | intel_dsi->burst_mode_ratio); | |
1199 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
1200 | intel_dsi->burst_mode_ratio); | |
1201 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
1202 | intel_dsi->burst_mode_ratio); | |
1203 | ||
1204 | if (intel_dsi->dual_link) { | |
1205 | hfp_sw *= 2; | |
1206 | hsync_sw *= 2; | |
1207 | hbp_sw *= 2; | |
1208 | } | |
1209 | ||
1210 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
1211 | hsync_sw + hbp_sw; | |
1212 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
1213 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
1214 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
1215 | crtc_hblank_end_sw = crtc_htotal_sw; | |
1216 | ||
1217 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
1218 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
1219 | ||
1220 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
1221 | adjusted_mode->crtc_hsync_start = | |
1222 | adjusted_mode_sw->crtc_hsync_start; | |
1223 | ||
1224 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
1225 | adjusted_mode->crtc_hsync_end = | |
1226 | adjusted_mode_sw->crtc_hsync_end; | |
1227 | ||
1228 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
1229 | adjusted_mode->crtc_hblank_start = | |
1230 | adjusted_mode_sw->crtc_hblank_start; | |
1231 | ||
1232 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
1233 | adjusted_mode->crtc_hblank_end = | |
1234 | adjusted_mode_sw->crtc_hblank_end; | |
1235 | } | |
6f0e7535 | 1236 | |
4e646495 | 1237 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 1238 | struct intel_crtc_state *pipe_config) |
4e646495 | 1239 | { |
e2d214ae | 1240 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d7d85d85 | 1241 | u32 pclk; |
4e646495 JN |
1242 | DRM_DEBUG_KMS("\n"); |
1243 | ||
e1214b95 VS |
1244 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); |
1245 | ||
e518634b | 1246 | if (IS_GEN9_LP(dev_priv)) { |
6f0e7535 | 1247 | bxt_dsi_get_pipe_config(encoder, pipe_config); |
ca0b04db | 1248 | pclk = bxt_dsi_get_pclk(encoder, pipe_config); |
e518634b | 1249 | } else { |
ca0b04db | 1250 | pclk = vlv_dsi_get_pclk(encoder, pipe_config); |
e518634b | 1251 | } |
6f0e7535 | 1252 | |
e518634b JN |
1253 | if (pclk) { |
1254 | pipe_config->base.adjusted_mode.crtc_clock = pclk; | |
1255 | pipe_config->port_clock = pclk; | |
1256 | } | |
4e646495 JN |
1257 | } |
1258 | ||
4e646495 JN |
1259 | /* return txclkesc cycles in terms of divider and duration in us */ |
1260 | static u16 txclkesc(u32 divider, unsigned int us) | |
1261 | { | |
1262 | switch (divider) { | |
1263 | case ESCAPE_CLOCK_DIVIDER_1: | |
1264 | default: | |
1265 | return 20 * us; | |
1266 | case ESCAPE_CLOCK_DIVIDER_2: | |
1267 | return 10 * us; | |
1268 | case ESCAPE_CLOCK_DIVIDER_4: | |
1269 | return 5 * us; | |
1270 | } | |
1271 | } | |
1272 | ||
4e646495 | 1273 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1274 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1275 | { |
1276 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1277 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 1278 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1279 | enum port port; |
1e78aa01 | 1280 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1281 | unsigned int lane_count = intel_dsi->lane_count; |
1282 | ||
1283 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1284 | ||
aad941d5 VS |
1285 | hactive = adjusted_mode->crtc_hdisplay; |
1286 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1287 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1288 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1289 | |
aa102d28 GS |
1290 | if (intel_dsi->dual_link) { |
1291 | hactive /= 2; | |
1292 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1293 | hactive += intel_dsi->pixel_overlap; | |
1294 | hfp /= 2; | |
1295 | hsync /= 2; | |
1296 | hbp /= 2; | |
1297 | } | |
1298 | ||
aad941d5 VS |
1299 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1300 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1301 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1302 | |
1303 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1304 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1305 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1306 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1307 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1308 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1309 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1310 | |
aa102d28 | 1311 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1312 | if (IS_GEN9_LP(dev_priv)) { |
d2e08c0f SS |
1313 | /* |
1314 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1315 | * This is different from calculated hactive and | |
1316 | * vactive, as they are calculated per channel basis, | |
1317 | * whereas these values should be based on resolution. | |
1318 | */ | |
1319 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1320 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1321 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1322 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1323 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1324 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1325 | } |
1326 | ||
aa102d28 GS |
1327 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1328 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1329 | ||
1330 | /* meaningful for video mode non-burst sync pulse mode only, | |
1331 | * can be zero for non-burst sync events and burst modes */ | |
1332 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1333 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1334 | ||
1335 | /* vertical values are in terms of lines */ | |
1336 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1337 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1338 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1339 | } | |
4e646495 JN |
1340 | } |
1341 | ||
1e78aa01 JN |
1342 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1343 | { | |
1344 | switch (fmt) { | |
1345 | case MIPI_DSI_FMT_RGB888: | |
1346 | return VID_MODE_FORMAT_RGB888; | |
1347 | case MIPI_DSI_FMT_RGB666: | |
1348 | return VID_MODE_FORMAT_RGB666; | |
1349 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1350 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1351 | case MIPI_DSI_FMT_RGB565: | |
1352 | return VID_MODE_FORMAT_RGB565; | |
1353 | default: | |
1354 | MISSING_CASE(fmt); | |
1355 | return VID_MODE_FORMAT_RGB666; | |
1356 | } | |
1357 | } | |
1358 | ||
5eff0edf | 1359 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
5f88a9c6 | 1360 | const struct intel_crtc_state *pipe_config) |
4e646495 JN |
1361 | { |
1362 | struct drm_encoder *encoder = &intel_encoder->base; | |
1363 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1364 | struct drm_i915_private *dev_priv = to_i915(dev); |
5eff0edf | 1365 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e646495 | 1366 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5eff0edf | 1367 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
24ee0e64 | 1368 | enum port port; |
1e78aa01 | 1369 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1370 | u32 val, tmp; |
24ee0e64 | 1371 | u16 mode_hdisplay; |
4e646495 | 1372 | |
e7d7cad0 | 1373 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1374 | |
aad941d5 | 1375 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1376 | |
24ee0e64 GS |
1377 | if (intel_dsi->dual_link) { |
1378 | mode_hdisplay /= 2; | |
1379 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1380 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1381 | } | |
4e646495 | 1382 | |
24ee0e64 | 1383 | for_each_dsi_port(port, intel_dsi->ports) { |
920a14b2 | 1384 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d2e08c0f SS |
1385 | /* |
1386 | * escape clock divider, 20MHz, shared for A and C. | |
1387 | * device ready must be off when doing this! txclkesc? | |
1388 | */ | |
1389 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1390 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1391 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1392 | ESCAPE_CLOCK_DIVIDER_1); | |
1393 | ||
1394 | /* read request priority is per pipe */ | |
1395 | tmp = I915_READ(MIPI_CTRL(port)); | |
1396 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1397 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1398 | READ_REQUEST_PRIORITY_HIGH); | |
cc3f90f0 | 1399 | } else if (IS_GEN9_LP(dev_priv)) { |
56c48978 D |
1400 | enum pipe pipe = intel_crtc->pipe; |
1401 | ||
d2e08c0f SS |
1402 | tmp = I915_READ(MIPI_CTRL(port)); |
1403 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1404 | ||
56c48978 | 1405 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1406 | I915_WRITE(MIPI_CTRL(port), tmp); |
1407 | } | |
24ee0e64 GS |
1408 | |
1409 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1410 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1411 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1412 | ||
1413 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1414 | ||
1415 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1416 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1417 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1418 | } | |
4e646495 JN |
1419 | |
1420 | set_dsi_timings(encoder, adjusted_mode); | |
1421 | ||
1422 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1423 | if (is_cmd_mode(intel_dsi)) { | |
1424 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1425 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1426 | } else { | |
1427 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1428 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1429 | } |
4e646495 | 1430 | |
24ee0e64 GS |
1431 | tmp = 0; |
1432 | if (intel_dsi->eotp_pkt == 0) | |
1433 | tmp |= EOT_DISABLE; | |
1434 | if (intel_dsi->clock_stop) | |
1435 | tmp |= CLOCKSTOP; | |
4e646495 | 1436 | |
cc3f90f0 | 1437 | if (IS_GEN9_LP(dev_priv)) { |
f90e8c36 JN |
1438 | tmp |= BXT_DPHY_DEFEATURE_EN; |
1439 | if (!is_cmd_mode(intel_dsi)) | |
1440 | tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; | |
1441 | } | |
1442 | ||
24ee0e64 GS |
1443 | for_each_dsi_port(port, intel_dsi->ports) { |
1444 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1445 | ||
1446 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1447 | * EOT and stop state. */ | |
1448 | ||
1449 | /* | |
1450 | * In burst mode, value greater than one DPI line Time in byte | |
1451 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1452 | * said value is recommended. | |
1453 | * | |
1454 | * In non-burst mode, Value greater than one DPI frame time in | |
1455 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1456 | * said value is recommended. | |
1457 | * | |
1458 | * In DBI only mode, value greater than one DBI frame time in | |
1459 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1460 | * said value is recommended. | |
1461 | */ | |
4e646495 | 1462 | |
24ee0e64 GS |
1463 | if (is_vid_mode(intel_dsi) && |
1464 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1465 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1466 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1467 | intel_dsi->lane_count, |
1468 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1469 | } else { |
1470 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1471 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1472 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1473 | bpp, intel_dsi->lane_count, |
1474 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1475 | } |
1476 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1477 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1478 | intel_dsi->turn_arnd_val); | |
1479 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1480 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1481 | |
24ee0e64 | 1482 | /* dphy stuff */ |
f1c79f16 | 1483 | |
24ee0e64 GS |
1484 | /* in terms of low power clock */ |
1485 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1486 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1487 | |
cc3f90f0 | 1488 | if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { |
d2e08c0f SS |
1489 | /* |
1490 | * BXT spec says write MIPI_INIT_COUNT for | |
1491 | * both the ports, even if only one is | |
1492 | * getting used. So write the other port | |
1493 | * if not in dual link mode. | |
1494 | */ | |
1495 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1496 | PORT_A ? PORT_C : PORT_A), | |
1497 | intel_dsi->init_count); | |
1498 | } | |
4e646495 | 1499 | |
24ee0e64 | 1500 | /* recovery disables */ |
87c54d0e | 1501 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1502 | |
24ee0e64 GS |
1503 | /* in terms of low power clock */ |
1504 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1505 | |
24ee0e64 GS |
1506 | /* in terms of txbyteclkhs. actual high to low switch + |
1507 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1508 | * | |
1509 | * XXX: write MIPI_STOP_STATE_STALL? | |
1510 | */ | |
1511 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1512 | intel_dsi->hs_to_lp_count); | |
1513 | ||
1514 | /* XXX: low power clock equivalence in terms of byte clock. | |
1515 | * the number of byte clocks occupied in one low power clock. | |
1516 | * based on txbyteclkhs and txclkesc. | |
1517 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1518 | * ) / 105.??? | |
1519 | */ | |
1520 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1521 | ||
b426f985 D |
1522 | if (IS_GEMINILAKE(dev_priv)) { |
1523 | I915_WRITE(MIPI_TLPX_TIME_COUNT(port), | |
1524 | intel_dsi->lp_byte_clk); | |
1525 | /* Shadow of DPHY reg */ | |
1526 | I915_WRITE(MIPI_CLK_LANE_TIMING(port), | |
1527 | intel_dsi->dphy_reg); | |
1528 | } | |
1529 | ||
24ee0e64 GS |
1530 | /* the bw essential for transmitting 16 long packets containing |
1531 | * 252 bytes meant for dcs write memory command is programmed in | |
1532 | * this register in terms of byte clocks. based on dsi transfer | |
1533 | * rate and the number of lanes configured the time taken to | |
1534 | * transmit 16 long packets in a dsi stream varies. */ | |
1535 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1536 | ||
1537 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1538 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1539 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1540 | ||
1541 | if (is_vid_mode(intel_dsi)) | |
1542 | /* Some panels might have resolution which is not a | |
1543 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1544 | * resolution support for such panels by default */ | |
1545 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1546 | intel_dsi->video_frmt_cfg_bits | | |
1547 | intel_dsi->video_mode_format | | |
1548 | IP_TG_CONFIG | | |
1549 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1550 | } | |
4e646495 JN |
1551 | } |
1552 | ||
c7991eca HG |
1553 | static void intel_dsi_unprepare(struct intel_encoder *encoder) |
1554 | { | |
1555 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1556 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
1557 | enum port port; | |
1558 | u32 val; | |
1559 | ||
012bf847 JN |
1560 | if (IS_GEMINILAKE(dev_priv)) |
1561 | return; | |
c7991eca | 1562 | |
012bf847 JN |
1563 | for_each_dsi_port(port, intel_dsi->ports) { |
1564 | /* Panel commands can be sent when clock is in LP11 */ | |
1565 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
c7991eca | 1566 | |
012bf847 JN |
1567 | if (IS_GEN9_LP(dev_priv)) |
1568 | bxt_dsi_reset_clocks(encoder, port); | |
1569 | else | |
1570 | vlv_dsi_reset_clocks(encoder, port); | |
1571 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
c7991eca | 1572 | |
012bf847 JN |
1573 | val = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
1574 | val &= ~VID_MODE_FORMAT_MASK; | |
1575 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1576 | ||
1577 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); | |
c7991eca HG |
1578 | } |
1579 | } | |
1580 | ||
593e0622 JN |
1581 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1582 | { | |
1583 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1584 | ||
fc45e821 SK |
1585 | /* dispose of the gpios */ |
1586 | if (intel_dsi->gpio_panel) | |
1587 | gpiod_put(intel_dsi->gpio_panel); | |
1588 | ||
593e0622 JN |
1589 | intel_encoder_destroy(encoder); |
1590 | } | |
1591 | ||
4e646495 | 1592 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1593 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1594 | }; |
1595 | ||
1596 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1597 | .get_modes = intel_dsi_get_modes, | |
1598 | .mode_valid = intel_dsi_mode_valid, | |
ba14a1ad | 1599 | .atomic_check = intel_digital_connector_atomic_check, |
4e646495 JN |
1600 | }; |
1601 | ||
1602 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
1ebaa0b9 | 1603 | .late_register = intel_connector_register, |
c191eca1 | 1604 | .early_unregister = intel_connector_unregister, |
d4b26e4f | 1605 | .destroy = intel_connector_destroy, |
4e646495 | 1606 | .fill_modes = drm_helper_probe_single_connector_modes, |
ba14a1ad ML |
1607 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
1608 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
c6f95f27 | 1609 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
ba14a1ad | 1610 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
4e646495 JN |
1611 | }; |
1612 | ||
86ef615f VS |
1613 | static enum drm_panel_orientation |
1614 | vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) | |
82daca29 HG |
1615 | { |
1616 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
86ef615f VS |
1617 | struct intel_encoder *encoder = connector->encoder; |
1618 | enum intel_display_power_domain power_domain; | |
1619 | enum drm_panel_orientation orientation; | |
1620 | struct intel_plane *plane; | |
1621 | struct intel_crtc *crtc; | |
0e6e0be4 | 1622 | intel_wakeref_t wakeref; |
86ef615f | 1623 | enum pipe pipe; |
82daca29 HG |
1624 | u32 val; |
1625 | ||
86ef615f VS |
1626 | if (!encoder->get_hw_state(encoder, &pipe)) |
1627 | return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
82daca29 | 1628 | |
86ef615f VS |
1629 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
1630 | plane = to_intel_plane(crtc->base.primary); | |
1631 | ||
1632 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
0e6e0be4 CW |
1633 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
1634 | if (!wakeref) | |
86ef615f VS |
1635 | return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; |
1636 | ||
1637 | val = I915_READ(DSPCNTR(plane->i9xx_plane)); | |
1638 | ||
1639 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
1640 | orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
1641 | else if (val & DISPPLANE_ROTATE_180) | |
1642 | orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; | |
1643 | else | |
1644 | orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; | |
1645 | ||
0e6e0be4 | 1646 | intel_display_power_put(dev_priv, power_domain, wakeref); |
82daca29 HG |
1647 | |
1648 | return orientation; | |
1649 | } | |
1650 | ||
86ef615f VS |
1651 | static enum drm_panel_orientation |
1652 | vlv_dsi_get_panel_orientation(struct intel_connector *connector) | |
1653 | { | |
1654 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
1655 | enum drm_panel_orientation orientation; | |
1656 | ||
1657 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1658 | orientation = vlv_dsi_get_hw_panel_orientation(connector); | |
1659 | if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) | |
1660 | return orientation; | |
1661 | } | |
1662 | ||
c1cd5b24 | 1663 | return intel_dsi_get_panel_orientation(connector); |
86ef615f VS |
1664 | } |
1665 | ||
f4ee265f VS |
1666 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1667 | { | |
8b45330a | 1668 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
f4ee265f VS |
1669 | |
1670 | if (connector->panel.fixed_mode) { | |
8b45330a ML |
1671 | u32 allowed_scalers; |
1672 | ||
1673 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
b2ae318a | 1674 | if (!HAS_GMCH(dev_priv)) |
8b45330a ML |
1675 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); |
1676 | ||
1677 | drm_connector_attach_scaling_mode_property(&connector->base, | |
1678 | allowed_scalers); | |
1679 | ||
eead06df | 1680 | connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
82daca29 HG |
1681 | |
1682 | connector->base.display_info.panel_orientation = | |
86ef615f | 1683 | vlv_dsi_get_panel_orientation(connector); |
82daca29 HG |
1684 | drm_connector_init_panel_orientation_property( |
1685 | &connector->base, | |
1686 | connector->panel.fixed_mode->hdisplay, | |
1687 | connector->panel.fixed_mode->vdisplay); | |
f4ee265f VS |
1688 | } |
1689 | } | |
1690 | ||
e518634b | 1691 | void vlv_dsi_init(struct drm_i915_private *dev_priv) |
4e646495 | 1692 | { |
c39055b0 | 1693 | struct drm_device *dev = &dev_priv->drm; |
4e646495 JN |
1694 | struct intel_dsi *intel_dsi; |
1695 | struct intel_encoder *intel_encoder; | |
1696 | struct drm_encoder *encoder; | |
1697 | struct intel_connector *intel_connector; | |
1698 | struct drm_connector *connector; | |
dee2370c | 1699 | struct drm_display_mode *fixed_mode; |
7e9804fd | 1700 | enum port port; |
4e646495 JN |
1701 | |
1702 | DRM_DEBUG_KMS("\n"); | |
1703 | ||
3e6bd011 | 1704 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1705 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1706 | return; |
3e6bd011 | 1707 | |
012bf847 | 1708 | if (IS_GEN9_LP(dev_priv)) |
c6c794a2 | 1709 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; |
012bf847 JN |
1710 | else |
1711 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
3e6bd011 | 1712 | |
4e646495 JN |
1713 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1714 | if (!intel_dsi) | |
4328633d | 1715 | return; |
4e646495 | 1716 | |
08d9bc92 | 1717 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1718 | if (!intel_connector) { |
1719 | kfree(intel_dsi); | |
4328633d | 1720 | return; |
4e646495 JN |
1721 | } |
1722 | ||
1723 | intel_encoder = &intel_dsi->base; | |
1724 | encoder = &intel_encoder->base; | |
1725 | intel_dsi->attached_connector = intel_connector; | |
1726 | ||
1727 | connector = &intel_connector->base; | |
1728 | ||
13a3d91f | 1729 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1730 | "DSI %c", port_name(port)); |
4e646495 | 1731 | |
4e646495 | 1732 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1733 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
fefc51e8 | 1734 | intel_encoder->disable = intel_dsi_disable; |
4e646495 JN |
1735 | intel_encoder->post_disable = intel_dsi_post_disable; |
1736 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1737 | intel_encoder->get_config = intel_dsi_get_config; | |
63a23d24 | 1738 | intel_encoder->update_pipe = intel_panel_update_backlight; |
4e646495 JN |
1739 | |
1740 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1741 | ||
03cdc1d4 | 1742 | intel_encoder->port = port; |
79f255a0 | 1743 | |
2e85ab4f JN |
1744 | /* |
1745 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1746 | * port C. BXT isn't limited like this. | |
1747 | */ | |
cc3f90f0 | 1748 | if (IS_GEN9_LP(dev_priv)) |
2e85ab4f JN |
1749 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
1750 | else if (port == PORT_A) | |
701d25b4 | 1751 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1752 | else |
701d25b4 | 1753 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1754 | |
6a2f0641 | 1755 | if (dev_priv->vbt.dsi.config->dual_link) |
701d25b4 | 1756 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
6a2f0641 | 1757 | else |
701d25b4 | 1758 | intel_dsi->ports = BIT(port); |
82425785 | 1759 | |
6a2f0641 MC |
1760 | intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; |
1761 | intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; | |
1ecc1c6c | 1762 | |
7e9804fd JN |
1763 | /* Create a DSI host (and a device) for each port. */ |
1764 | for_each_dsi_port(port, intel_dsi->ports) { | |
1765 | struct intel_dsi_host *host; | |
1766 | ||
8e54d4fe MC |
1767 | host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, |
1768 | port); | |
7e9804fd JN |
1769 | if (!host) |
1770 | goto err; | |
1771 | ||
1772 | intel_dsi->dsi_hosts[port] = host; | |
1773 | } | |
1774 | ||
3f751d65 | 1775 | if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { |
4e646495 JN |
1776 | DRM_DEBUG_KMS("no device found\n"); |
1777 | goto err; | |
1778 | } | |
1779 | ||
fc45e821 SK |
1780 | /* |
1781 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1782 | * Panel control. | |
1783 | */ | |
645a2f6e US |
1784 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1785 | (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { | |
fc45e821 SK |
1786 | intel_dsi->gpio_panel = |
1787 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1788 | ||
1789 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1790 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1791 | intel_dsi->gpio_panel = NULL; | |
1792 | } | |
1793 | } | |
1794 | ||
4e646495 | 1795 | intel_encoder->type = INTEL_OUTPUT_DSI; |
79f255a0 | 1796 | intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; |
bc079e8b | 1797 | intel_encoder->cloneable = 0; |
4e646495 JN |
1798 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1799 | DRM_MODE_CONNECTOR_DSI); | |
1800 | ||
1801 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1802 | ||
1803 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1804 | connector->interlace_allowed = false; | |
1805 | connector->doublescan_allowed = false; | |
1806 | ||
1807 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1808 | ||
593e0622 | 1809 | mutex_lock(&dev->mode_config.mutex); |
dee2370c | 1810 | fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); |
593e0622 JN |
1811 | mutex_unlock(&dev->mode_config.mutex); |
1812 | ||
4e646495 JN |
1813 | if (!fixed_mode) { |
1814 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1815 | goto err; | |
1816 | } | |
1817 | ||
d93fa1b4 | 1818 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
fda9ee98 | 1819 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
f4ee265f VS |
1820 | |
1821 | intel_dsi_add_properties(intel_connector); | |
1822 | ||
4328633d | 1823 | return; |
4e646495 JN |
1824 | |
1825 | err: | |
1826 | drm_encoder_cleanup(&intel_encoder->base); | |
1827 | kfree(intel_dsi); | |
1828 | kfree(intel_connector); | |
4e646495 | 1829 | } |