[thirdparty/kernel/stable.git] / drivers / gpu / drm / imx / dw_hdmi-imx.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
 *
 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
 */
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <drm/bridge/dw_hdmi.h>
#include <video/imx-ipu-v3.h>
#include <linux/regmap.h>
#include <drm/drm_of.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder_slave.h>

#include "imx-drm.h"

struct imx_hdmi {
	struct device *dev;
	struct drm_encoder encoder;
	struct dw_hdmi *hdmi;
	struct regmap *regmap;
};

static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
{
	return container_of(e, struct imx_hdmi, encoder);
}

static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
	{
		45250000, {
			{ 0x01e0, 0x0000 },
			{ 0x21e1, 0x0000 },
			{ 0x41e2, 0x0000 }
		},
	}, {
		92500000, {
			{ 0x0140, 0x0005 },
			{ 0x2141, 0x0005 },
			{ 0x4142, 0x0005 },
	},
	}, {
		148500000, {
			{ 0x00a0, 0x000a },
			{ 0x20a1, 0x000a },
			{ 0x40a2, 0x000a },
		},
	}, {
		216000000, {
			{ 0x00a0, 0x000a },
			{ 0x2001, 0x000f },
			{ 0x4002, 0x000f },
		},
	}, {
		~0UL, {
			{ 0x0000, 0x0000 },
			{ 0x0000, 0x0000 },
			{ 0x0000, 0x0000 },
		},
	}
};

static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
	/*      pixelclk     bpp8    bpp10   bpp12 */
	{
		54000000, { 0x091c, 0x091c, 0x06dc },
	}, {
		58400000, { 0x091c, 0x06dc, 0x06dc },
	}, {
		72000000, { 0x06dc, 0x06dc, 0x091c },
	}, {
		74250000, { 0x06dc, 0x0b5c, 0x091c },
	}, {
		118800000, { 0x091c, 0x091c, 0x06dc },
	}, {
		216000000, { 0x06dc, 0x0b5c, 0x091c },
	}, {
		~0UL, { 0x0000, 0x0000, 0x0000 },
	},
};

/*
 * Resistance term 133Ohm Cfg
 * PREEMP config 0.00
 * TX/CK level 10
 */
static const struct dw_hdmi_phy_config imx_phy_config[] = {
	/*pixelclk   symbol   term   vlev */
	{ 216000000, 0x800d, 0x0005, 0x01ad},
	{ ~0UL,      0x0000, 0x0000, 0x0000}
};

static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
{
	struct device_node *np = hdmi->dev->of_node;

	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	if (IS_ERR(hdmi->regmap)) {
		dev_err(hdmi->dev, "Unable to get gpr\n");
		return PTR_ERR(hdmi->regmap);
	}

	return 0;
}

static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
{
}

static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
{
	struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
	int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);

	regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
			   IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
			   mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
}

static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
				    struct drm_crtc_state *crtc_state,
				    struct drm_connector_state *conn_state)
{
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

	imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
	imx_crtc_state->di_hsync_pin = 2;
	imx_crtc_state->di_vsync_pin = 3;

	return 0;
}

static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
	.enable     = dw_hdmi_imx_encoder_enable,
	.disable    = dw_hdmi_imx_encoder_disable,
	.atomic_check = dw_hdmi_imx_atomic_check,
};

static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
	.destroy = drm_encoder_cleanup,
};

static enum drm_mode_status
imx6q_hdmi_mode_valid(struct drm_connector *con,
		      const struct drm_display_mode *mode)
{
	if (mode->clock < 13500)
		return MODE_CLOCK_LOW;
	/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
	if (mode->clock > 216000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static enum drm_mode_status
imx6dl_hdmi_mode_valid(struct drm_connector *con,
		       const struct drm_display_mode *mode)
{
	if (mode->clock < 13500)
		return MODE_CLOCK_LOW;
	/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
	if (mode->clock > 216000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
	.mpll_cfg   = imx_mpll_cfg,
	.cur_ctr    = imx_cur_ctr,
	.phy_config = imx_phy_config,
	.mode_valid = imx6q_hdmi_mode_valid,
};

static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
	.mpll_cfg = imx_mpll_cfg,
	.cur_ctr  = imx_cur_ctr,
	.phy_config = imx_phy_config,
	.mode_valid = imx6dl_hdmi_mode_valid,
};

static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
	{ .compatible = "fsl,imx6q-hdmi",
	  .data = &imx6q_hdmi_drv_data
	}, {
	  .compatible = "fsl,imx6dl-hdmi",
	  .data = &imx6dl_hdmi_drv_data
	},
	{},
};
MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);

static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	const struct dw_hdmi_plat_data *plat_data;
	const struct of_device_id *match;
	struct drm_device *drm = data;
	struct drm_encoder *encoder;
	struct imx_hdmi *hdmi;
	int ret;

	if (!pdev->dev.of_node)
		return -ENODEV;

	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
	if (!hdmi)
		return -ENOMEM;

	match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
	plat_data = match->data;
	hdmi->dev = &pdev->dev;
	encoder = &hdmi->encoder;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
	/*
	 * If we failed to find the CRTC(s) which this encoder is
	 * supposed to be connected to, it's because the CRTC has
	 * not been registered yet.  Defer probing, and hope that
	 * the required CRTC is added later.
	 */
	if (encoder->possible_crtcs == 0)
		return -EPROBE_DEFER;

	ret = dw_hdmi_imx_parse_dt(hdmi);
	if (ret < 0)
		return ret;

	drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
	drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
			 DRM_MODE_ENCODER_TMDS, NULL);

	platform_set_drvdata(pdev, hdmi);

	hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);

	/*
	 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
	 * which would have called the encoder cleanup.  Do it manually.
	 */
	if (IS_ERR(hdmi->hdmi)) {
		ret = PTR_ERR(hdmi->hdmi);
		drm_encoder_cleanup(encoder);
	}

	return ret;
}

static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
			       void *data)
{
	struct imx_hdmi *hdmi = dev_get_drvdata(dev);

	dw_hdmi_unbind(hdmi->hdmi);
}

static const struct component_ops dw_hdmi_imx_ops = {
	.bind	= dw_hdmi_imx_bind,
	.unbind	= dw_hdmi_imx_unbind,
};

static int dw_hdmi_imx_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &dw_hdmi_imx_ops);
}

static int dw_hdmi_imx_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &dw_hdmi_imx_ops);

	return 0;
}

static struct platform_driver dw_hdmi_imx_platform_driver = {
	.probe  = dw_hdmi_imx_probe,
	.remove = dw_hdmi_imx_remove,
	.driver = {
		.name = "dwhdmi-imx",
		.of_match_table = dw_hdmi_imx_dt_ids,
	},
};

module_platform_driver(dw_hdmi_imx_platform_driver);

MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:dwhdmi-imx");
Commit	Line	Data
946485d0	1	// SPDX-License-Identifier: GPL-2.0
3d1b35a3 AY	2	/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3d1b35a3 AY	3	*
b21f4b65	4	* derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
3d1b35a3 AY	5	*/
	6	#include <linux/module.h>
	7	#include <linux/platform_device.h>
	8	#include <linux/component.h>
	9	#include <linux/mfd/syscon.h>
	10	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
b21f4b65	11	#include <drm/bridge/dw_hdmi.h>
3d1b35a3 AY	12	#include <video/imx-ipu-v3.h>
	13	#include <linux/regmap.h>
	14	#include <drm/drm_of.h>
	15	#include <drm/drmP.h>
fcd70cd3	16	#include <drm/drm_atomic_helper.h>
3d1b35a3 AY	17	#include <drm/drm_edid.h>
	18	#include <drm/drm_encoder_slave.h>
	19
	20	#include "imx-drm.h"
3d1b35a3	21
b21f4b65	22	struct imx_hdmi {
3d1b35a3	23	struct device *dev;
49f98bc4	24	struct drm_encoder encoder;
eea034af	25	struct dw_hdmi *hdmi;
3d1b35a3 AY	26	struct regmap *regmap;
	27	};
	28
49f98bc4 PZ	29	static inline struct imx_hdmi enc_to_imx_hdmi(struct drm_encoder e)
	30	{
	31	return container_of(e, struct imx_hdmi, encoder);
	32	}
	33
b21f4b65	34	static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
aaa757a0 AY	35	{
	36	45250000, {
	37	{ 0x01e0, 0x0000 },
	38	{ 0x21e1, 0x0000 },
	39	{ 0x41e2, 0x0000 }
	40	},
	41	}, {
	42	92500000, {
	43	{ 0x0140, 0x0005 },
	44	{ 0x2141, 0x0005 },
	45	{ 0x4142, 0x0005 },
	46	},
	47	}, {
	48	148500000, {
	49	{ 0x00a0, 0x000a },
	50	{ 0x20a1, 0x000a },
	51	{ 0x40a2, 0x000a },
	52	},
	53	}, {
a5f4185c	54	216000000, {
aaa757a0 AY	55	{ 0x00a0, 0x000a },
	56	{ 0x2001, 0x000f },
	57	{ 0x4002, 0x000f },
	58	},
a5f4185c LS	59	}, {
	60	~0UL, {
	61	{ 0x0000, 0x0000 },
	62	{ 0x0000, 0x0000 },
	63	{ 0x0000, 0x0000 },
	64	},
aaa757a0 AY	65	}
	66	};
	67
b21f4b65	68	static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
aaa757a0 AY	69	/* pixelclk bpp8 bpp10 bpp12 */
	70	{
	71	54000000, { 0x091c, 0x091c, 0x06dc },
	72	}, {
	73	58400000, { 0x091c, 0x06dc, 0x06dc },
	74	}, {
	75	72000000, { 0x06dc, 0x06dc, 0x091c },
	76	}, {
	77	74250000, { 0x06dc, 0x0b5c, 0x091c },
	78	}, {
	79	118800000, { 0x091c, 0x091c, 0x06dc },
	80	}, {
	81	216000000, { 0x06dc, 0x0b5c, 0x091c },
6e8958ec PZ	82	}, {
	83	~0UL, { 0x0000, 0x0000, 0x0000 },
	84	},
aaa757a0 AY	85	};
aaa757a0 AY	86
36b8ae0d RK	87	/*
	88	* Resistance term 133Ohm Cfg
	89	* PREEMP config 0.00
	90	* TX/CK level 10
	91	*/
034705a4 YY	92	static const struct dw_hdmi_phy_config imx_phy_config[] = {
034705a4 YY	93	/pixelclk symbol term vlev /
a5f4185c	94	{ 216000000, 0x800d, 0x0005, 0x01ad},
034705a4	95	{ ~0UL, 0x0000, 0x0000, 0x0000}
aaa757a0 AY	96	};
aaa757a0 AY	97
b21f4b65	98	static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
3d1b35a3 AY	99	{
	100	struct device_node *np = hdmi->dev->of_node;
	101
	102	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	103	if (IS_ERR(hdmi->regmap)) {
	104	dev_err(hdmi->dev, "Unable to get gpr\n");
	105	return PTR_ERR(hdmi->regmap);
	106	}
	107
	108	return 0;
	109	}
	110
b21f4b65	111	static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
3d1b35a3 AY	112	{
	113	}
	114
f6e396e5	115	static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
3d1b35a3	116	{
49f98bc4	117	struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
53141e42	118	int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
3d1b35a3 AY	119
	120	regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
	121	IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
	122	mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
	123	}
	124
49f98bc4 PZ	125	static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
	126	struct drm_crtc_state *crtc_state,
	127	struct drm_connector_state *conn_state)
	128	{
	129	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
	130
	131	imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
	132	imx_crtc_state->di_hsync_pin = 2;
	133	imx_crtc_state->di_vsync_pin = 3;
	134
	135	return 0;
	136	}
	137
7ae847dd	138	static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
f6e396e5	139	.enable = dw_hdmi_imx_encoder_enable,
b21f4b65	140	.disable = dw_hdmi_imx_encoder_disable,
49f98bc4	141	.atomic_check = dw_hdmi_imx_atomic_check,
3d1b35a3 AY	142	};
3d1b35a3 AY	143
7ae847dd	144	static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
3d1b35a3 AY	145	.destroy = drm_encoder_cleanup,
	146	};
	147
b0febde7 JA	148	static enum drm_mode_status
	149	imx6q_hdmi_mode_valid(struct drm_connector *con,
	150	const struct drm_display_mode *mode)
081c80e8 PZ	151	{
	152	if (mode->clock < 13500)
	153	return MODE_CLOCK_LOW;
a5f4185c LS	154	/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
a5f4185c LS	155	if (mode->clock > 216000)
081c80e8 PZ	156	return MODE_CLOCK_HIGH;
	157
	158	return MODE_OK;
	159	}
	160
b0febde7 JA	161	static enum drm_mode_status
	162	imx6dl_hdmi_mode_valid(struct drm_connector *con,
	163	const struct drm_display_mode *mode)
081c80e8 PZ	164	{
	165	if (mode->clock < 13500)
	166	return MODE_CLOCK_LOW;
a5f4185c LS	167	/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
a5f4185c LS	168	if (mode->clock > 216000)
081c80e8 PZ	169	return MODE_CLOCK_HIGH;
	170
	171	return MODE_OK;
	172	}
	173
b21f4b65	174	static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
081c80e8 PZ	175	.mpll_cfg = imx_mpll_cfg,
081c80e8 PZ	176	.cur_ctr = imx_cur_ctr,
034705a4	177	.phy_config = imx_phy_config,
081c80e8	178	.mode_valid = imx6q_hdmi_mode_valid,
3d1b35a3 AY	179	};
3d1b35a3 AY	180
b21f4b65	181	static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
aaa757a0 AY	182	.mpll_cfg = imx_mpll_cfg,
aaa757a0 AY	183	.cur_ctr = imx_cur_ctr,
034705a4	184	.phy_config = imx_phy_config,
081c80e8	185	.mode_valid = imx6dl_hdmi_mode_valid,
3d1b35a3 AY	186	};
3d1b35a3 AY	187
b21f4b65	188	static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
3d1b35a3 AY	189	{ .compatible = "fsl,imx6q-hdmi",
	190	.data = &imx6q_hdmi_drv_data
	191	}, {
	192	.compatible = "fsl,imx6dl-hdmi",
	193	.data = &imx6dl_hdmi_drv_data
	194	},
	195	{},
	196	};
b21f4b65	197	MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
3d1b35a3	198
b21f4b65 AY	199	static int dw_hdmi_imx_bind(struct device dev, struct device master,
b21f4b65 AY	200	void *data)
3d1b35a3 AY	201	{
3d1b35a3 AY	202	struct platform_device *pdev = to_platform_device(dev);
b21f4b65	203	const struct dw_hdmi_plat_data *plat_data;
3d1b35a3 AY	204	const struct of_device_id *match;
	205	struct drm_device *drm = data;
	206	struct drm_encoder *encoder;
b21f4b65	207	struct imx_hdmi *hdmi;
3d1b35a3 AY	208	int ret;
	209
	210	if (!pdev->dev.of_node)
	211	return -ENODEV;
	212
	213	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
	214	if (!hdmi)
	215	return -ENOMEM;
	216
b21f4b65	217	match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
3d1b35a3 AY	218	plat_data = match->data;
3d1b35a3 AY	219	hdmi->dev = &pdev->dev;
49f98bc4	220	encoder = &hdmi->encoder;
3d1b35a3	221
3d1b35a3 AY	222	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
	223	/*
	224	* If we failed to find the CRTC(s) which this encoder is
	225	* supposed to be connected to, it's because the CRTC has
	226	* not been registered yet. Defer probing, and hope that
	227	* the required CRTC is added later.
	228	*/
	229	if (encoder->possible_crtcs == 0)
	230	return -EPROBE_DEFER;
	231
b21f4b65	232	ret = dw_hdmi_imx_parse_dt(hdmi);
3d1b35a3 AY	233	if (ret < 0)
	234	return ret;
	235
b21f4b65 AY	236	drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
b21f4b65 AY	237	drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
13a3d91f	238	DRM_MODE_ENCODER_TMDS, NULL);
3d1b35a3	239
eea034af JS	240	platform_set_drvdata(pdev, hdmi);
	241
	242	hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
788c8ddb DA	243
	244	/*
	245	* If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
	246	* which would have called the encoder cleanup. Do it manually.
	247	*/
eea034af JS	248	if (IS_ERR(hdmi->hdmi)) {
eea034af JS	249	ret = PTR_ERR(hdmi->hdmi);
788c8ddb	250	drm_encoder_cleanup(encoder);
eea034af	251	}
788c8ddb DA	252
788c8ddb DA	253	return ret;
3d1b35a3 AY	254	}
3d1b35a3 AY	255
b21f4b65 AY	256	static void dw_hdmi_imx_unbind(struct device dev, struct device master,
b21f4b65 AY	257	void *data)
3d1b35a3	258	{
eea034af JS	259	struct imx_hdmi *hdmi = dev_get_drvdata(dev);
	260
	261	dw_hdmi_unbind(hdmi->hdmi);
3d1b35a3 AY	262	}
3d1b35a3 AY	263
b21f4b65 AY	264	static const struct component_ops dw_hdmi_imx_ops = {
	265	.bind = dw_hdmi_imx_bind,
	266	.unbind = dw_hdmi_imx_unbind,
3d1b35a3 AY	267	};
3d1b35a3 AY	268
b21f4b65	269	static int dw_hdmi_imx_probe(struct platform_device *pdev)
3d1b35a3	270	{
b21f4b65	271	return component_add(&pdev->dev, &dw_hdmi_imx_ops);
3d1b35a3 AY	272	}
3d1b35a3 AY	273
b21f4b65	274	static int dw_hdmi_imx_remove(struct platform_device *pdev)
3d1b35a3	275	{
b21f4b65	276	component_del(&pdev->dev, &dw_hdmi_imx_ops);
3d1b35a3 AY	277
	278	return 0;
	279	}
	280
b21f4b65 AY	281	static struct platform_driver dw_hdmi_imx_platform_driver = {
	282	.probe = dw_hdmi_imx_probe,
	283	.remove = dw_hdmi_imx_remove,
3d1b35a3	284	.driver = {
b21f4b65 AY	285	.name = "dwhdmi-imx",
b21f4b65 AY	286	.of_match_table = dw_hdmi_imx_dt_ids,
3d1b35a3 AY	287	},
	288	};
	289
b21f4b65	290	module_platform_driver(dw_hdmi_imx_platform_driver);
3d1b35a3 AY	291
	292	MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
	293	MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
	294	MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
	295	MODULE_LICENSE("GPL");
b21f4b65	296	MODULE_ALIAS("platform:dwhdmi-imx");