[thirdparty/kernel/stable.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 */
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_probe_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
				   struct drm_crtc_state *old_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_prg_enable(ipu);
	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	bool disable_partial = false;
	bool disable_full = false;
	struct drm_plane *plane;

	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
		if (plane == &ipu_crtc->plane[0]->base)
			disable_full = true;
		if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
			disable_partial = true;
	}

	if (disable_partial)
		ipu_plane_disable(ipu_crtc->plane[1], true);
	if (disable_full)
		ipu_plane_disable(ipu_crtc->plane[0], false);
}

static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	/*
	 * Planes must be disabled before DC clock is removed, as otherwise the
	 * attached IDMACs will be left in undefined state, possibly hanging
	 * the IPU or even system.
	 */
	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
	ipu_dc_disable(ipu);
	ipu_prg_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_blob_put(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	drm_crtc_handle_vblank(&ipu_crtc->base);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = drm_plane_mask(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);
}

static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.atomic_flush = ipu_crtc_atomic_flush,
	.atomic_disable = ipu_crtc_atomic_disable,
	.atomic_enable = ipu_crtc_atomic_enable,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	struct drm_crtc *crtc = &ipu_crtc->base;
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	crtc->port = pdata->of_node;
	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
				  &ipu_crtc_funcs, NULL);

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_put_resources;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
Commit	Line	Data
946485d0	1	// SPDX-License-Identifier: GPL-2.0+
f326f799 SH	2	/*
	3	* i.MX IPUv3 Graphics driver
	4	*
	5	* Copyright (C) 2011 Sascha Hauer, Pengutronix
f326f799	6	*/
fcd70cd3	7	#include <linux/clk.h>
17b5001b	8	#include <linux/component.h>
f326f799	9	#include <linux/device.h>
fcd70cd3 SV	10	#include <linux/errno.h>
	11	#include <linux/export.h>
	12	#include <linux/module.h>
f326f799 SH	13	#include <linux/platform_device.h>
f326f799 SH	14	#include <drm/drmP.h>
ae2531ab	15	#include <drm/drm_atomic.h>
255c35f8	16	#include <drm/drm_atomic_helper.h>
f326f799	17	#include <drm/drm_fb_cma_helper.h>
fcd70cd3 SV	18	#include <drm/drm_gem_cma_helper.h>
fcd70cd3 SV	19	#include <drm/drm_probe_helper.h>
f326f799	20
39b9004d	21	#include <video/imx-ipu-v3.h>
f326f799	22	#include "imx-drm.h"
b8d181e4	23	#include "ipuv3-plane.h"
f326f799 SH	24
	25	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	26
f326f799	27	struct ipu_crtc {
f326f799 SH	28	struct device *dev;
f326f799 SH	29	struct drm_crtc base;
b8d181e4 PZ	30
	31	/* plane[0] is the full plane, plane[1] is the partial plane */
	32	struct ipu_plane *plane[2];
	33
f326f799	34	struct ipu_dc *dc;
f326f799	35	struct ipu_di *di;
f326f799	36	int irq;
f326f799 SH	37	};
f326f799 SH	38
3df07390 PZ	39	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	40	{
	41	return container_of(crtc, struct ipu_crtc, base);
	42	}
f326f799	43
0b20a0f8 LP	44	static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
0b20a0f8 LP	45	struct drm_crtc_state *old_state)
f326f799	46	{
f6e396e5	47	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	48	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	49
e0fb7dd2	50	ipu_prg_enable(ipu);
1e6d486b	51	ipu_dc_enable(ipu);
c115edb8 PZ	52	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	53	ipu_di_enable(ipu_crtc->di);
f326f799 SH	54	}
f326f799 SH	55
eb8c8880 PZ	56	static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
	57	struct drm_crtc_state *old_crtc_state)
	58	{
	59	bool disable_partial = false;
	60	bool disable_full = false;
	61	struct drm_plane *plane;
	62
	63	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
	64	if (plane == &ipu_crtc->plane[0]->base)
	65	disable_full = true;
	66	if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
	67	disable_partial = true;
	68	}
	69
	70	if (disable_partial)
	71	ipu_plane_disable(ipu_crtc->plane[1], true);
	72	if (disable_full)
	73	ipu_plane_disable(ipu_crtc->plane[0], false);
	74	}
	75
8cc17b59 LY	76	static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
8cc17b59 LY	77	struct drm_crtc_state *old_crtc_state)
f326f799	78	{
f6e396e5	79	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	80	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	81
f326f799	82	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	83	ipu_di_disable(ipu_crtc->di);
5ced937b LS	84	/*
	85	* Planes must be disabled before DC clock is removed, as otherwise the
	86	* attached IDMACs will be left in undefined state, possibly hanging
	87	* the IPU or even system.
	88	*/
eb8c8880	89	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
1e6d486b	90	ipu_dc_disable(ipu);
e0fb7dd2	91	ipu_prg_disable(ipu);
33f14235	92
5f2f9115 LY	93	spin_lock_irq(&crtc->dev->event_lock);
	94	if (crtc->state->event) {
	95	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	96	crtc->state->event = NULL;
	97	}
	98	spin_unlock_irq(&crtc->dev->event_lock);
5f4df0c7	99
a4744786	100	drm_crtc_vblank_off(crtc);
f326f799 SH	101	}
f326f799 SH	102
49f98bc4 PZ	103	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	104	{
	105	struct imx_crtc_state *state;
	106
	107	if (crtc->state) {
	108	if (crtc->state->mode_blob)
a8f2023d	109	drm_property_blob_put(crtc->state->mode_blob);
49f98bc4 PZ	110
	111	state = to_imx_crtc_state(crtc->state);
	112	memset(state, 0, sizeof(*state));
	113	} else {
	114	state = kzalloc(sizeof(*state), GFP_KERNEL);
	115	if (!state)
	116	return;
	117	crtc->state = &state->base;
	118	}
	119
	120	state->base.crtc = crtc;
	121	}
	122
	123	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	124	{
	125	struct imx_crtc_state *state;
	126
	127	state = kzalloc(sizeof(*state), GFP_KERNEL);
	128	if (!state)
	129	return NULL;
	130
	131	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	132
	133	WARN_ON(state->base.crtc != crtc);
	134	state->base.crtc = crtc;
	135
	136	return &state->base;
	137	}
	138
	139	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	140	struct drm_crtc_state *state)
	141	{
	142	__drm_atomic_helper_crtc_destroy_state(state);
	143	kfree(to_imx_crtc_state(state));
	144	}
	145
44b460cf SG	146	static int ipu_enable_vblank(struct drm_crtc *crtc)
	147	{
	148	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	149
	150	enable_irq(ipu_crtc->irq);
	151
	152	return 0;
	153	}
	154
	155	static void ipu_disable_vblank(struct drm_crtc *crtc)
8e3b16e2	156	{
44b460cf SG	157	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	158
	159	disable_irq_nosync(ipu_crtc->irq);
8e3b16e2 LS	160	}
8e3b16e2 LS	161
f326f799	162	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	163	.set_config = drm_atomic_helper_set_config,
44b460cf	164	.destroy = drm_crtc_cleanup,
5f2f9115	165	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	166	.reset = imx_drm_crtc_reset,
	167	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	168	.atomic_destroy_state = imx_drm_crtc_destroy_state,
44b460cf SG	169	.enable_vblank = ipu_enable_vblank,
44b460cf SG	170	.disable_vblank = ipu_disable_vblank,
f326f799 SH	171	};
f326f799 SH	172
f326f799 SH	173	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	174	{
	175	struct ipu_crtc *ipu_crtc = dev_id;
	176
3ec2e506	177	drm_crtc_handle_vblank(&ipu_crtc->base);
f326f799	178
f326f799 SH	179	return IRQ_HANDLED;
	180	}
	181
	182	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	183	const struct drm_display_mode *mode,
	184	struct drm_display_mode *adjusted_mode)
	185	{
0c460a55 SL	186	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	187	struct videomode vm;
	188	int ret;
	189
	190	drm_display_mode_to_videomode(adjusted_mode, &vm);
	191
	192	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	193	if (ret)
	194	return false;
	195
33f14235 LY	196	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	197	return false;
	198
0c460a55 SL	199	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	200
f326f799 SH	201	return true;
	202	}
	203
33f14235 LY	204	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	205	struct drm_crtc_state *state)
	206	{
2d4569fd	207	u32 primary_plane_mask = drm_plane_mask(crtc->primary);
5f2f9115 LY	208
	209	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	210	return -EINVAL;
	211
33f14235 LY	212	return 0;
	213	}
	214
5f2f9115 LY	215	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	216	struct drm_crtc_state *old_crtc_state)
	217	{
a4744786	218	drm_crtc_vblank_on(crtc);
6a055b92	219	}
a4744786	220
6a055b92 LS	221	static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
	222	struct drm_crtc_state *old_crtc_state)
	223	{
5f2f9115 LY	224	spin_lock_irq(&crtc->dev->event_lock);
	225	if (crtc->state->event) {
	226	WARN_ON(drm_crtc_vblank_get(crtc));
	227	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	228	crtc->state->event = NULL;
	229	}
	230	spin_unlock_irq(&crtc->dev->event_lock);
	231	}
	232
33f14235 LY	233	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	234	{
	235	struct drm_device *dev = crtc->dev;
	236	struct drm_encoder *encoder;
	237	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	238	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	239	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	240	struct ipu_di_signal_cfg sig_cfg = {};
	241	unsigned long encoder_types = 0;
	242
	243	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	244	mode->hdisplay);
	245	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	246	mode->vdisplay);
	247
032003c5	248	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	249	if (encoder->crtc == crtc)
33f14235	250	encoder_types \|= BIT(encoder->encoder_type);
032003c5	251	}
33f14235 LY	252
	253	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	254	__func__, encoder_types);
	255
	256	/*
	257	* If we have DAC or LDB, then we need the IPU DI clock to be
	258	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	259	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	260	*/
	261	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	262	BIT(DRM_MODE_ENCODER_LVDS)))
	263	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	264	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	265	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	266	else
	267	sig_cfg.clkflags = 0;
	268
49f98bc4	269	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	270	/* Default to driving pixel data on negative clock edges */
49f98bc4	271	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	272	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	273	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	274	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	275	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	276	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	277
	278	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	279
	280	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	281	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	282	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	283	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	284	}
f326f799 SH	285
7ae847dd	286	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	287	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	288	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	289	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	290	.atomic_begin = ipu_crtc_atomic_begin,
6a055b92	291	.atomic_flush = ipu_crtc_atomic_flush,
8cc17b59	292	.atomic_disable = ipu_crtc_atomic_disable,
0b20a0f8	293	.atomic_enable = ipu_crtc_atomic_enable,
f326f799 SH	294	};
f326f799 SH	295
f326f799 SH	296	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
f326f799 SH	297	{
b8d181e4 PZ	298	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	299	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	300	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	301	ipu_di_put(ipu_crtc->di);
	302	}
	303
	304	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	305	struct ipu_client_platformdata *pdata)
	306	{
	307	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	308	int ret;
	309
f326f799 SH	310	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	311	if (IS_ERR(ipu_crtc->dc)) {
	312	ret = PTR_ERR(ipu_crtc->dc);
	313	goto err_out;
	314	}
	315
f326f799 SH	316	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	317	if (IS_ERR(ipu_crtc->di)) {
	318	ret = PTR_ERR(ipu_crtc->di);
	319	goto err_out;
	320	}
	321
f326f799 SH	322	return 0;
	323	err_out:
	324	ipu_put_resources(ipu_crtc);
	325
	326	return ret;
	327	}
	328
	329	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	330	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	331	{
47b1be5c	332	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
44b460cf	333	struct drm_crtc *crtc = &ipu_crtc->base;
b8d181e4	334	int dp = -EINVAL;
f326f799 SH	335	int ret;
	336
	337	ret = ipu_get_resources(ipu_crtc, pdata);
	338	if (ret) {
	339	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	340	ret);
	341	return ret;
	342	}
	343
43895599 PZ	344	if (pdata->dp >= 0)
	345	dp = IPU_DP_FLOW_SYNC_BG;
	346	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	347	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	348	if (IS_ERR(ipu_crtc->plane[0])) {
	349	ret = PTR_ERR(ipu_crtc->plane[0]);
	350	goto err_put_resources;
	351	}
43895599	352
44b460cf SG	353	crtc->port = pdata->of_node;
	354	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	355	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
	356	&ipu_crtc_funcs, NULL);
f326f799	357
b8d181e4 PZ	358	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	359	if (ret) {
	360	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	361	ret);
44b460cf	362	goto err_put_resources;
b8d181e4 PZ	363	}
	364
	365	/* If this crtc is using the DP, add an overlay plane */
	366	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	367	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	368	IPU_DP_FLOW_SYNC_FG,
	369	drm_crtc_mask(&ipu_crtc->base),
	370	DRM_PLANE_TYPE_OVERLAY);
33f14235	371	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	372	ipu_crtc->plane[1] = NULL;
33f14235 LY	373	} else {
	374	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	375	if (ret) {
	376	dev_err(ipu_crtc->dev, "getting plane 1 "
	377	"resources failed with %d.\n", ret);
	378	goto err_put_plane0_res;
	379	}
	380	}
b8d181e4 PZ	381	}
	382
	383	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	384	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	385	"imx_drm", ipu_crtc);
	386	if (ret < 0) {
	387	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	388	goto err_put_plane1_res;
47b1be5c	389	}
411b0336 LS	390	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	391	disable_irq(ipu_crtc->irq);
47b1be5c	392
f326f799 SH	393	return 0;
f326f799 SH	394
33f14235 LY	395	err_put_plane1_res:
	396	if (ipu_crtc->plane[1])
	397	ipu_plane_put_resources(ipu_crtc->plane[1]);
	398	err_put_plane0_res:
b8d181e4	399	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799 SH	400	err_put_resources:
	401	ipu_put_resources(ipu_crtc);
	402
	403	return ret;
	404	}
	405
17b5001b	406	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	407	{
17b5001b	408	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	409	struct drm_device *drm = data;
f326f799 SH	410	struct ipu_crtc *ipu_crtc;
	411	int ret;
	412
17b5001b	413	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	414	if (!ipu_crtc)
	415	return -ENOMEM;
	416
17b5001b	417	ipu_crtc->dev = dev;
f326f799	418
32266b45	419	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	420	if (ret)
9a8f3f44 LW	421	return ret;
f326f799	422
17b5001b	423	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	424
	425	return 0;
	426	}
	427
17b5001b RK	428	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	429	void *data)
f326f799	430	{
17b5001b	431	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799	432
f326f799	433	ipu_put_resources(ipu_crtc);
33f14235 LY	434	if (ipu_crtc->plane[1])
	435	ipu_plane_put_resources(ipu_crtc->plane[1]);
	436	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	437	}
	438
	439	static const struct component_ops ipu_crtc_ops = {
	440	.bind = ipu_drm_bind,
	441	.unbind = ipu_drm_unbind,
	442	};
f326f799	443
17b5001b RK	444	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	445	{
655b43cc	446	struct device *dev = &pdev->dev;
17b5001b RK	447	int ret;
17b5001b RK	448
655b43cc	449	if (!dev->platform_data)
17b5001b RK	450	return -EINVAL;
17b5001b RK	451
655b43cc	452	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	453	if (ret)
	454	return ret;
	455
655b43cc	456	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	457	}
	458
	459	static int ipu_drm_remove(struct platform_device *pdev)
	460	{
	461	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	462	return 0;
	463	}
	464
3d1df96a	465	struct platform_driver ipu_drm_driver = {
f326f799 SH	466	.driver = {
	467	.name = "imx-ipuv3-crtc",
	468	},
	469	.probe = ipu_drm_probe,
99c28f10	470	.remove = ipu_drm_remove,
f326f799	471	};