[thirdparty/linux.git] / drivers / gpu / drm / meson / meson_drv.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2016 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 * Copyright (C) 2014 Endless Mobile
 *
 * Written by:
 *     Jasper St. Pierre <jstpierre@mecheye.net>
 */

#include <linux/component.h>
#include <linux/module.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/soc/amlogic/meson-canvas.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_irq.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>

#include "meson_crtc.h"
#include "meson_drv.h"
#include "meson_overlay.h"
#include "meson_plane.h"
#include "meson_osd_afbcd.h"
#include "meson_registers.h"
#include "meson_venc_cvbs.h"
#include "meson_viu.h"
#include "meson_vpp.h"
#include "meson_rdma.h"

#define DRIVER_NAME "meson"
#define DRIVER_DESC "Amlogic Meson DRM driver"

/**
 * DOC: Video Processing Unit
 *
 * VPU Handles the Global Video Processing, it includes management of the
 * clocks gates, blocks reset lines and power domains.
 *
 * What is missing :
 *
 * - Full reset of entire video processing HW blocks
 * - Scaling and setup of the VPU clock
 * - Bus clock gates
 * - Powering up video processing HW blocks
 * - Powering Up HDMI controller and PHY
 */

static const struct drm_mode_config_funcs meson_mode_config_funcs = {
	.atomic_check        = drm_atomic_helper_check,
	.atomic_commit       = drm_atomic_helper_commit,
	.fb_create           = drm_gem_fb_create,
};

static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};

static irqreturn_t meson_irq(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct meson_drm *priv = dev->dev_private;

	(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));

	meson_crtc_irq(priv);

	return IRQ_HANDLED;
}

static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
			     struct drm_mode_create_dumb *args)
{
	/*
	 * We need 64bytes aligned stride, and PAGE aligned size
	 */
	args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
	args->size = PAGE_ALIGN(args->pitch * args->height);

	return drm_gem_cma_dumb_create_internal(file, dev, args);
}

DEFINE_DRM_GEM_CMA_FOPS(fops);

static struct drm_driver meson_driver = {
	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,

	/* IRQ */
	.irq_handler		= meson_irq,

	/* PRIME Ops */
	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
	.gem_prime_mmap		= drm_gem_cma_prime_mmap,

	/* GEM Ops */
	.dumb_create		= meson_dumb_create,
	.gem_free_object_unlocked = drm_gem_cma_free_object,
	.gem_vm_ops		= &drm_gem_cma_vm_ops,

	/* Misc */
	.fops			= &fops,
	.name			= DRIVER_NAME,
	.desc			= DRIVER_DESC,
	.date			= "20161109",
	.major			= 1,
	.minor			= 0,
};

static bool meson_vpu_has_available_connectors(struct device *dev)
{
	struct device_node *ep, *remote;

	/* Parses each endpoint and check if remote exists */
	for_each_endpoint_of_node(dev->of_node, ep) {
		/* If the endpoint node exists, consider it enabled */
		remote = of_graph_get_remote_port(ep);
		if (remote)
			return true;
	}

	return false;
}

static struct regmap_config meson_regmap_config = {
	.reg_bits       = 32,
	.val_bits       = 32,
	.reg_stride     = 4,
	.max_register   = 0x1000,
};

static void meson_vpu_init(struct meson_drm *priv)
{
	u32 value;

	/*
	 * Slave dc0 and dc5 connected to master port 1.
	 * By default other slaves are connected to master port 0.
	 */
	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
		VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));

	/* Slave dc0 connected to master port 1 */
	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));

	/* Slave dc4 and dc7 connected to master port 1 */
	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
		VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));

	/* Slave dc1 connected to master port 1 */
	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
}

static void meson_remove_framebuffers(void)
{
	struct apertures_struct *ap;

	ap = alloc_apertures(1);
	if (!ap)
		return;

	/* The framebuffer can be located anywhere in RAM */
	ap->ranges[0].base = 0;
	ap->ranges[0].size = ~0;

	drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb",
						      false);
	kfree(ap);
}

static int meson_drv_bind_master(struct device *dev, bool has_components)
{
	struct platform_device *pdev = to_platform_device(dev);
	const struct meson_drm_match_data *match;
	struct meson_drm *priv;
	struct drm_device *drm;
	struct resource *res;
	void __iomem *regs;
	int ret;

	/* Checks if an output connector is available */
	if (!meson_vpu_has_available_connectors(dev)) {
		dev_err(dev, "No output connector available\n");
		return -ENODEV;
	}

	match = of_device_get_match_data(dev);
	if (!match)
		return -ENODEV;

	drm = drm_dev_alloc(&meson_driver, dev);
	if (IS_ERR(drm))
		return PTR_ERR(drm);

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto free_drm;
	}
	drm->dev_private = priv;
	priv->drm = drm;
	priv->dev = dev;
	priv->compat = match->compat;
	priv->afbcd.ops = match->afbcd_ops;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
	regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(regs)) {
		ret = PTR_ERR(regs);
		goto free_drm;
	}

	priv->io_base = regs;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
	if (!res) {
		ret = -EINVAL;
		goto free_drm;
	}
	/* Simply ioremap since it may be a shared register zone */
	regs = devm_ioremap(dev, res->start, resource_size(res));
	if (!regs) {
		ret = -EADDRNOTAVAIL;
		goto free_drm;
	}

	priv->hhi = devm_regmap_init_mmio(dev, regs,
					  &meson_regmap_config);
	if (IS_ERR(priv->hhi)) {
		dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
		ret = PTR_ERR(priv->hhi);
		goto free_drm;
	}

	priv->canvas = meson_canvas_get(dev);
	if (IS_ERR(priv->canvas)) {
		ret = PTR_ERR(priv->canvas);
		goto free_drm;
	}

	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
	if (ret)
		goto free_drm;
	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
	if (ret) {
		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
		goto free_drm;
	}
	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
	if (ret) {
		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
		goto free_drm;
	}
	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
	if (ret) {
		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
		goto free_drm;
	}

	priv->vsync_irq = platform_get_irq(pdev, 0);

	ret = drm_vblank_init(drm, 1);
	if (ret)
		goto free_drm;

	/* Remove early framebuffers (ie. simplefb) */
	meson_remove_framebuffers();

	drm_mode_config_init(drm);
	drm->mode_config.max_width = 3840;
	drm->mode_config.max_height = 2160;
	drm->mode_config.funcs = &meson_mode_config_funcs;
	drm->mode_config.helper_private	= &meson_mode_config_helpers;

	/* Hardware Initialization */

	meson_vpu_init(priv);
	meson_venc_init(priv);
	meson_vpp_init(priv);
	meson_viu_init(priv);
	if (priv->afbcd.ops) {
		ret = priv->afbcd.ops->init(priv);
		if (ret)
			return ret;
	}

	/* Encoder Initialization */

	ret = meson_venc_cvbs_create(priv);
	if (ret)
		goto free_drm;

	if (has_components) {
		ret = component_bind_all(drm->dev, drm);
		if (ret) {
			dev_err(drm->dev, "Couldn't bind all components\n");
			goto free_drm;
		}
	}

	ret = meson_plane_create(priv);
	if (ret)
		goto free_drm;

	ret = meson_overlay_create(priv);
	if (ret)
		goto free_drm;

	ret = meson_crtc_create(priv);
	if (ret)
		goto free_drm;

	ret = drm_irq_install(drm, priv->vsync_irq);
	if (ret)
		goto free_drm;

	drm_mode_config_reset(drm);

	drm_kms_helper_poll_init(drm);

	platform_set_drvdata(pdev, priv);

	ret = drm_dev_register(drm, 0);
	if (ret)
		goto uninstall_irq;

	drm_fbdev_generic_setup(drm, 32);

	return 0;

uninstall_irq:
	drm_irq_uninstall(drm);
free_drm:
	drm_dev_put(drm);

	return ret;
}

static int meson_drv_bind(struct device *dev)
{
	return meson_drv_bind_master(dev, true);
}

static void meson_drv_unbind(struct device *dev)
{
	struct meson_drm *priv = dev_get_drvdata(dev);
	struct drm_device *drm = priv->drm;

	if (priv->canvas) {
		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
	}

	if (priv->afbcd.ops) {
		priv->afbcd.ops->reset(priv);
		meson_rdma_free(priv);
	}

	drm_dev_unregister(drm);
	drm_irq_uninstall(drm);
	drm_kms_helper_poll_fini(drm);
	drm_mode_config_cleanup(drm);
	drm_dev_put(drm);
}

static const struct component_master_ops meson_drv_master_ops = {
	.bind	= meson_drv_bind,
	.unbind	= meson_drv_unbind,
};

static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
{
	struct meson_drm *priv = dev_get_drvdata(dev);

	if (!priv)
		return 0;

	return drm_mode_config_helper_suspend(priv->drm);
}

static int __maybe_unused meson_drv_pm_resume(struct device *dev)
{
	struct meson_drm *priv = dev_get_drvdata(dev);

	if (!priv)
		return 0;

	meson_vpu_init(priv);
	meson_venc_init(priv);
	meson_vpp_init(priv);
	meson_viu_init(priv);
	if (priv->afbcd.ops)
		priv->afbcd.ops->init(priv);

	return drm_mode_config_helper_resume(priv->drm);
}

static int compare_of(struct device *dev, void *data)
{
	DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
			 dev->of_node, data);

	return dev->of_node == data;
}

/* Possible connectors nodes to ignore */
static const struct of_device_id connectors_match[] = {
	{ .compatible = "composite-video-connector" },
	{ .compatible = "svideo-connector" },
	{ .compatible = "hdmi-connector" },
	{ .compatible = "dvi-connector" },
	{}
};

static int meson_probe_remote(struct platform_device *pdev,
			      struct component_match **match,
			      struct device_node *parent,
			      struct device_node *remote)
{
	struct device_node *ep, *remote_node;
	int count = 1;

	/* If node is a connector, return and do not add to match table */
	if (of_match_node(connectors_match, remote))
		return 1;

	component_match_add(&pdev->dev, match, compare_of, remote);

	for_each_endpoint_of_node(remote, ep) {
		remote_node = of_graph_get_remote_port_parent(ep);
		if (!remote_node ||
		    remote_node == parent || /* Ignore parent endpoint */
		    !of_device_is_available(remote_node)) {
			of_node_put(remote_node);
			continue;
		}

		count += meson_probe_remote(pdev, match, remote, remote_node);

		of_node_put(remote_node);
	}

	return count;
}

static int meson_drv_probe(struct platform_device *pdev)
{
	struct component_match *match = NULL;
	struct device_node *np = pdev->dev.of_node;
	struct device_node *ep, *remote;
	int count = 0;

	for_each_endpoint_of_node(np, ep) {
		remote = of_graph_get_remote_port_parent(ep);
		if (!remote || !of_device_is_available(remote)) {
			of_node_put(remote);
			continue;
		}

		count += meson_probe_remote(pdev, &match, np, remote);
		of_node_put(remote);
	}

	if (count && !match)
		return meson_drv_bind_master(&pdev->dev, false);

	/* If some endpoints were found, initialize the nodes */
	if (count) {
		dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);

		return component_master_add_with_match(&pdev->dev,
						       &meson_drv_master_ops,
						       match);
	}

	/* If no output endpoints were available, simply bail out */
	return 0;
};

static struct meson_drm_match_data meson_drm_gxbb_data = {
	.compat = VPU_COMPATIBLE_GXBB,
};

static struct meson_drm_match_data meson_drm_gxl_data = {
	.compat = VPU_COMPATIBLE_GXL,
};

static struct meson_drm_match_data meson_drm_gxm_data = {
	.compat = VPU_COMPATIBLE_GXM,
	.afbcd_ops = &meson_afbcd_gxm_ops,
};

static struct meson_drm_match_data meson_drm_g12a_data = {
	.compat = VPU_COMPATIBLE_G12A,
	.afbcd_ops = &meson_afbcd_g12a_ops,
};

static const struct of_device_id dt_match[] = {
	{ .compatible = "amlogic,meson-gxbb-vpu",
	  .data       = (void *)&meson_drm_gxbb_data },
	{ .compatible = "amlogic,meson-gxl-vpu",
	  .data       = (void *)&meson_drm_gxl_data },
	{ .compatible = "amlogic,meson-gxm-vpu",
	  .data       = (void *)&meson_drm_gxm_data },
	{ .compatible = "amlogic,meson-g12a-vpu",
	  .data       = (void *)&meson_drm_g12a_data },
	{}
};
MODULE_DEVICE_TABLE(of, dt_match);

static const struct dev_pm_ops meson_drv_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
};

static struct platform_driver meson_drm_platform_driver = {
	.probe      = meson_drv_probe,
	.driver     = {
		.name	= "meson-drm",
		.of_match_table = dt_match,
		.pm = &meson_drv_pm_ops,
	},
};

module_platform_driver(meson_drm_platform_driver);

MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
bbbe775e NA	2	/*
	3	* Copyright (C) 2016 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	* Copyright (C) 2014 Endless Mobile
	6	*
bbbe775e NA	7	* Written by:
	8	* Jasper St. Pierre <jstpierre@mecheye.net>
	9	*/
	10
a41e82e6	11	#include <linux/component.h>
66620f48	12	#include <linux/module.h>
bbbe775e	13	#include <linux/of_graph.h>
66620f48 SR	14	#include <linux/platform_device.h>
66620f48 SR	15	#include <linux/soc/amlogic/meson-canvas.h>
bbbe775e	16
bbbe775e	17	#include <drm/drm_atomic_helper.h>
66620f48	18	#include <drm/drm_drv.h>
fcd70cd3	19	#include <drm/drm_fb_helper.h>
bbbe775e	20	#include <drm/drm_gem_cma_helper.h>
24ef8157	21	#include <drm/drm_gem_framebuffer_helper.h>
66620f48 SR	22	#include <drm/drm_irq.h>
66620f48 SR	23	#include <drm/drm_modeset_helper_vtables.h>
fcd70cd3	24	#include <drm/drm_probe_helper.h>
66620f48	25	#include <drm/drm_vblank.h>
bbbe775e	26
66620f48	27	#include "meson_crtc.h"
bbbe775e	28	#include "meson_drv.h"
f9a23481	29	#include "meson_overlay.h"
66620f48	30	#include "meson_plane.h"
d1b5e41e	31	#include "meson_osd_afbcd.h"
66620f48	32	#include "meson_registers.h"
bbbe775e	33	#include "meson_venc_cvbs.h"
bbbe775e	34	#include "meson_viu.h"
66620f48	35	#include "meson_vpp.h"
d1b5e41e	36	#include "meson_rdma.h"
bbbe775e NA	37
	38	#define DRIVER_NAME "meson"
	39	#define DRIVER_DESC "Amlogic Meson DRM driver"
	40
2021d5b7 NA	41	/**
2021d5b7 NA	42	* DOC: Video Processing Unit
bbbe775e NA	43	*
	44	* VPU Handles the Global Video Processing, it includes management of the
	45	* clocks gates, blocks reset lines and power domains.
	46	*
	47	* What is missing :
2021d5b7	48	*
bbbe775e NA	49	* - Full reset of entire video processing HW blocks
	50	* - Scaling and setup of the VPU clock
	51	* - Bus clock gates
	52	* - Powering up video processing HW blocks
	53	* - Powering Up HDMI controller and PHY
	54	*/
	55
bbbe775e	56	static const struct drm_mode_config_funcs meson_mode_config_funcs = {
bbbe775e NA	57	.atomic_check = drm_atomic_helper_check,
bbbe775e NA	58	.atomic_commit = drm_atomic_helper_commit,
24ef8157	59	.fb_create = drm_gem_fb_create,
bbbe775e NA	60	};
bbbe775e NA	61
ce0210c1 NA	62	static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
	63	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
	64	};
	65
bbbe775e NA	66	static irqreturn_t meson_irq(int irq, void *arg)
	67	{
	68	struct drm_device *dev = arg;
	69	struct meson_drm *priv = dev->dev_private;
	70
	71	(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
	72
	73	meson_crtc_irq(priv);
	74
	75	return IRQ_HANDLED;
	76	}
	77
852ce728 NA	78	static int meson_dumb_create(struct drm_file file, struct drm_device dev,
	79	struct drm_mode_create_dumb *args)
	80	{
	81	/*
	82	* We need 64bytes aligned stride, and PAGE aligned size
	83	*/
	84	args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
	85	args->size = PAGE_ALIGN(args->pitch * args->height);
	86
	87	return drm_gem_cma_dumb_create_internal(file, dev, args);
	88	}
	89
d55f7e5d	90	DEFINE_DRM_GEM_CMA_FOPS(fops);
bbbe775e NA	91
bbbe775e NA	92	static struct drm_driver meson_driver = {
0424fdaf	93	.driver_features = DRIVER_GEM \| DRIVER_MODESET \| DRIVER_ATOMIC,
bbbe775e	94
bbbe775e NA	95	/* IRQ */
	96	.irq_handler = meson_irq,
	97
	98	/* PRIME Ops */
	99	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	100	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
bbbe775e NA	101	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
	102	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	103	.gem_prime_vmap = drm_gem_cma_prime_vmap,
	104	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
	105	.gem_prime_mmap = drm_gem_cma_prime_mmap,
	106
	107	/* GEM Ops */
852ce728	108	.dumb_create = meson_dumb_create,
bbbe775e NA	109	.gem_free_object_unlocked = drm_gem_cma_free_object,
	110	.gem_vm_ops = &drm_gem_cma_vm_ops,
	111
	112	/* Misc */
	113	.fops = &fops,
	114	.name = DRIVER_NAME,
	115	.desc = DRIVER_DESC,
	116	.date = "20161109",
	117	.major = 1,
	118	.minor = 0,
	119	};
	120
	121	static bool meson_vpu_has_available_connectors(struct device *dev)
	122	{
	123	struct device_node ep, remote;
	124
	125	/* Parses each endpoint and check if remote exists */
	126	for_each_endpoint_of_node(dev->of_node, ep) {
	127	/* If the endpoint node exists, consider it enabled */
	128	remote = of_graph_get_remote_port(ep);
	129	if (remote)
	130	return true;
	131	}
	132
	133	return false;
	134	}
	135
	136	static struct regmap_config meson_regmap_config = {
	137	.reg_bits = 32,
	138	.val_bits = 32,
	139	.reg_stride = 4,
	140	.max_register = 0x1000,
	141	};
	142
09762525 NA	143	static void meson_vpu_init(struct meson_drm *priv)
09762525 NA	144	{
bfb86819 JM	145	u32 value;
	146
	147	/*
	148	* Slave dc0 and dc5 connected to master port 1.
	149	* By default other slaves are connected to master port 0.
	150	*/
	151	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) \|
	152	VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
	153	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
	154
	155	/* Slave dc0 connected to master port 1 */
	156	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
	157	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
	158
	159	/* Slave dc4 and dc7 connected to master port 1 */
	160	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) \|
	161	VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
	162	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
	163
	164	/* Slave dc1 connected to master port 1 */
	165	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
	166	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
09762525 NA	167	}
09762525 NA	168
e3de0aa6 MJ	169	static void meson_remove_framebuffers(void)
	170	{
	171	struct apertures_struct *ap;
	172
	173	ap = alloc_apertures(1);
	174	if (!ap)
	175	return;
	176
	177	/* The framebuffer can be located anywhere in RAM */
	178	ap->ranges[0].base = 0;
	179	ap->ranges[0].size = ~0;
	180
	181	drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb",
	182	false);
	183	kfree(ap);
	184	}
	185
8604889f	186	static int meson_drv_bind_master(struct device *dev, bool has_components)
bbbe775e	187	{
a41e82e6	188	struct platform_device *pdev = to_platform_device(dev);
d1b5e41e	189	const struct meson_drm_match_data *match;
bbbe775e NA	190	struct meson_drm *priv;
	191	struct drm_device *drm;
	192	struct resource *res;
	193	void __iomem *regs;
	194	int ret;
	195
	196	/* Checks if an output connector is available */
	197	if (!meson_vpu_has_available_connectors(dev)) {
	198	dev_err(dev, "No output connector available\n");
	199	return -ENODEV;
	200	}
	201
d1b5e41e NA	202	match = of_device_get_match_data(dev);
	203	if (!match)
	204	return -ENODEV;
	205
bbbe775e NA	206	drm = drm_dev_alloc(&meson_driver, dev);
	207	if (IS_ERR(drm))
	208	return PTR_ERR(drm);
	209
	210	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	211	if (!priv) {
	212	ret = -ENOMEM;
	213	goto free_drm;
	214	}
	215	drm->dev_private = priv;
	216	priv->drm = drm;
	217	priv->dev = dev;
d1b5e41e NA	218	priv->compat = match->compat;
d1b5e41e NA	219	priv->afbcd.ops = match->afbcd_ops;
528a25d0	220
bbbe775e NA	221	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
bbbe775e NA	222	regs = devm_ioremap_resource(dev, res);
2c18107b CJ	223	if (IS_ERR(regs)) {
	224	ret = PTR_ERR(regs);
	225	goto free_drm;
	226	}
bbbe775e NA	227
	228	priv->io_base = regs;
	229
	230	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
01a9e949 CJ	231	if (!res) {
	232	ret = -EINVAL;
	233	goto free_drm;
	234	}
bbbe775e NA	235	/* Simply ioremap since it may be a shared register zone */
bbbe775e NA	236	regs = devm_ioremap(dev, res->start, resource_size(res));
2c18107b CJ	237	if (!regs) {
	238	ret = -EADDRNOTAVAIL;
	239	goto free_drm;
	240	}
bbbe775e NA	241
	242	priv->hhi = devm_regmap_init_mmio(dev, regs,
	243	&meson_regmap_config);
	244	if (IS_ERR(priv->hhi)) {
	245	dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
2c18107b CJ	246	ret = PTR_ERR(priv->hhi);
2c18107b CJ	247	goto free_drm;
bbbe775e NA	248	}
bbbe775e NA	249
66cae477	250	priv->canvas = meson_canvas_get(dev);
2bf6b5b0 MJ	251	if (IS_ERR(priv->canvas)) {
	252	ret = PTR_ERR(priv->canvas);
	253	goto free_drm;
	254	}
	255
	256	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
	257	if (ret)
	258	goto free_drm;
	259	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
	260	if (ret) {
	261	meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
	262	goto free_drm;
	263	}
	264	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
	265	if (ret) {
	266	meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
	267	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
	268	goto free_drm;
	269	}
	270	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
	271	if (ret) {
	272	meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
	273	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
	274	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
	275	goto free_drm;
bbbe775e NA	276	}
	277
	278	priv->vsync_irq = platform_get_irq(pdev, 0);
	279
e770f6bf CJ	280	ret = drm_vblank_init(drm, 1);
	281	if (ret)
	282	goto free_drm;
	283
e3de0aa6 MJ	284	/* Remove early framebuffers (ie. simplefb) */
	285	meson_remove_framebuffers();
	286
bbbe775e	287	drm_mode_config_init(drm);
a41e82e6 NA	288	drm->mode_config.max_width = 3840;
	289	drm->mode_config.max_height = 2160;
	290	drm->mode_config.funcs = &meson_mode_config_funcs;
ce0210c1	291	drm->mode_config.helper_private = &meson_mode_config_helpers;
a41e82e6 NA	292
	293	/* Hardware Initialization */
	294
09762525	295	meson_vpu_init(priv);
a41e82e6 NA	296	meson_venc_init(priv);
	297	meson_vpp_init(priv);
	298	meson_viu_init(priv);
d1b5e41e NA	299	if (priv->afbcd.ops) {
	300	ret = priv->afbcd.ops->init(priv);
	301	if (ret)
	302	return ret;
	303	}
bbbe775e NA	304
	305	/* Encoder Initialization */
	306
	307	ret = meson_venc_cvbs_create(priv);
	308	if (ret)
	309	goto free_drm;
	310
8604889f NA	311	if (has_components) {
	312	ret = component_bind_all(drm->dev, drm);
	313	if (ret) {
	314	dev_err(drm->dev, "Couldn't bind all components\n");
	315	goto free_drm;
	316	}
a41e82e6	317	}
bbbe775e NA	318
	319	ret = meson_plane_create(priv);
	320	if (ret)
	321	goto free_drm;
	322
f9a23481 NA	323	ret = meson_overlay_create(priv);
	324	if (ret)
	325	goto free_drm;
	326
bbbe775e NA	327	ret = meson_crtc_create(priv);
	328	if (ret)
	329	goto free_drm;
	330
	331	ret = drm_irq_install(drm, priv->vsync_irq);
	332	if (ret)
	333	goto free_drm;
	334
	335	drm_mode_config_reset(drm);
bbbe775e	336
bbbe775e NA	337	drm_kms_helper_poll_init(drm);
	338
	339	platform_set_drvdata(pdev, priv);
	340
	341	ret = drm_dev_register(drm, 0);
	342	if (ret)
2d8f9289	343	goto uninstall_irq;
bbbe775e	344
efbb9df9 NT	345	drm_fbdev_generic_setup(drm, 32);
efbb9df9 NT	346
bbbe775e NA	347	return 0;
bbbe775e NA	348
2d8f9289 JPB	349	uninstall_irq:
2d8f9289 JPB	350	drm_irq_uninstall(drm);
bbbe775e	351	free_drm:
dcacf651	352	drm_dev_put(drm);
bbbe775e NA	353
	354	return ret;
	355	}
	356
8604889f NA	357	static int meson_drv_bind(struct device *dev)
	358	{
	359	return meson_drv_bind_master(dev, true);
	360	}
	361
a41e82e6	362	static void meson_drv_unbind(struct device *dev)
bbbe775e	363	{
776e7867 JPB	364	struct meson_drm *priv = dev_get_drvdata(dev);
776e7867 JPB	365	struct drm_device *drm = priv->drm;
66cae477	366
f9a23481	367	if (priv->canvas) {
66cae477	368	meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
f9a23481 NA	369	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
	370	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
	371	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
	372	}
bbbe775e	373
d1b5e41e NA	374	if (priv->afbcd.ops) {
	375	priv->afbcd.ops->reset(priv);
	376	meson_rdma_free(priv);
	377	}
	378
bbbe775e	379	drm_dev_unregister(drm);
2d8f9289	380	drm_irq_uninstall(drm);
bbbe775e	381	drm_kms_helper_poll_fini(drm);
bbbe775e	382	drm_mode_config_cleanup(drm);
dcacf651	383	drm_dev_put(drm);
bbbe775e NA	384	}
bbbe775e NA	385
a41e82e6 NA	386	static const struct component_master_ops meson_drv_master_ops = {
	387	.bind = meson_drv_bind,
	388	.unbind = meson_drv_unbind,
	389	};
	390
cf3d4e53 NA	391	static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
	392	{
	393	struct meson_drm *priv = dev_get_drvdata(dev);
	394
	395	if (!priv)
	396	return 0;
	397
	398	return drm_mode_config_helper_suspend(priv->drm);
	399	}
	400
	401	static int __maybe_unused meson_drv_pm_resume(struct device *dev)
	402	{
	403	struct meson_drm *priv = dev_get_drvdata(dev);
	404
	405	if (!priv)
	406	return 0;
	407
	408	meson_vpu_init(priv);
	409	meson_venc_init(priv);
	410	meson_vpp_init(priv);
	411	meson_viu_init(priv);
d1b5e41e NA	412	if (priv->afbcd.ops)
d1b5e41e NA	413	priv->afbcd.ops->init(priv);
cf3d4e53	414
c54a8f1f	415	return drm_mode_config_helper_resume(priv->drm);
cf3d4e53 NA	416	}
cf3d4e53 NA	417
a41e82e6 NA	418	static int compare_of(struct device dev, void data)
a41e82e6 NA	419	{
4bf99144 RH	420	DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
4bf99144 RH	421	dev->of_node, data);
a41e82e6 NA	422
	423	return dev->of_node == data;
	424	}
	425
	426	/* Possible connectors nodes to ignore */
	427	static const struct of_device_id connectors_match[] = {
	428	{ .compatible = "composite-video-connector" },
	429	{ .compatible = "svideo-connector" },
	430	{ .compatible = "hdmi-connector" },
	431	{ .compatible = "dvi-connector" },
	432	{}
	433	};
	434
	435	static int meson_probe_remote(struct platform_device *pdev,
	436	struct component_match **match,
	437	struct device_node *parent,
	438	struct device_node *remote)
	439	{
	440	struct device_node ep, remote_node;
	441	int count = 1;
	442
	443	/* If node is a connector, return and do not add to match table */
	444	if (of_match_node(connectors_match, remote))
	445	return 1;
	446
	447	component_match_add(&pdev->dev, match, compare_of, remote);
	448
	449	for_each_endpoint_of_node(remote, ep) {
	450	remote_node = of_graph_get_remote_port_parent(ep);
	451	if (!remote_node \|\|
	452	remote_node == parent \|\| /* Ignore parent endpoint */
f672b93e JL	453	!of_device_is_available(remote_node)) {
f672b93e JL	454	of_node_put(remote_node);
a41e82e6	455	continue;
f672b93e	456	}
a41e82e6 NA	457
	458	count += meson_probe_remote(pdev, match, remote, remote_node);
	459
	460	of_node_put(remote_node);
	461	}
	462
	463	return count;
	464	}
	465
	466	static int meson_drv_probe(struct platform_device *pdev)
	467	{
	468	struct component_match *match = NULL;
	469	struct device_node *np = pdev->dev.of_node;
	470	struct device_node ep, remote;
	471	int count = 0;
	472
	473	for_each_endpoint_of_node(np, ep) {
	474	remote = of_graph_get_remote_port_parent(ep);
f672b93e JL	475	if (!remote \|\| !of_device_is_available(remote)) {
f672b93e JL	476	of_node_put(remote);
a41e82e6	477	continue;
f672b93e	478	}
a41e82e6 NA	479
a41e82e6 NA	480	count += meson_probe_remote(pdev, &match, np, remote);
f672b93e	481	of_node_put(remote);
a41e82e6 NA	482	}
a41e82e6 NA	483
8604889f NA	484	if (count && !match)
	485	return meson_drv_bind_master(&pdev->dev, false);
	486
a41e82e6 NA	487	/* If some endpoints were found, initialize the nodes */
	488	if (count) {
	489	dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
	490
	491	return component_master_add_with_match(&pdev->dev,
	492	&meson_drv_master_ops,
	493	match);
	494	}
	495
	496	/* If no output endpoints were available, simply bail out */
	497	return 0;
	498	};
	499
d1b5e41e NA	500	static struct meson_drm_match_data meson_drm_gxbb_data = {
	501	.compat = VPU_COMPATIBLE_GXBB,
	502	};
	503
	504	static struct meson_drm_match_data meson_drm_gxl_data = {
	505	.compat = VPU_COMPATIBLE_GXL,
	506	};
	507
	508	static struct meson_drm_match_data meson_drm_gxm_data = {
	509	.compat = VPU_COMPATIBLE_GXM,
	510	.afbcd_ops = &meson_afbcd_gxm_ops,
	511	};
	512
	513	static struct meson_drm_match_data meson_drm_g12a_data = {
	514	.compat = VPU_COMPATIBLE_G12A,
	515	.afbcd_ops = &meson_afbcd_g12a_ops,
	516	};
	517
bbbe775e	518	static const struct of_device_id dt_match[] = {
528a25d0	519	{ .compatible = "amlogic,meson-gxbb-vpu",
d1b5e41e	520	.data = (void *)&meson_drm_gxbb_data },
528a25d0	521	{ .compatible = "amlogic,meson-gxl-vpu",
d1b5e41e	522	.data = (void *)&meson_drm_gxl_data },
528a25d0	523	{ .compatible = "amlogic,meson-gxm-vpu",
d1b5e41e	524	.data = (void *)&meson_drm_gxm_data },
528a25d0	525	{ .compatible = "amlogic,meson-g12a-vpu",
d1b5e41e	526	.data = (void *)&meson_drm_g12a_data },
bbbe775e NA	527	{}
	528	};
	529	MODULE_DEVICE_TABLE(of, dt_match);
	530
cf3d4e53 NA	531	static const struct dev_pm_ops meson_drv_pm_ops = {
	532	SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
	533	};
	534
bbbe775e NA	535	static struct platform_driver meson_drm_platform_driver = {
bbbe775e NA	536	.probe = meson_drv_probe,
bbbe775e	537	.driver = {
8aaacbc0	538	.name = "meson-drm",
bbbe775e	539	.of_match_table = dt_match,
cf3d4e53	540	.pm = &meson_drv_pm_ops,
bbbe775e NA	541	},
	542	};
	543
	544	module_platform_driver(meson_drm_platform_driver);
	545
	546	MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
	547	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
	548	MODULE_DESCRIPTION(DRIVER_DESC);
	549	MODULE_LICENSE("GPL");