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Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm...
[thirdparty/kernel/stable.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
CommitLineData
414c4531
DA		 1/*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14#include <linux/delay.h>
15
760285e7
DH		 16#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
3cb9ae4f 18#include <drm/drm_plane_helper.h>
fcd70cd3 19#include <drm/drm_probe_helper.h>
414c4531
DA		 20
21#include "mgag200_drv.h"
22
23#define MGAG200_LUT_SIZE 256
24
25/*
26 * This file contains setup code for the CRTC.
27 */
28
29static void mga_crtc_load_lut(struct drm_crtc *crtc)
30{
414c4531
DA		 31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
f4510a27 33 struct drm_framebuffer *fb = crtc->primary->fb;
9ed85e14 34 u16 *r_ptr, *g_ptr, *b_ptr;
414c4531
DA		 35 int i;
36
37 if (!crtc->enabled)
38 return;
39
9ed85e14
PR		 40 r_ptr = crtc->gamma_store;
41 g_ptr = r_ptr + crtc->gamma_size;
42 b_ptr = g_ptr + crtc->gamma_size;
43
414c4531
DA		 44 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
45
272725c7 46 if (fb && fb->format->cpp[0] * 8 == 16) {
b00c600e 47 int inc = (fb->format->depth == 15) ? 8 : 4;
de7500ea
EE		 48 u8 r, b;
49 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
b00c600e 50 if (fb->format->depth == 16) {
de7500ea
EE		 51 if (i > (MGAG200_LUT_SIZE >> 1)) {
52 r = b = 0;
53 } else {
9ed85e14
PR		 54 r = *r_ptr++ >> 8;
55 b = *b_ptr++ >> 8;
56 r_ptr++;
57 b_ptr++;
de7500ea
EE		 58 }
59 } else {
9ed85e14
PR		 60 r = *r_ptr++ >> 8;
61 b = *b_ptr++ >> 8;
de7500ea
EE		 62 }
63 /* VGA registers */
64 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
9ed85e14 65 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
de7500ea
EE		 66 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
67 }
68 return;
69 }
414c4531
DA		 70 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
71 /* VGA registers */
9ed85e14
PR		 72 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
414c4531
DA		 75 }
76}
77
78static inline void mga_wait_vsync(struct mga_device *mdev)
79{
3cdc0e8d 80 unsigned long timeout = jiffies + HZ/10;
414c4531
DA		 81 unsigned int status = 0;
82
83 do {
84 status = RREG32(MGAREG_Status);
3cdc0e8d
CH		 85 } while ((status & 0x08) && time_before(jiffies, timeout));
86 timeout = jiffies + HZ/10;
414c4531
DA		 87 status = 0;
88 do {
89 status = RREG32(MGAREG_Status);
3cdc0e8d 90 } while (!(status & 0x08) && time_before(jiffies, timeout));
414c4531
DA		 91}
92
93static inline void mga_wait_busy(struct mga_device *mdev)
94{
3cdc0e8d 95 unsigned long timeout = jiffies + HZ;
414c4531
DA		 96 unsigned int status = 0;
97 do {
98 status = RREG8(MGAREG_Status + 2);
3cdc0e8d 99 } while ((status & 0x01) && time_before(jiffies, timeout));
414c4531
DA		 100}
101
e829d7ef
ML		 102#define P_ARRAY_SIZE 9
103
414c4531
DA		 104static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
105{
106 unsigned int vcomax, vcomin, pllreffreq;
107 unsigned int delta, tmpdelta, permitteddelta;
108 unsigned int testp, testm, testn;
109 unsigned int p, m, n;
110 unsigned int computed;
e829d7ef
ML		 111 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
112 unsigned int fvv;
113 unsigned int i;
414c4531 114
e829d7ef 115 if (mdev->unique_rev_id <= 0x03) {
414c4531 116
e829d7ef
ML		 117 m = n = p = 0;
118 vcomax = 320000;
119 vcomin = 160000;
120 pllreffreq = 25000;
414c4531 121
e829d7ef
ML		 122 delta = 0xffffffff;
123 permitteddelta = clock * 5 / 1000;
414c4531 124
e829d7ef
ML		 125 for (testp = 8; testp > 0; testp /= 2) {
126 if (clock * testp > vcomax)
127 continue;
128 if (clock * testp < vcomin)
129 continue;
130
131 for (testn = 17; testn < 256; testn++) {
132 for (testm = 1; testm < 32; testm++) {
133 computed = (pllreffreq * testn) /
134 (testm * testp);
135 if (computed > clock)
136 tmpdelta = computed - clock;
137 else
138 tmpdelta = clock - computed;
139 if (tmpdelta < delta) {
140 delta = tmpdelta;
141 m = testm - 1;
142 n = testn - 1;
143 p = testp - 1;
144 }
145 }
146 }
147 }
148 } else {
149
150
151 m = n = p = 0;
152 vcomax = 1600000;
153 vcomin = 800000;
154 pllreffreq = 25000;
155
156 if (clock < 25000)
157 clock = 25000;
158
159 clock = clock * 2;
160
161 delta = 0xFFFFFFFF;
162 /* Permited delta is 0.5% as VESA Specification */
163 permitteddelta = clock * 5 / 1000;
164
165 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
166 testp = pvalues_e4[i];
167
168 if ((clock * testp) > vcomax)
169 continue;
170 if ((clock * testp) < vcomin)
171 continue;
172
173 for (testn = 50; testn <= 256; testn++) {
174 for (testm = 1; testm <= 32; testm++) {
175 computed = (pllreffreq * testn) /
176 (testm * testp);
177 if (computed > clock)
178 tmpdelta = computed - clock;
179 else
180 tmpdelta = clock - computed;
181
182 if (tmpdelta < delta) {
183 delta = tmpdelta;
184 m = testm - 1;
185 n = testn - 1;
186 p = testp - 1;
187 }
414c4531
DA		 188 }
189 }
190 }
e829d7ef 191
d3922b69 192 fvv = pllreffreq * (n + 1) / (m + 1);
e829d7ef
ML		 193 fvv = (fvv - 800000) / 50000;
194
195 if (fvv > 15)
196 fvv = 15;
197
198 p |= (fvv << 4);
199 m |= 0x80;
200
201 clock = clock / 2;
414c4531
DA		 202 }
203
204 if (delta > permitteddelta) {
8dfe162a 205 pr_warn("PLL delta too large\n");
414c4531
DA		 206 return 1;
207 }
208
209 WREG_DAC(MGA1064_PIX_PLLC_M, m);
210 WREG_DAC(MGA1064_PIX_PLLC_N, n);
211 WREG_DAC(MGA1064_PIX_PLLC_P, p);
d3922b69
ML		 212
213 if (mdev->unique_rev_id >= 0x04) {
214 WREG_DAC(0x1a, 0x09);
215 msleep(20);
216 WREG_DAC(0x1a, 0x01);
217
218 }
219
414c4531
DA		 220 return 0;
221}
222
223static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
224{
225 unsigned int vcomax, vcomin, pllreffreq;
546aee51 226 unsigned int delta, tmpdelta;
6d857c18 227 unsigned int testp, testm, testn, testp2;
414c4531
DA		 228 unsigned int p, m, n;
229 unsigned int computed;
230 int i, j, tmpcount, vcount;
231 bool pll_locked = false;
232 u8 tmp;
233
234 m = n = p = 0;
414c4531
DA		 235
236 delta = 0xffffffff;
414c4531 237
6d857c18
ML		 238 if (mdev->type == G200_EW3) {
239
240 vcomax = 800000;
241 vcomin = 400000;
242 pllreffreq = 25000;
243
244 for (testp = 1; testp < 8; testp++) {
245 for (testp2 = 1; testp2 < 8; testp2++) {
246 if (testp < testp2)
247 continue;
248 if ((clock * testp * testp2) > vcomax)
249 continue;
250 if ((clock * testp * testp2) < vcomin)
251 continue;
252 for (testm = 1; testm < 26; testm++) {
253 for (testn = 32; testn < 2048 ; testn++) {
254 computed = (pllreffreq * testn) /
255 (testm * testp * testp2);
256 if (computed > clock)
257 tmpdelta = computed - clock;
258 else
259 tmpdelta = clock - computed;
260 if (tmpdelta < delta) {
261 delta = tmpdelta;
262 m = ((testn & 0x100) >> 1) |
263 (testm);
264 n = (testn & 0xFF);
265 p = ((testn & 0x600) >> 3) |
266 (testp2 << 3) |
267 (testp);
268 }
269 }
270 }
271 }
272 }
273 } else {
414c4531 274
6d857c18
ML		 275 vcomax = 550000;
276 vcomin = 150000;
277 pllreffreq = 48000;
278
279 for (testp = 1; testp < 9; testp++) {
280 if (clock * testp > vcomax)
281 continue;
282 if (clock * testp < vcomin)
283 continue;
284
285 for (testm = 1; testm < 17; testm++) {
286 for (testn = 1; testn < 151; testn++) {
287 computed = (pllreffreq * testn) /
288 (testm * testp);
289 if (computed > clock)
290 tmpdelta = computed - clock;
291 else
292 tmpdelta = clock - computed;
293 if (tmpdelta < delta) {
294 delta = tmpdelta;
295 n = testn - 1;
296 m = (testm - 1) |
297 ((n >> 1) & 0x80);
298 p = testp - 1;
299 }
414c4531
DA		 300 }
301 }
302 }
303 }
304
305 for (i = 0; i <= 32 && pll_locked == false; i++) {
306 if (i > 0) {
307 WREG8(MGAREG_CRTC_INDEX, 0x1e);
308 tmp = RREG8(MGAREG_CRTC_DATA);
309 if (tmp < 0xff)
310 WREG8(MGAREG_CRTC_DATA, tmp+1);
311 }
312
313 /* set pixclkdis to 1 */
314 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
315 tmp = RREG8(DAC_DATA);
316 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 317 WREG8(DAC_DATA, tmp);
414c4531
DA		 318
319 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
320 tmp = RREG8(DAC_DATA);
321 tmp |= MGA1064_REMHEADCTL_CLKDIS;
fb70a669 322 WREG8(DAC_DATA, tmp);
414c4531
DA		 323
324 /* select PLL Set C */
325 tmp = RREG8(MGAREG_MEM_MISC_READ);
326 tmp |= 0x3 << 2;
327 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
328
329 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
330 tmp = RREG8(DAC_DATA);
331 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
fb70a669 332 WREG8(DAC_DATA, tmp);
414c4531
DA		 333
334 udelay(500);
335
336 /* reset the PLL */
337 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
338 tmp = RREG8(DAC_DATA);
339 tmp &= ~0x04;
fb70a669 340 WREG8(DAC_DATA, tmp);
414c4531
DA		 341
342 udelay(50);
343
344 /* program pixel pll register */
345 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
346 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
347 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
348
349 udelay(50);
350
351 /* turn pll on */
352 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
353 tmp = RREG8(DAC_DATA);
354 tmp |= 0x04;
355 WREG_DAC(MGA1064_VREF_CTL, tmp);
356
357 udelay(500);
358
359 /* select the pixel pll */
360 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
361 tmp = RREG8(DAC_DATA);
362 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
363 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 364 WREG8(DAC_DATA, tmp);
414c4531
DA		 365
366 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
367 tmp = RREG8(DAC_DATA);
368 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
369 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
fb70a669 370 WREG8(DAC_DATA, tmp);
414c4531
DA		 371
372 /* reset dotclock rate bit */
373 WREG8(MGAREG_SEQ_INDEX, 1);
374 tmp = RREG8(MGAREG_SEQ_DATA);
375 tmp &= ~0x8;
376 WREG8(MGAREG_SEQ_DATA, tmp);
377
378 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
379 tmp = RREG8(DAC_DATA);
380 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 381 WREG8(DAC_DATA, tmp);
414c4531
DA		 382
383 vcount = RREG8(MGAREG_VCOUNT);
384
385 for (j = 0; j < 30 && pll_locked == false; j++) {
386 tmpcount = RREG8(MGAREG_VCOUNT);
387 if (tmpcount < vcount)
388 vcount = 0;
389 if ((tmpcount - vcount) > 2)
390 pll_locked = true;
391 else
392 udelay(5);
393 }
394 }
395 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
396 tmp = RREG8(DAC_DATA);
397 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
398 WREG_DAC(MGA1064_REMHEADCTL, tmp);
399 return 0;
400}
401
402static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
403{
404 unsigned int vcomax, vcomin, pllreffreq;
546aee51 405 unsigned int delta, tmpdelta;
414c4531
DA		 406 unsigned int testp, testm, testn;
407 unsigned int p, m, n;
408 unsigned int computed;
409 u8 tmp;
410
411 m = n = p = 0;
412 vcomax = 550000;
413 vcomin = 150000;
414 pllreffreq = 50000;
415
416 delta = 0xffffffff;
414c4531
DA		 417
418 for (testp = 16; testp > 0; testp--) {
419 if (clock * testp > vcomax)
420 continue;
421 if (clock * testp < vcomin)
422 continue;
423
424 for (testn = 1; testn < 257; testn++) {
425 for (testm = 1; testm < 17; testm++) {
426 computed = (pllreffreq * testn) /
427 (testm * testp);
428 if (computed > clock)
429 tmpdelta = computed - clock;
430 else
431 tmpdelta = clock - computed;
432 if (tmpdelta < delta) {
433 delta = tmpdelta;
434 n = testn - 1;
435 m = testm - 1;
436 p = testp - 1;
437 }
438 }
439 }
440 }
441
442 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
443 tmp = RREG8(DAC_DATA);
444 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 445 WREG8(DAC_DATA, tmp);
414c4531
DA		 446
447 tmp = RREG8(MGAREG_MEM_MISC_READ);
448 tmp |= 0x3 << 2;
449 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
450
451 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
452 tmp = RREG8(DAC_DATA);
fb70a669 453 WREG8(DAC_DATA, tmp & ~0x40);
414c4531
DA		 454
455 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
456 tmp = RREG8(DAC_DATA);
457 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 458 WREG8(DAC_DATA, tmp);
414c4531
DA		 459
460 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
461 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
462 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
463
464 udelay(50);
465
466 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
467 tmp = RREG8(DAC_DATA);
468 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 469 WREG8(DAC_DATA, tmp);
414c4531
DA		 470
471 udelay(500);
472
473 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
474 tmp = RREG8(DAC_DATA);
475 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
476 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 477 WREG8(DAC_DATA, tmp);
414c4531
DA		 478
479 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
480 tmp = RREG8(DAC_DATA);
fb70a669 481 WREG8(DAC_DATA, tmp | 0x40);
414c4531
DA		 482
483 tmp = RREG8(MGAREG_MEM_MISC_READ);
484 tmp |= (0x3 << 2);
485 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
486
487 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
488 tmp = RREG8(DAC_DATA);
489 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 490 WREG8(DAC_DATA, tmp);
414c4531
DA		 491
492 return 0;
493}
494
495static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
496{
497 unsigned int vcomax, vcomin, pllreffreq;
546aee51 498 unsigned int delta, tmpdelta;
414c4531
DA		 499 unsigned int testp, testm, testn;
500 unsigned int p, m, n;
501 unsigned int computed;
502 int i, j, tmpcount, vcount;
503 u8 tmp;
504 bool pll_locked = false;
505
506 m = n = p = 0;
414c4531 507
f0493e65
ML		 508 if (mdev->type == G200_EH3) {
509 vcomax = 3000000;
510 vcomin = 1500000;
511 pllreffreq = 25000;
414c4531 512
f0493e65 513 delta = 0xffffffff;
414c4531 514
f0493e65
ML		 515 testp = 0;
516
517 for (testm = 150; testm >= 6; testm--) {
518 if (clock * testm > vcomax)
519 continue;
520 if (clock * testm < vcomin)
521 continue;
522 for (testn = 120; testn >= 60; testn--) {
523 computed = (pllreffreq * testn) / testm;
414c4531
DA		 524 if (computed > clock)
525 tmpdelta = computed - clock;
526 else
527 tmpdelta = clock - computed;
528 if (tmpdelta < delta) {
529 delta = tmpdelta;
f0493e65
ML		 530 n = testn;
531 m = testm;
532 p = testp;
533 }
534 if (delta == 0)
535 break;
536 }
537 if (delta == 0)
538 break;
539 }
540 } else {
541
542 vcomax = 800000;
543 vcomin = 400000;
544 pllreffreq = 33333;
545
546 delta = 0xffffffff;
547
548 for (testp = 16; testp > 0; testp >>= 1) {
549 if (clock * testp > vcomax)
550 continue;
551 if (clock * testp < vcomin)
552 continue;
553
554 for (testm = 1; testm < 33; testm++) {
555 for (testn = 17; testn < 257; testn++) {
556 computed = (pllreffreq * testn) /
557 (testm * testp);
558 if (computed > clock)
559 tmpdelta = computed - clock;
560 else
561 tmpdelta = clock - computed;
562 if (tmpdelta < delta) {
563 delta = tmpdelta;
564 n = testn - 1;
565 m = (testm - 1);
566 p = testp - 1;
567 }
568 if ((clock * testp) >= 600000)
569 p |= 0x80;
414c4531 570 }
414c4531
DA		 571 }
572 }
573 }
574 for (i = 0; i <= 32 && pll_locked == false; i++) {
575 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
576 tmp = RREG8(DAC_DATA);
577 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 578 WREG8(DAC_DATA, tmp);
414c4531
DA		 579
580 tmp = RREG8(MGAREG_MEM_MISC_READ);
581 tmp |= 0x3 << 2;
582 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
583
584 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
585 tmp = RREG8(DAC_DATA);
586 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 587 WREG8(DAC_DATA, tmp);
414c4531
DA		 588
589 udelay(500);
590
591 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
592 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
593 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
594
595 udelay(500);
596
597 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
598 tmp = RREG8(DAC_DATA);
599 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
600 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 601 WREG8(DAC_DATA, tmp);
414c4531
DA		 602
603 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
604 tmp = RREG8(DAC_DATA);
605 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
606 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 607 WREG8(DAC_DATA, tmp);
414c4531
DA		 608
609 vcount = RREG8(MGAREG_VCOUNT);
610
611 for (j = 0; j < 30 && pll_locked == false; j++) {
612 tmpcount = RREG8(MGAREG_VCOUNT);
613 if (tmpcount < vcount)
614 vcount = 0;
615 if ((tmpcount - vcount) > 2)
616 pll_locked = true;
617 else
618 udelay(5);
619 }
620 }
621
622 return 0;
623}
624
625static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
626{
627 unsigned int vcomax, vcomin, pllreffreq;
628 unsigned int delta, tmpdelta;
9830605d 629 int testr, testn, testm, testo;
414c4531 630 unsigned int p, m, n;
9830605d 631 unsigned int computed, vco;
414c4531 632 int tmp;
9830605d 633 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
414c4531
DA		 634
635 m = n = p = 0;
636 vcomax = 1488000;
637 vcomin = 1056000;
638 pllreffreq = 48000;
639
640 delta = 0xffffffff;
641
642 for (testr = 0; testr < 4; testr++) {
643 if (delta == 0)
644 break;
645 for (testn = 5; testn < 129; testn++) {
646 if (delta == 0)
647 break;
648 for (testm = 3; testm >= 0; testm--) {
649 if (delta == 0)
650 break;
651 for (testo = 5; testo < 33; testo++) {
9830605d 652 vco = pllreffreq * (testn + 1) /
414c4531 653 (testr + 1);
9830605d 654 if (vco < vcomin)
414c4531 655 continue;
9830605d 656 if (vco > vcomax)
414c4531 657 continue;
9830605d 658 computed = vco / (m_div_val[testm] * (testo + 1));
414c4531
DA		 659 if (computed > clock)
660 tmpdelta = computed - clock;
661 else
662 tmpdelta = clock - computed;
663 if (tmpdelta < delta) {
664 delta = tmpdelta;
665 m = testm | (testo << 3);
666 n = testn;
667 p = testr | (testr << 3);
668 }
669 }
670 }
671 }
672 }
673
674 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
675 tmp = RREG8(DAC_DATA);
676 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 677 WREG8(DAC_DATA, tmp);
414c4531
DA		 678
679 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
680 tmp = RREG8(DAC_DATA);
681 tmp |= MGA1064_REMHEADCTL_CLKDIS;
fb70a669 682 WREG8(DAC_DATA, tmp);
414c4531
DA		 683
684 tmp = RREG8(MGAREG_MEM_MISC_READ);
685 tmp |= (0x3<<2) | 0xc0;
686 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
687
688 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
689 tmp = RREG8(DAC_DATA);
690 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
691 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 692 WREG8(DAC_DATA, tmp);
414c4531
DA		 693
694 udelay(500);
695
696 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
697 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
698 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
699
700 udelay(50);
701
702 return 0;
703}
704
705static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
706{
707 switch(mdev->type) {
708 case G200_SE_A:
709 case G200_SE_B:
710 return mga_g200se_set_plls(mdev, clock);
711 break;
712 case G200_WB:
6d857c18 713 case G200_EW3:
414c4531
DA		 714 return mga_g200wb_set_plls(mdev, clock);
715 break;
716 case G200_EV:
717 return mga_g200ev_set_plls(mdev, clock);
718 break;
719 case G200_EH:
f0493e65 720 case G200_EH3:
414c4531
DA		 721 return mga_g200eh_set_plls(mdev, clock);
722 break;
723 case G200_ER:
724 return mga_g200er_set_plls(mdev, clock);
725 break;
726 }
727 return 0;
728}
729
730static void mga_g200wb_prepare(struct drm_crtc *crtc)
731{
732 struct mga_device *mdev = crtc->dev->dev_private;
733 u8 tmp;
734 int iter_max;
735
736 /* 1- The first step is to warn the BMC of an upcoming mode change.
737 * We are putting the misc<0> to output.*/
738
739 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
740 tmp = RREG8(DAC_DATA);
741 tmp |= 0x10;
742 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
743
744 /* we are putting a 1 on the misc<0> line */
745 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
746 tmp = RREG8(DAC_DATA);
747 tmp |= 0x10;
748 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
749
750 /* 2- Second step to mask and further scan request
751 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
752 */
753 WREG8(DAC_INDEX, MGA1064_SPAREREG);
754 tmp = RREG8(DAC_DATA);
755 tmp |= 0x80;
756 WREG_DAC(MGA1064_SPAREREG, tmp);
757
758 /* 3a- the third step is to verifu if there is an active scan
759 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
760 */
761 iter_max = 300;
762 while (!(tmp & 0x1) && iter_max) {
763 WREG8(DAC_INDEX, MGA1064_SPAREREG);
764 tmp = RREG8(DAC_DATA);
765 udelay(1000);
766 iter_max--;
767 }
768
769 /* 3b- this step occurs only if the remove is actually scanning
770 * we are waiting for the end of the frame which is a 1 on
771 * remvsyncsts (XSPAREREG<1>)
772 */
773 if (iter_max) {
774 iter_max = 300;
775 while ((tmp & 0x2) && iter_max) {
776 WREG8(DAC_INDEX, MGA1064_SPAREREG);
777 tmp = RREG8(DAC_DATA);
778 udelay(1000);
779 iter_max--;
780 }
781 }
782}
783
784static void mga_g200wb_commit(struct drm_crtc *crtc)
785{
786 u8 tmp;
787 struct mga_device *mdev = crtc->dev->dev_private;
788
789 /* 1- The first step is to ensure that the vrsten and hrsten are set */
790 WREG8(MGAREG_CRTCEXT_INDEX, 1);
791 tmp = RREG8(MGAREG_CRTCEXT_DATA);
792 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
793
794 /* 2- second step is to assert the rstlvl2 */
795 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
796 tmp = RREG8(DAC_DATA);
797 tmp |= 0x8;
798 WREG8(DAC_DATA, tmp);
799
800 /* wait 10 us */
801 udelay(10);
802
803 /* 3- deassert rstlvl2 */
804 tmp &= ~0x08;
805 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
806 WREG8(DAC_DATA, tmp);
807
808 /* 4- remove mask of scan request */
809 WREG8(DAC_INDEX, MGA1064_SPAREREG);
810 tmp = RREG8(DAC_DATA);
811 tmp &= ~0x80;
812 WREG8(DAC_DATA, tmp);
813
814 /* 5- put back a 0 on the misc<0> line */
815 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
816 tmp = RREG8(DAC_DATA);
817 tmp &= ~0x10;
818 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
819}
820
9f1d0366
CH		 821/*
822 This is how the framebuffer base address is stored in g200 cards:
823 * Assume @offset is the gpu_addr variable of the framebuffer object
824 * Then addr is the number of _pixels_ (not bytes) from the start of
825 VRAM to the first pixel we want to display. (divided by 2 for 32bit
826 framebuffers)
827 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
828 addr<20> -> CRTCEXT0<6>
829 addr<19-16> -> CRTCEXT0<3-0>
830 addr<15-8> -> CRTCC<7-0>
831 addr<7-0> -> CRTCD<7-0>
832 CRTCEXT0 has to be programmed last to trigger an update and make the
833 new addr variable take effect.
834 */
080fd6b5 835static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
414c4531
DA		 836{
837 struct mga_device *mdev = crtc->dev->dev_private;
838 u32 addr;
839 int count;
9f1d0366 840 u8 crtcext0;
414c4531
DA		 841
842 while (RREG8(0x1fda) & 0x08);
843 while (!(RREG8(0x1fda) & 0x08));
844
845 count = RREG8(MGAREG_VCOUNT) + 2;
846 while (RREG8(MGAREG_VCOUNT) < count);
847
9f1d0366
CH		 848 WREG8(MGAREG_CRTCEXT_INDEX, 0);
849 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
850 crtcext0 &= 0xB0;
851 addr = offset / 8;
852 /* Can't store addresses any higher than that...
853 but we also don't have more than 16MB of memory, so it should be fine. */
854 WARN_ON(addr > 0x1fffff);
855 crtcext0 |= (!!(addr & (1<<20)))<<6;
414c4531
DA		 856 WREG_CRT(0x0d, (u8)(addr & 0xff));
857 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
9f1d0366 858 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
414c4531
DA		 859}
860
861
862/* ast is different - we will force move buffers out of VRAM */
863static int mga_crtc_do_set_base(struct drm_crtc *crtc,
864 struct drm_framebuffer *fb,
865 int x, int y, int atomic)
866{
867 struct mga_device *mdev = crtc->dev->dev_private;
868 struct drm_gem_object *obj;
869 struct mga_framebuffer *mga_fb;
870 struct mgag200_bo *bo;
871 int ret;
872 u64 gpu_addr;
873
874 /* push the previous fb to system ram */
875 if (!atomic && fb) {
876 mga_fb = to_mga_framebuffer(fb);
877 obj = mga_fb->obj;
878 bo = gem_to_mga_bo(obj);
879 ret = mgag200_bo_reserve(bo, false);
880 if (ret)
881 return ret;
882 mgag200_bo_push_sysram(bo);
883 mgag200_bo_unreserve(bo);
884 }
885
f4510a27 886 mga_fb = to_mga_framebuffer(crtc->primary->fb);
414c4531
DA		 887 obj = mga_fb->obj;
888 bo = gem_to_mga_bo(obj);
889
890 ret = mgag200_bo_reserve(bo, false);
891 if (ret)
892 return ret;
893
894 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
895 if (ret) {
896 mgag200_bo_unreserve(bo);
897 return ret;
898 }
899
900 if (&mdev->mfbdev->mfb == mga_fb) {
901 /* if pushing console in kmap it */
902 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
903 if (ret)
904 DRM_ERROR("failed to kmap fbcon\n");
905
906 }
907 mgag200_bo_unreserve(bo);
908
414c4531
DA		 909 mga_set_start_address(crtc, (u32)gpu_addr);
910
911 return 0;
912}
913
914static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
915 struct drm_framebuffer *old_fb)
916{
917 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
918}
919
920static int mga_crtc_mode_set(struct drm_crtc *crtc,
921 struct drm_display_mode *mode,
922 struct drm_display_mode *adjusted_mode,
923 int x, int y, struct drm_framebuffer *old_fb)
924{
925 struct drm_device *dev = crtc->dev;
926 struct mga_device *mdev = dev->dev_private;
72952757 927 const struct drm_framebuffer *fb = crtc->primary->fb;
414c4531
DA		 928 int hdisplay, hsyncstart, hsyncend, htotal;
929 int vdisplay, vsyncstart, vsyncend, vtotal;
930 int pitch;
931 int option = 0, option2 = 0;
932 int i;
933 unsigned char misc = 0;
934 unsigned char ext_vga[6];
414c4531
DA		 935 u8 bppshift;
936
937 static unsigned char dacvalue[] = {
938 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
939 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
940 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
941 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
942 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
943 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
944 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
945 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
946 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
947 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
948 };
949
272725c7 950 bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1];
414c4531
DA		 951
952 switch (mdev->type) {
953 case G200_SE_A:
954 case G200_SE_B:
955 dacvalue[MGA1064_VREF_CTL] = 0x03;
956 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
957 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
958 MGA1064_MISC_CTL_VGA8 |
959 MGA1064_MISC_CTL_DAC_RAM_CS;
960 if (mdev->has_sdram)
961 option = 0x40049120;
962 else
963 option = 0x4004d120;
964 option2 = 0x00008000;
965 break;
966 case G200_WB:
6d857c18 967 case G200_EW3:
414c4531
DA		 968 dacvalue[MGA1064_VREF_CTL] = 0x07;
969 option = 0x41049120;
970 option2 = 0x0000b000;
971 break;
972 case G200_EV:
973 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
974 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
975 MGA1064_MISC_CTL_DAC_RAM_CS;
976 option = 0x00000120;
977 option2 = 0x0000b000;
978 break;
979 case G200_EH:
f0493e65 980 case G200_EH3:
414c4531
DA		 981 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
982 MGA1064_MISC_CTL_DAC_RAM_CS;
983 option = 0x00000120;
984 option2 = 0x0000b000;
985 break;
986 case G200_ER:
414c4531
DA		 987 break;
988 }
989
272725c7 990 switch (fb->format->cpp[0] * 8) {
414c4531
DA		 991 case 8:
992 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
993 break;
994 case 16:
b00c600e 995 if (fb->format->depth == 15)
414c4531
DA		 996 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
997 else
998 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
999 break;
1000 case 24:
1001 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
1002 break;
1003 case 32:
1004 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
1005 break;
1006 }
1007
1008 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1009 misc |= 0x40;
1010 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1011 misc |= 0x80;
1012
1013
1014 for (i = 0; i < sizeof(dacvalue); i++) {
9d8aa55f 1015 if ((i <= 0x17) ||
414c4531
DA		 1016 (i == 0x1b) ||
1017 (i == 0x1c) ||
1018 ((i >= 0x1f) && (i <= 0x29)) ||
1019 ((i >= 0x30) && (i <= 0x37)))
1020 continue;
1021 if (IS_G200_SE(mdev) &&
1022 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1023 continue;
6d857c18
ML		 1024 if ((mdev->type == G200_EV ||
1025 mdev->type == G200_WB ||
1026 mdev->type == G200_EH ||
f0493e65
ML		 1027 mdev->type == G200_EW3 ||
1028 mdev->type == G200_EH3) &&
414c4531
DA		 1029 (i >= 0x44) && (i <= 0x4e))
1030 continue;
1031
1032 WREG_DAC(i, dacvalue[i]);
1033 }
1034
1812a3db
CH		 1035 if (mdev->type == G200_ER)
1036 WREG_DAC(0x90, 0);
414c4531
DA		 1037
1038 if (option)
1039 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
1040 if (option2)
1041 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
1042
1043 WREG_SEQ(2, 0xf);
1044 WREG_SEQ(3, 0);
1045 WREG_SEQ(4, 0xe);
1046
272725c7
VS		 1047 pitch = fb->pitches[0] / fb->format->cpp[0];
1048 if (fb->format->cpp[0] * 8 == 24)
da558398 1049 pitch = (pitch * 3) >> (4 - bppshift);
414c4531
DA		 1050 else
1051 pitch = pitch >> (4 - bppshift);
1052
1053 hdisplay = mode->hdisplay / 8 - 1;
1054 hsyncstart = mode->hsync_start / 8 - 1;
1055 hsyncend = mode->hsync_end / 8 - 1;
1056 htotal = mode->htotal / 8 - 1;
1057
1058 /* Work around hardware quirk */
1059 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1060 htotal++;
1061
1062 vdisplay = mode->vdisplay - 1;
1063 vsyncstart = mode->vsync_start - 1;
1064 vsyncend = mode->vsync_end - 1;
1065 vtotal = mode->vtotal - 2;
1066
1067 WREG_GFX(0, 0);
1068 WREG_GFX(1, 0);
1069 WREG_GFX(2, 0);
1070 WREG_GFX(3, 0);
1071 WREG_GFX(4, 0);
1072 WREG_GFX(5, 0x40);
1073 WREG_GFX(6, 0x5);
1074 WREG_GFX(7, 0xf);
1075 WREG_GFX(8, 0xf);
1076
1077 WREG_CRT(0, htotal - 4);
1078 WREG_CRT(1, hdisplay);
1079 WREG_CRT(2, hdisplay);
1080 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1081 WREG_CRT(4, hsyncstart);
1082 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1083 WREG_CRT(6, vtotal & 0xFF);
1084 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1085 ((vdisplay & 0x100) >> 7) |
1086 ((vsyncstart & 0x100) >> 6) |
1087 ((vdisplay & 0x100) >> 5) |
1088 ((vdisplay & 0x100) >> 4) | /* linecomp */
1089 ((vtotal & 0x200) >> 4)|
1090 ((vdisplay & 0x200) >> 3) |
1091 ((vsyncstart & 0x200) >> 2));
1092 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1093 ((vdisplay & 0x200) >> 3));
1094 WREG_CRT(10, 0);
1095 WREG_CRT(11, 0);
1096 WREG_CRT(12, 0);
1097 WREG_CRT(13, 0);
1098 WREG_CRT(14, 0);
1099 WREG_CRT(15, 0);
1100 WREG_CRT(16, vsyncstart & 0xFF);
1101 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1102 WREG_CRT(18, vdisplay & 0xFF);
1103 WREG_CRT(19, pitch & 0xFF);
1104 WREG_CRT(20, 0);
1105 WREG_CRT(21, vdisplay & 0xFF);
1106 WREG_CRT(22, (vtotal + 1) & 0xFF);
1107 WREG_CRT(23, 0xc3);
1108 WREG_CRT(24, vdisplay & 0xFF);
1109
1110 ext_vga[0] = 0;
1111 ext_vga[5] = 0;
1112
1113 /* TODO interlace */
1114
1115 ext_vga[0] |= (pitch & 0x300) >> 4;
1116 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1117 ((hdisplay & 0x100) >> 7) |
1118 ((hsyncstart & 0x100) >> 6) |
1119 (htotal & 0x40);
1120 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1121 ((vdisplay & 0x400) >> 8) |
1122 ((vdisplay & 0xc00) >> 7) |
1123 ((vsyncstart & 0xc00) >> 5) |
1124 ((vdisplay & 0x400) >> 3);
272725c7 1125 if (fb->format->cpp[0] * 8 == 24)
414c4531
DA		 1126 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1127 else
1128 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1129 ext_vga[4] = 0;
6d857c18 1130 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1131 ext_vga[1] |= 0x88;
1132
414c4531
DA		 1133 /* Set pixel clocks */
1134 misc = 0x2d;
1135 WREG8(MGA_MISC_OUT, misc);
1136
1137 mga_crtc_set_plls(mdev, mode->clock);
1138
1139 for (i = 0; i < 6; i++) {
1140 WREG_ECRT(i, ext_vga[i]);
1141 }
1142
1143 if (mdev->type == G200_ER)
1812a3db 1144 WREG_ECRT(0x24, 0x5);
414c4531 1145
6d857c18
ML		 1146 if (mdev->type == G200_EW3)
1147 WREG_ECRT(0x34, 0x5);
1148
414c4531
DA		 1149 if (mdev->type == G200_EV) {
1150 WREG_ECRT(6, 0);
1151 }
1152
1153 WREG_ECRT(0, ext_vga[0]);
1154 /* Enable mga pixel clock */
1155 misc = 0x2d;
1156
1157 WREG8(MGA_MISC_OUT, misc);
1158
1159 if (adjusted_mode)
1160 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1161
1162 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1163
1164 /* reset tagfifo */
1165 if (mdev->type == G200_ER) {
1166 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1167 u8 seq1;
1168
1169 /* screen off */
1170 WREG8(MGAREG_SEQ_INDEX, 0x01);
1171 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1172 WREG8(MGAREG_SEQ_DATA, seq1);
1173
1174 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1175 udelay(1000);
1176 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1177
1178 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1179 }
1180
1181
1182 if (IS_G200_SE(mdev)) {
0cbb7381
ML		 1183 if (mdev->unique_rev_id >= 0x04) {
1184 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1185 WREG8(MGAREG_CRTCEXT_DATA, 0);
1186 } else if (mdev->unique_rev_id >= 0x02) {
414c4531
DA		 1187 u8 hi_pri_lvl;
1188 u32 bpp;
1189 u32 mb;
1190
272725c7 1191 if (fb->format->cpp[0] * 8 > 16)
414c4531 1192 bpp = 32;
272725c7 1193 else if (fb->format->cpp[0] * 8 > 8)
414c4531
DA		 1194 bpp = 16;
1195 else
1196 bpp = 8;
1197
1198 mb = (mode->clock * bpp) / 1000;
1199 if (mb > 3100)
1200 hi_pri_lvl = 0;
1201 else if (mb > 2600)
1202 hi_pri_lvl = 1;
1203 else if (mb > 1900)
1204 hi_pri_lvl = 2;
1205 else if (mb > 1160)
1206 hi_pri_lvl = 3;
1207 else if (mb > 440)
1208 hi_pri_lvl = 4;
1209 else
1210 hi_pri_lvl = 5;
1211
91f8f105
CH		 1212 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1213 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
414c4531 1214 } else {
91f8f105 1215 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
abbee623 1216 if (mdev->unique_rev_id >= 0x01)
91f8f105 1217 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
414c4531 1218 else
91f8f105 1219 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
414c4531
DA		 1220 }
1221 }
1222 return 0;
1223}
1224
1225#if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1226static int mga_suspend(struct drm_crtc *crtc)
1227{
1228 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1229 struct drm_device *dev = crtc->dev;
1230 struct mga_device *mdev = dev->dev_private;
1231 struct pci_dev *pdev = dev->pdev;
1232 int option;
1233
1234 if (mdev->suspended)
1235 return 0;
1236
1237 WREG_SEQ(1, 0x20);
1238 WREG_ECRT(1, 0x30);
1239 /* Disable the pixel clock */
1240 WREG_DAC(0x1a, 0x05);
1241 /* Power down the DAC */
1242 WREG_DAC(0x1e, 0x18);
1243 /* Power down the pixel PLL */
1244 WREG_DAC(0x1a, 0x0d);
1245
1246 /* Disable PLLs and clocks */
1247 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1248 option &= ~(0x1F8024);
1249 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1250 pci_set_power_state(pdev, PCI_D3hot);
1251 pci_disable_device(pdev);
1252
1253 mdev->suspended = true;
1254
1255 return 0;
1256}
1257
1258static int mga_resume(struct drm_crtc *crtc)
1259{
1260 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1261 struct drm_device *dev = crtc->dev;
1262 struct mga_device *mdev = dev->dev_private;
1263 struct pci_dev *pdev = dev->pdev;
1264 int option;
1265
1266 if (!mdev->suspended)
1267 return 0;
1268
1269 pci_set_power_state(pdev, PCI_D0);
1270 pci_enable_device(pdev);
1271
1272 /* Disable sysclk */
1273 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1274 option &= ~(0x4);
1275 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1276
1277 mdev->suspended = false;
1278
1279 return 0;
1280}
1281
1282#endif
1283
1284static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1285{
1286 struct drm_device *dev = crtc->dev;
1287 struct mga_device *mdev = dev->dev_private;
1288 u8 seq1 = 0, crtcext1 = 0;
1289
1290 switch (mode) {
1291 case DRM_MODE_DPMS_ON:
1292 seq1 = 0;
1293 crtcext1 = 0;
1294 mga_crtc_load_lut(crtc);
1295 break;
1296 case DRM_MODE_DPMS_STANDBY:
1297 seq1 = 0x20;
1298 crtcext1 = 0x10;
1299 break;
1300 case DRM_MODE_DPMS_SUSPEND:
1301 seq1 = 0x20;
1302 crtcext1 = 0x20;
1303 break;
1304 case DRM_MODE_DPMS_OFF:
1305 seq1 = 0x20;
1306 crtcext1 = 0x30;
1307 break;
1308 }
1309
1310#if 0
1311 if (mode == DRM_MODE_DPMS_OFF) {
1312 mga_suspend(crtc);
1313 }
1314#endif
1315 WREG8(MGAREG_SEQ_INDEX, 0x01);
1316 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1317 mga_wait_vsync(mdev);
1318 mga_wait_busy(mdev);
1319 WREG8(MGAREG_SEQ_DATA, seq1);
1320 msleep(20);
1321 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1322 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1323 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1324
1325#if 0
1326 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1327 mga_resume(crtc);
1328 drm_helper_resume_force_mode(dev);
1329 }
1330#endif
1331}
1332
1333/*
1334 * This is called before a mode is programmed. A typical use might be to
1335 * enable DPMS during the programming to avoid seeing intermediate stages,
1336 * but that's not relevant to us
1337 */
1338static void mga_crtc_prepare(struct drm_crtc *crtc)
1339{
1340 struct drm_device *dev = crtc->dev;
1341 struct mga_device *mdev = dev->dev_private;
1342 u8 tmp;
1343
1344 /* mga_resume(crtc);*/
1345
1346 WREG8(MGAREG_CRTC_INDEX, 0x11);
1347 tmp = RREG8(MGAREG_CRTC_DATA);
1348 WREG_CRT(0x11, tmp | 0x80);
1349
1350 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1351 WREG_SEQ(0, 1);
1352 msleep(50);
1353 WREG_SEQ(1, 0x20);
1354 msleep(20);
1355 } else {
1356 WREG8(MGAREG_SEQ_INDEX, 0x1);
1357 tmp = RREG8(MGAREG_SEQ_DATA);
1358
1359 /* start sync reset */
1360 WREG_SEQ(0, 1);
1361 WREG_SEQ(1, tmp | 0x20);
1362 }
1363
6d857c18 1364 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1365 mga_g200wb_prepare(crtc);
1366
1367 WREG_CRT(17, 0);
1368}
1369
1370/*
1371 * This is called after a mode is programmed. It should reverse anything done
1372 * by the prepare function
1373 */
1374static void mga_crtc_commit(struct drm_crtc *crtc)
1375{
1376 struct drm_device *dev = crtc->dev;
1377 struct mga_device *mdev = dev->dev_private;
d584ff82 1378 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
414c4531
DA		 1379 u8 tmp;
1380
6d857c18 1381 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1382 mga_g200wb_commit(crtc);
1383
1384 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1385 msleep(50);
1386 WREG_SEQ(1, 0x0);
1387 msleep(20);
1388 WREG_SEQ(0, 0x3);
1389 } else {
1390 WREG8(MGAREG_SEQ_INDEX, 0x1);
1391 tmp = RREG8(MGAREG_SEQ_DATA);
1392
1393 tmp &= ~0x20;
1394 WREG_SEQ(0x1, tmp);
1395 WREG_SEQ(0, 3);
1396 }
1397 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1398}
1399
1400/*
1401 * The core can pass us a set of gamma values to program. We actually only
1402 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1403 * but it's a requirement that we provide the function
1404 */
7ea77283 1405static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6d124ff8
SV		 1406 u16 *blue, uint32_t size,
1407 struct drm_modeset_acquire_ctx *ctx)
414c4531 1408{
414c4531 1409 mga_crtc_load_lut(crtc);
7ea77283
ML		 1410
1411 return 0;
414c4531
DA		 1412}
1413
1414/* Simple cleanup function */
1415static void mga_crtc_destroy(struct drm_crtc *crtc)
1416{
1417 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1418
1419 drm_crtc_cleanup(crtc);
1420 kfree(mga_crtc);
1421}
1422
64c29076
EE		 1423static void mga_crtc_disable(struct drm_crtc *crtc)
1424{
1425 int ret;
1426 DRM_DEBUG_KMS("\n");
1427 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27
MR		 1428 if (crtc->primary->fb) {
1429 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
64c29076
EE		 1430 struct drm_gem_object *obj = mga_fb->obj;
1431 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1432 ret = mgag200_bo_reserve(bo, false);
1433 if (ret)
1434 return;
1435 mgag200_bo_push_sysram(bo);
1436 mgag200_bo_unreserve(bo);
1437 }
f4510a27 1438 crtc->primary->fb = NULL;
64c29076
EE		 1439}
1440
414c4531
DA		 1441/* These provide the minimum set of functions required to handle a CRTC */
1442static const struct drm_crtc_funcs mga_crtc_funcs = {
a080db9f
CH		 1443 .cursor_set = mga_crtc_cursor_set,
1444 .cursor_move = mga_crtc_cursor_move,
414c4531
DA		 1445 .gamma_set = mga_crtc_gamma_set,
1446 .set_config = drm_crtc_helper_set_config,
1447 .destroy = mga_crtc_destroy,
1448};
1449
1450static const struct drm_crtc_helper_funcs mga_helper_funcs = {
64c29076 1451 .disable = mga_crtc_disable,
414c4531 1452 .dpms = mga_crtc_dpms,
414c4531
DA		 1453 .mode_set = mga_crtc_mode_set,
1454 .mode_set_base = mga_crtc_mode_set_base,
1455 .prepare = mga_crtc_prepare,
1456 .commit = mga_crtc_commit,
414c4531
DA		 1457};
1458
1459/* CRTC setup */
f1998fe2 1460static void mga_crtc_init(struct mga_device *mdev)
414c4531 1461{
414c4531 1462 struct mga_crtc *mga_crtc;
414c4531
DA		 1463
1464 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1465 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1466 GFP_KERNEL);
1467
1468 if (mga_crtc == NULL)
1469 return;
1470
f1998fe2 1471 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
414c4531
DA		 1472
1473 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1474 mdev->mode_info.crtc = mga_crtc;
1475
414c4531
DA		 1476 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1477}
1478
414c4531
DA		 1479/*
1480 * The encoder comes after the CRTC in the output pipeline, but before
1481 * the connector. It's responsible for ensuring that the digital
1482 * stream is appropriately converted into the output format. Setup is
1483 * very simple in this case - all we have to do is inform qemu of the
1484 * colour depth in order to ensure that it displays appropriately
1485 */
1486
1487/*
1488 * These functions are analagous to those in the CRTC code, but are intended
1489 * to handle any encoder-specific limitations
1490 */
414c4531
DA		 1491static void mga_encoder_mode_set(struct drm_encoder *encoder,
1492 struct drm_display_mode *mode,
1493 struct drm_display_mode *adjusted_mode)
1494{
1495
1496}
1497
1498static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1499{
1500 return;
1501}
1502
1503static void mga_encoder_prepare(struct drm_encoder *encoder)
1504{
1505}
1506
1507static void mga_encoder_commit(struct drm_encoder *encoder)
1508{
1509}
1510
080fd6b5 1511static void mga_encoder_destroy(struct drm_encoder *encoder)
414c4531
DA		 1512{
1513 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1514 drm_encoder_cleanup(encoder);
1515 kfree(mga_encoder);
1516}
1517
1518static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1519 .dpms = mga_encoder_dpms,
414c4531
DA		 1520 .mode_set = mga_encoder_mode_set,
1521 .prepare = mga_encoder_prepare,
1522 .commit = mga_encoder_commit,
1523};
1524
1525static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1526 .destroy = mga_encoder_destroy,
1527};
1528
1529static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1530{
1531 struct drm_encoder *encoder;
1532 struct mga_encoder *mga_encoder;
1533
1534 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1535 if (!mga_encoder)
1536 return NULL;
1537
1538 encoder = &mga_encoder->base;
1539 encoder->possible_crtcs = 0x1;
1540
1541 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
13a3d91f 1542 DRM_MODE_ENCODER_DAC, NULL);
414c4531
DA		 1543 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1544
1545 return encoder;
1546}
1547
1548
1549static int mga_vga_get_modes(struct drm_connector *connector)
1550{
1551 struct mga_connector *mga_connector = to_mga_connector(connector);
1552 struct edid *edid;
1553 int ret = 0;
1554
1555 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1556 if (edid) {
c555f023 1557 drm_connector_update_edid_property(connector, edid);
414c4531 1558 ret = drm_add_edid_modes(connector, edid);
414c4531
DA		 1559 kfree(edid);
1560 }
1561 return ret;
1562}
1563
abbee623
JL		 1564static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1565 int bits_per_pixel)
1566{
1567 uint32_t total_area, divisor;
c24ca5be 1568 uint64_t active_area, pixels_per_second, bandwidth;
abbee623
JL		 1569 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1570
1571 divisor = 1024;
1572
1573 if (!mode->htotal || !mode->vtotal || !mode->clock)
1574 return 0;
1575
1576 active_area = mode->hdisplay * mode->vdisplay;
1577 total_area = mode->htotal * mode->vtotal;
1578
1579 pixels_per_second = active_area * mode->clock * 1000;
1580 do_div(pixels_per_second, total_area);
1581
1582 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1583 do_div(bandwidth, divisor);
1584
1585 return (uint32_t)(bandwidth);
1586}
1587
1588#define MODE_BANDWIDTH MODE_BAD
1589
c69e52de 1590static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
414c4531
DA		 1591 struct drm_display_mode *mode)
1592{
0ba53171
CH		 1593 struct drm_device *dev = connector->dev;
1594 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
0ba53171 1595 int bpp = 32;
0ba53171 1596
abbee623
JL		 1597 if (IS_G200_SE(mdev)) {
1598 if (mdev->unique_rev_id == 0x01) {
1599 if (mode->hdisplay > 1600)
1600 return MODE_VIRTUAL_X;
1601 if (mode->vdisplay > 1200)
1602 return MODE_VIRTUAL_Y;
1603 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1604 > (24400 * 1024))
1605 return MODE_BANDWIDTH;
e829d7ef 1606 } else if (mdev->unique_rev_id == 0x02) {
abbee623
JL		 1607 if (mode->hdisplay > 1920)
1608 return MODE_VIRTUAL_X;
1609 if (mode->vdisplay > 1200)
1610 return MODE_VIRTUAL_Y;
1611 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1612 > (30100 * 1024))
1613 return MODE_BANDWIDTH;
0cbb7381
ML		 1614 } else {
1615 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1616 > (55000 * 1024))
1617 return MODE_BANDWIDTH;
abbee623
JL		 1618 }
1619 } else if (mdev->type == G200_WB) {
1620 if (mode->hdisplay > 1280)
1621 return MODE_VIRTUAL_X;
1622 if (mode->vdisplay > 1024)
1623 return MODE_VIRTUAL_Y;
9eb8d7a9
DC		 1624 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1625 (31877 * 1024))
abbee623
JL		 1626 return MODE_BANDWIDTH;
1627 } else if (mdev->type == G200_EV &&
1628 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1629 > (32700 * 1024))) {
1630 return MODE_BANDWIDTH;
ec22b4aa 1631 } else if (mdev->type == G200_EH &&
abbee623
JL		 1632 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1633 > (37500 * 1024))) {
1634 return MODE_BANDWIDTH;
ec22b4aa 1635 } else if (mdev->type == G200_ER &&
abbee623
JL		 1636 (mga_vga_calculate_mode_bandwidth(mode,
1637 bpp) > (55000 * 1024))) {
1638 return MODE_BANDWIDTH;
1639 }
414c4531 1640
25161084
AJ		 1641 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1642 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1643 return MODE_H_ILLEGAL;
1644 }
1645
414c4531
DA		 1646 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1647 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1648 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1649 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1650 return MODE_BAD;
1651 }
1652
0ba53171 1653 /* Validate the mode input by the user */
eaf99c74
CW		 1654 if (connector->cmdline_mode.specified) {
1655 if (connector->cmdline_mode.bpp_specified)
1656 bpp = connector->cmdline_mode.bpp;
0ba53171
CH		 1657 }
1658
1659 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
eaf99c74
CW		 1660 if (connector->cmdline_mode.specified)
1661 connector->cmdline_mode.specified = false;
0ba53171
CH		 1662 return MODE_BAD;
1663 }
1664
414c4531
DA		 1665 return MODE_OK;
1666}
1667
080fd6b5 1668static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
414c4531
DA		 1669 *connector)
1670{
1671 int enc_id = connector->encoder_ids[0];
414c4531 1672 /* pick the encoder ids */
c7e95114 1673 if (enc_id)
418da172 1674 return drm_encoder_find(connector->dev, NULL, enc_id);
414c4531
DA		 1675 return NULL;
1676}
1677
414c4531
DA		 1678static void mga_connector_destroy(struct drm_connector *connector)
1679{
1680 struct mga_connector *mga_connector = to_mga_connector(connector);
1681 mgag200_i2c_destroy(mga_connector->i2c);
1682 drm_connector_cleanup(connector);
1683 kfree(connector);
1684}
1685
71cb7495 1686static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
414c4531
DA		 1687 .get_modes = mga_vga_get_modes,
1688 .mode_valid = mga_vga_mode_valid,
1689 .best_encoder = mga_connector_best_encoder,
1690};
1691
71cb7495 1692static const struct drm_connector_funcs mga_vga_connector_funcs = {
414c4531 1693 .dpms = drm_helper_connector_dpms,
414c4531
DA		 1694 .fill_modes = drm_helper_probe_single_connector_modes,
1695 .destroy = mga_connector_destroy,
1696};
1697
1698static struct drm_connector *mga_vga_init(struct drm_device *dev)
1699{
1700 struct drm_connector *connector;
1701 struct mga_connector *mga_connector;
1702
1703 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1704 if (!mga_connector)
1705 return NULL;
1706
1707 connector = &mga_connector->base;
1708
1709 drm_connector_init(dev, connector,
1710 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1711
1712 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1713
34ea3d38 1714 drm_connector_register(connector);
3d5a1c5e 1715
414c4531
DA		 1716 mga_connector->i2c = mgag200_i2c_create(dev);
1717 if (!mga_connector->i2c)
1718 DRM_ERROR("failed to add ddc bus\n");
1719
1720 return connector;
1721}
1722
1723
1724int mgag200_modeset_init(struct mga_device *mdev)
1725{
1726 struct drm_encoder *encoder;
1727 struct drm_connector *connector;
1728 int ret;
1729
1730 mdev->mode_info.mode_config_initialized = true;
1731
1732 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1733 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1734
1735 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1736
f1998fe2 1737 mga_crtc_init(mdev);
414c4531
DA		 1738
1739 encoder = mga_encoder_init(mdev->dev);
1740 if (!encoder) {
1741 DRM_ERROR("mga_encoder_init failed\n");
1742 return -1;
1743 }
1744
1745 connector = mga_vga_init(mdev->dev);
1746 if (!connector) {
1747 DRM_ERROR("mga_vga_init failed\n");
1748 return -1;
1749 }
1750
cde4c44d 1751 drm_connector_attach_encoder(connector, encoder);
414c4531
DA		 1752
1753 ret = mgag200_fbdev_init(mdev);
1754 if (ret) {
1755 DRM_ERROR("mga_fbdev_init failed\n");
1756 return ret;
1757 }
1758
1759 return 0;
1760}
1761
1762void mgag200_modeset_fini(struct mga_device *mdev)
1763{
1764
1765}
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