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Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm...
[thirdparty/kernel/stable.git] / drivers / gpu / drm / msm / disp / mdp5 / mdp5_crtc.c
CommitLineData
06c0dd96 1/*
68cdbed9 2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
06c0dd96
RC		 3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
ed851963 19#include <linux/sort.h>
06c0dd96 20#include <drm/drm_mode.h>
78f27b1c 21#include <drm/drm_crtc.h>
78f27b1c 22#include <drm/drm_flip_work.h>
fcd70cd3 23#include <drm/drm_probe_helper.h>
78f27b1c
MY		 24
25#include "mdp5_kms.h"
06c0dd96 26
e172d10a
BG		 27#define CURSOR_WIDTH 64
28#define CURSOR_HEIGHT 64
29
06c0dd96
RC		 30struct mdp5_crtc {
31 struct drm_crtc base;
06c0dd96
RC		 32 int id;
33 bool enabled;
34
adfc0e63 35 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */
0deed25b 36
06c0dd96
RC		 37 /* if there is a pending flip, these will be non-null: */
38 struct drm_pending_vblank_event *event;
06c0dd96 39
0a5c9aad
HL		 40 /* Bits have been flushed at the last commit,
41 * used to decide if a vsync has happened since last commit.
42 */
43 u32 flushed_mask;
44
06c0dd96
RC		 45#define PENDING_CURSOR 0x1
46#define PENDING_FLIP 0x2
47 atomic_t pending;
48
e172d10a
BG		 49 /* for unref'ing cursor bo's after scanout completes: */
50 struct drm_flip_work unref_cursor_work;
51
06c0dd96
RC		 52 struct mdp_irq vblank;
53 struct mdp_irq err;
68cdbed9
HL		 54 struct mdp_irq pp_done;
55
56 struct completion pp_completion;
57
aa649e87
AT		 58 bool lm_cursor_enabled;
59
e172d10a
BG		 60 struct {
61 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
62 spinlock_t lock;
63
64 /* current cursor being scanned out: */
65 struct drm_gem_object *scanout_bo;
9d9ea7a9 66 uint64_t iova;
58560890 67 uint32_t width, height;
23f94551 68 int x, y;
e172d10a 69 } cursor;
06c0dd96
RC		 70};
71#define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
72
9d9ea7a9
RC		 73static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
74
06c0dd96
RC		 75static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
76{
77 struct msm_drm_private *priv = crtc->dev->dev_private;
78 return to_mdp5_kms(to_mdp_kms(priv->kms));
79}
80
81static void request_pending(struct drm_crtc *crtc, uint32_t pending)
82{
83 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
84
85 atomic_or(pending, &mdp5_crtc->pending);
86 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
87}
88
68cdbed9
HL		 89static void request_pp_done_pending(struct drm_crtc *crtc)
90{
91 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
92 reinit_completion(&mdp5_crtc->pp_completion);
93}
94
0a5c9aad 95static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
0deed25b 96{
0ddc3a63
AT		 97 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
98 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
f316b25a 99 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
f9cb8d8d
RC		 100 bool start = !mdp5_cstate->defer_start;
101
102 mdp5_cstate->defer_start = false;
0deed25b 103
cee26588 104 DBG("%s: flush=%08x", crtc->name, flush_mask);
f9cb8d8d
RC		 105
106 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
0deed25b
SV		 107}
108
109/*
110 * flush updates, to make sure hw is updated to new scanout fb,
111 * so that we can safely queue unref to current fb (ie. next
112 * vblank we know hw is done w/ previous scanout_fb).
113 */
0a5c9aad 114static u32 crtc_flush_all(struct drm_crtc *crtc)
06c0dd96 115{
0ddc3a63 116 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
b7621b2a 117 struct mdp5_hw_mixer *mixer, *r_mixer;
a8cecf33 118 struct drm_plane *plane;
0deed25b
SV		 119 uint32_t flush_mask = 0;
120
ba0312a6 121 /* this should not happen: */
0ddc3a63 122 if (WARN_ON(!mdp5_cstate->ctl))
0a5c9aad 123 return 0;
06c0dd96 124
93b02beb 125 drm_atomic_crtc_for_each_plane(plane, crtc) {
a055cf3a
RC		 126 if (!plane->state->visible)
127 continue;
0deed25b 128 flush_mask |= mdp5_plane_get_flush(plane);
06c0dd96 129 }
389b09a1 130
0ddc3a63 131 mixer = mdp5_cstate->pipeline.mixer;
adfc0e63 132 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
a8cecf33 133
b7621b2a
AT		 134 r_mixer = mdp5_cstate->pipeline.r_mixer;
135 if (r_mixer)
136 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
137
0a5c9aad 138 return crtc_flush(crtc, flush_mask);
06c0dd96
RC		 139}
140
06c0dd96
RC		 141/* if file!=NULL, this is preclose potential cancel-flip path */
142static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
143{
0ddc3a63 144 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
f316b25a 145 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
06c0dd96 146 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 147 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
06c0dd96
RC		 148 struct drm_device *dev = crtc->dev;
149 struct drm_pending_vblank_event *event;
a8cecf33 150 unsigned long flags;
06c0dd96
RC		 151
152 spin_lock_irqsave(&dev->event_lock, flags);
153 event = mdp5_crtc->event;
154 if (event) {
02efb359
SV		 155 mdp5_crtc->event = NULL;
156 DBG("%s: send event: %p", crtc->name, event);
157 drm_crtc_send_vblank_event(crtc, event);
06c0dd96
RC		 158 }
159 spin_unlock_irqrestore(&dev->event_lock, flags);
160
0ddc3a63 161 if (ctl && !crtc->state->enable) {
e5989ee1 162 /* set STAGE_UNUSED for all layers */
b7621b2a 163 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
0ddc3a63
AT		 164 /* XXX: What to do here? */
165 /* mdp5_crtc->ctl = NULL; */
ba0312a6 166 }
06c0dd96
RC		 167}
168
e172d10a
BG		 169static void unref_cursor_worker(struct drm_flip_work *work, void *val)
170{
171 struct mdp5_crtc *mdp5_crtc =
172 container_of(work, struct mdp5_crtc, unref_cursor_work);
173 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
f59f62d5 174 struct msm_kms *kms = &mdp5_kms->base.base;
e172d10a 175
7ad0e8cf 176 msm_gem_unpin_iova(val, kms->aspace);
dc9a9b32 177 drm_gem_object_put_unlocked(val);
e172d10a
BG		 178}
179
06c0dd96
RC		 180static void mdp5_crtc_destroy(struct drm_crtc *crtc)
181{
182 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
183
06c0dd96 184 drm_crtc_cleanup(crtc);
e172d10a 185 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
06c0dd96
RC		 186
187 kfree(mdp5_crtc);
188}
189
829200ac
AT		 190static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
191{
192 switch (stage) {
193 case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
194 case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
195 case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
196 case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
197 case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
198 case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
199 case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
200 default:
201 return 0;
202 }
203}
204
b7621b2a
AT		 205/*
206 * left/right pipe offsets for the stage array used in blend_setup()
207 */
208#define PIPE_LEFT 0
209#define PIPE_RIGHT 1
210
0deed25b
SV		 211/*
212 * blend_setup() - blend all the planes of a CRTC
213 *
12987781
JW		 214 * If no base layer is available, border will be enabled as the base layer.
215 * Otherwise all layers will be blended based on their stage calculated
216 * in mdp5_crtc_atomic_check.
0deed25b 217 */
06c0dd96
RC		 218static void blend_setup(struct drm_crtc *crtc)
219{
220 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 221 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
f316b25a 222 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
06c0dd96 223 struct mdp5_kms *mdp5_kms = get_kms(crtc);
0deed25b
SV		 224 struct drm_plane *plane;
225 const struct mdp5_cfg_hw *hw_cfg;
12987781
JW		 226 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
227 const struct mdp_format *format;
f316b25a 228 struct mdp5_hw_mixer *mixer = pipeline->mixer;
adfc0e63 229 uint32_t lm = mixer->lm;
b7621b2a
AT		 230 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
231 uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
0ddc3a63 232 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
12987781 233 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
0deed25b 234 unsigned long flags;
d490c9cd
VK		 235 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
236 enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
12987781 237 int i, plane_cnt = 0;
829200ac
AT		 238 bool bg_alpha_enabled = false;
239 u32 mixer_op_mode = 0;
ed78560d 240 u32 val;
12987781 241#define blender(stage) ((stage) - STAGE0)
06c0dd96 242
42238da8 243 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
06c0dd96 244
0deed25b
SV		 245 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
246
247 /* ctl could be released already when we are shutting down: */
0ddc3a63
AT		 248 /* XXX: Can this happen now? */
249 if (!ctl)
0deed25b
SV		 250 goto out;
251
12987781 252 /* Collect all plane information */
93b02beb 253 drm_atomic_crtc_for_each_plane(plane, crtc) {
bf8dc0a0
AT		 254 enum mdp5_pipe right_pipe;
255
a055cf3a
RC		 256 if (!plane->state->visible)
257 continue;
258
12987781
JW		 259 pstate = to_mdp5_plane_state(plane->state);
260 pstates[pstate->stage] = pstate;
b7621b2a
AT		 261 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
262 /*
263 * if we have a right mixer, stage the same pipe as we
264 * have on the left mixer
265 */
266 if (r_mixer)
267 r_stage[pstate->stage][PIPE_LEFT] =
268 mdp5_plane_pipe(plane);
bf8dc0a0
AT		 269 /*
270 * if we have a right pipe (i.e, the plane comprises of 2
271 * hwpipes, then stage the right pipe on the right side of both
272 * the layer mixers
273 */
274 right_pipe = mdp5_plane_right_pipe(plane);
275 if (right_pipe) {
276 stage[pstate->stage][PIPE_RIGHT] = right_pipe;
277 r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
278 }
b7621b2a 279
12987781
JW		 280 plane_cnt++;
281 }
06c0dd96 282
1455adbd 283 if (!pstates[STAGE_BASE]) {
12987781
JW		 284 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
285 DBG("Border Color is enabled");
829200ac
AT		 286 } else if (plane_cnt) {
287 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
288
289 if (format->alpha_enable)
290 bg_alpha_enabled = true;
12987781
JW		 291 }
292
293 /* The reset for blending */
294 for (i = STAGE0; i <= STAGE_MAX; i++) {
295 if (!pstates[i])
296 continue;
297
298 format = to_mdp_format(
299 msm_framebuffer_format(pstates[i]->base.fb));
300 plane = pstates[i]->base.plane;
301 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
302 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
303 fg_alpha = pstates[i]->alpha;
304 bg_alpha = 0xFF - pstates[i]->alpha;
829200ac
AT		 305
306 if (!format->alpha_enable && bg_alpha_enabled)
307 mixer_op_mode = 0;
308 else
309 mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
310
12987781
JW		 311 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
312
313 if (format->alpha_enable && pstates[i]->premultiplied) {
314 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
315 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
316 if (fg_alpha != 0xff) {
317 bg_alpha = fg_alpha;
318 blend_op |=
319 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
320 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
321 } else {
322 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
323 }
324 } else if (format->alpha_enable) {
325 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
326 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
327 if (fg_alpha != 0xff) {
328 bg_alpha = fg_alpha;
329 blend_op |=
330 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
331 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
332 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
333 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
334 } else {
335 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
336 }
337 }
0deed25b 338
12987781
JW		 339 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
340 blender(i)), blend_op);
0deed25b 341 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
12987781 342 blender(i)), fg_alpha);
0deed25b 343 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
12987781 344 blender(i)), bg_alpha);
b7621b2a
AT		 345 if (r_mixer) {
346 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
347 blender(i)), blend_op);
348 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
349 blender(i)), fg_alpha);
350 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
351 blender(i)), bg_alpha);
352 }
0deed25b
SV		 353 }
354
ed78560d
AT		 355 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
356 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
357 val | mixer_op_mode);
358 if (r_mixer) {
359 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
b7621b2a 360 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
ed78560d
AT		 361 val | mixer_op_mode);
362 }
829200ac 363
b7621b2a
AT		 364 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
365 ctl_blend_flags);
0deed25b
SV		 366out:
367 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
06c0dd96
RC		 368}
369
ed851963 370static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
06c0dd96
RC		 371{
372 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 373 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
06c0dd96 374 struct mdp5_kms *mdp5_kms = get_kms(crtc);
0ddc3a63 375 struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
b7621b2a 376 struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
adfc0e63 377 uint32_t lm = mixer->lm;
ed78560d 378 u32 mixer_width, val;
0deed25b 379 unsigned long flags;
ed851963
RC		 380 struct drm_display_mode *mode;
381
382 if (WARN_ON(!crtc->state))
383 return;
06c0dd96 384
ed851963 385 mode = &crtc->state->adjusted_mode;
06c0dd96 386
7510a9c6 387 DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode));
06c0dd96 388
ed78560d
AT		 389 mixer_width = mode->hdisplay;
390 if (r_mixer)
391 mixer_width /= 2;
392
0deed25b 393 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
adfc0e63 394 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
ed78560d 395 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
06c0dd96 396 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
ed78560d
AT		 397
398 /* Assign mixer to LEFT side in source split mode */
399 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
400 val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
401 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
402
403 if (r_mixer) {
404 u32 r_lm = r_mixer->lm;
405
406 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
407 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
b7621b2a 408 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
ed78560d
AT		 409
410 /* Assign mixer to RIGHT side in source split mode */
411 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
412 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
413 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
414 }
415
0deed25b 416 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
06c0dd96
RC		 417}
418
64581714
LP		 419static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
420 struct drm_crtc_state *old_state)
06c0dd96
RC		 421{
422 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 423 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
0b776d45 424 struct mdp5_kms *mdp5_kms = get_kms(crtc);
d68fe15b 425 struct device *dev = &mdp5_kms->pdev->dev;
e765ea77 426 unsigned long flags;
0b776d45 427
cee26588 428 DBG("%s", crtc->name);
0b776d45
RC		 429
430 if (WARN_ON(!mdp5_crtc->enabled))
431 return;
432
0033e1b5
RC		 433 /* Disable/save vblank irq handling before power is disabled */
434 drm_crtc_vblank_off(crtc);
435
0ddc3a63 436 if (mdp5_cstate->cmd_mode)
68cdbed9
HL		 437 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
438
0b776d45 439 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
3c352b66 440 pm_runtime_put_sync(dev);
0b776d45 441
e765ea77
SP		 442 if (crtc->state->event && !crtc->state->active) {
443 WARN_ON(mdp5_crtc->event);
444 spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
445 drm_crtc_send_vblank_event(crtc, crtc->state->event);
446 crtc->state->event = NULL;
447 spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
448 }
449
0b776d45 450 mdp5_crtc->enabled = false;
06c0dd96
RC		 451}
452
0b20a0f8
LP		 453static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
454 struct drm_crtc_state *old_state)
06c0dd96 455{
ed851963 456 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 457 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
0b776d45 458 struct mdp5_kms *mdp5_kms = get_kms(crtc);
d68fe15b 459 struct device *dev = &mdp5_kms->pdev->dev;
0b776d45 460
cee26588 461 DBG("%s", crtc->name);
0b776d45
RC		 462
463 if (WARN_ON(mdp5_crtc->enabled))
464 return;
465
d68fe15b 466 pm_runtime_get_sync(dev);
710e7a44 467
aa649e87
AT		 468 if (mdp5_crtc->lm_cursor_enabled) {
469 /*
470 * Restore LM cursor state, as it might have been lost
471 * with suspend:
472 */
473 if (mdp5_crtc->cursor.iova) {
474 unsigned long flags;
475
476 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
477 mdp5_crtc_restore_cursor(crtc);
478 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
479
480 mdp5_ctl_set_cursor(mdp5_cstate->ctl,
481 &mdp5_cstate->pipeline, 0, true);
482 } else {
483 mdp5_ctl_set_cursor(mdp5_cstate->ctl,
484 &mdp5_cstate->pipeline, 0, false);
485 }
9d9ea7a9
RC		 486 }
487
0033e1b5
RC		 488 /* Restore vblank irq handling after power is enabled */
489 drm_crtc_vblank_on(crtc);
490
710e7a44
AT		 491 mdp5_crtc_mode_set_nofb(crtc);
492
0b776d45
RC		 493 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
494
0ddc3a63 495 if (mdp5_cstate->cmd_mode)
68cdbed9
HL		 496 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
497
0b776d45 498 mdp5_crtc->enabled = true;
06c0dd96
RC		 499}
500
894558ec 501int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
8480adac
AT		 502 struct drm_crtc_state *new_crtc_state,
503 bool need_right_mixer)
894558ec
AT		 504{
505 struct mdp5_crtc_state *mdp5_cstate =
506 to_mdp5_crtc_state(new_crtc_state);
507 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
bcb877b7 508 struct mdp5_interface *intf;
894558ec
AT		 509 bool new_mixer = false;
510
511 new_mixer = !pipeline->mixer;
512
8480adac
AT		 513 if ((need_right_mixer && !pipeline->r_mixer) ||
514 (!need_right_mixer && pipeline->r_mixer))
515 new_mixer = true;
516
894558ec
AT		 517 if (new_mixer) {
518 struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
8480adac
AT		 519 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
520 u32 caps;
521 int ret;
522
523 caps = MDP_LM_CAP_DISPLAY;
524 if (need_right_mixer)
525 caps |= MDP_LM_CAP_PAIR;
894558ec 526
8480adac
AT		 527 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
528 &pipeline->mixer, need_right_mixer ?
529 &pipeline->r_mixer : NULL);
530 if (ret)
531 return ret;
894558ec
AT		 532
533 mdp5_mixer_release(new_crtc_state->state, old_mixer);
8480adac
AT		 534 if (old_r_mixer) {
535 mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
536 if (!need_right_mixer)
537 pipeline->r_mixer = NULL;
538 }
894558ec
AT		 539 }
540
bcb877b7
AT		 541 /*
542 * these should have been already set up in the encoder's atomic
543 * check (called by drm_atomic_helper_check_modeset)
544 */
545 intf = pipeline->intf;
546
547 mdp5_cstate->err_irqmask = intf2err(intf->num);
548 mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
549
550 if ((intf->type == INTF_DSI) &&
551 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
552 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
553 mdp5_cstate->cmd_mode = true;
554 } else {
555 mdp5_cstate->pp_done_irqmask = 0;
556 mdp5_cstate->cmd_mode = false;
557 }
558
894558ec
AT		 559 return 0;
560}
561
ed851963
RC		 562struct plane_state {
563 struct drm_plane *plane;
564 struct mdp5_plane_state *state;
565};
566
567static int pstate_cmp(const void *a, const void *b)
06c0dd96 568{
ed851963
RC		 569 struct plane_state *pa = (struct plane_state *)a;
570 struct plane_state *pb = (struct plane_state *)b;
571 return pa->state->zpos - pb->state->zpos;
06c0dd96
RC		 572}
573
1455adbd
RC		 574/* is there a helper for this? */
575static bool is_fullscreen(struct drm_crtc_state *cstate,
576 struct drm_plane_state *pstate)
577{
578 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
579 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
580 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
581}
582
5c3ddb85 583static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
359ae862
AT		 584 struct drm_crtc_state *new_crtc_state,
585 struct drm_plane_state *bpstate)
586{
587 struct mdp5_crtc_state *mdp5_cstate =
588 to_mdp5_crtc_state(new_crtc_state);
589
590 /*
591 * if we're in source split mode, it's mandatory to have
592 * border out on the base stage
593 */
594 if (mdp5_cstate->pipeline.r_mixer)
595 return STAGE0;
596
597 /* if the bottom-most layer is not fullscreen, we need to use
598 * it for solid-color:
599 */
600 if (!is_fullscreen(new_crtc_state, bpstate))
601 return STAGE0;
602
603 return STAGE_BASE;
604}
605
ed851963
RC		 606static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
607 struct drm_crtc_state *state)
0deed25b 608{
ed851963
RC		 609 struct mdp5_kms *mdp5_kms = get_kms(crtc);
610 struct drm_plane *plane;
611 struct drm_device *dev = crtc->dev;
12987781
JW		 612 struct plane_state pstates[STAGE_MAX + 1];
613 const struct mdp5_cfg_hw *hw_cfg;
2f196b7c 614 const struct drm_plane_state *pstate;
8480adac 615 const struct drm_display_mode *mode = &state->adjusted_mode;
5798c8e0 616 bool cursor_plane = false;
8480adac 617 bool need_right_mixer = false;
359ae862 618 int cnt = 0, i;
894558ec 619 int ret;
359ae862 620 enum mdp_mixer_stage_id start;
0deed25b 621
cee26588 622 DBG("%s: check", crtc->name);
0deed25b 623
2f196b7c 624 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
a055cf3a
RC		 625 if (!pstate->visible)
626 continue;
627
ed851963
RC		 628 pstates[cnt].plane = plane;
629 pstates[cnt].state = to_mdp5_plane_state(pstate);
630
8480adac
AT		 631 /*
632 * if any plane on this crtc uses 2 hwpipes, then we need
633 * the crtc to have a right hwmixer.
634 */
635 if (pstates[cnt].state->r_hwpipe)
636 need_right_mixer = true;
ed851963 637 cnt++;
5798c8e0
AT		 638
639 if (plane->type == DRM_PLANE_TYPE_CURSOR)
640 cursor_plane = true;
ed851963
RC		 641 }
642
359ae862
AT		 643 /* bail out early if there aren't any planes */
644 if (!cnt)
645 return 0;
646
8480adac
AT		 647 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
648
649 /*
650 * we need a right hwmixer if the mode's width is greater than a single
651 * LM's max width
652 */
653 if (mode->hdisplay > hw_cfg->lm.max_width)
654 need_right_mixer = true;
655
656 ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer);
894558ec 657 if (ret) {
6a41da17 658 DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret);
894558ec
AT		 659 return ret;
660 }
661
12987781 662 /* assign a stage based on sorted zpos property */
ed851963
RC		 663 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
664
5798c8e0
AT		 665 /* trigger a warning if cursor isn't the highest zorder */
666 WARN_ON(cursor_plane &&
667 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
668
359ae862
AT		 669 start = get_start_stage(crtc, state, &pstates[0].state->base);
670
1455adbd
RC		 671 /* verify that there are not too many planes attached to crtc
672 * and that we don't have conflicting mixer stages:
673 */
359ae862 674 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
6a41da17 675 DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
359ae862 676 cnt, start);
1455adbd
RC		 677 return -EINVAL;
678 }
679
ed851963 680 for (i = 0; i < cnt; i++) {
5798c8e0
AT		 681 if (cursor_plane && (i == (cnt - 1)))
682 pstates[i].state->stage = hw_cfg->lm.nb_stages;
683 else
359ae862 684 pstates[i].state->stage = start + i;
cee26588 685 DBG("%s: assign pipe %s on stage=%d", crtc->name,
4a0f012d 686 pstates[i].plane->name,
ed851963
RC		 687 pstates[i].state->stage);
688 }
689
690 return 0;
0deed25b
SV		 691}
692
613d2b27
ML		 693static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
694 struct drm_crtc_state *old_crtc_state)
ed851963 695{
cee26588 696 DBG("%s: begin", crtc->name);
ed851963 697}
0deed25b 698
613d2b27
ML		 699static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
700 struct drm_crtc_state *old_crtc_state)
06c0dd96
RC		 701{
702 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 703 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
06c0dd96 704 struct drm_device *dev = crtc->dev;
06c0dd96
RC		 705 unsigned long flags;
706
cee26588 707 DBG("%s: event: %p", crtc->name, crtc->state->event);
06c0dd96 708
ed851963 709 WARN_ON(mdp5_crtc->event);
06c0dd96
RC		 710
711 spin_lock_irqsave(&dev->event_lock, flags);
ed851963 712 mdp5_crtc->event = crtc->state->event;
78b32d49 713 crtc->state->event = NULL;
06c0dd96
RC		 714 spin_unlock_irqrestore(&dev->event_lock, flags);
715
ba0312a6
SV		 716 /*
717 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
718 * it means we are trying to flush a CRTC whose state is disabled:
719 * nothing else needs to be done.
720 */
0ddc3a63
AT		 721 /* XXX: Can this happen now ? */
722 if (unlikely(!mdp5_cstate->ctl))
ba0312a6
SV		 723 return;
724
ed851963 725 blend_setup(crtc);
0a5c9aad 726
68cdbed9
HL		 727 /* PP_DONE irq is only used by command mode for now.
728 * It is better to request pending before FLUSH and START trigger
729 * to make sure no pp_done irq missed.
730 * This is safe because no pp_done will happen before SW trigger
731 * in command mode.
732 */
0ddc3a63 733 if (mdp5_cstate->cmd_mode)
68cdbed9
HL		 734 request_pp_done_pending(crtc);
735
0a5c9aad
HL		 736 mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
737
0ddc3a63
AT		 738 /* XXX are we leaking out state here? */
739 mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
740 mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
741 mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
742
ed851963 743 request_pending(crtc, PENDING_FLIP);
06c0dd96
RC		 744}
745
58560890
RC		 746static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
747{
748 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
749 uint32_t xres = crtc->mode.hdisplay;
750 uint32_t yres = crtc->mode.vdisplay;
751
752 /*
753 * Cursor Region Of Interest (ROI) is a plane read from cursor
754 * buffer to render. The ROI region is determined by the visibility of
755 * the cursor point. In the default Cursor image the cursor point will
23f94551 756 * be at the top left of the cursor image.
58560890 757 *
23f94551 758 * Without rotation:
58560890
RC		 759 * If the cursor point reaches the right (xres - x < cursor.width) or
760 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
761 * width and ROI height need to be evaluated to crop the cursor image
762 * accordingly.
763 * (xres-x) will be new cursor width when x > (xres - cursor.width)
764 * (yres-y) will be new cursor height when y > (yres - cursor.height)
23f94551
CB		 765 *
766 * With rotation:
767 * We get negative x and/or y coordinates.
768 * (cursor.width - abs(x)) will be new cursor width when x < 0
769 * (cursor.height - abs(y)) will be new cursor width when y < 0
58560890 770 */
23f94551
CB		 771 if (mdp5_crtc->cursor.x >= 0)
772 *roi_w = min(mdp5_crtc->cursor.width, xres -
58560890 773 mdp5_crtc->cursor.x);
23f94551
CB		 774 else
775 *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
776 if (mdp5_crtc->cursor.y >= 0)
777 *roi_h = min(mdp5_crtc->cursor.height, yres -
58560890 778 mdp5_crtc->cursor.y);
23f94551
CB		 779 else
780 *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
58560890
RC		 781}
782
9d9ea7a9
RC		 783static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
784{
785 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
786 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
787 struct mdp5_kms *mdp5_kms = get_kms(crtc);
788 const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
789 uint32_t blendcfg, stride;
23f94551 790 uint32_t x, y, src_x, src_y, width, height;
9d9ea7a9
RC		 791 uint32_t roi_w, roi_h;
792 int lm;
793
794 assert_spin_locked(&mdp5_crtc->cursor.lock);
795
796 lm = mdp5_cstate->pipeline.mixer->lm;
797
798 x = mdp5_crtc->cursor.x;
799 y = mdp5_crtc->cursor.y;
800 width = mdp5_crtc->cursor.width;
801 height = mdp5_crtc->cursor.height;
802
803 stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
804
805 get_roi(crtc, &roi_w, &roi_h);
806
23f94551
CB		 807 /* If cusror buffer overlaps due to rotation on the
808 * upper or left screen border the pixel offset inside
809 * the cursor buffer of the ROI is the positive overlap
810 * distance.
811 */
812 if (mdp5_crtc->cursor.x < 0) {
813 src_x = abs(mdp5_crtc->cursor.x);
814 x = 0;
815 } else {
816 src_x = 0;
817 }
818 if (mdp5_crtc->cursor.y < 0) {
819 src_y = abs(mdp5_crtc->cursor.y);
820 y = 0;
821 } else {
822 src_y = 0;
823 }
824 DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
825 crtc->name, x, y, roi_w, roi_h, src_x, src_y);
826
9d9ea7a9
RC		 827 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
828 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
829 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
830 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
831 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
832 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
833 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
834 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
835 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
836 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
837 MDP5_LM_CURSOR_START_XY_Y_START(y) |
838 MDP5_LM_CURSOR_START_XY_X_START(x));
23f94551
CB		 839 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
840 MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
841 MDP5_LM_CURSOR_XY_SRC_X(src_x));
9d9ea7a9
RC		 842 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
843 mdp5_crtc->cursor.iova);
844
845 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
846 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
847 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
848}
849
e172d10a
BG		 850static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
851 struct drm_file *file, uint32_t handle,
852 uint32_t width, uint32_t height)
853{
854 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 855 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
f316b25a 856 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
e172d10a
BG		 857 struct drm_device *dev = crtc->dev;
858 struct mdp5_kms *mdp5_kms = get_kms(crtc);
d68fe15b 859 struct platform_device *pdev = mdp5_kms->pdev;
f59f62d5 860 struct msm_kms *kms = &mdp5_kms->base.base;
389b09a1 861 struct drm_gem_object *cursor_bo, *old_bo = NULL;
0ddc3a63 862 struct mdp5_ctl *ctl;
9d9ea7a9 863 int ret;
e172d10a 864 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
389b09a1 865 bool cursor_enable = true;
e172d10a
BG		 866 unsigned long flags;
867
aa649e87
AT		 868 if (!mdp5_crtc->lm_cursor_enabled) {
869 dev_warn(dev->dev,
870 "cursor_set is deprecated with cursor planes\n");
871 return -EINVAL;
872 }
873
e172d10a 874 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
6a41da17 875 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
e172d10a
BG		 876 return -EINVAL;
877 }
878
0ddc3a63
AT		 879 ctl = mdp5_cstate->ctl;
880 if (!ctl)
e172d10a
BG		 881 return -EINVAL;
882
b7621b2a
AT		 883 /* don't support LM cursors when we we have source split enabled */
884 if (mdp5_cstate->pipeline.r_mixer)
885 return -EINVAL;
886
e172d10a
BG		 887 if (!handle) {
888 DBG("Cursor off");
389b09a1 889 cursor_enable = false;
9d9ea7a9 890 mdp5_crtc->cursor.iova = 0;
d68fe15b 891 pm_runtime_get_sync(&pdev->dev);
389b09a1 892 goto set_cursor;
e172d10a
BG		 893 }
894
a8ad0bd8 895 cursor_bo = drm_gem_object_lookup(file, handle);
e172d10a
BG		 896 if (!cursor_bo)
897 return -ENOENT;
898
9fe041f6 899 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace,
9d9ea7a9 900 &mdp5_crtc->cursor.iova);
e172d10a
BG		 901 if (ret)
902 return -EINVAL;
903
d68fe15b
AT		 904 pm_runtime_get_sync(&pdev->dev);
905
e172d10a
BG		 906 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
907 old_bo = mdp5_crtc->cursor.scanout_bo;
908
58560890
RC		 909 mdp5_crtc->cursor.scanout_bo = cursor_bo;
910 mdp5_crtc->cursor.width = width;
911 mdp5_crtc->cursor.height = height;
912
9d9ea7a9 913 mdp5_crtc_restore_cursor(crtc);
e172d10a 914
e172d10a
BG		 915 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
916
389b09a1 917set_cursor:
f316b25a 918 ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
389b09a1 919 if (ret) {
6a41da17 920 DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n",
389b09a1 921 cursor_enable ? "en" : "dis", ret);
e172d10a 922 goto end;
389b09a1 923 }
e172d10a 924
e172d10a
BG		 925 crtc_flush(crtc, flush_mask);
926
927end:
3c352b66 928 pm_runtime_put_sync(&pdev->dev);
e172d10a
BG		 929 if (old_bo) {
930 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
931 /* enable vblank to complete cursor work: */
932 request_pending(crtc, PENDING_CURSOR);
933 }
934 return ret;
935}
936
937static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
938{
939 struct mdp5_kms *mdp5_kms = get_kms(crtc);
940 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 941 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
e172d10a 942 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
aa649e87 943 struct drm_device *dev = crtc->dev;
e172d10a
BG		 944 uint32_t roi_w;
945 uint32_t roi_h;
946 unsigned long flags;
947
aa649e87
AT		 948 if (!mdp5_crtc->lm_cursor_enabled) {
949 dev_warn(dev->dev,
950 "cursor_move is deprecated with cursor planes\n");
951 return -EINVAL;
952 }
953
b7621b2a
AT		 954 /* don't support LM cursors when we we have source split enabled */
955 if (mdp5_cstate->pipeline.r_mixer)
956 return -EINVAL;
957
ba0312a6
SV		 958 /* In case the CRTC is disabled, just drop the cursor update */
959 if (unlikely(!crtc->state->enable))
960 return 0;
961
23f94551
CB		 962 /* accept negative x/y coordinates up to maximum cursor overlap */
963 mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
964 mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
e172d10a 965
58560890 966 get_roi(crtc, &roi_w, &roi_h);
e172d10a 967
d68fe15b 968 pm_runtime_get_sync(&mdp5_kms->pdev->dev);
af1f5f12 969
e172d10a 970 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
9d9ea7a9 971 mdp5_crtc_restore_cursor(crtc);
e172d10a
BG		 972 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
973
974 crtc_flush(crtc, flush_mask);
975
3c352b66 976 pm_runtime_put_sync(&mdp5_kms->pdev->dev);
af1f5f12 977
e172d10a
BG		 978 return 0;
979}
980
c1e2a130
AT		 981static void
982mdp5_crtc_atomic_print_state(struct drm_printer *p,
983 const struct drm_crtc_state *state)
984{
985 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
986 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
b7621b2a 987 struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
c1e2a130
AT		 988
989 if (WARN_ON(!pipeline))
990 return;
991
1af81790
RC		 992 if (mdp5_cstate->ctl)
993 drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
994
c1e2a130
AT		 995 drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
996 pipeline->mixer->name : "(null)");
b7621b2a
AT		 997
998 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
999 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1000 pipeline->r_mixer->name : "(null)");
1af81790
RC		 1001
1002 drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
c1e2a130
AT		 1003}
1004
1005static void mdp5_crtc_reset(struct drm_crtc *crtc)
1006{
1007 struct mdp5_crtc_state *mdp5_cstate;
1008
1009 if (crtc->state) {
1010 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1011 kfree(to_mdp5_crtc_state(crtc->state));
1012 }
1013
1014 mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1015
1016 if (mdp5_cstate) {
1017 mdp5_cstate->base.crtc = crtc;
1018 crtc->state = &mdp5_cstate->base;
1019 }
1020}
1021
1022static struct drm_crtc_state *
1023mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1024{
1025 struct mdp5_crtc_state *mdp5_cstate;
1026
1027 if (WARN_ON(!crtc->state))
1028 return NULL;
1029
1030 mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1031 sizeof(*mdp5_cstate), GFP_KERNEL);
1032 if (!mdp5_cstate)
1033 return NULL;
1034
1035 __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1036
1037 return &mdp5_cstate->base;
1038}
1039
1040static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1041{
1042 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1043
1044 __drm_atomic_helper_crtc_destroy_state(state);
1045
1046 kfree(mdp5_cstate);
1047}
1048
06c0dd96 1049static const struct drm_crtc_funcs mdp5_crtc_funcs = {
ed851963 1050 .set_config = drm_atomic_helper_set_config,
06c0dd96 1051 .destroy = mdp5_crtc_destroy,
ed851963 1052 .page_flip = drm_atomic_helper_page_flip,
c1e2a130
AT		 1053 .reset = mdp5_crtc_reset,
1054 .atomic_duplicate_state = mdp5_crtc_duplicate_state,
1055 .atomic_destroy_state = mdp5_crtc_destroy_state,
e172d10a
BG		 1056 .cursor_set = mdp5_crtc_cursor_set,
1057 .cursor_move = mdp5_crtc_cursor_move,
c1e2a130 1058 .atomic_print_state = mdp5_crtc_atomic_print_state,
06c0dd96
RC		 1059};
1060
1061static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
ed851963 1062 .mode_set_nofb = mdp5_crtc_mode_set_nofb,
ed851963
RC		 1063 .atomic_check = mdp5_crtc_atomic_check,
1064 .atomic_begin = mdp5_crtc_atomic_begin,
1065 .atomic_flush = mdp5_crtc_atomic_flush,
0b20a0f8 1066 .atomic_enable = mdp5_crtc_atomic_enable,
64581714 1067 .atomic_disable = mdp5_crtc_atomic_disable,
06c0dd96
RC		 1068};
1069
1070static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1071{
1072 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1073 struct drm_crtc *crtc = &mdp5_crtc->base;
e172d10a 1074 struct msm_drm_private *priv = crtc->dev->dev_private;
06c0dd96
RC		 1075 unsigned pending;
1076
1077 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1078
1079 pending = atomic_xchg(&mdp5_crtc->pending, 0);
1080
1081 if (pending & PENDING_FLIP) {
1082 complete_flip(crtc, NULL);
06c0dd96 1083 }
e172d10a
BG		 1084
1085 if (pending & PENDING_CURSOR)
1086 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
06c0dd96
RC		 1087}
1088
1089static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1090{
1091 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
0deed25b 1092
cee26588 1093 DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
06c0dd96
RC		 1094}
1095
68cdbed9
HL		 1096static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1097{
1098 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1099 pp_done);
1100
1101 complete(&mdp5_crtc->pp_completion);
1102}
1103
1104static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1105{
1106 struct drm_device *dev = crtc->dev;
1107 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63 1108 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
68cdbed9
HL		 1109 int ret;
1110
1111 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1112 msecs_to_jiffies(50));
1113 if (ret == 0)
adfc0e63 1114 dev_warn(dev->dev, "pp done time out, lm=%d\n",
0ddc3a63 1115 mdp5_cstate->pipeline.mixer->lm);
68cdbed9
HL		 1116}
1117
0a5c9aad
HL		 1118static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1119{
1120 struct drm_device *dev = crtc->dev;
1121 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
0ddc3a63
AT		 1122 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1123 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
0a5c9aad
HL		 1124 int ret;
1125
1126 /* Should not call this function if crtc is disabled. */
0ddc3a63 1127 if (!ctl)
0a5c9aad
HL		 1128 return;
1129
1130 ret = drm_crtc_vblank_get(crtc);
1131 if (ret)
1132 return;
1133
1134 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
0ddc3a63 1135 ((mdp5_ctl_get_commit_status(ctl) &
0a5c9aad
HL		 1136 mdp5_crtc->flushed_mask) == 0),
1137 msecs_to_jiffies(50));
1138 if (ret <= 0)
1139 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1140
1141 mdp5_crtc->flushed_mask = 0;
1142
1143 drm_crtc_vblank_put(crtc);
1144}
1145
06c0dd96
RC		 1146uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1147{
1148 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1149 return mdp5_crtc->vblank.irqmask;
1150}
1151
f316b25a 1152void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
06c0dd96 1153{
0ddc3a63 1154 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
06c0dd96 1155 struct mdp5_kms *mdp5_kms = get_kms(crtc);
0a5c9aad 1156
0ddc3a63 1157 /* should this be done elsewhere ? */
8bc1fe92 1158 mdp_irq_update(&mdp5_kms->base);
06c0dd96 1159
f316b25a 1160 mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
0deed25b 1161}
06c0dd96 1162
10967a06
AT		 1163struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1164{
0ddc3a63 1165 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
10967a06 1166
0ddc3a63 1167 return mdp5_cstate->ctl;
10967a06
AT		 1168}
1169
adfc0e63 1170struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
0deed25b 1171{
0ddc3a63
AT		 1172 struct mdp5_crtc_state *mdp5_cstate;
1173
1174 if (WARN_ON(!crtc))
1175 return ERR_PTR(-EINVAL);
1176
1177 mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1178
1179 return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1180 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
389b09a1 1181}
0deed25b 1182
f316b25a
AT		 1183struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1184{
1185 struct mdp5_crtc_state *mdp5_cstate;
1186
1187 if (WARN_ON(!crtc))
1188 return ERR_PTR(-EINVAL);
1189
1190 mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1191
1192 return &mdp5_cstate->pipeline;
1193}
1194
0a5c9aad
HL		 1195void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1196{
0ddc3a63 1197 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
68cdbed9 1198
0ddc3a63 1199 if (mdp5_cstate->cmd_mode)
68cdbed9
HL		 1200 mdp5_crtc_wait_for_pp_done(crtc);
1201 else
1202 mdp5_crtc_wait_for_flush_done(crtc);
0a5c9aad
HL		 1203}
1204
06c0dd96
RC		 1205/* initialize crtc */
1206struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
5798c8e0
AT		 1207 struct drm_plane *plane,
1208 struct drm_plane *cursor_plane, int id)
06c0dd96
RC		 1209{
1210 struct drm_crtc *crtc = NULL;
1211 struct mdp5_crtc *mdp5_crtc;
06c0dd96
RC		 1212
1213 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
d7f8db53
BB		 1214 if (!mdp5_crtc)
1215 return ERR_PTR(-ENOMEM);
06c0dd96
RC		 1216
1217 crtc = &mdp5_crtc->base;
1218
06c0dd96 1219 mdp5_crtc->id = id;
0deed25b
SV		 1220
1221 spin_lock_init(&mdp5_crtc->lm_lock);
e172d10a 1222 spin_lock_init(&mdp5_crtc->cursor.lock);
68cdbed9 1223 init_completion(&mdp5_crtc->pp_completion);
06c0dd96
RC		 1224
1225 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1226 mdp5_crtc->err.irq = mdp5_crtc_err_irq;
0ddc3a63 1227 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
06c0dd96 1228
aa649e87
AT		 1229 mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1230
1231 drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1232 &mdp5_crtc_funcs, NULL);
e172d10a
BG		 1233
1234 drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1235 "unref cursor", unref_cursor_worker);
1236
06c0dd96
RC		 1237 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1238
06c0dd96 1239 return crtc;
06c0dd96 1240}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git