[thirdparty/linux.git] / drivers / gpu / drm / msm / hdmi / hdmi_phy_8x60.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 */

#include "hdmi.h"

static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
		unsigned long int pixclock)
{
	/* De-serializer delay D/C for non-lbk mode: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
		       HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));

	if (pixclock == 27000000) {
		/* video_format == HDMI_VFRMT_720x480p60_16_9 */
		hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
			       HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
			       HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
	} else {
		hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
			       HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
			       HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
	}

	/* No matter what, start from the power down mode: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_PD_PWRGEN |
		       HDMI_8x60_PHY_REG2_PD_PLL |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
		       HDMI_8x60_PHY_REG2_PD_DESER);

	/* Turn PowerGen on: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_PD_PLL |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
		       HDMI_8x60_PHY_REG2_PD_DESER);

	/* Turn PLL power on: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
		       HDMI_8x60_PHY_REG2_PD_DESER);

	/* Write to HIGH after PLL power down de-assert: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
		       HDMI_8x60_PHY_REG3_PLL_ENABLE);

	/* ASIC power on; PHY REG9 = 0 */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);

	/* Enable PLL lock detect, PLL lock det will go high after lock
	 * Enable the re-time logic
	 */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
		       HDMI_8x60_PHY_REG12_RETIMING_EN |
		       HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);

	/* Drivers are on: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_PD_DESER);

	/* If the RX detector is needed: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
		       HDMI_8x60_PHY_REG2_PD_DESER);

	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);

	/* If we want to use lock enable based on counting: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
		       HDMI_8x60_PHY_REG12_RETIMING_EN |
		       HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
		       HDMI_8x60_PHY_REG12_FORCE_LOCK);
}

static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
{
	/* Assert RESET PHY from controller */
	hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
		       HDMI_PHY_CTRL_SW_RESET);
	udelay(10);
	/* De-assert RESET PHY from controller */
	hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
	/* Turn off Driver */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
		       HDMI_8x60_PHY_REG2_PD_DESER);
	udelay(10);
	/* Disable PLL */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
	/* Power down PHY, but keep RX-sense: */
	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
		       HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
		       HDMI_8x60_PHY_REG2_PD_PWRGEN |
		       HDMI_8x60_PHY_REG2_PD_PLL |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
		       HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
		       HDMI_8x60_PHY_REG2_PD_DESER);
}

const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
	.type = MSM_HDMI_PHY_8x60,
	.powerup = hdmi_phy_8x60_powerup,
	.powerdown = hdmi_phy_8x60_powerdown,
};
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
c8afe684 RC	2	/*
	3	* Copyright (C) 2013 Red Hat
	4	* Author: Rob Clark <robdclark@gmail.com>
c8afe684 RC	5	*/
	6
	7	#include "hdmi.h"
	8
c8afe684 RC	9	static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
	10	unsigned long int pixclock)
	11	{
c8afe684	12	/* De-serializer delay D/C for non-lbk mode: */
ba3d7bf3 AT	13	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
ba3d7bf3 AT	14	HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
c8afe684 RC	15
	16	if (pixclock == 27000000) {
	17	/* video_format == HDMI_VFRMT_720x480p60_16_9 */
ba3d7bf3 AT	18	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
	19	HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) \|
	20	HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
c8afe684	21	} else {
ba3d7bf3 AT	22	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
	23	HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) \|
	24	HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
c8afe684 RC	25	}
	26
	27	/* No matter what, start from the power down mode: */
ba3d7bf3 AT	28	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	29	HDMI_8x60_PHY_REG2_PD_PWRGEN \|
	30	HDMI_8x60_PHY_REG2_PD_PLL \|
	31	HDMI_8x60_PHY_REG2_PD_DRIVE_4 \|
	32	HDMI_8x60_PHY_REG2_PD_DRIVE_3 \|
	33	HDMI_8x60_PHY_REG2_PD_DRIVE_2 \|
	34	HDMI_8x60_PHY_REG2_PD_DRIVE_1 \|
	35	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	36
c8afe684 RC	37	/* Turn PowerGen on: */
ba3d7bf3 AT	38	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	39	HDMI_8x60_PHY_REG2_PD_PLL \|
	40	HDMI_8x60_PHY_REG2_PD_DRIVE_4 \|
	41	HDMI_8x60_PHY_REG2_PD_DRIVE_3 \|
	42	HDMI_8x60_PHY_REG2_PD_DRIVE_2 \|
	43	HDMI_8x60_PHY_REG2_PD_DRIVE_1 \|
	44	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	45
c8afe684 RC	46	/* Turn PLL power on: */
ba3d7bf3 AT	47	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	48	HDMI_8x60_PHY_REG2_PD_DRIVE_4 \|
	49	HDMI_8x60_PHY_REG2_PD_DRIVE_3 \|
	50	HDMI_8x60_PHY_REG2_PD_DRIVE_2 \|
	51	HDMI_8x60_PHY_REG2_PD_DRIVE_1 \|
	52	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	53
c8afe684 RC	54	/* Write to HIGH after PLL power down de-assert: */
ba3d7bf3 AT	55	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
ba3d7bf3 AT	56	HDMI_8x60_PHY_REG3_PLL_ENABLE);
c8afe684 RC	57
c8afe684 RC	58	/* ASIC power on; PHY REG9 = 0 */
ba3d7bf3	59	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
c8afe684 RC	60
	61	/* Enable PLL lock detect, PLL lock det will go high after lock
	62	* Enable the re-time logic
	63	*/
ba3d7bf3 AT	64	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
	65	HDMI_8x60_PHY_REG12_RETIMING_EN \|
	66	HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
c8afe684 RC	67
c8afe684 RC	68	/* Drivers are on: */
ba3d7bf3 AT	69	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
ba3d7bf3 AT	70	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	71
c8afe684 RC	72	/* If the RX detector is needed: */
ba3d7bf3 AT	73	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	74	HDMI_8x60_PHY_REG2_RCV_SENSE_EN \|
	75	HDMI_8x60_PHY_REG2_PD_DESER);
	76
	77	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
	78	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
	79	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
	80	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
	81	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
	82	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
	83	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
	84	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);
c8afe684 RC	85
c8afe684 RC	86	/* If we want to use lock enable based on counting: */
ba3d7bf3 AT	87	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
	88	HDMI_8x60_PHY_REG12_RETIMING_EN \|
	89	HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN \|
	90	HDMI_8x60_PHY_REG12_FORCE_LOCK);
c8afe684 RC	91	}
	92
	93	static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
	94	{
c8afe684	95	/* Assert RESET PHY from controller */
ba3d7bf3 AT	96	hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
ba3d7bf3 AT	97	HDMI_PHY_CTRL_SW_RESET);
c8afe684 RC	98	udelay(10);
c8afe684 RC	99	/* De-assert RESET PHY from controller */
ba3d7bf3	100	hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
c8afe684	101	/* Turn off Driver */
ba3d7bf3 AT	102	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	103	HDMI_8x60_PHY_REG2_PD_DRIVE_4 \|
	104	HDMI_8x60_PHY_REG2_PD_DRIVE_3 \|
	105	HDMI_8x60_PHY_REG2_PD_DRIVE_2 \|
	106	HDMI_8x60_PHY_REG2_PD_DRIVE_1 \|
	107	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	108	udelay(10);
c8afe684 RC	109	/* Disable PLL */
ba3d7bf3	110	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
c8afe684	111	/* Power down PHY, but keep RX-sense: */
ba3d7bf3 AT	112	hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
	113	HDMI_8x60_PHY_REG2_RCV_SENSE_EN \|
	114	HDMI_8x60_PHY_REG2_PD_PWRGEN \|
	115	HDMI_8x60_PHY_REG2_PD_PLL \|
	116	HDMI_8x60_PHY_REG2_PD_DRIVE_4 \|
	117	HDMI_8x60_PHY_REG2_PD_DRIVE_3 \|
	118	HDMI_8x60_PHY_REG2_PD_DRIVE_2 \|
	119	HDMI_8x60_PHY_REG2_PD_DRIVE_1 \|
	120	HDMI_8x60_PHY_REG2_PD_DESER);
c8afe684 RC	121	}
c8afe684 RC	122
fcda50c8	123	const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
15b4a452 AT	124	.type = MSM_HDMI_PHY_8x60,
	125	.powerup = hdmi_phy_8x60_powerup,
	126	.powerdown = hdmi_phy_8x60_powerdown,
	127	};