[thirdparty/linux.git] / drivers / gpu / drm / msm / msm_drv.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/component.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/of_graph.h>
#include <linux/of_device.h>
#include <linux/sizes.h>
#include <linux/kthread.h>

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;
struct msm_mdss;
struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;
struct msm_fence_context;
struct msm_gem_address_space;
struct msm_gem_vma;

#define MAX_CRTCS      8
#define MAX_PLANES     20
#define MAX_ENCODERS   8
#define MAX_BRIDGES    8
#define MAX_CONNECTORS 8

#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))

struct msm_file_private {
	rwlock_t queuelock;
	struct list_head submitqueues;
	int queueid;
};

enum msm_mdp_plane_property {
	PLANE_PROP_ZPOS,
	PLANE_PROP_ALPHA,
	PLANE_PROP_PREMULTIPLIED,
	PLANE_PROP_MAX_NUM
};

#define MSM_GPU_MAX_RINGS 4
#define MAX_H_TILES_PER_DISPLAY 2

/**
 * enum msm_display_caps - features/capabilities supported by displays
 * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
 * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
 * @MSM_DISPLAY_CAP_HOT_PLUG:           Hot plug detection supported
 * @MSM_DISPLAY_CAP_EDID:               EDID supported
 */
enum msm_display_caps {
	MSM_DISPLAY_CAP_VID_MODE	= BIT(0),
	MSM_DISPLAY_CAP_CMD_MODE	= BIT(1),
	MSM_DISPLAY_CAP_HOT_PLUG	= BIT(2),
	MSM_DISPLAY_CAP_EDID		= BIT(3),
};

/**
 * enum msm_event_wait - type of HW events to wait for
 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
 */
enum msm_event_wait {
	MSM_ENC_COMMIT_DONE = 0,
	MSM_ENC_TX_COMPLETE,
	MSM_ENC_VBLANK,
};

/**
 * struct msm_display_topology - defines a display topology pipeline
 * @num_lm:       number of layer mixers used
 * @num_enc:      number of compression encoder blocks used
 * @num_intf:     number of interfaces the panel is mounted on
 */
struct msm_display_topology {
	u32 num_lm;
	u32 num_enc;
	u32 num_intf;
};

/**
 * struct msm_display_info - defines display properties
 * @intf_type:          DRM_MODE_ENCODER_ type
 * @capabilities:       Bitmask of display flags
 * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
 * @h_tile_instance:    Controller instance used per tile. Number of elements is
 *                      based on num_of_h_tiles
 * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
 *				 used instead of panel TE in cmd mode panels
 */
struct msm_display_info {
	int intf_type;
	uint32_t capabilities;
	uint32_t num_of_h_tiles;
	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
	bool is_te_using_watchdog_timer;
};

/* Commit/Event thread specific structure */
struct msm_drm_thread {
	struct drm_device *dev;
	struct task_struct *thread;
	unsigned int crtc_id;
	struct kthread_worker worker;
};

struct msm_drm_private {

	struct drm_device *dev;

	struct msm_kms *kms;

	/* subordinate devices, if present: */
	struct platform_device *gpu_pdev;

	/* top level MDSS wrapper device (for MDP5/DPU only) */
	struct msm_mdss *mdss;

	/* possibly this should be in the kms component, but it is
	 * shared by both mdp4 and mdp5..
	 */
	struct hdmi *hdmi;

	/* eDP is for mdp5 only, but kms has not been created
	 * when edp_bind() and edp_init() are called. Here is the only
	 * place to keep the edp instance.
	 */
	struct msm_edp *edp;

	/* DSI is shared by mdp4 and mdp5 */
	struct msm_dsi *dsi[2];

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;
	/* gpu is only set on open(), but we need this info earlier */
	bool is_a2xx;

	struct drm_fb_helper *fbdev;

	struct msm_rd_state *rd;       /* debugfs to dump all submits */
	struct msm_rd_state *hangrd;   /* debugfs to dump hanging submits */
	struct msm_perf_state *perf;

	/* list of GEM objects: */
	struct list_head inactive_list;

	/* worker for delayed free of objects: */
	struct work_struct free_work;
	struct llist_head free_list;

	struct workqueue_struct *wq;

	unsigned int num_planes;
	struct drm_plane *planes[MAX_PLANES];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[MAX_CRTCS];

	struct msm_drm_thread event_thread[MAX_CRTCS];

	unsigned int num_encoders;
	struct drm_encoder *encoders[MAX_ENCODERS];

	unsigned int num_bridges;
	struct drm_bridge *bridges[MAX_BRIDGES];

	unsigned int num_connectors;
	struct drm_connector *connectors[MAX_CONNECTORS];

	/* Properties */
	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
		spinlock_t lock; /* Protects drm_mm node allocation/removal */
	} vram;

	struct notifier_block vmap_notifier;
	struct shrinker shrinker;

	struct drm_atomic_state *pm_state;
};

struct msm_format {
	uint32_t pixel_format;
};

int msm_atomic_prepare_fb(struct drm_plane *plane,
			  struct drm_plane_state *new_state);
void msm_atomic_commit_tail(struct drm_atomic_state *state);
struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
void msm_atomic_state_clear(struct drm_atomic_state *state);
void msm_atomic_state_free(struct drm_atomic_state *state);

int msm_gem_init_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, int npages);
void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma);
void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma);
int msm_gem_map_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, int prot,
		struct sg_table *sgt, int npages);
void msm_gem_close_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma);

void msm_gem_address_space_put(struct msm_gem_address_space *aspace);

struct msm_gem_address_space *
msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
		const char *name);

struct msm_gem_address_space *
msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu,
		const char *name, uint64_t va_start, uint64_t va_end);

int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);

bool msm_use_mmu(struct drm_device *dev);

void msm_gem_submit_free(struct msm_gem_submit *submit);
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

void msm_gem_shrinker_init(struct drm_device *dev);
void msm_gem_shrinker_cleanup(struct drm_device *dev);

int msm_gem_mmap_obj(struct drm_gem_object *obj,
			struct vm_area_struct *vma);
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
vm_fault_t msm_gem_fault(struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace, uint64_t *iova);
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace, uint64_t *iova);
uint64_t msm_gem_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace);
void msm_gem_unpin_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		struct dma_buf_attachment *attach, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
void msm_gem_put_vaddr(struct drm_gem_object *obj);
int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
int msm_gem_sync_object(struct drm_gem_object *obj,
		struct msm_fence_context *fctx, bool exclusive);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle, char *name);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
		uint32_t size, uint32_t flags);
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
		uint32_t flags, struct msm_gem_address_space *aspace,
		struct drm_gem_object **bo, uint64_t *iova);
void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
		uint32_t flags, struct msm_gem_address_space *aspace,
		struct drm_gem_object **bo, uint64_t *iova);
void msm_gem_kernel_put(struct drm_gem_object *bo,
		struct msm_gem_address_space *aspace, bool locked);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		struct dma_buf *dmabuf, struct sg_table *sgt);
void msm_gem_free_work(struct work_struct *work);

__printf(2, 3)
void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);

int msm_framebuffer_prepare(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace);
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace);
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace, int plane);
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
		int w, int h, int p, uint32_t format);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
void msm_fbdev_free(struct drm_device *dev);

struct hdmi;
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
		struct drm_encoder *encoder);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);

struct msm_edp;
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
		struct drm_encoder *encoder);

struct msm_dsi;
#ifdef CONFIG_DRM_MSM_DSI
void __init msm_dsi_register(void);
void __exit msm_dsi_unregister(void);
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
			 struct drm_encoder *encoder);
#else
static inline void __init msm_dsi_register(void)
{
}
static inline void __exit msm_dsi_unregister(void)
{
}
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
				       struct drm_device *dev,
				       struct drm_encoder *encoder)
{
	return -EINVAL;
}
#endif

void __init msm_mdp_register(void);
void __exit msm_mdp_unregister(void);
void __init msm_dpu_register(void);
void __exit msm_dpu_unregister(void);

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
int msm_debugfs_late_init(struct drm_device *dev);
int msm_rd_debugfs_init(struct drm_minor *minor);
void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
__printf(3, 4)
void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
		const char *fmt, ...);
int msm_perf_debugfs_init(struct drm_minor *minor);
void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
#else
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
__printf(3, 4)
static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
		const char *fmt, ...) {}
static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
#endif

struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);

struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
	const char *name);
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

struct msm_gpu_submitqueue;
int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
		u32 id);
int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
		u32 prio, u32 flags, u32 *id);
int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
		struct drm_msm_submitqueue_query *args);
int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
void msm_submitqueue_close(struct msm_file_private *ctx);

void msm_submitqueue_destroy(struct kref *kref);


#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)

static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
{
	ktime_t now = ktime_get();
	unsigned long remaining_jiffies;

	if (ktime_compare(*timeout, now) < 0) {
		remaining_jiffies = 0;
	} else {
		ktime_t rem = ktime_sub(*timeout, now);
		struct timespec ts = ktime_to_timespec(rem);
		remaining_jiffies = timespec_to_jiffies(&ts);
	}

	return remaining_jiffies;
}

#endif /* __MSM_DRV_H__ */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
c8afe684	2	/*
25fdd593	3	* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
c8afe684 RC	4	* Copyright (C) 2013 Red Hat
c8afe684 RC	5	* Author: Rob Clark <robdclark@gmail.com>
c8afe684 RC	6	*/
	7
	8	#ifndef __MSM_DRV_H__
	9	#define __MSM_DRV_H__
	10
	11	#include <linux/kernel.h>
	12	#include <linux/clk.h>
	13	#include <linux/cpufreq.h>
	14	#include <linux/module.h>
060530f1	15	#include <linux/component.h>
c8afe684 RC	16	#include <linux/platform_device.h>
	17	#include <linux/pm.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/slab.h>
	20	#include <linux/list.h>
	21	#include <linux/iommu.h>
	22	#include <linux/types.h>
3d6df062	23	#include <linux/of_graph.h>
e9fbdaf2	24	#include <linux/of_device.h>
87dfb311	25	#include <linux/sizes.h>
25fdd593	26	#include <linux/kthread.h>
c8afe684	27
c8afe684	28	#include <drm/drmP.h>
cf3a7e4c RC	29	#include <drm/drm_atomic.h>
cf3a7e4c RC	30	#include <drm/drm_atomic_helper.h>
cf3a7e4c	31	#include <drm/drm_plane_helper.h>
fcd70cd3	32	#include <drm/drm_probe_helper.h>
c8afe684	33	#include <drm/drm_fb_helper.h>
7198e6b0	34	#include <drm/msm_drm.h>
d9fc9413	35	#include <drm/drm_gem.h>
c8afe684 RC	36
c8afe684 RC	37	struct msm_kms;
7198e6b0	38	struct msm_gpu;
871d812a	39	struct msm_mmu;
990a4007	40	struct msm_mdss;
a7d3c950	41	struct msm_rd_state;
70c70f09	42	struct msm_perf_state;
a7d3c950	43	struct msm_gem_submit;
ca762a8a	44	struct msm_fence_context;
667ce33e RC	45	struct msm_gem_address_space;
667ce33e RC	46	struct msm_gem_vma;
c8afe684	47
7305a0ce	48	#define MAX_CRTCS 8
25fdd593	49	#define MAX_PLANES 20
7305a0ce JS	50	#define MAX_ENCODERS 8
	51	#define MAX_BRIDGES 8
	52	#define MAX_CONNECTORS 8
	53
96fc56a7 SP	54	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
96fc56a7 SP	55
7198e6b0	56	struct msm_file_private {
f7de1545 JC	57	rwlock_t queuelock;
	58	struct list_head submitqueues;
	59	int queueid;
7198e6b0	60	};
c8afe684	61
12987781 JW	62	enum msm_mdp_plane_property {
	63	PLANE_PROP_ZPOS,
	64	PLANE_PROP_ALPHA,
	65	PLANE_PROP_PREMULTIPLIED,
	66	PLANE_PROP_MAX_NUM
	67	};
	68
b1fc2839	69	#define MSM_GPU_MAX_RINGS 4
25fdd593 JS	70	#define MAX_H_TILES_PER_DISPLAY 2
	71
	72	/**
	73	* enum msm_display_caps - features/capabilities supported by displays
	74	* @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
	75	* @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
	76	* @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
	77	* @MSM_DISPLAY_CAP_EDID: EDID supported
	78	*/
	79	enum msm_display_caps {
	80	MSM_DISPLAY_CAP_VID_MODE = BIT(0),
	81	MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
	82	MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
	83	MSM_DISPLAY_CAP_EDID = BIT(3),
	84	};
	85
	86	/**
	87	* enum msm_event_wait - type of HW events to wait for
	88	* @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
	89	* @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
	90	* @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
	91	*/
	92	enum msm_event_wait {
	93	MSM_ENC_COMMIT_DONE = 0,
	94	MSM_ENC_TX_COMPLETE,
	95	MSM_ENC_VBLANK,
	96	};
	97
	98	/**
	99	* struct msm_display_topology - defines a display topology pipeline
	100	* @num_lm: number of layer mixers used
	101	* @num_enc: number of compression encoder blocks used
	102	* @num_intf: number of interfaces the panel is mounted on
	103	*/
	104	struct msm_display_topology {
	105	u32 num_lm;
	106	u32 num_enc;
	107	u32 num_intf;
	108	};
	109
	110	/**
	111	* struct msm_display_info - defines display properties
9b9c8e7e	112	* @intf_type: DRM_MODE_ENCODER_ type
25fdd593 JS	113	* @capabilities: Bitmask of display flags
	114	* @num_of_h_tiles: Number of horizontal tiles in case of split interface
	115	* @h_tile_instance: Controller instance used per tile. Number of elements is
	116	* based on num_of_h_tiles
	117	* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
	118	* used instead of panel TE in cmd mode panels
	119	*/
	120	struct msm_display_info {
	121	int intf_type;
	122	uint32_t capabilities;
	123	uint32_t num_of_h_tiles;
	124	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
	125	bool is_te_using_watchdog_timer;
	126	};
	127
	128	/* Commit/Event thread specific structure */
	129	struct msm_drm_thread {
	130	struct drm_device *dev;
	131	struct task_struct *thread;
	132	unsigned int crtc_id;
	133	struct kthread_worker worker;
	134	};
f97decac	135
c8afe684 RC	136	struct msm_drm_private {
c8afe684 RC	137
68209390 RC	138	struct drm_device *dev;
68209390 RC	139
c8afe684 RC	140	struct msm_kms *kms;
c8afe684 RC	141
060530f1	142	/* subordinate devices, if present: */
067fef37 RC	143	struct platform_device *gpu_pdev;
067fef37 RC	144
25fdd593	145	/* top level MDSS wrapper device (for MDP5/DPU only) */
990a4007 AT	146	struct msm_mdss *mdss;
990a4007 AT	147
067fef37 RC	148	/* possibly this should be in the kms component, but it is
	149	* shared by both mdp4 and mdp5..
	150	*/
	151	struct hdmi *hdmi;
060530f1	152
ab5b0107 HL	153	/* eDP is for mdp5 only, but kms has not been created
	154	* when edp_bind() and edp_init() are called. Here is the only
	155	* place to keep the edp instance.
	156	*/
	157	struct msm_edp *edp;
	158
a689554b HL	159	/* DSI is shared by mdp4 and mdp5 */
	160	struct msm_dsi *dsi[2];
	161
7198e6b0 RC	162	/* when we have more than one 'msm_gpu' these need to be an array: */
	163	struct msm_gpu *gpu;
	164	struct msm_file_private *lastctx;
c2052a4e JM	165	/* gpu is only set on open(), but we need this info earlier */
c2052a4e JM	166	bool is_a2xx;
7198e6b0	167
c8afe684 RC	168	struct drm_fb_helper *fbdev;
c8afe684 RC	169
2165e2b9 RC	170	struct msm_rd_state rd; / debugfs to dump all submits */
2165e2b9 RC	171	struct msm_rd_state hangrd; / debugfs to dump hanging submits */
70c70f09	172	struct msm_perf_state *perf;
a7d3c950	173
c8afe684 RC	174	/* list of GEM objects: */
	175	struct list_head inactive_list;
	176
48e7f183 KK	177	/* worker for delayed free of objects: */
	178	struct work_struct free_work;
	179	struct llist_head free_list;
	180
c8afe684 RC	181	struct workqueue_struct *wq;
c8afe684 RC	182
a8623918	183	unsigned int num_planes;
7305a0ce	184	struct drm_plane *planes[MAX_PLANES];
a8623918	185
c8afe684	186	unsigned int num_crtcs;
7305a0ce	187	struct drm_crtc *crtcs[MAX_CRTCS];
c8afe684	188
25fdd593 JS	189	struct msm_drm_thread event_thread[MAX_CRTCS];
25fdd593 JS	190
c8afe684	191	unsigned int num_encoders;
7305a0ce	192	struct drm_encoder *encoders[MAX_ENCODERS];
c8afe684	193
a3376e3e	194	unsigned int num_bridges;
7305a0ce	195	struct drm_bridge *bridges[MAX_BRIDGES];
a3376e3e	196
c8afe684	197	unsigned int num_connectors;
7305a0ce	198	struct drm_connector *connectors[MAX_CONNECTORS];
871d812a	199
12987781 JW	200	/* Properties */
	201	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
	202
871d812a RC	203	/* VRAM carveout, used when no IOMMU: */
	204	struct {
	205	unsigned long size;
	206	dma_addr_t paddr;
	207	/* NOTE: mm managed at the page level, size is in # of pages
	208	* and position mm_node->start is in # of pages:
	209	*/
	210	struct drm_mm mm;
0e08270a	211	spinlock_t lock; /* Protects drm_mm node allocation/removal */
871d812a	212	} vram;
78b1d470	213
e1e9db2c	214	struct notifier_block vmap_notifier;
68209390 RC	215	struct shrinker shrinker;
68209390 RC	216
ec446d09	217	struct drm_atomic_state *pm_state;
c8afe684 RC	218	};
	219
	220	struct msm_format {
	221	uint32_t pixel_format;
	222	};
	223
db8f4d5d SP	224	int msm_atomic_prepare_fb(struct drm_plane *plane,
db8f4d5d SP	225	struct drm_plane_state *new_state);
d14659f5	226	void msm_atomic_commit_tail(struct drm_atomic_state *state);
870d738a RC	227	struct drm_atomic_state msm_atomic_state_alloc(struct drm_device dev);
	228	void msm_atomic_state_clear(struct drm_atomic_state *state);
	229	void msm_atomic_state_free(struct drm_atomic_state *state);
cf3a7e4c	230
c0ee9794 JC	231	int msm_gem_init_vma(struct msm_gem_address_space *aspace,
c0ee9794 JC	232	struct msm_gem_vma *vma, int npages);
7ad0e8cf JC	233	void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
7ad0e8cf JC	234	struct msm_gem_vma *vma);
667ce33e	235	void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
70dc51b4	236	struct msm_gem_vma *vma);
667ce33e	237	int msm_gem_map_vma(struct msm_gem_address_space *aspace,
bbc2cd07 RC	238	struct msm_gem_vma *vma, int prot,
bbc2cd07 RC	239	struct sg_table *sgt, int npages);
7ad0e8cf JC	240	void msm_gem_close_vma(struct msm_gem_address_space *aspace,
7ad0e8cf JC	241	struct msm_gem_vma *vma);
667ce33e	242
ee546cd3 JC	243	void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
ee546cd3 JC	244
667ce33e RC	245	struct msm_gem_address_space *
	246	msm_gem_address_space_create(struct device dev, struct iommu_domain domain,
	247	const char *name);
c8afe684	248
c2052a4e JM	249	struct msm_gem_address_space *
	250	msm_gem_address_space_create_a2xx(struct device dev, struct msm_gpu gpu,
	251	const char *name, uint64_t va_start, uint64_t va_end);
	252
25fdd593 JS	253	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);
	254	void msm_unregister_mmu(struct drm_device dev, struct msm_mmu mmu);
	255
c2052a4e JM	256	bool msm_use_mmu(struct drm_device *dev);
c2052a4e JM	257
40e6815b	258	void msm_gem_submit_free(struct msm_gem_submit *submit);
7198e6b0 RC	259	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	260	struct drm_file *file);
	261
68209390 RC	262	void msm_gem_shrinker_init(struct drm_device *dev);
	263	void msm_gem_shrinker_cleanup(struct drm_device *dev);
	264
77a147e7 DT	265	int msm_gem_mmap_obj(struct drm_gem_object *obj,
77a147e7 DT	266	struct vm_area_struct *vma);
c8afe684	267	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
a5f74ec7	268	vm_fault_t msm_gem_fault(struct vm_fault *vmf);
c8afe684	269	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
8bdcd949 RC	270	int msm_gem_get_iova(struct drm_gem_object *obj,
8bdcd949 RC	271	struct msm_gem_address_space aspace, uint64_t iova);
9fe041f6 JC	272	int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
9fe041f6 JC	273	struct msm_gem_address_space aspace, uint64_t iova);
8bdcd949 RC	274	uint64_t msm_gem_iova(struct drm_gem_object *obj,
8bdcd949 RC	275	struct msm_gem_address_space *aspace);
7ad0e8cf JC	276	void msm_gem_unpin_iova(struct drm_gem_object *obj,
7ad0e8cf JC	277	struct msm_gem_address_space *aspace);
05b84911 RC	278	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	279	void msm_gem_put_pages(struct drm_gem_object *obj);
c8afe684 RC	280	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
c8afe684 RC	281	struct drm_mode_create_dumb *args);
c8afe684 RC	282	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	283	uint32_t handle, uint64_t *offset);
05b84911 RC	284	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	285	void msm_gem_prime_vmap(struct drm_gem_object obj);
	286	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
77a147e7	287	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
05b84911	288	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
b5e9c1a2	289	struct dma_buf_attachment attach, struct sg_table sg);
05b84911 RC	290	int msm_gem_prime_pin(struct drm_gem_object *obj);
05b84911 RC	291	void msm_gem_prime_unpin(struct drm_gem_object *obj);
18f23049	292	void msm_gem_get_vaddr(struct drm_gem_object obj);
fad33f4b	293	void msm_gem_get_vaddr_active(struct drm_gem_object obj);
18f23049	294	void msm_gem_put_vaddr(struct drm_gem_object *obj);
4cd33c48	295	int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
b6295f9a RC	296	int msm_gem_sync_object(struct drm_gem_object *obj,
b6295f9a RC	297	struct msm_fence_context *fctx, bool exclusive);
7198e6b0	298	void msm_gem_move_to_active(struct drm_gem_object *obj,
f54d1867	299	struct msm_gpu gpu, bool exclusive, struct dma_fence fence);
7198e6b0	300	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
ba00c3f2	301	int msm_gem_cpu_prep(struct drm_gem_object obj, uint32_t op, ktime_t timeout);
7198e6b0	302	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	303	void msm_gem_free_object(struct drm_gem_object *obj);
c8afe684 RC	304	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
0815d774	305	uint32_t size, uint32_t flags, uint32_t handle, char name);
c8afe684 RC	306	struct drm_gem_object msm_gem_new(struct drm_device dev,
c8afe684 RC	307	uint32_t size, uint32_t flags);
0e08270a SS	308	struct drm_gem_object msm_gem_new_locked(struct drm_device dev,
0e08270a SS	309	uint32_t size, uint32_t flags);
8223286d JC	310	void msm_gem_kernel_new(struct drm_device dev, uint32_t size,
	311	uint32_t flags, struct msm_gem_address_space *aspace,
	312	struct drm_gem_object *bo, uint64_t iova);
	313	void msm_gem_kernel_new_locked(struct drm_device dev, uint32_t size,
	314	uint32_t flags, struct msm_gem_address_space *aspace,
	315	struct drm_gem_object *bo, uint64_t iova);
1e29dff0 JC	316	void msm_gem_kernel_put(struct drm_gem_object *bo,
1e29dff0 JC	317	struct msm_gem_address_space *aspace, bool locked);
05b84911	318	struct drm_gem_object msm_gem_import(struct drm_device dev,
79f0e202	319	struct dma_buf dmabuf, struct sg_table sgt);
48e7f183	320	void msm_gem_free_work(struct work_struct *work);
c8afe684	321
023014e7	322	__printf(2, 3)
0815d774 JC	323	void msm_gem_object_set_name(struct drm_gem_object bo, const char fmt, ...);
0815d774 JC	324
8bdcd949 RC	325	int msm_framebuffer_prepare(struct drm_framebuffer *fb,
	326	struct msm_gem_address_space *aspace);
	327	void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
	328	struct msm_gem_address_space *aspace);
	329	uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
	330	struct msm_gem_address_space *aspace, int plane);
c8afe684 RC	331	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
c8afe684 RC	332	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
c8afe684	333	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
1eb83451	334	struct drm_file file, const struct drm_mode_fb_cmd2 mode_cmd);
466e5606 RC	335	struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
466e5606 RC	336	int w, int h, int p, uint32_t format);
c8afe684 RC	337
c8afe684 RC	338	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
1aaa57f5	339	void msm_fbdev_free(struct drm_device *dev);
c8afe684	340
dada25bd	341	struct hdmi;
fcda50c8	342	int msm_hdmi_modeset_init(struct hdmi hdmi, struct drm_device dev,
067fef37	343	struct drm_encoder *encoder);
fcda50c8 AB	344	void __init msm_hdmi_register(void);
fcda50c8 AB	345	void __exit msm_hdmi_unregister(void);
c8afe684	346
00453981 HL	347	struct msm_edp;
	348	void __init msm_edp_register(void);
	349	void __exit msm_edp_unregister(void);
	350	int msm_edp_modeset_init(struct msm_edp edp, struct drm_device dev,
	351	struct drm_encoder *encoder);
	352
a689554b	353	struct msm_dsi;
a689554b HL	354	#ifdef CONFIG_DRM_MSM_DSI
	355	void __init msm_dsi_register(void);
	356	void __exit msm_dsi_unregister(void);
	357	int msm_dsi_modeset_init(struct msm_dsi msm_dsi, struct drm_device dev,
97e00119	358	struct drm_encoder *encoder);
a689554b HL	359	#else
	360	static inline void __init msm_dsi_register(void)
	361	{
	362	}
	363	static inline void __exit msm_dsi_unregister(void)
	364	{
	365	}
	366	static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
97e00119 AT	367	struct drm_device *dev,
97e00119 AT	368	struct drm_encoder *encoder)
a689554b HL	369	{
	370	return -EINVAL;
	371	}
	372	#endif
	373
1dd0a0b1 AT	374	void __init msm_mdp_register(void);
1dd0a0b1 AT	375	void __exit msm_mdp_unregister(void);
25fdd593 JS	376	void __init msm_dpu_register(void);
25fdd593 JS	377	void __exit msm_dpu_unregister(void);
1dd0a0b1	378
c8afe684 RC	379	#ifdef CONFIG_DEBUG_FS
	380	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	381	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	382	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
a7d3c950 RC	383	int msm_debugfs_late_init(struct drm_device *dev);
a7d3c950 RC	384	int msm_rd_debugfs_init(struct drm_minor *minor);
85eac470	385	void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
023014e7	386	__printf(3, 4)
998b9a58 RC	387	void msm_rd_dump_submit(struct msm_rd_state rd, struct msm_gem_submit submit,
998b9a58 RC	388	const char *fmt, ...);
70c70f09	389	int msm_perf_debugfs_init(struct drm_minor *minor);
85eac470	390	void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
a7d3c950 RC	391	#else
a7d3c950 RC	392	static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
023014e7	393	__printf(3, 4)
e6756d7c AB	394	static inline void msm_rd_dump_submit(struct msm_rd_state rd, struct msm_gem_submit submit,
e6756d7c AB	395	const char *fmt, ...) {}
3a270e4d AB	396	static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
3a270e4d AB	397	static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
c8afe684 RC	398	#endif
c8afe684 RC	399
720c3bb8	400	struct clk msm_clk_get(struct platform_device pdev, const char *name);
8e54eea5 JC	401	int msm_clk_bulk_get(struct device dev, struct clk_bulk_data *bulk);
	402
	403	struct clk msm_clk_bulk_get_clock(struct clk_bulk_data bulk, int count,
	404	const char *name);
c8afe684 RC	405	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	406	const char *dbgname);
	407	void msm_writel(u32 data, void __iomem *addr);
	408	u32 msm_readl(const void __iomem *addr);
	409
f7de1545	410	struct msm_gpu_submitqueue;
f97decac	411	int msm_submitqueue_init(struct drm_device drm, struct msm_file_private ctx);
f7de1545 JC	412	struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
f7de1545 JC	413	u32 id);
f97decac JC	414	int msm_submitqueue_create(struct drm_device drm, struct msm_file_private ctx,
f97decac JC	415	u32 prio, u32 flags, u32 *id);
b0fb6604 JC	416	int msm_submitqueue_query(struct drm_device drm, struct msm_file_private ctx,
b0fb6604 JC	417	struct drm_msm_submitqueue_query *args);
f7de1545 JC	418	int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
	419	void msm_submitqueue_close(struct msm_file_private *ctx);
	420
	421	void msm_submitqueue_destroy(struct kref *kref);
	422
	423
7ed216e5 RC	424	#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
7ed216e5 RC	425	#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
c8afe684 RC	426
	427	static inline int align_pitch(int width, int bpp)
	428	{
	429	int bytespp = (bpp + 7) / 8;
	430	/* adreno needs pitch aligned to 32 pixels: */
	431	return bytespp * ALIGN(width, 32);
	432	}
	433
	434	/* for the generated headers: */
	435	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	436	#define fui(x) ({BUG(); 0;})
	437	#define util_float_to_half(x) ({BUG(); 0;})
	438
c8afe684 RC	439
	440	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	441
	442	/* for conditionally setting boolean flag(s): */
	443	#define COND(bool, val) ((bool) ? (val) : 0)
	444
340ff410 RC	445	static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
	446	{
	447	ktime_t now = ktime_get();
	448	unsigned long remaining_jiffies;
	449
	450	if (ktime_compare(*timeout, now) < 0) {
	451	remaining_jiffies = 0;
	452	} else {
	453	ktime_t rem = ktime_sub(*timeout, now);
	454	struct timespec ts = ktime_to_timespec(rem);
	455	remaining_jiffies = timespec_to_jiffies(&ts);
	456	}
	457
	458	return remaining_jiffies;
	459	}
c8afe684 RC	460
c8afe684 RC	461	#endif /* __MSM_DRV_H__ */