[thirdparty/kernel/linux.git] / drivers / gpu / drm / nouveau / include / nvkm / subdev / clk.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __NVKM_CLK_H__
#define __NVKM_CLK_H__
#include <core/subdev.h>
#include <core/notify.h>
#include <subdev/pci.h>
struct nvbios_pll;
struct nvkm_pll_vals;

#define NVKM_CLK_CSTATE_DEFAULT -1 /* POSTed default */
#define NVKM_CLK_CSTATE_BASE    -2 /* pstate base */
#define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */

enum nv_clk_src {
	nv_clk_src_crystal,
	nv_clk_src_href,

	nv_clk_src_hclk,
	nv_clk_src_hclkm3,
	nv_clk_src_hclkm3d2,
	nv_clk_src_hclkm2d3, /* NVAA */
	nv_clk_src_hclkm4, /* NVAA */
	nv_clk_src_cclk, /* NVAA */

	nv_clk_src_host,

	nv_clk_src_sppll0,
	nv_clk_src_sppll1,

	nv_clk_src_mpllsrcref,
	nv_clk_src_mpllsrc,
	nv_clk_src_mpll,
	nv_clk_src_mdiv,

	nv_clk_src_core,
	nv_clk_src_core_intm,
	nv_clk_src_shader,

	nv_clk_src_mem,

	nv_clk_src_gpc,
	nv_clk_src_rop,
	nv_clk_src_hubk01,
	nv_clk_src_hubk06,
	nv_clk_src_hubk07,
	nv_clk_src_copy,
	nv_clk_src_pmu,
	nv_clk_src_disp,
	nv_clk_src_vdec,

	nv_clk_src_dom6,

	nv_clk_src_max,
};

struct nvkm_cstate {
	struct list_head head;
	u8  voltage;
	u32 domain[nv_clk_src_max];
	u8  id;
};

struct nvkm_pstate {
	struct list_head head;
	struct list_head list; /* c-states */
	struct nvkm_cstate base;
	u8 pstate;
	u8 fanspeed;
	enum nvkm_pcie_speed pcie_speed;
	u8 pcie_width;
};

struct nvkm_domain {
	enum nv_clk_src name;
	u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE    0x01
#define NVKM_CLK_DOM_FLAG_VPSTATE 0x02
	u8 flags;
	const char *mname;
	int mdiv;
};

struct nvkm_clk {
	const struct nvkm_clk_func *func;
	struct nvkm_subdev subdev;

	const struct nvkm_domain *domains;
	struct nvkm_pstate bstate;

	struct list_head states;
	int state_nr;

	struct work_struct work;
	wait_queue_head_t wait;
	atomic_t waiting;

	struct nvkm_notify pwrsrc_ntfy;
	int pwrsrc;
	int pstate; /* current */
	int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
	int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
	int astate; /* perfmon adjustment (base) */
	int dstate; /* display adjustment (min+) */
	u8  temp;

	bool allow_reclock;
#define NVKM_CLK_BOOST_NONE 0x0
#define NVKM_CLK_BOOST_BIOS 0x1
#define NVKM_CLK_BOOST_FULL 0x2
	u8  boost_mode;
	u32 base_khz;
	u32 boost_khz;

	/*XXX: die, these are here *only* to support the completely
	 *     bat-shit insane what-was-nouveau_hw.c code
	 */
	int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
			struct nvkm_pll_vals *pv);
	int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
};

int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);
int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);

int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
7632b30e BS	2	#ifndef __NVKM_CLK_H__
7632b30e BS	3	#define __NVKM_CLK_H__
f3867f43	4	#include <core/subdev.h>
7632b30e	5	#include <core/notify.h>
d3b378c0	6	#include <subdev/pci.h>
f3867f43	7	struct nvbios_pll;
7632b30e	8	struct nvkm_pll_vals;
f3867f43	9
0d6f8100 KH	10	#define NVKM_CLK_CSTATE_DEFAULT -1 /* POSTed default */
	11	#define NVKM_CLK_CSTATE_BASE -2 /* pstate base */
	12	#define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */
	13
f3867f43 BS	14	enum nv_clk_src {
	15	nv_clk_src_crystal,
	16	nv_clk_src_href,
	17
	18	nv_clk_src_hclk,
	19	nv_clk_src_hclkm3,
	20	nv_clk_src_hclkm3d2,
	21	nv_clk_src_hclkm2d3, /* NVAA */
	22	nv_clk_src_hclkm4, /* NVAA */
	23	nv_clk_src_cclk, /* NVAA */
	24
	25	nv_clk_src_host,
	26
	27	nv_clk_src_sppll0,
	28	nv_clk_src_sppll1,
	29
	30	nv_clk_src_mpllsrcref,
	31	nv_clk_src_mpllsrc,
	32	nv_clk_src_mpll,
	33	nv_clk_src_mdiv,
	34
	35	nv_clk_src_core,
	36	nv_clk_src_core_intm,
	37	nv_clk_src_shader,
	38
	39	nv_clk_src_mem,
	40
	41	nv_clk_src_gpc,
	42	nv_clk_src_rop,
	43	nv_clk_src_hubk01,
	44	nv_clk_src_hubk06,
	45	nv_clk_src_hubk07,
	46	nv_clk_src_copy,
547dd271	47	nv_clk_src_pmu,
f3867f43 BS	48	nv_clk_src_disp,
	49	nv_clk_src_vdec,
	50
	51	nv_clk_src_dom6,
	52
	53	nv_clk_src_max,
	54	};
	55
7632b30e	56	struct nvkm_cstate {
f3867f43 BS	57	struct list_head head;
	58	u8 voltage;
	59	u32 domain[nv_clk_src_max];
761c8f69	60	u8 id;
f3867f43 BS	61	};
f3867f43 BS	62
7632b30e	63	struct nvkm_pstate {
f3867f43 BS	64	struct list_head head;
f3867f43 BS	65	struct list_head list; /* c-states */
7632b30e	66	struct nvkm_cstate base;
f3867f43 BS	67	u8 pstate;
f3867f43 BS	68	u8 fanspeed;
d3b378c0 KH	69	enum nvkm_pcie_speed pcie_speed;
d3b378c0 KH	70	u8 pcie_width;
f3867f43 BS	71	};
f3867f43 BS	72
7632b30e BS	73	struct nvkm_domain {
	74	enum nv_clk_src name;
	75	u8 bios; /* 0xff for none */
4b9ce6e7 KH	76	#define NVKM_CLK_DOM_FLAG_CORE 0x01
4b9ce6e7 KH	77	#define NVKM_CLK_DOM_FLAG_VPSTATE 0x02
7632b30e BS	78	u8 flags;
	79	const char *mname;
	80	int mdiv;
	81	};
f3867f43	82
7632b30e	83	struct nvkm_clk {
6625f55c	84	const struct nvkm_clk_func *func;
3eca809b	85	struct nvkm_subdev subdev;
7632b30e	86
6625f55c	87	const struct nvkm_domain *domains;
7632b30e	88	struct nvkm_pstate bstate;
f3867f43 BS	89
	90	struct list_head states;
	91	int state_nr;
	92
	93	struct work_struct work;
	94	wait_queue_head_t wait;
	95	atomic_t waiting;
	96
	97	struct nvkm_notify pwrsrc_ntfy;
	98	int pwrsrc;
	99	int pstate; /* current */
	100	int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
	101	int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
	102	int astate; /* perfmon adjustment (base) */
f3867f43	103	int dstate; /* display adjustment (min+) */
61a8b84f	104	u8 temp;
f3867f43 BS	105
f3867f43 BS	106	bool allow_reclock;
4b9ce6e7 KH	107	#define NVKM_CLK_BOOST_NONE 0x0
	108	#define NVKM_CLK_BOOST_BIOS 0x1
	109	#define NVKM_CLK_BOOST_FULL 0x2
	110	u8 boost_mode;
	111	u32 base_khz;
	112	u32 boost_khz;
f3867f43	113
f3867f43	114	/XXX: die, these are here only* to support the completely
6625f55c	115	* bat-shit insane what-was-nouveau_hw.c code
f3867f43	116	*/
7632b30e BS	117	int (pll_calc)(struct nvkm_clk , struct nvbios_pll *, int clk,
	118	struct nvkm_pll_vals *pv);
	119	int (pll_prog)(struct nvkm_clk , u32 reg1, struct nvkm_pll_vals *pv);
f3867f43 BS	120	};
f3867f43 BS	121
6625f55c	122	int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);
7632b30e BS	123	int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
	124	int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
	125	int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
61a8b84f	126	int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);
6625f55c BS	127
	128	int nv04_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	129	int nv40_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	130	int nv50_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	131	int g84_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	132	int mcp77_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	133	int gt215_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	134	int gf100_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	135	int gk104_clk_new(struct nvkm_device , int, struct nvkm_clk *);
	136	int gk20a_clk_new(struct nvkm_device , int, struct nvkm_clk *);
52829d4f	137	int gm20b_clk_new(struct nvkm_device , int, struct nvkm_clk *);
f3867f43	138	#endif