[thirdparty/linux.git] / drivers / gpu / drm / nouveau / nouveau_abi16.h

/* SPDX-License-Identifier: MIT */
#ifndef __NOUVEAU_ABI16_H__
#define __NOUVEAU_ABI16_H__

#define ABI16_IOCTL_ARGS                                                       \
	struct drm_device *dev, void *data, struct drm_file *file_priv

int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);

struct nouveau_abi16_ntfy {
	struct nvif_object object;
	struct list_head head;
	struct nvkm_mm_node *node;
};

struct nouveau_abi16_chan {
	struct list_head head;
	struct nouveau_channel *chan;
	struct nvif_object ce;
	struct list_head notifiers;
	struct nouveau_bo *ntfy;
	struct nouveau_vma *ntfy_vma;
	struct nvkm_mm  heap;
	struct nouveau_sched_entity sched_entity;
};

struct nouveau_abi16 {
	struct nvif_device device;
	struct list_head channels;
	u64 handles;
};

struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *);
int  nouveau_abi16_put(struct nouveau_abi16 *, int);
void nouveau_abi16_fini(struct nouveau_abi16 *);
s32  nouveau_abi16_swclass(struct nouveau_drm *);
int  nouveau_abi16_usif(struct drm_file *, void *data, u32 size);

#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)

struct drm_nouveau_grobj_alloc {
	int      channel;
	uint32_t handle;
	int      class;
};

struct drm_nouveau_notifierobj_alloc {
	uint32_t channel;
	uint32_t handle;
	uint32_t size;
	uint32_t offset;
};

struct drm_nouveau_gpuobj_free {
	int      channel;
	uint32_t handle;
};

struct drm_nouveau_setparam {
	uint64_t param;
	uint64_t value;
};

#define DRM_IOCTL_NOUVEAU_SETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC  DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)

#endif
Commit	Line	Data
b7019ac5	1	/* SPDX-License-Identifier: MIT */
2a259a3d BS	2	#ifndef __NOUVEAU_ABI16_H__
	3	#define __NOUVEAU_ABI16_H__
	4
	5	#define ABI16_IOCTL_ARGS \
	6	struct drm_device dev, void data, struct drm_file *file_priv
ebb945a9	7
2a259a3d	8	int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
2a259a3d BS	9	int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
	10	int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
	11	int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
	12	int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
	13	int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
	14
ebb945a9	15	struct nouveau_abi16_ntfy {
a01ca78c	16	struct nvif_object object;
ebb945a9	17	struct list_head head;
be83cd4e	18	struct nvkm_mm_node *node;
ebb945a9 BS	19	};
	20
	21	struct nouveau_abi16_chan {
	22	struct list_head head;
	23	struct nouveau_channel *chan;
40184ece	24	struct nvif_object ce;
ebb945a9 BS	25	struct list_head notifiers;
ebb945a9 BS	26	struct nouveau_bo *ntfy;
24e8375b	27	struct nouveau_vma *ntfy_vma;
be83cd4e	28	struct nvkm_mm heap;
b88baab8	29	struct nouveau_sched_entity sched_entity;
ebb945a9 BS	30	};
	31
	32	struct nouveau_abi16 {
967e7bde	33	struct nvif_device device;
ebb945a9 BS	34	struct list_head channels;
	35	u64 handles;
	36	};
	37
09433f24	38	struct nouveau_abi16 nouveau_abi16_get(struct drm_file );
ebb945a9 BS	39	int nouveau_abi16_put(struct nouveau_abi16 *, int);
ebb945a9 BS	40	void nouveau_abi16_fini(struct nouveau_abi16 *);
f58ddf95	41	s32 nouveau_abi16_swclass(struct nouveau_drm *);
2621a416	42	int nouveau_abi16_usif(struct drm_file , void data, u32 size);
ebb945a9 BS	43
	44	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	45	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	46
2a259a3d BS	47	struct drm_nouveau_grobj_alloc {
	48	int channel;
	49	uint32_t handle;
	50	int class;
	51	};
	52
	53	struct drm_nouveau_notifierobj_alloc {
	54	uint32_t channel;
	55	uint32_t handle;
	56	uint32_t size;
	57	uint32_t offset;
	58	};
	59
	60	struct drm_nouveau_gpuobj_free {
	61	int channel;
	62	uint32_t handle;
	63	};
	64
2a259a3d BS	65	struct drm_nouveau_setparam {
	66	uint64_t param;
	67	uint64_t value;
	68	};
	69
2a259a3d	70	#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
2a259a3d BS	71	#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
	72	#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
	73	#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
	74
	75	#endif