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drm/nouveau: don't execute INIT_GPIO unless we're really running the table
[people/ms/linux.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861
BS		 30
31/* these defines are made up */
32#define NV_CIO_CRE_44_HEADA 0x0
33#define NV_CIO_CRE_44_HEADB 0x3
34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
35#define LEGACY_I2C_CRT 0x80
36#define LEGACY_I2C_PANEL 0x81
37#define LEGACY_I2C_TV 0x82
38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
46
47struct init_exec {
48 bool execute;
49 bool repeat;
50};
51
52static bool nv_cksum(const uint8_t *data, unsigned int length)
53{
54 /*
55 * There's a few checksums in the BIOS, so here's a generic checking
56 * function.
57 */
58 int i;
59 uint8_t sum = 0;
60
61 for (i = 0; i < length; i++)
62 sum += data[i];
63
64 if (sum)
65 return true;
66
67 return false;
68}
69
70static int
71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72{
73 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
74 NV_TRACEWARN(dev, "... BIOS signature not found\n");
75 return 0;
76 }
77
78 if (nv_cksum(data, data[2] * 512)) {
79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
80 /* if a ro image is somewhat bad, it's probably all rubbish */
81 return writeable ? 2 : 1;
82 } else
83 NV_TRACE(dev, "... appears to be valid\n");
84
85 return 3;
86}
87
88static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89{
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t pci_nv_20, save_pci_nv_20;
92 int pcir_ptr;
93 int i;
94
95 if (dev_priv->card_type >= NV_50)
96 pci_nv_20 = 0x88050;
97 else
98 pci_nv_20 = NV_PBUS_PCI_NV_20;
99
100 /* enable ROM access */
101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
102 nvWriteMC(dev, pci_nv_20,
103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104
105 /* bail if no rom signature */
106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
108 goto out;
109
110 /* additional check (see note below) - read PCI record header */
111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
117 goto out;
118
119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
120 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
121 * each byte. we'll hope pramin has something usable instead
122 */
123 for (i = 0; i < NV_PROM_SIZE; i++)
124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
125
126out:
127 /* disable ROM access */
128 nvWriteMC(dev, pci_nv_20,
129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
130}
131
132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133{
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 uint32_t old_bar0_pramin = 0;
136 int i;
137
138 if (dev_priv->card_type >= NV_50) {
139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
140
141 if (!vbios_vram)
142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, vbios_vram >> 16);
146 }
147
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
151 goto out;
152
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
155
156out:
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
159}
160
161static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162{
163 void __iomem *rom = NULL;
164 size_t rom_len;
165 int ret;
166
167 ret = pci_enable_rom(dev->pdev);
168 if (ret)
169 return;
170
171 rom = pci_map_rom(dev->pdev, &rom_len);
172 if (!rom)
173 goto out;
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
176
177out:
178 pci_disable_rom(dev->pdev);
179}
180
181struct methods {
182 const char desc[8];
183 void (*loadbios)(struct drm_device *, uint8_t *);
184 const bool rw;
6ee73861
BS		 185};
186
187static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 191};
192
193static struct methods nv50_methods[] = {
194 { "PRAMIN", load_vbios_pramin, true },
195 { "PROM", load_vbios_prom, false },
196 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 197};
198
657b6245
MK		 199#define METHODCNT 3
200
6ee73861
BS		 201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{
203 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 204 struct methods *methods;
205 int i;
6ee73861 206 int testscore = 3;
657b6245 207 int scores[METHODCNT];
6ee73861
BS		 208
209 if (nouveau_vbios) {
657b6245
MK		 210 methods = nv04_methods;
211 for (i = 0; i < METHODCNT; i++)
212 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 213 break;
6ee73861 214
657b6245 215 if (i < METHODCNT) {
6ee73861 216 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 217 methods[i].desc);
6ee73861 218
657b6245
MK		 219 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 221 return true;
222 }
223
224 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
225 }
226
227 if (dev_priv->card_type < NV_50)
228 methods = nv04_methods;
229 else
230 methods = nv50_methods;
231
657b6245 232 for (i = 0; i < METHODCNT; i++) {
6ee73861 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 234 methods[i].desc);
6ee73861 235 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 236 methods[i].loadbios(dev, data);
237 scores[i] = score_vbios(dev, data, methods[i].rw);
238 if (scores[i] == testscore)
6ee73861 239 return true;
6ee73861
BS		 240 }
241
242 while (--testscore > 0) {
657b6245
MK		 243 for (i = 0; i < METHODCNT; i++) {
244 if (scores[i] == testscore) {
6ee73861 245 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 246 methods[i].desc);
247 methods[i].loadbios(dev, data);
6ee73861
BS		 248 return true;
249 }
6ee73861
BS		 250 }
251 }
252
253 NV_ERROR(dev, "No valid BIOS image found\n");
254 return false;
255}
256
257struct init_tbl_entry {
258 char *name;
259 uint8_t id;
9170a824
BS		 260 /* Return:
261 * > 0: success, length of opcode
262 * 0: success, but abort further parsing of table (INIT_DONE etc)
263 * < 0: failure, table parsing will be aborted
264 */
37383650 265 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 266};
267
268struct bit_entry {
269 uint8_t id[2];
270 uint16_t length;
271 uint16_t offset;
272};
273
274static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
275
276#define MACRO_INDEX_SIZE 2
277#define MACRO_SIZE 8
278#define CONDITION_SIZE 12
279#define IO_FLAG_CONDITION_SIZE 9
280#define IO_CONDITION_SIZE 5
281#define MEM_INIT_SIZE 66
282
283static void still_alive(void)
284{
285#if 0
286 sync();
287 msleep(2);
288#endif
289}
290
291static uint32_t
292munge_reg(struct nvbios *bios, uint32_t reg)
293{
294 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
295 struct dcb_entry *dcbent = bios->display.output;
296
297 if (dev_priv->card_type < NV_50)
298 return reg;
299
300 if (reg & 0x40000000) {
301 BUG_ON(!dcbent);
302
303 reg += (ffs(dcbent->or) - 1) * 0x800;
304 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
305 reg += 0x00000080;
306 }
307
308 reg &= ~0x60000000;
309 return reg;
310}
311
312static int
313valid_reg(struct nvbios *bios, uint32_t reg)
314{
315 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
316 struct drm_device *dev = bios->dev;
317
318 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 319 if (reg & 0x2 ||
04a39c57 320 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 321 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
322
323 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 324 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 325 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
326 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
327 reg);
328
9855e584
BS		 329 if (reg >= (8*1024*1024)) {
330 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
331 return 0;
6ee73861 332 }
9855e584
BS		 333
334 return 1;
6ee73861
BS		 335}
336
337static bool
338valid_idx_port(struct nvbios *bios, uint16_t port)
339{
340 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
341 struct drm_device *dev = bios->dev;
342
343 /*
344 * If adding more ports here, the read/write functions below will need
345 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
346 * used for the port in question
347 */
348 if (dev_priv->card_type < NV_50) {
349 if (port == NV_CIO_CRX__COLOR)
350 return true;
351 if (port == NV_VIO_SRX)
352 return true;
353 } else {
354 if (port == NV_CIO_CRX__COLOR)
355 return true;
356 }
357
358 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
359 port);
360
361 return false;
362}
363
364static bool
365valid_port(struct nvbios *bios, uint16_t port)
366{
367 struct drm_device *dev = bios->dev;
368
369 /*
370 * If adding more ports here, the read/write functions below will need
371 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
372 * used for the port in question
373 */
374 if (port == NV_VIO_VSE2)
375 return true;
376
377 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
378
379 return false;
380}
381
382static uint32_t
383bios_rd32(struct nvbios *bios, uint32_t reg)
384{
385 uint32_t data;
386
387 reg = munge_reg(bios, reg);
388 if (!valid_reg(bios, reg))
389 return 0;
390
391 /*
392 * C51 sometimes uses regs with bit0 set in the address. For these
393 * cases there should exist a translation in a BIOS table to an IO
394 * port address which the BIOS uses for accessing the reg
395 *
396 * These only seem to appear for the power control regs to a flat panel,
397 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
398 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
399 * suspend-resume mmio trace from a C51 will be required to see if this
400 * is true for the power microcode in 0x14.., or whether the direct IO
401 * port access method is needed
402 */
403 if (reg & 0x1)
404 reg &= ~0x1;
405
406 data = nv_rd32(bios->dev, reg);
407
408 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
409
410 return data;
411}
412
413static void
414bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
415{
416 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
417
418 reg = munge_reg(bios, reg);
419 if (!valid_reg(bios, reg))
420 return;
421
422 /* see note in bios_rd32 */
423 if (reg & 0x1)
424 reg &= 0xfffffffe;
425
426 LOG_OLD_VALUE(bios_rd32(bios, reg));
427 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
428
04a39c57 429 if (dev_priv->vbios.execute) {
6ee73861
BS		 430 still_alive();
431 nv_wr32(bios->dev, reg, data);
432 }
433}
434
435static uint8_t
436bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
437{
438 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
439 struct drm_device *dev = bios->dev;
440 uint8_t data;
441
442 if (!valid_idx_port(bios, port))
443 return 0;
444
445 if (dev_priv->card_type < NV_50) {
446 if (port == NV_VIO_SRX)
447 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
448 else /* assume NV_CIO_CRX__COLOR */
449 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
450 } else {
451 uint32_t data32;
452
453 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
454 data = (data32 >> ((index & 3) << 3)) & 0xff;
455 }
456
457 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
458 "Head: 0x%02X, Data: 0x%02X\n",
459 port, index, bios->state.crtchead, data);
460 return data;
461}
462
463static void
464bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
465{
466 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
467 struct drm_device *dev = bios->dev;
468
469 if (!valid_idx_port(bios, port))
470 return;
471
472 /*
473 * The current head is maintained in the nvbios member state.crtchead.
474 * We trap changes to CR44 and update the head variable and hence the
475 * register set written.
476 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
477 * of the write, and to head1 after the write
478 */
479 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
480 data != NV_CIO_CRE_44_HEADB)
481 bios->state.crtchead = 0;
482
483 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
484 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
485 "Head: 0x%02X, Data: 0x%02X\n",
486 port, index, bios->state.crtchead, data);
487
488 if (bios->execute && dev_priv->card_type < NV_50) {
489 still_alive();
490 if (port == NV_VIO_SRX)
491 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
492 else /* assume NV_CIO_CRX__COLOR */
493 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
494 } else
495 if (bios->execute) {
496 uint32_t data32, shift = (index & 3) << 3;
497
498 still_alive();
499
500 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
501 data32 &= ~(0xff << shift);
502 data32 |= (data << shift);
503 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
504 }
505
506 if (port == NV_CIO_CRX__COLOR &&
507 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
508 bios->state.crtchead = 1;
509}
510
511static uint8_t
512bios_port_rd(struct nvbios *bios, uint16_t port)
513{
514 uint8_t data, head = bios->state.crtchead;
515
516 if (!valid_port(bios, port))
517 return 0;
518
519 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
520
521 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
522 port, head, data);
523
524 return data;
525}
526
527static void
528bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
529{
530 int head = bios->state.crtchead;
531
532 if (!valid_port(bios, port))
533 return;
534
535 LOG_OLD_VALUE(bios_port_rd(bios, port));
536 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
537 port, head, data);
538
539 if (!bios->execute)
540 return;
541
542 still_alive();
543 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
544}
545
546static bool
547io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
548{
549 /*
550 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
551 * for the CRTC index; 1 byte for the mask to apply to the value
552 * retrieved from the CRTC; 1 byte for the shift right to apply to the
553 * masked CRTC value; 2 bytes for the offset to the flag array, to
554 * which the shifted value is added; 1 byte for the mask applied to the
555 * value read from the flag array; and 1 byte for the value to compare
556 * against the masked byte from the flag table.
557 */
558
559 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
560 uint16_t crtcport = ROM16(bios->data[condptr]);
561 uint8_t crtcindex = bios->data[condptr + 2];
562 uint8_t mask = bios->data[condptr + 3];
563 uint8_t shift = bios->data[condptr + 4];
564 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
565 uint8_t flagarraymask = bios->data[condptr + 7];
566 uint8_t cmpval = bios->data[condptr + 8];
567 uint8_t data;
568
569 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
570 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
571 "Cmpval: 0x%02X\n",
572 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
573
574 data = bios_idxprt_rd(bios, crtcport, crtcindex);
575
576 data = bios->data[flagarray + ((data & mask) >> shift)];
577 data &= flagarraymask;
578
579 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
580 offset, data, cmpval);
581
582 return (data == cmpval);
583}
584
585static bool
586bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
587{
588 /*
589 * The condition table entry has 4 bytes for the address of the
590 * register to check, 4 bytes for a mask to apply to the register and
591 * 4 for a test comparison value
592 */
593
594 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
595 uint32_t reg = ROM32(bios->data[condptr]);
596 uint32_t mask = ROM32(bios->data[condptr + 4]);
597 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
598 uint32_t data;
599
600 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
601 offset, cond, reg, mask);
602
603 data = bios_rd32(bios, reg) & mask;
604
605 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
606 offset, data, cmpval);
607
608 return (data == cmpval);
609}
610
611static bool
612io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
613{
614 /*
615 * The IO condition entry has 2 bytes for the IO port address; 1 byte
616 * for the index to write to io_port; 1 byte for the mask to apply to
617 * the byte read from io_port+1; and 1 byte for the value to compare
618 * against the masked byte.
619 */
620
621 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
622 uint16_t io_port = ROM16(bios->data[condptr]);
623 uint8_t port_index = bios->data[condptr + 2];
624 uint8_t mask = bios->data[condptr + 3];
625 uint8_t cmpval = bios->data[condptr + 4];
626
627 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
628
629 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
630 offset, data, cmpval);
631
632 return (data == cmpval);
633}
634
635static int
636nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
637{
638 struct drm_nouveau_private *dev_priv = dev->dev_private;
639 uint32_t reg0 = nv_rd32(dev, reg + 0);
640 uint32_t reg1 = nv_rd32(dev, reg + 4);
641 struct nouveau_pll_vals pll;
642 struct pll_lims pll_limits;
643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
653 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
654 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
655
04a39c57 656 if (dev_priv->vbios.execute) {
6ee73861
BS		 657 still_alive();
658 nv_wr32(dev, reg + 4, reg1);
659 nv_wr32(dev, reg + 0, reg0);
660 }
661
662 return 0;
663}
664
665static int
666setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
667{
668 struct drm_device *dev = bios->dev;
669 struct drm_nouveau_private *dev_priv = dev->dev_private;
670 /* clk in kHz */
671 struct pll_lims pll_lim;
672 struct nouveau_pll_vals pllvals;
673 int ret;
674
675 if (dev_priv->card_type >= NV_50)
676 return nv50_pll_set(dev, reg, clk);
677
678 /* high regs (such as in the mac g5 table) are not -= 4 */
679 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
680 if (ret)
681 return ret;
682
683 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
684 if (!clk)
685 return -ERANGE;
686
687 if (bios->execute) {
688 still_alive();
689 nouveau_hw_setpll(dev, reg, &pllvals);
690 }
691
692 return 0;
693}
694
695static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
696{
697 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 698 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 699
700 /*
701 * For the results of this function to be correct, CR44 must have been
702 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
703 * and the DCB table parsed, before the script calling the function is
704 * run. run_digital_op_script is example of how to do such setup
705 */
706
707 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
708
7f245b20 709 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 710 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
711 "(%02X)\n", dcb_entry);
712 dcb_entry = 0x7f; /* unused / invalid marker */
713 }
714
715 return dcb_entry;
716}
717
f8b0be1a
BS		 718static int
719read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
720{
721 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
722 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
723 int recordoffset = 0, rdofs = 1, wrofs = 0;
724 uint8_t port_type = 0;
725
726 if (!i2ctable)
727 return -EINVAL;
728
729 if (dcb_version >= 0x30) {
730 if (i2ctable[0] != dcb_version) /* necessary? */
731 NV_WARN(dev,
732 "DCB I2C table version mismatch (%02X vs %02X)\n",
733 i2ctable[0], dcb_version);
734 dcb_i2c_ver = i2ctable[0];
735 headerlen = i2ctable[1];
736 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
737 i2c_entries = i2ctable[2];
738 else
739 NV_WARN(dev,
740 "DCB I2C table has more entries than indexable "
741 "(%d entries, max %d)\n", i2ctable[2],
742 DCB_MAX_NUM_I2C_ENTRIES);
743 entry_len = i2ctable[3];
744 /* [4] is i2c_default_indices, read in parse_dcb_table() */
745 }
746 /*
747 * It's your own fault if you call this function on a DCB 1.1 BIOS --
748 * the test below is for DCB 1.2
749 */
750 if (dcb_version < 0x14) {
751 recordoffset = 2;
752 rdofs = 0;
753 wrofs = 1;
754 }
755
756 if (index == 0xf)
757 return 0;
758 if (index >= i2c_entries) {
759 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
760 index, i2ctable[2]);
761 return -ENOENT;
762 }
763 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
764 NV_ERROR(dev, "DCB I2C entry invalid\n");
765 return -EINVAL;
766 }
767
768 if (dcb_i2c_ver >= 0x30) {
769 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
770
771 /*
772 * Fixup for chips using same address offset for read and
773 * write.
774 */
775 if (port_type == 4) /* seen on C51 */
776 rdofs = wrofs = 1;
777 if (port_type >= 5) /* G80+ */
778 rdofs = wrofs = 0;
779 }
780
781 if (dcb_i2c_ver >= 0x40) {
782 if (port_type != 5 && port_type != 6)
783 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
784
785 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
786 }
787
788 i2c->port_type = port_type;
789 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
790 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
791
792 return 0;
793}
794
6ee73861
BS		 795static struct nouveau_i2c_chan *
796init_i2c_device_find(struct drm_device *dev, int i2c_index)
797{
798 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 799 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 800
801 if (i2c_index == 0xff) {
802 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
803 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 804 int default_indices = dcb->i2c_default_indices;
6ee73861 805
7f245b20 806 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 807 shift = 4;
808
809 i2c_index = (default_indices >> shift) & 0xf;
810 }
811 if (i2c_index == 0x80) /* g80+ */
7f245b20 812 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 813 else
814 if (i2c_index == 0x81)
815 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 816
f8b0be1a
BS		 817 if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) {
818 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
819 return NULL;
820 }
821
822 /* Make sure i2c table entry has been parsed, it may not
823 * have been if this is a bus not referenced by a DCB encoder
824 */
825 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
826 i2c_index, &dcb->i2c[i2c_index]);
827
6ee73861
BS		 828 return nouveau_i2c_find(dev, i2c_index);
829}
830
7f245b20
BS		 831static uint32_t
832get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 833{
834 /*
835 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
836 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
837 * CR58 for CR57 = 0 to index a table of offsets to the basic
838 * 0x6808b0 address.
839 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
840 * CR58 for CR57 = 0 to index a table of offsets to the basic
841 * 0x6808b0 address, and then flip the offset by 8.
842 */
843
844 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 845 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 846 const int pramdac_offset[13] = {
847 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
848 const uint32_t pramdac_table[4] = {
849 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
850
851 if (mlv >= 0x80) {
852 int dcb_entry, dacoffset;
853
854 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
855 dcb_entry = dcb_entry_idx_from_crtchead(dev);
856 if (dcb_entry == 0x7f)
857 return 0;
7f245b20 858 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 859 if (mlv == 0x81)
860 dacoffset ^= 8;
861 return 0x6808b0 + dacoffset;
862 } else {
df31ef4d 863 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 864 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
865 mlv);
866 return 0;
867 }
868 return pramdac_table[mlv];
869 }
870}
871
37383650 872static int
6ee73861
BS		 873init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
874 struct init_exec *iexec)
875{
876 /*
877 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
878 *
879 * offset (8 bit): opcode
880 * offset + 1 (16 bit): CRTC port
881 * offset + 3 (8 bit): CRTC index
882 * offset + 4 (8 bit): mask
883 * offset + 5 (8 bit): shift
884 * offset + 6 (8 bit): count
885 * offset + 7 (32 bit): register
886 * offset + 11 (32 bit): configuration 1
887 * ...
888 *
889 * Starting at offset + 11 there are "count" 32 bit values.
890 * To find out which value to use read index "CRTC index" on "CRTC
891 * port", AND this value with "mask" and then bit shift right "shift"
892 * bits. Read the appropriate value using this index and write to
893 * "register"
894 */
895
896 uint16_t crtcport = ROM16(bios->data[offset + 1]);
897 uint8_t crtcindex = bios->data[offset + 3];
898 uint8_t mask = bios->data[offset + 4];
899 uint8_t shift = bios->data[offset + 5];
900 uint8_t count = bios->data[offset + 6];
901 uint32_t reg = ROM32(bios->data[offset + 7]);
902 uint8_t config;
903 uint32_t configval;
37383650 904 int len = 11 + count * 4;
6ee73861
BS		 905
906 if (!iexec->execute)
37383650 907 return len;
6ee73861
BS		 908
909 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
910 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
911 offset, crtcport, crtcindex, mask, shift, count, reg);
912
913 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
914 if (config > count) {
915 NV_ERROR(bios->dev,
916 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
917 offset, config, count);
9170a824 918 return -EINVAL;
6ee73861
BS		 919 }
920
921 configval = ROM32(bios->data[offset + 11 + config * 4]);
922
923 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
924
925 bios_wr32(bios, reg, configval);
926
37383650 927 return len;
6ee73861
BS		 928}
929
37383650 930static int
6ee73861
BS		 931init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
932{
933 /*
934 * INIT_REPEAT opcode: 0x33 ('3')
935 *
936 * offset (8 bit): opcode
937 * offset + 1 (8 bit): count
938 *
939 * Execute script following this opcode up to INIT_REPEAT_END
940 * "count" times
941 */
942
943 uint8_t count = bios->data[offset + 1];
944 uint8_t i;
945
946 /* no iexec->execute check by design */
947
948 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
949 offset, count);
950
951 iexec->repeat = true;
952
953 /*
954 * count - 1, as the script block will execute once when we leave this
955 * opcode -- this is compatible with bios behaviour as:
956 * a) the block is always executed at least once, even if count == 0
957 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
958 * while we don't
959 */
960 for (i = 0; i < count - 1; i++)
961 parse_init_table(bios, offset + 2, iexec);
962
963 iexec->repeat = false;
964
37383650 965 return 2;
6ee73861
BS		 966}
967
37383650 968static int
6ee73861
BS		 969init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
970 struct init_exec *iexec)
971{
972 /*
973 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
974 *
975 * offset (8 bit): opcode
976 * offset + 1 (16 bit): CRTC port
977 * offset + 3 (8 bit): CRTC index
978 * offset + 4 (8 bit): mask
979 * offset + 5 (8 bit): shift
980 * offset + 6 (8 bit): IO flag condition index
981 * offset + 7 (8 bit): count
982 * offset + 8 (32 bit): register
983 * offset + 12 (16 bit): frequency 1
984 * ...
985 *
986 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
987 * Set PLL register "register" to coefficients for frequency n,
988 * selected by reading index "CRTC index" of "CRTC port" ANDed with
989 * "mask" and shifted right by "shift".
990 *
991 * If "IO flag condition index" > 0, and condition met, double
992 * frequency before setting it.
993 */
994
995 uint16_t crtcport = ROM16(bios->data[offset + 1]);
996 uint8_t crtcindex = bios->data[offset + 3];
997 uint8_t mask = bios->data[offset + 4];
998 uint8_t shift = bios->data[offset + 5];
999 int8_t io_flag_condition_idx = bios->data[offset + 6];
1000 uint8_t count = bios->data[offset + 7];
1001 uint32_t reg = ROM32(bios->data[offset + 8]);
1002 uint8_t config;
1003 uint16_t freq;
37383650 1004 int len = 12 + count * 2;
6ee73861
BS		 1005
1006 if (!iexec->execute)
37383650 1007 return len;
6ee73861
BS		 1008
1009 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1010 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1011 "Count: 0x%02X, Reg: 0x%08X\n",
1012 offset, crtcport, crtcindex, mask, shift,
1013 io_flag_condition_idx, count, reg);
1014
1015 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1016 if (config > count) {
1017 NV_ERROR(bios->dev,
1018 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1019 offset, config, count);
9170a824 1020 return -EINVAL;
6ee73861
BS		 1021 }
1022
1023 freq = ROM16(bios->data[offset + 12 + config * 2]);
1024
1025 if (io_flag_condition_idx > 0) {
1026 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1027 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1028 "frequency doubled\n", offset);
1029 freq *= 2;
1030 } else
1031 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1032 "frequency unchanged\n", offset);
1033 }
1034
1035 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1036 offset, reg, config, freq);
1037
1038 setPLL(bios, reg, freq * 10);
1039
37383650 1040 return len;
6ee73861
BS		 1041}
1042
37383650 1043static int
6ee73861
BS		 1044init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1045{
1046 /*
1047 * INIT_END_REPEAT opcode: 0x36 ('6')
1048 *
1049 * offset (8 bit): opcode
1050 *
1051 * Marks the end of the block for INIT_REPEAT to repeat
1052 */
1053
1054 /* no iexec->execute check by design */
1055
1056 /*
1057 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1058 * we're not in repeat mode
1059 */
1060 if (iexec->repeat)
37383650 1061 return 0;
6ee73861 1062
37383650 1063 return 1;
6ee73861
BS		 1064}
1065
37383650 1066static int
6ee73861
BS		 1067init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1068{
1069 /*
1070 * INIT_COPY opcode: 0x37 ('7')
1071 *
1072 * offset (8 bit): opcode
1073 * offset + 1 (32 bit): register
1074 * offset + 5 (8 bit): shift
1075 * offset + 6 (8 bit): srcmask
1076 * offset + 7 (16 bit): CRTC port
1077 * offset + 9 (8 bit): CRTC index
1078 * offset + 10 (8 bit): mask
1079 *
1080 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1081 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1082 * port
1083 */
1084
1085 uint32_t reg = ROM32(bios->data[offset + 1]);
1086 uint8_t shift = bios->data[offset + 5];
1087 uint8_t srcmask = bios->data[offset + 6];
1088 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1089 uint8_t crtcindex = bios->data[offset + 9];
1090 uint8_t mask = bios->data[offset + 10];
1091 uint32_t data;
1092 uint8_t crtcdata;
1093
1094 if (!iexec->execute)
37383650 1095 return 11;
6ee73861
BS		 1096
1097 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1098 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1099 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1100
1101 data = bios_rd32(bios, reg);
1102
1103 if (shift < 0x80)
1104 data >>= shift;
1105 else
1106 data <<= (0x100 - shift);
1107
1108 data &= srcmask;
1109
1110 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1111 crtcdata |= (uint8_t)data;
1112 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1113
37383650 1114 return 11;
6ee73861
BS		 1115}
1116
37383650 1117static int
6ee73861
BS		 1118init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1119{
1120 /*
1121 * INIT_NOT opcode: 0x38 ('8')
1122 *
1123 * offset (8 bit): opcode
1124 *
1125 * Invert the current execute / no-execute condition (i.e. "else")
1126 */
1127 if (iexec->execute)
1128 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1129 else
1130 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1131
1132 iexec->execute = !iexec->execute;
37383650 1133 return 1;
6ee73861
BS		 1134}
1135
37383650 1136static int
6ee73861
BS		 1137init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1138 struct init_exec *iexec)
1139{
1140 /*
1141 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1142 *
1143 * offset (8 bit): opcode
1144 * offset + 1 (8 bit): condition number
1145 *
1146 * Check condition "condition number" in the IO flag condition table.
1147 * If condition not met skip subsequent opcodes until condition is
1148 * inverted (INIT_NOT), or we hit INIT_RESUME
1149 */
1150
1151 uint8_t cond = bios->data[offset + 1];
1152
1153 if (!iexec->execute)
37383650 1154 return 2;
6ee73861
BS		 1155
1156 if (io_flag_condition_met(bios, offset, cond))
1157 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1158 else {
1159 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1160 iexec->execute = false;
1161 }
1162
37383650 1163 return 2;
6ee73861
BS		 1164}
1165
25908b77
BS		 1166static int
1167init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1168{
1169 /*
1170 * INIT_DP_CONDITION opcode: 0x3A ('')
1171 *
1172 * offset (8 bit): opcode
1173 * offset + 1 (8 bit): "sub" opcode
1174 * offset + 2 (8 bit): unknown
1175 *
1176 */
1177
1178 struct bit_displayport_encoder_table *dpe = NULL;
1179 struct dcb_entry *dcb = bios->display.output;
1180 struct drm_device *dev = bios->dev;
1181 uint8_t cond = bios->data[offset + 1];
1182 int dummy;
1183
1184 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1185
1186 if (!iexec->execute)
1187 return 3;
1188
1189 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1190 if (!dpe) {
1191 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1192 return -EINVAL;
1193 }
1194
1195 switch (cond) {
1196 case 0:
1197 {
1198 struct dcb_connector_table_entry *ent =
1199 &bios->dcb.connector.entry[dcb->connector];
1200
1201 if (ent->type != DCB_CONNECTOR_eDP)
1202 iexec->execute = false;
1203 }
1204 break;
1205 case 1:
1206 case 2:
1207 if (!(dpe->unknown & cond))
1208 iexec->execute = false;
1209 break;
1210 case 5:
1211 {
1212 struct nouveau_i2c_chan *auxch;
1213 int ret;
1214
1215 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1216 if (!auxch)
1217 return -ENODEV;
1218
1219 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1220 if (ret)
1221 return ret;
1222
1223 if (cond & 1)
1224 iexec->execute = false;
1225 }
1226 break;
1227 default:
1228 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1229 break;
1230 }
1231
1232 if (iexec->execute)
1233 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1234 else
1235 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1236
1237 return 3;
1238}
1239
1240static int
1241init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1242{
1243 /*
1244 * INIT_3B opcode: 0x3B ('')
1245 *
1246 * offset (8 bit): opcode
1247 * offset + 1 (8 bit): crtc index
1248 *
1249 */
1250
1251 uint8_t or = ffs(bios->display.output->or) - 1;
1252 uint8_t index = bios->data[offset + 1];
1253 uint8_t data;
1254
1255 if (!iexec->execute)
1256 return 2;
1257
1258 data = bios_idxprt_rd(bios, 0x3d4, index);
1259 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1260 return 2;
1261}
1262
1263static int
1264init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1265{
1266 /*
1267 * INIT_3C opcode: 0x3C ('')
1268 *
1269 * offset (8 bit): opcode
1270 * offset + 1 (8 bit): crtc index
1271 *
1272 */
1273
1274 uint8_t or = ffs(bios->display.output->or) - 1;
1275 uint8_t index = bios->data[offset + 1];
1276 uint8_t data;
1277
1278 if (!iexec->execute)
1279 return 2;
1280
1281 data = bios_idxprt_rd(bios, 0x3d4, index);
1282 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1283 return 2;
1284}
1285
37383650 1286static int
6ee73861
BS		 1287init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1288 struct init_exec *iexec)
1289{
1290 /*
1291 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1292 *
1293 * offset (8 bit): opcode
1294 * offset + 1 (32 bit): control register
1295 * offset + 5 (32 bit): data register
1296 * offset + 9 (32 bit): mask
1297 * offset + 13 (32 bit): data
1298 * offset + 17 (8 bit): count
1299 * offset + 18 (8 bit): address 1
1300 * offset + 19 (8 bit): data 1
1301 * ...
1302 *
1303 * For each of "count" address and data pairs, write "data n" to
1304 * "data register", read the current value of "control register",
1305 * and write it back once ANDed with "mask", ORed with "data",
1306 * and ORed with "address n"
1307 */
1308
1309 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1310 uint32_t datareg = ROM32(bios->data[offset + 5]);
1311 uint32_t mask = ROM32(bios->data[offset + 9]);
1312 uint32_t data = ROM32(bios->data[offset + 13]);
1313 uint8_t count = bios->data[offset + 17];
37383650 1314 int len = 18 + count * 2;
6ee73861
BS		 1315 uint32_t value;
1316 int i;
1317
1318 if (!iexec->execute)
37383650 1319 return len;
6ee73861
BS		 1320
1321 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1322 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1323 offset, controlreg, datareg, mask, data, count);
1324
1325 for (i = 0; i < count; i++) {
1326 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1327 uint8_t instdata = bios->data[offset + 19 + i * 2];
1328
1329 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1330 offset, instaddress, instdata);
1331
1332 bios_wr32(bios, datareg, instdata);
1333 value = bios_rd32(bios, controlreg) & mask;
1334 value |= data;
1335 value |= instaddress;
1336 bios_wr32(bios, controlreg, value);
1337 }
1338
37383650 1339 return len;
6ee73861
BS		 1340}
1341
37383650 1342static int
6ee73861
BS		 1343init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1344 struct init_exec *iexec)
1345{
1346 /*
1347 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1348 *
1349 * offset (8 bit): opcode
1350 * offset + 1 (16 bit): CRTC port
1351 * offset + 3 (8 bit): CRTC index
1352 * offset + 4 (8 bit): mask
1353 * offset + 5 (8 bit): shift
1354 * offset + 6 (8 bit): count
1355 * offset + 7 (32 bit): register
1356 * offset + 11 (32 bit): frequency 1
1357 * ...
1358 *
1359 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1360 * Set PLL register "register" to coefficients for frequency n,
1361 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1362 * "mask" and shifted right by "shift".
1363 */
1364
1365 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1366 uint8_t crtcindex = bios->data[offset + 3];
1367 uint8_t mask = bios->data[offset + 4];
1368 uint8_t shift = bios->data[offset + 5];
1369 uint8_t count = bios->data[offset + 6];
1370 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1371 int len = 11 + count * 4;
6ee73861
BS		 1372 uint8_t config;
1373 uint32_t freq;
1374
1375 if (!iexec->execute)
37383650 1376 return len;
6ee73861
BS		 1377
1378 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1379 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1380 offset, crtcport, crtcindex, mask, shift, count, reg);
1381
1382 if (!reg)
37383650 1383 return len;
6ee73861
BS		 1384
1385 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1386 if (config > count) {
1387 NV_ERROR(bios->dev,
1388 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1389 offset, config, count);
9170a824 1390 return -EINVAL;
6ee73861
BS		 1391 }
1392
1393 freq = ROM32(bios->data[offset + 11 + config * 4]);
1394
1395 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1396 offset, reg, config, freq);
1397
1398 setPLL(bios, reg, freq);
1399
37383650 1400 return len;
6ee73861
BS		 1401}
1402
37383650 1403static int
6ee73861
BS		 1404init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1405{
1406 /*
1407 * INIT_PLL2 opcode: 0x4B ('K')
1408 *
1409 * offset (8 bit): opcode
1410 * offset + 1 (32 bit): register
1411 * offset + 5 (32 bit): freq
1412 *
1413 * Set PLL register "register" to coefficients for frequency "freq"
1414 */
1415
1416 uint32_t reg = ROM32(bios->data[offset + 1]);
1417 uint32_t freq = ROM32(bios->data[offset + 5]);
1418
1419 if (!iexec->execute)
37383650 1420 return 9;
6ee73861
BS		 1421
1422 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1423 offset, reg, freq);
1424
1425 setPLL(bios, reg, freq);
37383650 1426 return 9;
6ee73861
BS		 1427}
1428
37383650 1429static int
6ee73861
BS		 1430init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1431{
1432 /*
1433 * INIT_I2C_BYTE opcode: 0x4C ('L')
1434 *
1435 * offset (8 bit): opcode
1436 * offset + 1 (8 bit): DCB I2C table entry index
1437 * offset + 2 (8 bit): I2C slave address
1438 * offset + 3 (8 bit): count
1439 * offset + 4 (8 bit): I2C register 1
1440 * offset + 5 (8 bit): mask 1
1441 * offset + 6 (8 bit): data 1
1442 * ...
1443 *
1444 * For each of "count" registers given by "I2C register n" on the device
1445 * addressed by "I2C slave address" on the I2C bus given by
1446 * "DCB I2C table entry index", read the register, AND the result with
1447 * "mask n" and OR it with "data n" before writing it back to the device
1448 */
1449
1450 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1451 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1452 uint8_t count = bios->data[offset + 3];
1453 struct nouveau_i2c_chan *chan;
893887ed
BS		 1454 int len = 4 + count * 3;
1455 int ret, i;
6ee73861
BS		 1456
1457 if (!iexec->execute)
37383650 1458 return len;
6ee73861
BS		 1459
1460 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1461 "Count: 0x%02X\n",
1462 offset, i2c_index, i2c_address, count);
1463
1464 chan = init_i2c_device_find(bios->dev, i2c_index);
1465 if (!chan)
9170a824 1466 return -ENODEV;
6ee73861
BS		 1467
1468 for (i = 0; i < count; i++) {
893887ed 1469 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1470 uint8_t mask = bios->data[offset + 5 + i * 3];
1471 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1472 union i2c_smbus_data val;
6ee73861 1473
893887ed
BS		 1474 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1475 I2C_SMBUS_READ, reg,
1476 I2C_SMBUS_BYTE_DATA, &val);
1477 if (ret < 0)
1478 return ret;
6ee73861
BS		 1479
1480 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1481 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1482 offset, reg, val.byte, mask, data);
6ee73861 1483
893887ed
BS		 1484 if (!bios->execute)
1485 continue;
6ee73861 1486
893887ed
BS		 1487 val.byte &= mask;
1488 val.byte |= data;
1489 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1490 I2C_SMBUS_WRITE, reg,
1491 I2C_SMBUS_BYTE_DATA, &val);
1492 if (ret < 0)
1493 return ret;
6ee73861
BS		 1494 }
1495
37383650 1496 return len;
6ee73861
BS		 1497}
1498
37383650 1499static int
6ee73861
BS		 1500init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1501{
1502 /*
1503 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1504 *
1505 * offset (8 bit): opcode
1506 * offset + 1 (8 bit): DCB I2C table entry index
1507 * offset + 2 (8 bit): I2C slave address
1508 * offset + 3 (8 bit): count
1509 * offset + 4 (8 bit): I2C register 1
1510 * offset + 5 (8 bit): data 1
1511 * ...
1512 *
1513 * For each of "count" registers given by "I2C register n" on the device
1514 * addressed by "I2C slave address" on the I2C bus given by
1515 * "DCB I2C table entry index", set the register to "data n"
1516 */
1517
1518 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1519 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1520 uint8_t count = bios->data[offset + 3];
1521 struct nouveau_i2c_chan *chan;
893887ed
BS		 1522 int len = 4 + count * 2;
1523 int ret, i;
6ee73861
BS		 1524
1525 if (!iexec->execute)
37383650 1526 return len;
6ee73861
BS		 1527
1528 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1529 "Count: 0x%02X\n",
1530 offset, i2c_index, i2c_address, count);
1531
1532 chan = init_i2c_device_find(bios->dev, i2c_index);
1533 if (!chan)
9170a824 1534 return -ENODEV;
6ee73861
BS		 1535
1536 for (i = 0; i < count; i++) {
893887ed
BS		 1537 uint8_t reg = bios->data[offset + 4 + i * 2];
1538 union i2c_smbus_data val;
1539
1540 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1541
1542 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1543 offset, reg, val.byte);
1544
1545 if (!bios->execute)
1546 continue;
1547
1548 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1549 I2C_SMBUS_WRITE, reg,
1550 I2C_SMBUS_BYTE_DATA, &val);
1551 if (ret < 0)
1552 return ret;
6ee73861
BS		 1553 }
1554
37383650 1555 return len;
6ee73861
BS		 1556}
1557
37383650 1558static int
6ee73861
BS		 1559init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1560{
1561 /*
1562 * INIT_ZM_I2C opcode: 0x4E ('N')
1563 *
1564 * offset (8 bit): opcode
1565 * offset + 1 (8 bit): DCB I2C table entry index
1566 * offset + 2 (8 bit): I2C slave address
1567 * offset + 3 (8 bit): count
1568 * offset + 4 (8 bit): data 1
1569 * ...
1570 *
1571 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1572 * address" on the I2C bus given by "DCB I2C table entry index"
1573 */
1574
1575 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1576 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1577 uint8_t count = bios->data[offset + 3];
37383650 1578 int len = 4 + count;
6ee73861
BS		 1579 struct nouveau_i2c_chan *chan;
1580 struct i2c_msg msg;
1581 uint8_t data[256];
1582 int i;
1583
1584 if (!iexec->execute)
37383650 1585 return len;
6ee73861
BS		 1586
1587 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1588 "Count: 0x%02X\n",
1589 offset, i2c_index, i2c_address, count);
1590
1591 chan = init_i2c_device_find(bios->dev, i2c_index);
1592 if (!chan)
9170a824 1593 return -ENODEV;
6ee73861
BS		 1594
1595 for (i = 0; i < count; i++) {
1596 data[i] = bios->data[offset + 4 + i];
1597
1598 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1599 }
1600
1601 if (bios->execute) {
1602 msg.addr = i2c_address;
1603 msg.flags = 0;
1604 msg.len = count;
1605 msg.buf = data;
1606 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1607 return -EIO;
6ee73861
BS		 1608 }
1609
37383650 1610 return len;
6ee73861
BS		 1611}
1612
37383650 1613static int
6ee73861
BS		 1614init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1615{
1616 /*
1617 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1618 *
1619 * offset (8 bit): opcode
1620 * offset + 1 (8 bit): magic lookup value
1621 * offset + 2 (8 bit): TMDS address
1622 * offset + 3 (8 bit): mask
1623 * offset + 4 (8 bit): data
1624 *
1625 * Read the data reg for TMDS address "TMDS address", AND it with mask
1626 * and OR it with data, then write it back
1627 * "magic lookup value" determines which TMDS base address register is
1628 * used -- see get_tmds_index_reg()
1629 */
1630
1631 uint8_t mlv = bios->data[offset + 1];
1632 uint32_t tmdsaddr = bios->data[offset + 2];
1633 uint8_t mask = bios->data[offset + 3];
1634 uint8_t data = bios->data[offset + 4];
1635 uint32_t reg, value;
1636
1637 if (!iexec->execute)
37383650 1638 return 5;
6ee73861
BS		 1639
1640 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1641 "Mask: 0x%02X, Data: 0x%02X\n",
1642 offset, mlv, tmdsaddr, mask, data);
1643
1644 reg = get_tmds_index_reg(bios->dev, mlv);
1645 if (!reg)
9170a824 1646 return -EINVAL;
6ee73861
BS		 1647
1648 bios_wr32(bios, reg,
1649 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1650 value = (bios_rd32(bios, reg + 4) & mask) | data;
1651 bios_wr32(bios, reg + 4, value);
1652 bios_wr32(bios, reg, tmdsaddr);
1653
37383650 1654 return 5;
6ee73861
BS		 1655}
1656
37383650 1657static int
6ee73861
BS		 1658init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1659 struct init_exec *iexec)
1660{
1661 /*
1662 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1663 *
1664 * offset (8 bit): opcode
1665 * offset + 1 (8 bit): magic lookup value
1666 * offset + 2 (8 bit): count
1667 * offset + 3 (8 bit): addr 1
1668 * offset + 4 (8 bit): data 1
1669 * ...
1670 *
1671 * For each of "count" TMDS address and data pairs write "data n" to
1672 * "addr n". "magic lookup value" determines which TMDS base address
1673 * register is used -- see get_tmds_index_reg()
1674 */
1675
1676 uint8_t mlv = bios->data[offset + 1];
1677 uint8_t count = bios->data[offset + 2];
37383650 1678 int len = 3 + count * 2;
6ee73861
BS		 1679 uint32_t reg;
1680 int i;
1681
1682 if (!iexec->execute)
37383650 1683 return len;
6ee73861
BS		 1684
1685 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1686 offset, mlv, count);
1687
1688 reg = get_tmds_index_reg(bios->dev, mlv);
1689 if (!reg)
9170a824 1690 return -EINVAL;
6ee73861
BS		 1691
1692 for (i = 0; i < count; i++) {
1693 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1694 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1695
1696 bios_wr32(bios, reg + 4, tmdsdata);
1697 bios_wr32(bios, reg, tmdsaddr);
1698 }
1699
37383650 1700 return len;
6ee73861
BS		 1701}
1702
37383650 1703static int
6ee73861
BS		 1704init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1705 struct init_exec *iexec)
1706{
1707 /*
1708 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1709 *
1710 * offset (8 bit): opcode
1711 * offset + 1 (8 bit): CRTC index1
1712 * offset + 2 (8 bit): CRTC index2
1713 * offset + 3 (8 bit): baseaddr
1714 * offset + 4 (8 bit): count
1715 * offset + 5 (8 bit): data 1
1716 * ...
1717 *
1718 * For each of "count" address and data pairs, write "baseaddr + n" to
1719 * "CRTC index1" and "data n" to "CRTC index2"
1720 * Once complete, restore initial value read from "CRTC index1"
1721 */
1722 uint8_t crtcindex1 = bios->data[offset + 1];
1723 uint8_t crtcindex2 = bios->data[offset + 2];
1724 uint8_t baseaddr = bios->data[offset + 3];
1725 uint8_t count = bios->data[offset + 4];
37383650 1726 int len = 5 + count;
6ee73861
BS		 1727 uint8_t oldaddr, data;
1728 int i;
1729
1730 if (!iexec->execute)
37383650 1731 return len;
6ee73861
BS		 1732
1733 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1734 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1735 offset, crtcindex1, crtcindex2, baseaddr, count);
1736
1737 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1738
1739 for (i = 0; i < count; i++) {
1740 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1741 baseaddr + i);
1742 data = bios->data[offset + 5 + i];
1743 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1744 }
1745
1746 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1747
37383650 1748 return len;
6ee73861
BS		 1749}
1750
37383650 1751static int
6ee73861
BS		 1752init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1753{
1754 /*
1755 * INIT_CR opcode: 0x52 ('R')
1756 *
1757 * offset (8 bit): opcode
1758 * offset + 1 (8 bit): CRTC index
1759 * offset + 2 (8 bit): mask
1760 * offset + 3 (8 bit): data
1761 *
1762 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1763 * data back to "CRTC index"
1764 */
1765
1766 uint8_t crtcindex = bios->data[offset + 1];
1767 uint8_t mask = bios->data[offset + 2];
1768 uint8_t data = bios->data[offset + 3];
1769 uint8_t value;
1770
1771 if (!iexec->execute)
37383650 1772 return 4;
6ee73861
BS		 1773
1774 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1775 offset, crtcindex, mask, data);
1776
1777 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1778 value |= data;
1779 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1780
37383650 1781 return 4;
6ee73861
BS		 1782}
1783
37383650 1784static int
6ee73861
BS		 1785init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1786{
1787 /*
1788 * INIT_ZM_CR opcode: 0x53 ('S')
1789 *
1790 * offset (8 bit): opcode
1791 * offset + 1 (8 bit): CRTC index
1792 * offset + 2 (8 bit): value
1793 *
1794 * Assign "value" to CRTC register with index "CRTC index".
1795 */
1796
1797 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1798 uint8_t data = bios->data[offset + 2];
1799
1800 if (!iexec->execute)
37383650 1801 return 3;
6ee73861
BS		 1802
1803 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1804
37383650 1805 return 3;
6ee73861
BS		 1806}
1807
37383650 1808static int
6ee73861
BS		 1809init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1810{
1811 /*
1812 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1813 *
1814 * offset (8 bit): opcode
1815 * offset + 1 (8 bit): count
1816 * offset + 2 (8 bit): CRTC index 1
1817 * offset + 3 (8 bit): value 1
1818 * ...
1819 *
1820 * For "count", assign "value n" to CRTC register with index
1821 * "CRTC index n".
1822 */
1823
1824 uint8_t count = bios->data[offset + 1];
37383650 1825 int len = 2 + count * 2;
6ee73861
BS		 1826 int i;
1827
1828 if (!iexec->execute)
37383650 1829 return len;
6ee73861
BS		 1830
1831 for (i = 0; i < count; i++)
1832 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1833
37383650 1834 return len;
6ee73861
BS		 1835}
1836
37383650 1837static int
6ee73861
BS		 1838init_condition_time(struct nvbios *bios, uint16_t offset,
1839 struct init_exec *iexec)
1840{
1841 /*
1842 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1843 *
1844 * offset (8 bit): opcode
1845 * offset + 1 (8 bit): condition number
1846 * offset + 2 (8 bit): retries / 50
1847 *
1848 * Check condition "condition number" in the condition table.
1849 * Bios code then sleeps for 2ms if the condition is not met, and
1850 * repeats up to "retries" times, but on one C51 this has proved
1851 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1852 * this, and bail after "retries" times, or 2s, whichever is less.
1853 * If still not met after retries, clear execution flag for this table.
1854 */
1855
1856 uint8_t cond = bios->data[offset + 1];
1857 uint16_t retries = bios->data[offset + 2] * 50;
1858 unsigned cnt;
1859
1860 if (!iexec->execute)
37383650 1861 return 3;
6ee73861
BS		 1862
1863 if (retries > 100)
1864 retries = 100;
1865
1866 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1867 offset, cond, retries);
1868
1869 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1870 retries = 1;
1871
1872 for (cnt = 0; cnt < retries; cnt++) {
1873 if (bios_condition_met(bios, offset, cond)) {
1874 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1875 offset);
1876 break;
1877 } else {
1878 BIOSLOG(bios, "0x%04X: "
1879 "Condition not met, sleeping for 20ms\n",
1880 offset);
1881 msleep(20);
1882 }
1883 }
1884
1885 if (!bios_condition_met(bios, offset, cond)) {
1886 NV_WARN(bios->dev,
1887 "0x%04X: Condition still not met after %dms, "
1888 "skipping following opcodes\n", offset, 20 * retries);
1889 iexec->execute = false;
1890 }
1891
37383650 1892 return 3;
6ee73861
BS		 1893}
1894
37383650 1895static int
6ee73861
BS		 1896init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1897 struct init_exec *iexec)
1898{
1899 /*
1900 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1901 *
1902 * offset (8 bit): opcode
1903 * offset + 1 (32 bit): base register
1904 * offset + 5 (8 bit): count
1905 * offset + 6 (32 bit): value 1
1906 * ...
1907 *
1908 * Starting at offset + 6 there are "count" 32 bit values.
1909 * For "count" iterations set "base register" + 4 * current_iteration
1910 * to "value current_iteration"
1911 */
1912
1913 uint32_t basereg = ROM32(bios->data[offset + 1]);
1914 uint32_t count = bios->data[offset + 5];
37383650 1915 int len = 6 + count * 4;
6ee73861
BS		 1916 int i;
1917
1918 if (!iexec->execute)
37383650 1919 return len;
6ee73861
BS		 1920
1921 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1922 offset, basereg, count);
1923
1924 for (i = 0; i < count; i++) {
1925 uint32_t reg = basereg + i * 4;
1926 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1927
1928 bios_wr32(bios, reg, data);
1929 }
1930
37383650 1931 return len;
6ee73861
BS		 1932}
1933
37383650 1934static int
6ee73861
BS		 1935init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1936{
1937 /*
1938 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1939 *
1940 * offset (8 bit): opcode
1941 * offset + 1 (16 bit): subroutine offset (in bios)
1942 *
1943 * Calls a subroutine that will execute commands until INIT_DONE
1944 * is found.
1945 */
1946
1947 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1948
1949 if (!iexec->execute)
37383650 1950 return 3;
6ee73861
BS		 1951
1952 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1953 offset, sub_offset);
1954
1955 parse_init_table(bios, sub_offset, iexec);
1956
1957 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1958
37383650 1959 return 3;
6ee73861
BS		 1960}
1961
37383650 1962static int
6ee73861
BS		 1963init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1964{
1965 /*
1966 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1967 *
1968 * offset (8 bit): opcode
1969 * offset + 1 (32 bit): src reg
1970 * offset + 5 (8 bit): shift
1971 * offset + 6 (32 bit): src mask
1972 * offset + 10 (32 bit): xor
1973 * offset + 14 (32 bit): dst reg
1974 * offset + 18 (32 bit): dst mask
1975 *
1976 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1977 * "src mask", then XOR with "xor". Write this OR'd with
1978 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1979 */
1980
1981 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1982 uint8_t shift = bios->data[offset + 5];
1983 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1984 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1985 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1986 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1987 uint32_t srcvalue, dstvalue;
1988
1989 if (!iexec->execute)
37383650 1990 return 22;
6ee73861
BS		 1991
1992 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1993 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1994 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1995
1996 srcvalue = bios_rd32(bios, srcreg);
1997
1998 if (shift < 0x80)
1999 srcvalue >>= shift;
2000 else
2001 srcvalue <<= (0x100 - shift);
2002
2003 srcvalue = (srcvalue & srcmask) ^ xor;
2004
2005 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2006
2007 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2008
37383650 2009 return 22;
6ee73861
BS		 2010}
2011
37383650 2012static int
6ee73861
BS		 2013init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2014{
2015 /*
2016 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2017 *
2018 * offset (8 bit): opcode
2019 * offset + 1 (16 bit): CRTC port
2020 * offset + 3 (8 bit): CRTC index
2021 * offset + 4 (8 bit): data
2022 *
2023 * Write "data" to index "CRTC index" of "CRTC port"
2024 */
2025 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2026 uint8_t crtcindex = bios->data[offset + 3];
2027 uint8_t data = bios->data[offset + 4];
2028
2029 if (!iexec->execute)
37383650 2030 return 5;
6ee73861
BS		 2031
2032 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2033
37383650 2034 return 5;
6ee73861
BS		 2035}
2036
37383650 2037static int
6ee73861
BS		 2038init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2039{
2040 /*
2041 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2042 *
2043 * offset (8 bit): opcode
2044 *
2045 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
2046 * that the hardware can correctly calculate how much VRAM it has
2047 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
2048 *
2049 * The implementation of this opcode in general consists of two parts:
2050 * 1) determination of the memory bus width
2051 * 2) determination of how many of the card's RAM pads have ICs attached
2052 *
2053 * 1) is done by a cunning combination of writes to offsets 0x1c and
2054 * 0x3c in the framebuffer, and seeing whether the written values are
2055 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
2056 *
2057 * 2) is done by a cunning combination of writes to an offset slightly
2058 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
2059 * if the test pattern can be read back. This then affects bits 12-15 of
2060 * NV_PFB_CFG0
2061 *
2062 * In this context a "cunning combination" may include multiple reads
2063 * and writes to varying locations, often alternating the test pattern
2064 * and 0, doubtless to make sure buffers are filled, residual charges
2065 * on tracks are removed etc.
2066 *
2067 * Unfortunately, the "cunning combination"s mentioned above, and the
2068 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
2069 * trace I have.
2070 *
2071 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
2072 * we started was correct, and use that instead
2073 */
2074
2075 /* no iexec->execute check by design */
2076
2077 /*
2078 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
2079 * and kmmio traces of the binary driver POSTing the card show nothing
2080 * being done for this opcode. why is it still listed in the table?!
2081 */
2082
2083 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2084
e235c1f3 2085 if (dev_priv->card_type >= NV_40)
37383650 2086 return 1;
6ee73861
BS		 2087
2088 /*
2089 * On every card I've seen, this step gets done for us earlier in
2090 * the init scripts
2091 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
2092 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
2093 */
2094
2095 /*
2096 * This also has probably been done in the scripts, but an mmio trace of
2097 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2098 */
2099 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
2100
2101 /* write back the saved configuration value */
2102 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2103
37383650 2104 return 1;
6ee73861
BS		 2105}
2106
37383650 2107static int
6ee73861
BS		 2108init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2109{
2110 /*
2111 * INIT_RESET opcode: 0x65 ('e')
2112 *
2113 * offset (8 bit): opcode
2114 * offset + 1 (32 bit): register
2115 * offset + 5 (32 bit): value1
2116 * offset + 9 (32 bit): value2
2117 *
2118 * Assign "value1" to "register", then assign "value2" to "register"
2119 */
2120
2121 uint32_t reg = ROM32(bios->data[offset + 1]);
2122 uint32_t value1 = ROM32(bios->data[offset + 5]);
2123 uint32_t value2 = ROM32(bios->data[offset + 9]);
2124 uint32_t pci_nv_19, pci_nv_20;
2125
2126 /* no iexec->execute check by design */
2127
2128 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2129 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
2130 bios_wr32(bios, reg, value1);
2131
2132 udelay(10);
2133
2134 bios_wr32(bios, reg, value2);
2135 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2136
2137 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2138 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2139 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2140
37383650 2141 return 13;
6ee73861
BS		 2142}
2143
37383650 2144static int
6ee73861
BS		 2145init_configure_mem(struct nvbios *bios, uint16_t offset,
2146 struct init_exec *iexec)
2147{
2148 /*
2149 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2150 *
2151 * offset (8 bit): opcode
2152 *
2153 * Equivalent to INIT_DONE on bios version 3 or greater.
2154 * For early bios versions, sets up the memory registers, using values
2155 * taken from the memory init table
2156 */
2157
2158 /* no iexec->execute check by design */
2159
2160 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2161 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2162 uint32_t reg, data;
2163
2164 if (bios->major_version > 2)
9170a824 2165 return -ENODEV;
6ee73861
BS		 2166
2167 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2168 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2169
2170 if (bios->data[meminitoffs] & 1)
2171 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2172
2173 for (reg = ROM32(bios->data[seqtbloffs]);
2174 reg != 0xffffffff;
2175 reg = ROM32(bios->data[seqtbloffs += 4])) {
2176
2177 switch (reg) {
2178 case NV_PFB_PRE:
2179 data = NV_PFB_PRE_CMD_PRECHARGE;
2180 break;
2181 case NV_PFB_PAD:
2182 data = NV_PFB_PAD_CKE_NORMAL;
2183 break;
2184 case NV_PFB_REF:
2185 data = NV_PFB_REF_CMD_REFRESH;
2186 break;
2187 default:
2188 data = ROM32(bios->data[meminitdata]);
2189 meminitdata += 4;
2190 if (data == 0xffffffff)
2191 continue;
2192 }
2193
2194 bios_wr32(bios, reg, data);
2195 }
2196
37383650 2197 return 1;
6ee73861
BS		 2198}
2199
37383650 2200static int
6ee73861
BS		 2201init_configure_clk(struct nvbios *bios, uint16_t offset,
2202 struct init_exec *iexec)
2203{
2204 /*
2205 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2206 *
2207 * offset (8 bit): opcode
2208 *
2209 * Equivalent to INIT_DONE on bios version 3 or greater.
2210 * For early bios versions, sets up the NVClk and MClk PLLs, using
2211 * values taken from the memory init table
2212 */
2213
2214 /* no iexec->execute check by design */
2215
2216 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2217 int clock;
2218
2219 if (bios->major_version > 2)
9170a824 2220 return -ENODEV;
6ee73861
BS		 2221
2222 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2223 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2224
2225 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2226 if (bios->data[meminitoffs] & 1) /* DDR */
2227 clock *= 2;
2228 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2229
37383650 2230 return 1;
6ee73861
BS		 2231}
2232
37383650 2233static int
6ee73861
BS		 2234init_configure_preinit(struct nvbios *bios, uint16_t offset,
2235 struct init_exec *iexec)
2236{
2237 /*
2238 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2239 *
2240 * offset (8 bit): opcode
2241 *
2242 * Equivalent to INIT_DONE on bios version 3 or greater.
2243 * For early bios versions, does early init, loading ram and crystal
2244 * configuration from straps into CR3C
2245 */
2246
2247 /* no iexec->execute check by design */
2248
2249 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2250 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2251
2252 if (bios->major_version > 2)
9170a824 2253 return -ENODEV;
6ee73861
BS		 2254
2255 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2256 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2257
37383650 2258 return 1;
6ee73861
BS		 2259}
2260
37383650 2261static int
6ee73861
BS		 2262init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2263{
2264 /*
2265 * INIT_IO opcode: 0x69 ('i')
2266 *
2267 * offset (8 bit): opcode
2268 * offset + 1 (16 bit): CRTC port
2269 * offset + 3 (8 bit): mask
2270 * offset + 4 (8 bit): data
2271 *
2272 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2273 */
2274
2275 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2276 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2277 uint8_t mask = bios->data[offset + 3];
2278 uint8_t data = bios->data[offset + 4];
2279
2280 if (!iexec->execute)
37383650 2281 return 5;
6ee73861
BS		 2282
2283 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2284 offset, crtcport, mask, data);
2285
2286 /*
2287 * I have no idea what this does, but NVIDIA do this magic sequence
2288 * in the places where this INIT_IO happens..
2289 */
2290 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2291 int i;
2292
2293 bios_wr32(bios, 0x614100, (bios_rd32(
2294 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2295
2296 bios_wr32(bios, 0x00e18c, bios_rd32(
2297 bios, 0x00e18c) | 0x00020000);
2298
2299 bios_wr32(bios, 0x614900, (bios_rd32(
2300 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2301
2302 bios_wr32(bios, 0x000200, bios_rd32(
2303 bios, 0x000200) & ~0x40000000);
2304
2305 mdelay(10);
2306
2307 bios_wr32(bios, 0x00e18c, bios_rd32(
2308 bios, 0x00e18c) & ~0x00020000);
2309
2310 bios_wr32(bios, 0x000200, bios_rd32(
2311 bios, 0x000200) | 0x40000000);
2312
2313 bios_wr32(bios, 0x614100, 0x00800018);
2314 bios_wr32(bios, 0x614900, 0x00800018);
2315
2316 mdelay(10);
2317
2318 bios_wr32(bios, 0x614100, 0x10000018);
2319 bios_wr32(bios, 0x614900, 0x10000018);
2320
2321 for (i = 0; i < 3; i++)
2322 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2323 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2324
2325 for (i = 0; i < 2; i++)
2326 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2327 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2328
2329 for (i = 0; i < 3; i++)
2330 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2331 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2332
2333 for (i = 0; i < 2; i++)
2334 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2335 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2336
2337 for (i = 0; i < 2; i++)
2338 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2339 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2340 return 5;
6ee73861
BS		 2341 }
2342
2343 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2344 data);
37383650 2345 return 5;
6ee73861
BS		 2346}
2347
37383650 2348static int
6ee73861
BS		 2349init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2350{
2351 /*
2352 * INIT_SUB opcode: 0x6B ('k')
2353 *
2354 * offset (8 bit): opcode
2355 * offset + 1 (8 bit): script number
2356 *
2357 * Execute script number "script number", as a subroutine
2358 */
2359
2360 uint8_t sub = bios->data[offset + 1];
2361
2362 if (!iexec->execute)
37383650 2363 return 2;
6ee73861
BS		 2364
2365 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2366
2367 parse_init_table(bios,
2368 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2369 iexec);
2370
2371 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2372
37383650 2373 return 2;
6ee73861
BS		 2374}
2375
37383650 2376static int
6ee73861
BS		 2377init_ram_condition(struct nvbios *bios, uint16_t offset,
2378 struct init_exec *iexec)
2379{
2380 /*
2381 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2382 *
2383 * offset (8 bit): opcode
2384 * offset + 1 (8 bit): mask
2385 * offset + 2 (8 bit): cmpval
2386 *
2387 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2388 * If condition not met skip subsequent opcodes until condition is
2389 * inverted (INIT_NOT), or we hit INIT_RESUME
2390 */
2391
2392 uint8_t mask = bios->data[offset + 1];
2393 uint8_t cmpval = bios->data[offset + 2];
2394 uint8_t data;
2395
2396 if (!iexec->execute)
37383650 2397 return 3;
6ee73861
BS		 2398
2399 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2400
2401 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2402 offset, data, cmpval);
2403
2404 if (data == cmpval)
2405 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2406 else {
2407 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2408 iexec->execute = false;
2409 }
2410
37383650 2411 return 3;
6ee73861
BS		 2412}
2413
37383650 2414static int
6ee73861
BS		 2415init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2416{
2417 /*
2418 * INIT_NV_REG opcode: 0x6E ('n')
2419 *
2420 * offset (8 bit): opcode
2421 * offset + 1 (32 bit): register
2422 * offset + 5 (32 bit): mask
2423 * offset + 9 (32 bit): data
2424 *
2425 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2426 */
2427
2428 uint32_t reg = ROM32(bios->data[offset + 1]);
2429 uint32_t mask = ROM32(bios->data[offset + 5]);
2430 uint32_t data = ROM32(bios->data[offset + 9]);
2431
2432 if (!iexec->execute)
37383650 2433 return 13;
6ee73861
BS		 2434
2435 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2436 offset, reg, mask, data);
2437
2438 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2439
37383650 2440 return 13;
6ee73861
BS		 2441}
2442
37383650 2443static int
6ee73861
BS		 2444init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2445{
2446 /*
2447 * INIT_MACRO opcode: 0x6F ('o')
2448 *
2449 * offset (8 bit): opcode
2450 * offset + 1 (8 bit): macro number
2451 *
2452 * Look up macro index "macro number" in the macro index table.
2453 * The macro index table entry has 1 byte for the index in the macro
2454 * table, and 1 byte for the number of times to repeat the macro.
2455 * The macro table entry has 4 bytes for the register address and
2456 * 4 bytes for the value to write to that register
2457 */
2458
2459 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2460 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2461 uint8_t macro_tbl_idx = bios->data[tmp];
2462 uint8_t count = bios->data[tmp + 1];
2463 uint32_t reg, data;
2464 int i;
2465
2466 if (!iexec->execute)
37383650 2467 return 2;
6ee73861
BS		 2468
2469 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2470 "Count: 0x%02X\n",
2471 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2472
2473 for (i = 0; i < count; i++) {
2474 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2475
2476 reg = ROM32(bios->data[macroentryptr]);
2477 data = ROM32(bios->data[macroentryptr + 4]);
2478
2479 bios_wr32(bios, reg, data);
2480 }
2481
37383650 2482 return 2;
6ee73861
BS		 2483}
2484
37383650 2485static int
6ee73861
BS		 2486init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2487{
2488 /*
2489 * INIT_DONE opcode: 0x71 ('q')
2490 *
2491 * offset (8 bit): opcode
2492 *
2493 * End the current script
2494 */
2495
2496 /* mild retval abuse to stop parsing this table */
37383650 2497 return 0;
6ee73861
BS		 2498}
2499
37383650 2500static int
6ee73861
BS		 2501init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2502{
2503 /*
2504 * INIT_RESUME opcode: 0x72 ('r')
2505 *
2506 * offset (8 bit): opcode
2507 *
2508 * End the current execute / no-execute condition
2509 */
2510
2511 if (iexec->execute)
37383650 2512 return 1;
6ee73861
BS		 2513
2514 iexec->execute = true;
2515 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2516
37383650 2517 return 1;
6ee73861
BS		 2518}
2519
37383650 2520static int
6ee73861
BS		 2521init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2522{
2523 /*
2524 * INIT_TIME opcode: 0x74 ('t')
2525 *
2526 * offset (8 bit): opcode
2527 * offset + 1 (16 bit): time
2528 *
2529 * Sleep for "time" microseconds.
2530 */
2531
2532 unsigned time = ROM16(bios->data[offset + 1]);
2533
2534 if (!iexec->execute)
37383650 2535 return 3;
6ee73861
BS		 2536
2537 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2538 offset, time);
2539
2540 if (time < 1000)
2541 udelay(time);
2542 else
2543 msleep((time + 900) / 1000);
2544
37383650 2545 return 3;
6ee73861
BS		 2546}
2547
37383650 2548static int
6ee73861
BS		 2549init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2550{
2551 /*
2552 * INIT_CONDITION opcode: 0x75 ('u')
2553 *
2554 * offset (8 bit): opcode
2555 * offset + 1 (8 bit): condition number
2556 *
2557 * Check condition "condition number" in the condition table.
2558 * If condition not met skip subsequent opcodes until condition is
2559 * inverted (INIT_NOT), or we hit INIT_RESUME
2560 */
2561
2562 uint8_t cond = bios->data[offset + 1];
2563
2564 if (!iexec->execute)
37383650 2565 return 2;
6ee73861
BS		 2566
2567 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2568
2569 if (bios_condition_met(bios, offset, cond))
2570 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2571 else {
2572 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2573 iexec->execute = false;
2574 }
2575
37383650 2576 return 2;
6ee73861
BS		 2577}
2578
37383650 2579static int
6ee73861
BS		 2580init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2581{
2582 /*
2583 * INIT_IO_CONDITION opcode: 0x76
2584 *
2585 * offset (8 bit): opcode
2586 * offset + 1 (8 bit): condition number
2587 *
2588 * Check condition "condition number" in the io condition table.
2589 * If condition not met skip subsequent opcodes until condition is
2590 * inverted (INIT_NOT), or we hit INIT_RESUME
2591 */
2592
2593 uint8_t cond = bios->data[offset + 1];
2594
2595 if (!iexec->execute)
37383650 2596 return 2;
6ee73861
BS		 2597
2598 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2599
2600 if (io_condition_met(bios, offset, cond))
2601 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2602 else {
2603 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2604 iexec->execute = false;
2605 }
2606
37383650 2607 return 2;
6ee73861
BS		 2608}
2609
37383650 2610static int
6ee73861
BS		 2611init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2612{
2613 /*
2614 * INIT_INDEX_IO opcode: 0x78 ('x')
2615 *
2616 * offset (8 bit): opcode
2617 * offset + 1 (16 bit): CRTC port
2618 * offset + 3 (8 bit): CRTC index
2619 * offset + 4 (8 bit): mask
2620 * offset + 5 (8 bit): data
2621 *
2622 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2623 * OR with "data", write-back
2624 */
2625
2626 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2627 uint8_t crtcindex = bios->data[offset + 3];
2628 uint8_t mask = bios->data[offset + 4];
2629 uint8_t data = bios->data[offset + 5];
2630 uint8_t value;
2631
2632 if (!iexec->execute)
37383650 2633 return 6;
6ee73861
BS		 2634
2635 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2636 "Data: 0x%02X\n",
2637 offset, crtcport, crtcindex, mask, data);
2638
2639 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2640 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2641
37383650 2642 return 6;
6ee73861
BS		 2643}
2644
37383650 2645static int
6ee73861
BS		 2646init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2647{
2648 /*
2649 * INIT_PLL opcode: 0x79 ('y')
2650 *
2651 * offset (8 bit): opcode
2652 * offset + 1 (32 bit): register
2653 * offset + 5 (16 bit): freq
2654 *
2655 * Set PLL register "register" to coefficients for frequency (10kHz)
2656 * "freq"
2657 */
2658
2659 uint32_t reg = ROM32(bios->data[offset + 1]);
2660 uint16_t freq = ROM16(bios->data[offset + 5]);
2661
2662 if (!iexec->execute)
37383650 2663 return 7;
6ee73861
BS		 2664
2665 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2666
2667 setPLL(bios, reg, freq * 10);
2668
37383650 2669 return 7;
6ee73861
BS		 2670}
2671
37383650 2672static int
6ee73861
BS		 2673init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2674{
2675 /*
2676 * INIT_ZM_REG opcode: 0x7A ('z')
2677 *
2678 * offset (8 bit): opcode
2679 * offset + 1 (32 bit): register
2680 * offset + 5 (32 bit): value
2681 *
2682 * Assign "value" to "register"
2683 */
2684
2685 uint32_t reg = ROM32(bios->data[offset + 1]);
2686 uint32_t value = ROM32(bios->data[offset + 5]);
2687
2688 if (!iexec->execute)
37383650 2689 return 9;
6ee73861
BS		 2690
2691 if (reg == 0x000200)
2692 value |= 1;
2693
2694 bios_wr32(bios, reg, value);
2695
37383650 2696 return 9;
6ee73861
BS		 2697}
2698
37383650 2699static int
6ee73861
BS		 2700init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2701 struct init_exec *iexec)
2702{
2703 /*
2704 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2705 *
2706 * offset (8 bit): opcode
2707 * offset + 1 (8 bit): PLL type
2708 * offset + 2 (32 bit): frequency 0
2709 *
2710 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2711 * ram_restrict_table_ptr. The value read from there is used to select
2712 * a frequency from the table starting at 'frequency 0' to be
2713 * programmed into the PLL corresponding to 'type'.
2714 *
2715 * The PLL limits table on cards using this opcode has a mapping of
2716 * 'type' to the relevant registers.
2717 */
2718
2719 struct drm_device *dev = bios->dev;
2720 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2721 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2722 uint8_t type = bios->data[offset + 1];
2723 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2724 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2725 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2726 int i;
2727
2728 if (!iexec->execute)
37383650 2729 return len;
6ee73861
BS		 2730
2731 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2732 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2733 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2734 }
2735
2736 entry = pll_limits + pll_limits[1];
2737 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2738 if (entry[0] == type) {
2739 uint32_t reg = ROM32(entry[3]);
2740
2741 BIOSLOG(bios, "0x%04X: "
2742 "Type %02x Reg 0x%08x Freq %dKHz\n",
2743 offset, type, reg, freq);
2744
2745 setPLL(bios, reg, freq);
37383650 2746 return len;
6ee73861
BS		 2747 }
2748 }
2749
2750 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2751 return len;
6ee73861
BS		 2752}
2753
37383650 2754static int
6ee73861
BS		 2755init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2756{
2757 /*
2758 * INIT_8C opcode: 0x8C ('')
2759 *
2760 * NOP so far....
2761 *
2762 */
2763
37383650 2764 return 1;
6ee73861
BS		 2765}
2766
37383650 2767static int
6ee73861
BS		 2768init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2769{
2770 /*
2771 * INIT_8D opcode: 0x8D ('')
2772 *
2773 * NOP so far....
2774 *
2775 */
2776
37383650 2777 return 1;
6ee73861
BS		 2778}
2779
37383650 2780static int
6ee73861
BS		 2781init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2782{
2783 /*
2784 * INIT_GPIO opcode: 0x8E ('')
2785 *
2786 * offset (8 bit): opcode
2787 *
2788 * Loop over all entries in the DCB GPIO table, and initialise
2789 * each GPIO according to various values listed in each entry
2790 */
2791
2535d71c 2792 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
6ee73861 2793 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 2794 int i;
2795
2535d71c
BS		 2796 if (dev_priv->card_type != NV_50) {
2797 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2798 return -ENODEV;
6ee73861
BS		 2799 }
2800
2535d71c
BS		 2801 if (!iexec->execute)
2802 return 1;
6ee73861 2803
2535d71c
BS		 2804 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2805 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2806 uint32_t r, s, v;
6ee73861 2807
2535d71c 2808 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 2809
73db4bed
BS		 2810 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
2811 offset, gpio->tag, gpio->state_default);
2812 if (bios->execute)
2813 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 2814
45284162
BS		 2815 /* The NVIDIA binary driver doesn't appear to actually do
2816 * any of this, my VBIOS does however.
2817 */
2818 /* Not a clue, needs de-magicing */
2535d71c
BS		 2819 r = nv50_gpio_ctl[gpio->line >> 4];
2820 s = (gpio->line & 0x0f);
6ee73861 2821 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 2822 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 2823 case 1:
2824 v |= (0x00000001 << s);
2825 break;
2826 case 2:
2827 v |= (0x00010000 << s);
2828 break;
2829 default:
2830 break;
2831 }
2832 bios_wr32(bios, r, v);
2833 }
2834
37383650 2835 return 1;
6ee73861
BS		 2836}
2837
37383650 2838static int
6ee73861
BS		 2839init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2840 struct init_exec *iexec)
2841{
2842 /*
2843 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2844 *
2845 * offset (8 bit): opcode
2846 * offset + 1 (32 bit): reg
2847 * offset + 5 (8 bit): regincrement
2848 * offset + 6 (8 bit): count
2849 * offset + 7 (32 bit): value 1,1
2850 * ...
2851 *
2852 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2853 * ram_restrict_table_ptr. The value read from here is 'n', and
2854 * "value 1,n" gets written to "reg". This repeats "count" times and on
2855 * each iteration 'm', "reg" increases by "regincrement" and
2856 * "value m,n" is used. The extent of n is limited by a number read
2857 * from the 'M' BIT table, herein called "blocklen"
2858 */
2859
2860 uint32_t reg = ROM32(bios->data[offset + 1]);
2861 uint8_t regincrement = bios->data[offset + 5];
2862 uint8_t count = bios->data[offset + 6];
2863 uint32_t strap_ramcfg, data;
37383650
MK		 2864 /* previously set by 'M' BIT table */
2865 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2866 int len = 7 + count * blocklen;
6ee73861
BS		 2867 uint8_t index;
2868 int i;
2869
6ee73861
BS		 2870
2871 if (!iexec->execute)
37383650 2872 return len;
6ee73861
BS		 2873
2874 if (!blocklen) {
2875 NV_ERROR(bios->dev,
2876 "0x%04X: Zero block length - has the M table "
2877 "been parsed?\n", offset);
9170a824 2878 return -EINVAL;
6ee73861
BS		 2879 }
2880
2881 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2882 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2883
2884 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2885 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2886 offset, reg, regincrement, count, strap_ramcfg, index);
2887
2888 for (i = 0; i < count; i++) {
2889 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2890
2891 bios_wr32(bios, reg, data);
2892
2893 reg += regincrement;
2894 }
2895
37383650 2896 return len;
6ee73861
BS		 2897}
2898
37383650 2899static int
6ee73861
BS		 2900init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2901{
2902 /*
2903 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2904 *
2905 * offset (8 bit): opcode
2906 * offset + 1 (32 bit): src reg
2907 * offset + 5 (32 bit): dst reg
2908 *
2909 * Put contents of "src reg" into "dst reg"
2910 */
2911
2912 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2913 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2914
2915 if (!iexec->execute)
37383650 2916 return 9;
6ee73861
BS		 2917
2918 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2919
37383650 2920 return 9;
6ee73861
BS		 2921}
2922
37383650 2923static int
6ee73861
BS		 2924init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2925 struct init_exec *iexec)
2926{
2927 /*
2928 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2929 *
2930 * offset (8 bit): opcode
2931 * offset + 1 (32 bit): dst reg
2932 * offset + 5 (8 bit): count
2933 * offset + 6 (32 bit): data 1
2934 * ...
2935 *
2936 * For each of "count" values write "data n" to "dst reg"
2937 */
2938
2939 uint32_t reg = ROM32(bios->data[offset + 1]);
2940 uint8_t count = bios->data[offset + 5];
37383650 2941 int len = 6 + count * 4;
6ee73861
BS		 2942 int i;
2943
2944 if (!iexec->execute)
37383650 2945 return len;
6ee73861
BS		 2946
2947 for (i = 0; i < count; i++) {
2948 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2949 bios_wr32(bios, reg, data);
2950 }
2951
37383650 2952 return len;
6ee73861
BS		 2953}
2954
37383650 2955static int
6ee73861
BS		 2956init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2957{
2958 /*
2959 * INIT_RESERVED opcode: 0x92 ('')
2960 *
2961 * offset (8 bit): opcode
2962 *
2963 * Seemingly does nothing
2964 */
2965
37383650 2966 return 1;
6ee73861
BS		 2967}
2968
37383650 2969static int
6ee73861
BS		 2970init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2971{
2972 /*
2973 * INIT_96 opcode: 0x96 ('')
2974 *
2975 * offset (8 bit): opcode
2976 * offset + 1 (32 bit): sreg
2977 * offset + 5 (8 bit): sshift
2978 * offset + 6 (8 bit): smask
2979 * offset + 7 (8 bit): index
2980 * offset + 8 (32 bit): reg
2981 * offset + 12 (32 bit): mask
2982 * offset + 16 (8 bit): shift
2983 *
2984 */
2985
2986 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2987 uint32_t reg = ROM32(bios->data[offset + 8]);
2988 uint32_t mask = ROM32(bios->data[offset + 12]);
2989 uint32_t val;
2990
2991 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2992 if (bios->data[offset + 5] < 0x80)
2993 val >>= bios->data[offset + 5];
2994 else
2995 val <<= (0x100 - bios->data[offset + 5]);
2996 val &= bios->data[offset + 6];
2997
2998 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2999 val <<= bios->data[offset + 16];
3000
3001 if (!iexec->execute)
37383650 3002 return 17;
6ee73861
BS		 3003
3004 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3005 return 17;
6ee73861
BS		 3006}
3007
37383650 3008static int
6ee73861
BS		 3009init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3010{
3011 /*
3012 * INIT_97 opcode: 0x97 ('')
3013 *
3014 * offset (8 bit): opcode
3015 * offset + 1 (32 bit): register
3016 * offset + 5 (32 bit): mask
3017 * offset + 9 (32 bit): value
3018 *
3019 * Adds "value" to "register" preserving the fields specified
3020 * by "mask"
3021 */
3022
3023 uint32_t reg = ROM32(bios->data[offset + 1]);
3024 uint32_t mask = ROM32(bios->data[offset + 5]);
3025 uint32_t add = ROM32(bios->data[offset + 9]);
3026 uint32_t val;
3027
3028 val = bios_rd32(bios, reg);
3029 val = (val & mask) | ((val + add) & ~mask);
3030
3031 if (!iexec->execute)
37383650 3032 return 13;
6ee73861
BS		 3033
3034 bios_wr32(bios, reg, val);
37383650 3035 return 13;
6ee73861
BS		 3036}
3037
37383650 3038static int
6ee73861
BS		 3039init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3040{
3041 /*
3042 * INIT_AUXCH opcode: 0x98 ('')
3043 *
3044 * offset (8 bit): opcode
3045 * offset + 1 (32 bit): address
3046 * offset + 5 (8 bit): count
3047 * offset + 6 (8 bit): mask 0
3048 * offset + 7 (8 bit): data 0
3049 * ...
3050 *
3051 */
3052
3053 struct drm_device *dev = bios->dev;
3054 struct nouveau_i2c_chan *auxch;
3055 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3056 uint8_t count = bios->data[offset + 5];
3057 int len = 6 + count * 2;
6ee73861
BS		 3058 int ret, i;
3059
3060 if (!bios->display.output) {
3061 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
9170a824 3062 return -EINVAL;
6ee73861
BS		 3063 }
3064
3065 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3066 if (!auxch) {
3067 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3068 bios->display.output->i2c_index);
9170a824 3069 return -ENODEV;
6ee73861
BS		 3070 }
3071
3072 if (!iexec->execute)
37383650 3073 return len;
6ee73861
BS		 3074
3075 offset += 6;
37383650 3076 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3077 uint8_t data;
3078
3079 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3080 if (ret) {
3081 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
9170a824 3082 return ret;
6ee73861
BS		 3083 }
3084
3085 data &= bios->data[offset + 0];
3086 data |= bios->data[offset + 1];
3087
3088 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3089 if (ret) {
3090 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
9170a824 3091 return ret;
6ee73861
BS		 3092 }
3093 }
3094
37383650 3095 return len;
6ee73861
BS		 3096}
3097
37383650 3098static int
6ee73861
BS		 3099init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3100{
3101 /*
3102 * INIT_ZM_AUXCH opcode: 0x99 ('')
3103 *
3104 * offset (8 bit): opcode
3105 * offset + 1 (32 bit): address
3106 * offset + 5 (8 bit): count
3107 * offset + 6 (8 bit): data 0
3108 * ...
3109 *
3110 */
3111
3112 struct drm_device *dev = bios->dev;
3113 struct nouveau_i2c_chan *auxch;
3114 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3115 uint8_t count = bios->data[offset + 5];
3116 int len = 6 + count;
6ee73861
BS		 3117 int ret, i;
3118
3119 if (!bios->display.output) {
3120 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
9170a824 3121 return -EINVAL;
6ee73861
BS		 3122 }
3123
3124 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3125 if (!auxch) {
3126 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3127 bios->display.output->i2c_index);
9170a824 3128 return -ENODEV;
6ee73861
BS		 3129 }
3130
3131 if (!iexec->execute)
37383650 3132 return len;
6ee73861
BS		 3133
3134 offset += 6;
37383650 3135 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3136 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3137 if (ret) {
3138 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
9170a824 3139 return ret;
6ee73861
BS		 3140 }
3141 }
3142
37383650 3143 return len;
6ee73861
BS		 3144}
3145
3146static struct init_tbl_entry itbl_entry[] = {
3147 /* command name , id , length , offset , mult , command handler */
3148 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3149 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3150 { "INIT_REPEAT" , 0x33, init_repeat },
3151 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3152 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3153 { "INIT_COPY" , 0x37, init_copy },
3154 { "INIT_NOT" , 0x38, init_not },
3155 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3156 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3157 { "INIT_OP_3B" , 0x3B, init_op_3b },
3158 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3159 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3160 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3161 { "INIT_PLL2" , 0x4B, init_pll2 },
3162 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3163 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3164 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3165 { "INIT_TMDS" , 0x4F, init_tmds },
3166 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3167 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3168 { "INIT_CR" , 0x52, init_cr },
3169 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3170 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3171 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3172 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3173 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3174 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3175 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3176 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3177 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3178 { "INIT_RESET" , 0x65, init_reset },
3179 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3180 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3181 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3182 { "INIT_IO" , 0x69, init_io },
3183 { "INIT_SUB" , 0x6B, init_sub },
3184 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3185 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3186 { "INIT_MACRO" , 0x6F, init_macro },
3187 { "INIT_DONE" , 0x71, init_done },
3188 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3189 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3190 { "INIT_TIME" , 0x74, init_time },
3191 { "INIT_CONDITION" , 0x75, init_condition },
3192 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3193 { "INIT_INDEX_IO" , 0x78, init_index_io },
3194 { "INIT_PLL" , 0x79, init_pll },
3195 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3196 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3197 { "INIT_8C" , 0x8C, init_8c },
3198 { "INIT_8D" , 0x8D, init_8d },
3199 { "INIT_GPIO" , 0x8E, init_gpio },
3200 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3201 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3202 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3203 { "INIT_RESERVED" , 0x92, init_reserved },
3204 { "INIT_96" , 0x96, init_96 },
3205 { "INIT_97" , 0x97, init_97 },
3206 { "INIT_AUXCH" , 0x98, init_auxch },
3207 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3208 { NULL , 0 , NULL }
6ee73861
BS		 3209};
3210
6ee73861
BS		 3211#define MAX_TABLE_OPS 1000
3212
3213static int
3214parse_init_table(struct nvbios *bios, unsigned int offset,
3215 struct init_exec *iexec)
3216{
3217 /*
3218 * Parses all commands in an init table.
3219 *
3220 * We start out executing all commands found in the init table. Some
3221 * opcodes may change the status of iexec->execute to SKIP, which will
3222 * cause the following opcodes to perform no operation until the value
3223 * is changed back to EXECUTE.
3224 */
3225
92b96187 3226 int count = 0, i, ret;
6ee73861
BS		 3227 uint8_t id;
3228
3229 /*
3230 * Loop until INIT_DONE causes us to break out of the loop
3231 * (or until offset > bios length just in case... )
3232 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3233 */
3234 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3235 id = bios->data[offset];
3236
3237 /* Find matching id in itbl_entry */
3238 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3239 ;
3240
92b96187 3241 if (!itbl_entry[i].name) {
6ee73861
BS		 3242 NV_ERROR(bios->dev,
3243 "0x%04X: Init table command not found: "
3244 "0x%02X\n", offset, id);
3245 return -ENOENT;
3246 }
92b96187
BS		 3247
3248 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3249 itbl_entry[i].id, itbl_entry[i].name);
3250
3251 /* execute eventual command handler */
3252 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3253 if (ret < 0) {
3254 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3255 "table opcode: %s %d\n", offset,
3256 itbl_entry[i].name, ret);
3257 }
3258
3259 if (ret <= 0)
3260 break;
3261
3262 /*
3263 * Add the offset of the current command including all data
3264 * of that command. The offset will then be pointing on the
3265 * next op code.
3266 */
3267 offset += ret;
6ee73861
BS		 3268 }
3269
3270 if (offset >= bios->length)
3271 NV_WARN(bios->dev,
3272 "Offset 0x%04X greater than known bios image length. "
3273 "Corrupt image?\n", offset);
3274 if (count >= MAX_TABLE_OPS)
3275 NV_WARN(bios->dev,
3276 "More than %d opcodes to a table is unlikely, "
3277 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3278
3279 return 0;
3280}
3281
3282static void
3283parse_init_tables(struct nvbios *bios)
3284{
3285 /* Loops and calls parse_init_table() for each present table. */
3286
3287 int i = 0;
3288 uint16_t table;
3289 struct init_exec iexec = {true, false};
3290
3291 if (bios->old_style_init) {
3292 if (bios->init_script_tbls_ptr)
3293 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3294 if (bios->extra_init_script_tbl_ptr)
3295 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3296
3297 return;
3298 }
3299
3300 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3301 NV_INFO(bios->dev,
3302 "Parsing VBIOS init table %d at offset 0x%04X\n",
3303 i / 2, table);
3304 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3305
3306 parse_init_table(bios, table, &iexec);
3307 i += 2;
3308 }
3309}
3310
3311static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3312{
3313 int compare_record_len, i = 0;
3314 uint16_t compareclk, scriptptr = 0;
3315
3316 if (bios->major_version < 5) /* pre BIT */
3317 compare_record_len = 3;
3318 else
3319 compare_record_len = 4;
3320
3321 do {
3322 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3323 if (pxclk >= compareclk * 10) {
3324 if (bios->major_version < 5) {
3325 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3326 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3327 } else
3328 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3329 break;
3330 }
3331 i++;
3332 } while (compareclk);
3333
3334 return scriptptr;
3335}
3336
3337static void
3338run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3339 struct dcb_entry *dcbent, int head, bool dl)
3340{
3341 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3342 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3343 struct init_exec iexec = {true, false};
3344
3345 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3346 scriptptr);
3347 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3348 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3349 /* note: if dcb entries have been merged, index may be misleading */
3350 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3351 parse_init_table(bios, scriptptr, &iexec);
3352
3353 nv04_dfp_bind_head(dev, dcbent, head, dl);
3354}
3355
3356static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3357{
3358 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3359 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3360 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3361 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3362
3363 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3364 return -EINVAL;
3365
3366 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3367
3368 if (script == LVDS_PANEL_OFF) {
3369 /* off-on delay in ms */
3370 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3371 }
3372#ifdef __powerpc__
3373 /* Powerbook specific quirks */
3d9aefb8
FJ		 3374 if ((dev->pci_device & 0xffff) == 0x0179 ||
3375 (dev->pci_device & 0xffff) == 0x0189 ||
3376 (dev->pci_device & 0xffff) == 0x0329) {
3377 if (script == LVDS_RESET) {
3378 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3379
3380 } else if (script == LVDS_PANEL_ON) {
3381 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3382 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3383 | (1 << 31));
3384 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3385 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3386
3387 } else if (script == LVDS_PANEL_OFF) {
3388 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3389 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3390 & ~(1 << 31));
3391 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3392 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3393 }
3394 }
3395#endif
3396
3397 return 0;
3398}
3399
3400static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3401{
3402 /*
3403 * The BIT LVDS table's header has the information to setup the
3404 * necessary registers. Following the standard 4 byte header are:
3405 * A bitmask byte and a dual-link transition pxclk value for use in
3406 * selecting the init script when not using straps; 4 script pointers
3407 * for panel power, selected by output and on/off; and 8 table pointers
3408 * for panel init, the needed one determined by output, and bits in the
3409 * conf byte. These tables are similar to the TMDS tables, consisting
3410 * of a list of pxclks and script pointers.
3411 */
3412 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3413 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3414 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3415 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3416
3417 /*
3418 * For now we assume version 3.0 table - g80 support will need some
3419 * changes
3420 */
3421
3422 switch (script) {
3423 case LVDS_INIT:
3424 return -ENOSYS;
3425 case LVDS_BACKLIGHT_ON:
3426 case LVDS_PANEL_ON:
3427 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3428 break;
3429 case LVDS_BACKLIGHT_OFF:
3430 case LVDS_PANEL_OFF:
3431 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3432 break;
3433 case LVDS_RESET:
f3bbb9cc
BS		 3434 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3435 if (dcbent->or == 4)
3436 clktable += 8;
3437
6ee73861
BS		 3438 if (dcbent->lvdsconf.use_straps_for_mode) {
3439 if (bios->fp.dual_link)
f3bbb9cc
BS		 3440 clktable += 4;
3441 if (bios->fp.if_is_24bit)
3442 clktable += 2;
6ee73861
BS		 3443 } else {
3444 /* using EDID */
f3bbb9cc 3445 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3446
3447 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3448 clktable += 4;
3449 cmpval_24bit <<= 1;
6ee73861 3450 }
f3bbb9cc
BS		 3451
3452 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3453 clktable += 2;
6ee73861
BS		 3454 }
3455
f3bbb9cc 3456 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3457 if (!clktable) {
3458 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3459 return -ENOENT;
3460 }
3461 scriptptr = clkcmptable(bios, clktable, pxclk);
3462 }
3463
3464 if (!scriptptr) {
3465 NV_ERROR(dev, "LVDS output init script not found\n");
3466 return -ENOENT;
3467 }
3468 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3469
3470 return 0;
3471}
3472
3473int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3474{
3475 /*
3476 * LVDS operations are multiplexed in an effort to present a single API
3477 * which works with two vastly differing underlying structures.
3478 * This acts as the demux
3479 */
3480
3481 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3482 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3483 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3484 uint32_t sel_clk_binding, sel_clk;
3485 int ret;
3486
3487 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3488 (lvds_ver >= 0x30 && script == LVDS_INIT))
3489 return 0;
3490
3491 if (!bios->fp.lvds_init_run) {
3492 bios->fp.lvds_init_run = true;
3493 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3494 }
3495
3496 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3497 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3498 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3499 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3500
3501 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3502
3503 /* don't let script change pll->head binding */
3504 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3505
3506 if (lvds_ver < 0x30)
3507 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3508 else
3509 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3510
3511 bios->fp.last_script_invoc = (script << 1 | head);
3512
3513 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3514 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3515 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3516 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3517
3518 return ret;
3519}
3520
3521struct lvdstableheader {
3522 uint8_t lvds_ver, headerlen, recordlen;
3523};
3524
3525static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3526{
3527 /*
3528 * BMP version (0xa) LVDS table has a simple header of version and
3529 * record length. The BIT LVDS table has the typical BIT table header:
3530 * version byte, header length byte, record length byte, and a byte for
3531 * the maximum number of records that can be held in the table.
3532 */
3533
3534 uint8_t lvds_ver, headerlen, recordlen;
3535
3536 memset(lth, 0, sizeof(struct lvdstableheader));
3537
3538 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3539 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3540 return -EINVAL;
3541 }
3542
3543 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3544
3545 switch (lvds_ver) {
3546 case 0x0a: /* pre NV40 */
3547 headerlen = 2;
3548 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3549 break;
3550 case 0x30: /* NV4x */
3551 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3552 if (headerlen < 0x1f) {
3553 NV_ERROR(dev, "LVDS table header not understood\n");
3554 return -EINVAL;
3555 }
3556 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3557 break;
3558 case 0x40: /* G80/G90 */
3559 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3560 if (headerlen < 0x7) {
3561 NV_ERROR(dev, "LVDS table header not understood\n");
3562 return -EINVAL;
3563 }
3564 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3565 break;
3566 default:
3567 NV_ERROR(dev,
3568 "LVDS table revision %d.%d not currently supported\n",
3569 lvds_ver >> 4, lvds_ver & 0xf);
3570 return -ENOSYS;
3571 }
3572
3573 lth->lvds_ver = lvds_ver;
3574 lth->headerlen = headerlen;
3575 lth->recordlen = recordlen;
3576
3577 return 0;
3578}
3579
3580static int
3581get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3582{
3583 struct drm_nouveau_private *dev_priv = dev->dev_private;
3584
3585 /*
3586 * The fp strap is normally dictated by the "User Strap" in
3587 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3588 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3589 * by the PCI subsystem ID during POST, but not before the previous user
3590 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3591 * read and used instead
3592 */
3593
3594 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3595 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3596
3597 if (dev_priv->card_type >= NV_50)
3598 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3599 else
3600 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3601}
3602
3603static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3604{
3605 uint8_t *fptable;
3606 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3607 int ret, ofs, fpstrapping;
3608 struct lvdstableheader lth;
3609
3610 if (bios->fp.fptablepointer == 0x0) {
3611 /* Apple cards don't have the fp table; the laptops use DDC */
3612 /* The table is also missing on some x86 IGPs */
3613#ifndef __powerpc__
3614 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3615#endif
04a39c57 3616 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3617 return 0;
3618 }
3619
3620 fptable = &bios->data[bios->fp.fptablepointer];
3621 fptable_ver = fptable[0];
3622
3623 switch (fptable_ver) {
3624 /*
3625 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3626 * version field, and miss one of the spread spectrum/PWM bytes.
3627 * This could affect early GF2Go parts (not seen any appropriate ROMs
3628 * though). Here we assume that a version of 0x05 matches this case
3629 * (combining with a BMP version check would be better), as the
3630 * common case for the panel type field is 0x0005, and that is in
3631 * fact what we are reading the first byte of.
3632 */
3633 case 0x05: /* some NV10, 11, 15, 16 */
3634 recordlen = 42;
3635 ofs = -1;
3636 break;
3637 case 0x10: /* some NV15/16, and NV11+ */
3638 recordlen = 44;
3639 ofs = 0;
3640 break;
3641 case 0x20: /* NV40+ */
3642 headerlen = fptable[1];
3643 recordlen = fptable[2];
3644 fpentries = fptable[3];
3645 /*
3646 * fptable[4] is the minimum
3647 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3648 */
04a39c57 3649 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3650 ofs = -7;
3651 break;
3652 default:
3653 NV_ERROR(dev,
3654 "FP table revision %d.%d not currently supported\n",
3655 fptable_ver >> 4, fptable_ver & 0xf);
3656 return -ENOSYS;
3657 }
3658
3659 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3660 return 0;
3661
3662 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3663 if (ret)
3664 return ret;
3665
3666 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3667 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3668 lth.headerlen + 1;
3669 bios->fp.xlatwidth = lth.recordlen;
3670 }
3671 if (bios->fp.fpxlatetableptr == 0x0) {
3672 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3673 return -EINVAL;
3674 }
3675
3676 fpstrapping = get_fp_strap(dev, bios);
3677
3678 fpindex = bios->data[bios->fp.fpxlatetableptr +
3679 fpstrapping * bios->fp.xlatwidth];
3680
3681 if (fpindex > fpentries) {
3682 NV_ERROR(dev, "Bad flat panel table index\n");
3683 return -ENOENT;
3684 }
3685
3686 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3687 if (lth.lvds_ver > 0x10)
04a39c57 3688 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3689
3690 /*
3691 * If either the strap or xlated fpindex value are 0xf there is no
3692 * panel using a strap-derived bios mode present. this condition
3693 * includes, but is different from, the DDC panel indicator above
3694 */
3695 if (fpstrapping == 0xf || fpindex == 0xf)
3696 return 0;
3697
3698 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3699 recordlen * fpindex + ofs;
3700
3701 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3702 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3703 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3704 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3705
3706 return 0;
3707}
3708
3709bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3710{
3711 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3712 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3713 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3714
3715 if (!mode) /* just checking whether we can produce a mode */
3716 return bios->fp.mode_ptr;
3717
3718 memset(mode, 0, sizeof(struct drm_display_mode));
3719 /*
3720 * For version 1.0 (version in byte 0):
3721 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3722 * single/dual link, and type (TFT etc.)
3723 * bytes 3-6 are bits per colour in RGBX
3724 */
3725 mode->clock = ROM16(mode_entry[7]) * 10;
3726 /* bytes 9-10 is HActive */
3727 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3728 /*
3729 * bytes 13-14 is HValid Start
3730 * bytes 15-16 is HValid End
3731 */
3732 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3733 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3734 mode->htotal = ROM16(mode_entry[21]) + 1;
3735 /* bytes 23-24, 27-30 similarly, but vertical */
3736 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3737 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3738 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3739 mode->vtotal = ROM16(mode_entry[35]) + 1;
3740 mode->flags |= (mode_entry[37] & 0x10) ?
3741 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3742 mode->flags |= (mode_entry[37] & 0x1) ?
3743 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3744 /*
3745 * bytes 38-39 relate to spread spectrum settings
3746 * bytes 40-43 are something to do with PWM
3747 */
3748
3749 mode->status = MODE_OK;
3750 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3751 drm_mode_set_name(mode);
3752 return bios->fp.mode_ptr;
3753}
3754
3755int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3756{
3757 /*
3758 * The LVDS table header is (mostly) described in
3759 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3760 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3761 * straps are not being used for the panel, this specifies the frequency
3762 * at which modes should be set up in the dual link style.
3763 *
3764 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3765 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3766 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3767 * numbers for use by INIT_SUB which controlled panel init and power,
3768 * and finally a dword of ms to sleep between power off and on
3769 * operations.
3770 *
3771 * In the BIT versions, the table following the header serves as an
3772 * integrated config and xlat table: the records in the table are
3773 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3774 * two bytes - the first as a config byte, the second for indexing the
3775 * fp mode table pointed to by the BIT 'D' table
3776 *
3777 * DDC is not used until after card init, so selecting the correct table
3778 * entry and setting the dual link flag for EDID equipped panels,
3779 * requiring tests against the native-mode pixel clock, cannot be done
3780 * until later, when this function should be called with non-zero pxclk
3781 */
3782 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3783 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3784 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3785 struct lvdstableheader lth;
3786 uint16_t lvdsofs;
04a39c57 3787 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3788
3789 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3790 if (ret)
3791 return ret;
3792
3793 switch (lth.lvds_ver) {
3794 case 0x0a: /* pre NV40 */
3795 lvdsmanufacturerindex = bios->data[
3796 bios->fp.fpxlatemanufacturertableptr +
3797 fpstrapping];
3798
3799 /* we're done if this isn't the EDID panel case */
3800 if (!pxclk)
3801 break;
3802
3803 if (chip_version < 0x25) {
3804 /* nv17 behaviour
3805 *
3806 * It seems the old style lvds script pointer is reused
3807 * to select 18/24 bit colour depth for EDID panels.
3808 */
3809 lvdsmanufacturerindex =
3810 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3811 2 : 0;
3812 if (pxclk >= bios->fp.duallink_transition_clk)
3813 lvdsmanufacturerindex++;
3814 } else if (chip_version < 0x30) {
3815 /* nv28 behaviour (off-chip encoder)
3816 *
3817 * nv28 does a complex dance of first using byte 121 of
3818 * the EDID to choose the lvdsmanufacturerindex, then
3819 * later attempting to match the EDID manufacturer and
3820 * product IDs in a table (signature 'pidt' (panel id
3821 * table?)), setting an lvdsmanufacturerindex of 0 and
3822 * an fp strap of the match index (or 0xf if none)
3823 */
3824 lvdsmanufacturerindex = 0;
3825 } else {
3826 /* nv31, nv34 behaviour */
3827 lvdsmanufacturerindex = 0;
3828 if (pxclk >= bios->fp.duallink_transition_clk)
3829 lvdsmanufacturerindex = 2;
3830 if (pxclk >= 140000)
3831 lvdsmanufacturerindex = 3;
3832 }
3833
3834 /*
3835 * nvidia set the high nibble of (cr57=f, cr58) to
3836 * lvdsmanufacturerindex in this case; we don't
3837 */
3838 break;
3839 case 0x30: /* NV4x */
3840 case 0x40: /* G80/G90 */
3841 lvdsmanufacturerindex = fpstrapping;
3842 break;
3843 default:
3844 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3845 return -ENOSYS;
3846 }
3847
3848 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3849 switch (lth.lvds_ver) {
3850 case 0x0a:
3851 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3852 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3853 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3854 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3855 *if_is_24bit = bios->data[lvdsofs] & 16;
3856 break;
3857 case 0x30:
f3bbb9cc 3858 case 0x40:
6ee73861
BS		 3859 /*
3860 * No sign of the "power off for reset" or "reset for panel
3861 * on" bits, but it's safer to assume we should
3862 */
3863 bios->fp.power_off_for_reset = true;
3864 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3865
6ee73861
BS		 3866 /*
3867 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3868 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3869 */
3870 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3871 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3872 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3873 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3874 break;
3875 }
3876
2eb92c80
BS		 3877 /* Dell Latitude D620 reports a too-high value for the dual-link
3878 * transition freq, causing us to program the panel incorrectly.
3879 *
3880 * It doesn't appear the VBIOS actually uses its transition freq
3881 * (90000kHz), instead it uses the "Number of LVDS channels" field
3882 * out of the panel ID structure (http://www.spwg.org/).
3883 *
3884 * For the moment, a quirk will do :)
3885 */
3886 if ((dev->pdev->device == 0x01d7) &&
3887 (dev->pdev->subsystem_vendor == 0x1028) &&
3888 (dev->pdev->subsystem_device == 0x01c2)) {
3889 bios->fp.duallink_transition_clk = 80000;
3890 }
3891
6ee73861
BS		 3892 /* set dual_link flag for EDID case */
3893 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3894 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3895
3896 *dl = bios->fp.dual_link;
3897
3898 return 0;
3899}
3900
3901static uint8_t *
3902bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3903 uint16_t record, int record_len, int record_nr)
3904{
3905 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3906 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3907 uint32_t entry;
3908 uint16_t table;
3909 int i, v;
3910
3911 for (i = 0; i < record_nr; i++, record += record_len) {
3912 table = ROM16(bios->data[record]);
3913 if (!table)
3914 continue;
3915 entry = ROM32(bios->data[table]);
3916
3917 v = (entry & 0x000f0000) >> 16;
3918 if (!(v & dcbent->or))
3919 continue;
3920
3921 v = (entry & 0x000000f0) >> 4;
3922 if (v != dcbent->location)
3923 continue;
3924
3925 v = (entry & 0x0000000f);
3926 if (v != dcbent->type)
3927 continue;
3928
3929 return &bios->data[table];
3930 }
3931
3932 return NULL;
3933}
3934
3935void *
3936nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3937 int *length)
3938{
3939 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3940 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3941 uint8_t *table;
3942
3943 if (!bios->display.dp_table_ptr) {
3944 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3945 return NULL;
3946 }
3947 table = &bios->data[bios->display.dp_table_ptr];
3948
c52e53fd 3949 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 3950 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3951 table[0]);
3952 return NULL;
3953 }
3954
3955 *length = table[4];
3956 return bios_output_config_match(dev, dcbent,
3957 bios->display.dp_table_ptr + table[1],
3958 table[2], table[3]);
3959}
3960
3961int
3962nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3963 uint32_t sub, int pxclk)
3964{
3965 /*
3966 * The display script table is located by the BIT 'U' table.
3967 *
3968 * It contains an array of pointers to various tables describing
3969 * a particular output type. The first 32-bits of the output
3970 * tables contains similar information to a DCB entry, and is
3971 * used to decide whether that particular table is suitable for
3972 * the output you want to access.
3973 *
3974 * The "record header length" field here seems to indicate the
3975 * offset of the first configuration entry in the output tables.
3976 * This is 10 on most cards I've seen, but 12 has been witnessed
3977 * on DP cards, and there's another script pointer within the
3978 * header.
3979 *
3980 * offset + 0 ( 8 bits): version
3981 * offset + 1 ( 8 bits): header length
3982 * offset + 2 ( 8 bits): record length
3983 * offset + 3 ( 8 bits): number of records
3984 * offset + 4 ( 8 bits): record header length
3985 * offset + 5 (16 bits): pointer to first output script table
3986 */
3987
3988 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3989 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3990 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3991 uint8_t *otable = NULL;
3992 uint16_t script;
3993 int i = 0;
3994
3995 if (!bios->display.script_table_ptr) {
3996 NV_ERROR(dev, "No pointer to output script table\n");
3997 return 1;
3998 }
3999
4000 /*
4001 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4002 * so until they are, we really don't need to care.
4003 */
4004 if (table[0] < 0x20)
4005 return 1;
4006
4007 if (table[0] != 0x20 && table[0] != 0x21) {
4008 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4009 table[0]);
4010 return 1;
4011 }
4012
4013 /*
4014 * The output script tables describing a particular output type
4015 * look as follows:
4016 *
4017 * offset + 0 (32 bits): output this table matches (hash of DCB)
4018 * offset + 4 ( 8 bits): unknown
4019 * offset + 5 ( 8 bits): number of configurations
4020 * offset + 6 (16 bits): pointer to some script
4021 * offset + 8 (16 bits): pointer to some script
4022 *
4023 * headerlen == 10
4024 * offset + 10 : configuration 0
4025 *
4026 * headerlen == 12
4027 * offset + 10 : pointer to some script
4028 * offset + 12 : configuration 0
4029 *
4030 * Each config entry is as follows:
4031 *
4032 * offset + 0 (16 bits): unknown, assumed to be a match value
4033 * offset + 2 (16 bits): pointer to script table (clock set?)
4034 * offset + 4 (16 bits): pointer to script table (reset?)
4035 *
4036 * There doesn't appear to be a count value to say how many
4037 * entries exist in each script table, instead, a 0 value in
4038 * the first 16-bit word seems to indicate both the end of the
4039 * list and the default entry. The second 16-bit word in the
4040 * script tables is a pointer to the script to execute.
4041 */
4042
ef2bb506 4043 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4044 dcbent->type, dcbent->location, dcbent->or);
4045 otable = bios_output_config_match(dev, dcbent, table[1] +
4046 bios->display.script_table_ptr,
4047 table[2], table[3]);
4048 if (!otable) {
4049 NV_ERROR(dev, "Couldn't find matching output script table\n");
4050 return 1;
4051 }
4052
4053 if (pxclk < -2 || pxclk > 0) {
4054 /* Try to find matching script table entry */
4055 for (i = 0; i < otable[5]; i++) {
4056 if (ROM16(otable[table[4] + i*6]) == sub)
4057 break;
4058 }
4059
4060 if (i == otable[5]) {
4061 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4062 "using first\n",
4063 sub, dcbent->type, dcbent->or);
4064 i = 0;
4065 }
4066 }
4067
6ee73861
BS		 4068 if (pxclk == 0) {
4069 script = ROM16(otable[6]);
4070 if (!script) {
ef2bb506 4071 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4072 return 1;
4073 }
4074
4075 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4076 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4077 } else
4078 if (pxclk == -1) {
4079 script = ROM16(otable[8]);
4080 if (!script) {
ef2bb506 4081 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4082 return 1;
4083 }
4084
4085 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4086 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4087 } else
4088 if (pxclk == -2) {
4089 if (table[4] >= 12)
4090 script = ROM16(otable[10]);
4091 else
4092 script = 0;
4093 if (!script) {
ef2bb506 4094 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4095 return 1;
4096 }
4097
4098 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4099 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4100 } else
4101 if (pxclk > 0) {
4102 script = ROM16(otable[table[4] + i*6 + 2]);
4103 if (script)
4104 script = clkcmptable(bios, script, pxclk);
4105 if (!script) {
4106 NV_ERROR(dev, "clock script 0 not found\n");
4107 return 1;
4108 }
4109
4110 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4111 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4112 } else
4113 if (pxclk < 0) {
4114 script = ROM16(otable[table[4] + i*6 + 4]);
4115 if (script)
4116 script = clkcmptable(bios, script, -pxclk);
4117 if (!script) {
ef2bb506 4118 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4119 return 1;
4120 }
4121
4122 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4123 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4124 }
4125
4126 return 0;
4127}
4128
4129
4130int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4131{
4132 /*
4133 * the pxclk parameter is in kHz
4134 *
4135 * This runs the TMDS regs setting code found on BIT bios cards
4136 *
4137 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4138 * ffs(or) == 3, use the second.
4139 */
4140
4141 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4142 struct nvbios *bios = &dev_priv->vbios;
4143 int cv = bios->chip_version;
6ee73861
BS		 4144 uint16_t clktable = 0, scriptptr;
4145 uint32_t sel_clk_binding, sel_clk;
4146
4147 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4148 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4149 dcbent->location != DCB_LOC_ON_CHIP)
4150 return 0;
4151
4152 switch (ffs(dcbent->or)) {
4153 case 1:
4154 clktable = bios->tmds.output0_script_ptr;
4155 break;
4156 case 2:
4157 case 3:
4158 clktable = bios->tmds.output1_script_ptr;
4159 break;
4160 }
4161
4162 if (!clktable) {
4163 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4164 return -EINVAL;
4165 }
4166
4167 scriptptr = clkcmptable(bios, clktable, pxclk);
4168
4169 if (!scriptptr) {
4170 NV_ERROR(dev, "TMDS output init script not found\n");
4171 return -ENOENT;
4172 }
4173
4174 /* don't let script change pll->head binding */
4175 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4176 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4177 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4178 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4179
4180 return 0;
4181}
4182
4183int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4184{
4185 /*
4186 * PLL limits table
4187 *
4188 * Version 0x10: NV30, NV31
4189 * One byte header (version), one record of 24 bytes
4190 * Version 0x11: NV36 - Not implemented
4191 * Seems to have same record style as 0x10, but 3 records rather than 1
4192 * Version 0x20: Found on Geforce 6 cards
4193 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4194 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4195 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4196 * length in general, some (integrated) have an extra configuration byte
4197 * Version 0x30: Found on Geforce 8, separates the register mapping
4198 * from the limits tables.
4199 */
4200
4201 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4202 struct nvbios *bios = &dev_priv->vbios;
4203 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4204 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4205 uint32_t crystal_strap_mask, crystal_straps;
4206
4207 if (!bios->pll_limit_tbl_ptr) {
4208 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4209 cv >= 0x40) {
4210 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4211 return -EINVAL;
4212 }
4213 } else
4214 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4215
4216 crystal_strap_mask = 1 << 6;
4217 /* open coded dev->twoHeads test */
4218 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4219 crystal_strap_mask |= 1 << 22;
4220 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4221 crystal_strap_mask;
4222
4223 switch (pll_lim_ver) {
4224 /*
4225 * We use version 0 to indicate a pre limit table bios (single stage
4226 * pll) and load the hard coded limits instead.
4227 */
4228 case 0:
4229 break;
4230 case 0x10:
4231 case 0x11:
4232 /*
4233 * Strictly v0x11 has 3 entries, but the last two don't seem
4234 * to get used.
4235 */
4236 headerlen = 1;
4237 recordlen = 0x18;
4238 entries = 1;
4239 pllindex = 0;
4240 break;
4241 case 0x20:
4242 case 0x21:
4243 case 0x30:
4244 case 0x40:
4245 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4246 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4247 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4248 break;
4249 default:
4250 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4251 "supported\n", pll_lim_ver);
4252 return -ENOSYS;
4253 }
4254
4255 /* initialize all members to zero */
4256 memset(pll_lim, 0, sizeof(struct pll_lims));
4257
4258 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4259 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4260
4261 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4262 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4263 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4264 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4265 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4266 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4267 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4268
4269 /* these values taken from nv30/31/36 */
4270 pll_lim->vco1.min_n = 0x1;
4271 if (cv == 0x36)
4272 pll_lim->vco1.min_n = 0x5;
4273 pll_lim->vco1.max_n = 0xff;
4274 pll_lim->vco1.min_m = 0x1;
4275 pll_lim->vco1.max_m = 0xd;
4276 pll_lim->vco2.min_n = 0x4;
4277 /*
4278 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4279 * table version (apart from nv35)), N2 is compared to
4280 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4281 * save a comparison
4282 */
4283 pll_lim->vco2.max_n = 0x28;
4284 if (cv == 0x30 || cv == 0x35)
4285 /* only 5 bits available for N2 on nv30/35 */
4286 pll_lim->vco2.max_n = 0x1f;
4287 pll_lim->vco2.min_m = 0x1;
4288 pll_lim->vco2.max_m = 0x4;
4289 pll_lim->max_log2p = 0x7;
4290 pll_lim->max_usable_log2p = 0x6;
4291 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4292 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4293 uint32_t reg = 0; /* default match */
4294 uint8_t *pll_rec;
4295 int i;
4296
4297 /*
4298 * First entry is default match, if nothing better. warn if
4299 * reg field nonzero
4300 */
4301 if (ROM32(bios->data[plloffs]))
4302 NV_WARN(dev, "Default PLL limit entry has non-zero "
4303 "register field\n");
4304
4305 if (limit_match > MAX_PLL_TYPES)
4306 /* we've been passed a reg as the match */
4307 reg = limit_match;
4308 else /* limit match is a pll type */
4309 for (i = 1; i < entries && !reg; i++) {
4310 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4311
4312 if (limit_match == NVPLL &&
4313 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4314 reg = cmpreg;
4315 if (limit_match == MPLL &&
4316 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4317 reg = cmpreg;
4318 if (limit_match == VPLL1 &&
4319 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4320 reg = cmpreg;
4321 if (limit_match == VPLL2 &&
4322 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4323 reg = cmpreg;
4324 }
4325
4326 for (i = 1; i < entries; i++)
4327 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4328 pllindex = i;
4329 break;
4330 }
4331
4332 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4333
4334 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4335 pllindex ? reg : 0);
4336
4337 /*
4338 * Frequencies are stored in tables in MHz, kHz are more
4339 * useful, so we convert.
4340 */
4341
4342 /* What output frequencies can each VCO generate? */
4343 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4344 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4345 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4346 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4347
4348 /* What input frequencies they accept (past the m-divider)? */
4349 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4350 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4351 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4352 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4353
4354 /* What values are accepted as multiplier and divider? */
4355 pll_lim->vco1.min_n = pll_rec[20];
4356 pll_lim->vco1.max_n = pll_rec[21];
4357 pll_lim->vco1.min_m = pll_rec[22];
4358 pll_lim->vco1.max_m = pll_rec[23];
4359 pll_lim->vco2.min_n = pll_rec[24];
4360 pll_lim->vco2.max_n = pll_rec[25];
4361 pll_lim->vco2.min_m = pll_rec[26];
4362 pll_lim->vco2.max_m = pll_rec[27];
4363
4364 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4365 if (pll_lim->max_log2p > 0x7)
4366 /* pll decoding in nv_hw.c assumes never > 7 */
4367 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4368 pll_lim->max_log2p);
4369 if (cv < 0x60)
4370 pll_lim->max_usable_log2p = 0x6;
4371 pll_lim->log2p_bias = pll_rec[30];
4372
4373 if (recordlen > 0x22)
4374 pll_lim->refclk = ROM32(pll_rec[31]);
4375
4376 if (recordlen > 0x23 && pll_rec[35])
4377 NV_WARN(dev,
4378 "Bits set in PLL configuration byte (%x)\n",
4379 pll_rec[35]);
4380
4381 /* C51 special not seen elsewhere */
4382 if (cv == 0x51 && !pll_lim->refclk) {
4383 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4384
4385 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4386 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4387 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4388 pll_lim->refclk = 200000;
4389 else
4390 pll_lim->refclk = 25000;
4391 }
4392 }
4393 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4394 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4395 uint8_t *record = NULL;
4396 int i;
4397
4398 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4399 limit_match);
4400
4401 for (i = 0; i < entries; i++, entry += recordlen) {
4402 if (ROM32(entry[3]) == limit_match) {
4403 record = &bios->data[ROM16(entry[1])];
4404 break;
4405 }
4406 }
4407
4408 if (!record) {
4409 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4410 "limits table", limit_match);
4411 return -ENOENT;
4412 }
4413
4414 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4415 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4416 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4417 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4418 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4419 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4420 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4421 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4422 pll_lim->vco1.min_n = record[16];
4423 pll_lim->vco1.max_n = record[17];
4424 pll_lim->vco1.min_m = record[18];
4425 pll_lim->vco1.max_m = record[19];
4426 pll_lim->vco2.min_n = record[20];
4427 pll_lim->vco2.max_n = record[21];
4428 pll_lim->vco2.min_m = record[22];
4429 pll_lim->vco2.max_m = record[23];
4430 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4431 pll_lim->log2p_bias = record[27];
4432 pll_lim->refclk = ROM32(record[28]);
4433 } else if (pll_lim_ver) { /* ver 0x40 */
4434 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4435 uint8_t *record = NULL;
4436 int i;
4437
4438 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4439 limit_match);
4440
4441 for (i = 0; i < entries; i++, entry += recordlen) {
4442 if (ROM32(entry[3]) == limit_match) {
4443 record = &bios->data[ROM16(entry[1])];
4444 break;
4445 }
4446 }
4447
4448 if (!record) {
4449 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4450 "limits table", limit_match);
4451 return -ENOENT;
4452 }
4453
4454 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4455 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4456 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4457 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4458 pll_lim->vco1.min_m = record[8];
4459 pll_lim->vco1.max_m = record[9];
4460 pll_lim->vco1.min_n = record[10];
4461 pll_lim->vco1.max_n = record[11];
4462 pll_lim->min_p = record[12];
4463 pll_lim->max_p = record[13];
4464 /* where did this go to?? */
4465 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4466 pll_lim->refclk = 27000;
4467 else
4468 pll_lim->refclk = 100000;
4469 }
4470
4471 /*
4472 * By now any valid limit table ought to have set a max frequency for
4473 * vco1, so if it's zero it's either a pre limit table bios, or one
4474 * with an empty limit table (seen on nv18)
4475 */
4476 if (!pll_lim->vco1.maxfreq) {
4477 pll_lim->vco1.minfreq = bios->fminvco;
4478 pll_lim->vco1.maxfreq = bios->fmaxvco;
4479 pll_lim->vco1.min_inputfreq = 0;
4480 pll_lim->vco1.max_inputfreq = INT_MAX;
4481 pll_lim->vco1.min_n = 0x1;
4482 pll_lim->vco1.max_n = 0xff;
4483 pll_lim->vco1.min_m = 0x1;
4484 if (crystal_straps == 0) {
4485 /* nv05 does this, nv11 doesn't, nv10 unknown */
4486 if (cv < 0x11)
4487 pll_lim->vco1.min_m = 0x7;
4488 pll_lim->vco1.max_m = 0xd;
4489 } else {
4490 if (cv < 0x11)
4491 pll_lim->vco1.min_m = 0x8;
4492 pll_lim->vco1.max_m = 0xe;
4493 }
4494 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4495 pll_lim->max_log2p = 4;
4496 else
4497 pll_lim->max_log2p = 5;
4498 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4499 }
4500
4501 if (!pll_lim->refclk)
4502 switch (crystal_straps) {
4503 case 0:
4504 pll_lim->refclk = 13500;
4505 break;
4506 case (1 << 6):
4507 pll_lim->refclk = 14318;
4508 break;
4509 case (1 << 22):
4510 pll_lim->refclk = 27000;
4511 break;
4512 case (1 << 22 | 1 << 6):
4513 pll_lim->refclk = 25000;
4514 break;
4515 }
4516
4c389f00
BS		 4517 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4518 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4519 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4520 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4521 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4522 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4523 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4524 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4525 if (pll_lim->vco2.maxfreq) {
4526 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4527 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4528 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4529 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4530 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4531 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4532 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4533 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4534 }
4535 if (!pll_lim->max_p) {
4536 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4537 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4538 } else {
4539 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4540 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4541 }
4542 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4543
4544 return 0;
4545}
4546
4547static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4548{
4549 /*
4550 * offset + 0 (8 bits): Micro version
4551 * offset + 1 (8 bits): Minor version
4552 * offset + 2 (8 bits): Chip version
4553 * offset + 3 (8 bits): Major version
4554 */
4555
4556 bios->major_version = bios->data[offset + 3];
04a39c57 4557 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4558 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4559 bios->data[offset + 3], bios->data[offset + 2],
4560 bios->data[offset + 1], bios->data[offset]);
4561}
4562
4563static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4564{
4565 /*
4566 * Parses the init table segment for pointers used in script execution.
4567 *
4568 * offset + 0 (16 bits): init script tables pointer
4569 * offset + 2 (16 bits): macro index table pointer
4570 * offset + 4 (16 bits): macro table pointer
4571 * offset + 6 (16 bits): condition table pointer
4572 * offset + 8 (16 bits): io condition table pointer
4573 * offset + 10 (16 bits): io flag condition table pointer
4574 * offset + 12 (16 bits): init function table pointer
4575 */
4576
4577 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4578 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4579 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4580 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4581 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4582 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4583 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4584}
4585
4586static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4587{
4588 /*
4589 * Parses the load detect values for g80 cards.
4590 *
4591 * offset + 0 (16 bits): loadval table pointer
4592 */
4593
4594 uint16_t load_table_ptr;
4595 uint8_t version, headerlen, entrylen, num_entries;
4596
4597 if (bitentry->length != 3) {
4598 NV_ERROR(dev, "Do not understand BIT A table\n");
4599 return -EINVAL;
4600 }
4601
4602 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4603
4604 if (load_table_ptr == 0x0) {
4605 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4606 return -EINVAL;
4607 }
4608
4609 version = bios->data[load_table_ptr];
4610
4611 if (version != 0x10) {
4612 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4613 version >> 4, version & 0xF);
4614 return -ENOSYS;
4615 }
4616
4617 headerlen = bios->data[load_table_ptr + 1];
4618 entrylen = bios->data[load_table_ptr + 2];
4619 num_entries = bios->data[load_table_ptr + 3];
4620
4621 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4622 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4623 return -EINVAL;
4624 }
4625
4626 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4627 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4628
4629 return 0;
4630}
4631
4632static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4633{
4634 /*
4635 * offset + 8 (16 bits): PLL limits table pointer
4636 *
4637 * There's more in here, but that's unknown.
4638 */
4639
4640 if (bitentry->length < 10) {
4641 NV_ERROR(dev, "Do not understand BIT C table\n");
4642 return -EINVAL;
4643 }
4644
4645 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4646
4647 return 0;
4648}
4649
4650static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4651{
4652 /*
4653 * Parses the flat panel table segment that the bit entry points to.
4654 * Starting at bitentry->offset:
4655 *
4656 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4657 * records beginning with a freq.
4658 * offset + 2 (16 bits): mode table pointer
4659 */
4660
4661 if (bitentry->length != 4) {
4662 NV_ERROR(dev, "Do not understand BIT display table\n");
4663 return -EINVAL;
4664 }
4665
4666 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4667
4668 return 0;
4669}
4670
4671static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4672{
4673 /*
4674 * Parses the init table segment that the bit entry points to.
4675 *
4676 * See parse_script_table_pointers for layout
4677 */
4678
4679 if (bitentry->length < 14) {
4680 NV_ERROR(dev, "Do not understand init table\n");
4681 return -EINVAL;
4682 }
4683
4684 parse_script_table_pointers(bios, bitentry->offset);
4685
4686 if (bitentry->length >= 16)
4687 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4688 if (bitentry->length >= 18)
4689 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4690
4691 return 0;
4692}
4693
4694static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4695{
4696 /*
4697 * BIT 'i' (info?) table
4698 *
4699 * offset + 0 (32 bits): BIOS version dword (as in B table)
4700 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4701 * offset + 13 (16 bits): pointer to table containing DAC load
4702 * detection comparison values
4703 *
4704 * There's other things in the table, purpose unknown
4705 */
4706
4707 uint16_t daccmpoffset;
4708 uint8_t dacver, dacheaderlen;
4709
4710 if (bitentry->length < 6) {
4711 NV_ERROR(dev, "BIT i table too short for needed information\n");
4712 return -EINVAL;
4713 }
4714
4715 parse_bios_version(dev, bios, bitentry->offset);
4716
4717 /*
4718 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4719 * Quadro identity crisis), other bits possibly as for BMP feature byte
4720 */
4721 bios->feature_byte = bios->data[bitentry->offset + 5];
4722 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4723
4724 if (bitentry->length < 15) {
4725 NV_WARN(dev, "BIT i table not long enough for DAC load "
4726 "detection comparison table\n");
4727 return -EINVAL;
4728 }
4729
4730 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4731
4732 /* doesn't exist on g80 */
4733 if (!daccmpoffset)
4734 return 0;
4735
4736 /*
4737 * The first value in the table, following the header, is the
4738 * comparison value, the second entry is a comparison value for
4739 * TV load detection.
4740 */
4741
4742 dacver = bios->data[daccmpoffset];
4743 dacheaderlen = bios->data[daccmpoffset + 1];
4744
4745 if (dacver != 0x00 && dacver != 0x10) {
4746 NV_WARN(dev, "DAC load detection comparison table version "
4747 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4748 return -ENOSYS;
4749 }
4750
04a39c57
BS		 4751 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4752 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4753
4754 return 0;
4755}
4756
4757static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4758{
4759 /*
4760 * Parses the LVDS table segment that the bit entry points to.
4761 * Starting at bitentry->offset:
4762 *
4763 * offset + 0 (16 bits): LVDS strap xlate table pointer
4764 */
4765
4766 if (bitentry->length != 2) {
4767 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4768 return -EINVAL;
4769 }
4770
4771 /*
4772 * No idea if it's still called the LVDS manufacturer table, but
4773 * the concept's close enough.
4774 */
4775 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4776
4777 return 0;
4778}
4779
4780static int
4781parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4782 struct bit_entry *bitentry)
4783{
4784 /*
4785 * offset + 2 (8 bits): number of options in an
4786 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4787 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4788 * restrict option selection
4789 *
4790 * There's a bunch of bits in this table other than the RAM restrict
4791 * stuff that we don't use - their use currently unknown
4792 */
4793
6ee73861
BS		 4794 /*
4795 * Older bios versions don't have a sufficiently long table for
4796 * what we want
4797 */
4798 if (bitentry->length < 0x5)
4799 return 0;
4800
4801 if (bitentry->id[1] < 2) {
37383650
MK		 4802 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4803 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4804 } else {
37383650
MK		 4805 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4806 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4807 }
4808
6ee73861
BS		 4809 return 0;
4810}
4811
4812static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4813{
4814 /*
4815 * Parses the pointer to the TMDS table
4816 *
4817 * Starting at bitentry->offset:
4818 *
4819 * offset + 0 (16 bits): TMDS table pointer
4820 *
4821 * The TMDS table is typically found just before the DCB table, with a
4822 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4823 * length?)
4824 *
4825 * At offset +7 is a pointer to a script, which I don't know how to
4826 * run yet.
4827 * At offset +9 is a pointer to another script, likewise
4828 * Offset +11 has a pointer to a table where the first word is a pxclk
4829 * frequency and the second word a pointer to a script, which should be
4830 * run if the comparison pxclk frequency is less than the pxclk desired.
4831 * This repeats for decreasing comparison frequencies
4832 * Offset +13 has a pointer to a similar table
4833 * The selection of table (and possibly +7/+9 script) is dictated by
4834 * "or" from the DCB.
4835 */
4836
4837 uint16_t tmdstableptr, script1, script2;
4838
4839 if (bitentry->length != 2) {
4840 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4841 return -EINVAL;
4842 }
4843
4844 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4845
4846 if (tmdstableptr == 0x0) {
4847 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4848 return -EINVAL;
4849 }
4850
4851 /* nv50+ has v2.0, but we don't parse it atm */
4852 if (bios->data[tmdstableptr] != 0x11) {
4853 NV_WARN(dev,
4854 "TMDS table revision %d.%d not currently supported\n",
4855 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4856 return -ENOSYS;
4857 }
4858
4859 /*
4860 * These two scripts are odd: they don't seem to get run even when
4861 * they are not stubbed.
4862 */
4863 script1 = ROM16(bios->data[tmdstableptr + 7]);
4864 script2 = ROM16(bios->data[tmdstableptr + 9]);
4865 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4866 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4867
4868 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4869 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4870
4871 return 0;
4872}
4873
4874static int
4875parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4876 struct bit_entry *bitentry)
4877{
4878 /*
4879 * Parses the pointer to the G80 output script tables
4880 *
4881 * Starting at bitentry->offset:
4882 *
4883 * offset + 0 (16 bits): output script table pointer
4884 */
4885
4886 uint16_t outputscripttableptr;
4887
4888 if (bitentry->length != 3) {
4889 NV_ERROR(dev, "Do not understand BIT U table\n");
4890 return -EINVAL;
4891 }
4892
4893 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4894 bios->display.script_table_ptr = outputscripttableptr;
4895 return 0;
4896}
4897
4898static int
4899parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4900 struct bit_entry *bitentry)
4901{
4902 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4903 return 0;
4904}
4905
4906struct bit_table {
4907 const char id;
4908 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4909};
4910
4911#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4912
4913static int
4914parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4915 struct bit_table *table)
4916{
4917 struct drm_device *dev = bios->dev;
4918 uint8_t maxentries = bios->data[bitoffset + 4];
4919 int i, offset;
4920 struct bit_entry bitentry;
4921
4922 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4923 bitentry.id[0] = bios->data[offset];
4924
4925 if (bitentry.id[0] != table->id)
4926 continue;
4927
4928 bitentry.id[1] = bios->data[offset + 1];
4929 bitentry.length = ROM16(bios->data[offset + 2]);
4930 bitentry.offset = ROM16(bios->data[offset + 4]);
4931
4932 return table->parse_fn(dev, bios, &bitentry);
4933 }
4934
4935 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4936 return -ENOSYS;
4937}
4938
4939static int
4940parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4941{
4942 int ret;
4943
4944 /*
4945 * The only restriction on parsing order currently is having 'i' first
4946 * for use of bios->*_version or bios->feature_byte while parsing;
4947 * functions shouldn't be actually *doing* anything apart from pulling
4948 * data from the image into the bios struct, thus no interdependencies
4949 */
4950 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4951 if (ret) /* info? */
4952 return ret;
4953 if (bios->major_version >= 0x60) /* g80+ */
4954 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4955 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4956 if (ret)
4957 return ret;
4958 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4959 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4960 if (ret)
4961 return ret;
4962 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4963 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4964 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4965 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4966 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4967
4968 return 0;
4969}
4970
4971static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4972{
4973 /*
4974 * Parses the BMP structure for useful things, but does not act on them
4975 *
4976 * offset + 5: BMP major version
4977 * offset + 6: BMP minor version
4978 * offset + 9: BMP feature byte
4979 * offset + 10: BCD encoded BIOS version
4980 *
4981 * offset + 18: init script table pointer (for bios versions < 5.10h)
4982 * offset + 20: extra init script table pointer (for bios
4983 * versions < 5.10h)
4984 *
4985 * offset + 24: memory init table pointer (used on early bios versions)
4986 * offset + 26: SDR memory sequencing setup data table
4987 * offset + 28: DDR memory sequencing setup data table
4988 *
4989 * offset + 54: index of I2C CRTC pair to use for CRT output
4990 * offset + 55: index of I2C CRTC pair to use for TV output
4991 * offset + 56: index of I2C CRTC pair to use for flat panel output
4992 * offset + 58: write CRTC index for I2C pair 0
4993 * offset + 59: read CRTC index for I2C pair 0
4994 * offset + 60: write CRTC index for I2C pair 1
4995 * offset + 61: read CRTC index for I2C pair 1
4996 *
4997 * offset + 67: maximum internal PLL frequency (single stage PLL)
4998 * offset + 71: minimum internal PLL frequency (single stage PLL)
4999 *
5000 * offset + 75: script table pointers, as described in
5001 * parse_script_table_pointers
5002 *
5003 * offset + 89: TMDS single link output A table pointer
5004 * offset + 91: TMDS single link output B table pointer
5005 * offset + 95: LVDS single link output A table pointer
5006 * offset + 105: flat panel timings table pointer
5007 * offset + 107: flat panel strapping translation table pointer
5008 * offset + 117: LVDS manufacturer panel config table pointer
5009 * offset + 119: LVDS manufacturer strapping translation table pointer
5010 *
5011 * offset + 142: PLL limits table pointer
5012 *
5013 * offset + 156: minimum pixel clock for LVDS dual link
5014 */
5015
5016 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5017 uint16_t bmplength;
5018 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5019
5020 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5021 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5022 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5023 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5024 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5025 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5026 bios->fmaxvco = 256000;
5027 bios->fminvco = 128000;
5028 bios->fp.duallink_transition_clk = 90000;
5029
5030 bmp_version_major = bmp[5];
5031 bmp_version_minor = bmp[6];
5032
5033 NV_TRACE(dev, "BMP version %d.%d\n",
5034 bmp_version_major, bmp_version_minor);
5035
5036 /*
5037 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5038 * pointer on early versions
5039 */
5040 if (bmp_version_major < 5)
5041 *(uint16_t *)&bios->data[0x36] = 0;
5042
5043 /*
5044 * Seems that the minor version was 1 for all major versions prior
5045 * to 5. Version 6 could theoretically exist, but I suspect BIT
5046 * happened instead.
5047 */
5048 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5049 NV_ERROR(dev, "You have an unsupported BMP version. "
5050 "Please send in your bios\n");
5051 return -ENOSYS;
5052 }
5053
5054 if (bmp_version_major == 0)
5055 /* nothing that's currently useful in this version */
5056 return 0;
5057 else if (bmp_version_major == 1)
5058 bmplength = 44; /* exact for 1.01 */
5059 else if (bmp_version_major == 2)
5060 bmplength = 48; /* exact for 2.01 */
5061 else if (bmp_version_major == 3)
5062 bmplength = 54;
5063 /* guessed - mem init tables added in this version */
5064 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5065 /* don't know if 5.0 exists... */
5066 bmplength = 62;
5067 /* guessed - BMP I2C indices added in version 4*/
5068 else if (bmp_version_minor < 0x6)
5069 bmplength = 67; /* exact for 5.01 */
5070 else if (bmp_version_minor < 0x10)
5071 bmplength = 75; /* exact for 5.06 */
5072 else if (bmp_version_minor == 0x10)
5073 bmplength = 89; /* exact for 5.10h */
5074 else if (bmp_version_minor < 0x14)
5075 bmplength = 118; /* exact for 5.11h */
5076 else if (bmp_version_minor < 0x24)
5077 /*
5078 * Not sure of version where pll limits came in;
5079 * certainly exist by 0x24 though.
5080 */
5081 /* length not exact: this is long enough to get lvds members */
5082 bmplength = 123;
5083 else if (bmp_version_minor < 0x27)
5084 /*
5085 * Length not exact: this is long enough to get pll limit
5086 * member
5087 */
5088 bmplength = 144;
5089 else
5090 /*
5091 * Length not exact: this is long enough to get dual link
5092 * transition clock.
5093 */
5094 bmplength = 158;
5095
5096 /* checksum */
5097 if (nv_cksum(bmp, 8)) {
5098 NV_ERROR(dev, "Bad BMP checksum\n");
5099 return -EINVAL;
5100 }
5101
5102 /*
5103 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5104 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5105 * (not nv10gl), bit 5 that the flat panel tables are present, and
5106 * bit 6 a tv bios.
5107 */
5108 bios->feature_byte = bmp[9];
5109
5110 parse_bios_version(dev, bios, offset + 10);
5111
5112 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5113 bios->old_style_init = true;
5114 legacy_scripts_offset = 18;
5115 if (bmp_version_major < 2)
5116 legacy_scripts_offset -= 4;
5117 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5118 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5119
5120 if (bmp_version_major > 2) { /* appears in BMP 3 */
5121 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5122 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5123 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5124 }
5125
5126 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5127 if (bmplength > 61)
5128 legacy_i2c_offset = offset + 54;
5129 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5130 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5131 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 5132 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5133 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5134 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5135 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5136
5137 if (bmplength > 74) {
5138 bios->fmaxvco = ROM32(bmp[67]);
5139 bios->fminvco = ROM32(bmp[71]);
5140 }
5141 if (bmplength > 88)
5142 parse_script_table_pointers(bios, offset + 75);
5143 if (bmplength > 94) {
5144 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5145 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5146 /*
5147 * Never observed in use with lvds scripts, but is reused for
5148 * 18/24 bit panel interface default for EDID equipped panels
5149 * (if_is_24bit not set directly to avoid any oscillation).
5150 */
5151 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5152 }
5153 if (bmplength > 108) {
5154 bios->fp.fptablepointer = ROM16(bmp[105]);
5155 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5156 bios->fp.xlatwidth = 1;
5157 }
5158 if (bmplength > 120) {
5159 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5160 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5161 }
5162 if (bmplength > 143)
5163 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5164
5165 if (bmplength > 157)
5166 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5167
5168 return 0;
5169}
5170
5171static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5172{
5173 int i, j;
5174
5175 for (i = 0; i <= (n - len); i++) {
5176 for (j = 0; j < len; j++)
5177 if (data[i + j] != str[j])
5178 break;
5179 if (j == len)
5180 return i;
5181 }
5182
5183 return 0;
5184}
5185
6ee73861
BS		 5186static struct dcb_gpio_entry *
5187new_gpio_entry(struct nvbios *bios)
5188{
7f245b20 5189 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5190
5191 return &gpio->entry[gpio->entries++];
5192}
5193
5194struct dcb_gpio_entry *
5195nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5196{
5197 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5198 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5199 int i;
5200
7f245b20
BS		 5201 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5202 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5203 continue;
5204
7f245b20 5205 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5206 }
5207
5208 return NULL;
5209}
5210
5211static void
5212parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5213{
5214 struct dcb_gpio_entry *gpio;
5215 uint16_t ent = ROM16(bios->data[offset]);
5216 uint8_t line = ent & 0x1f,
5217 tag = ent >> 5 & 0x3f,
5218 flags = ent >> 11 & 0x1f;
5219
5220 if (tag == 0x3f)
5221 return;
5222
5223 gpio = new_gpio_entry(bios);
5224
5225 gpio->tag = tag;
5226 gpio->line = line;
5227 gpio->invert = flags != 4;
2535d71c 5228 gpio->entry = ent;
6ee73861
BS		 5229}
5230
5231static void
5232parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5233{
02faec09 5234 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5235 struct dcb_gpio_entry *gpio;
6ee73861 5236
02faec09 5237 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5238 return;
5239
5240 gpio = new_gpio_entry(bios);
02faec09
BS		 5241 gpio->tag = (entry & 0x0000ff00) >> 8;
5242 gpio->line = (entry & 0x0000001f) >> 0;
5243 gpio->state_default = (entry & 0x01000000) >> 24;
5244 gpio->state[0] = (entry & 0x18000000) >> 27;
5245 gpio->state[1] = (entry & 0x60000000) >> 29;
5246 gpio->entry = entry;
6ee73861
BS		 5247}
5248
5249static void
5250parse_dcb_gpio_table(struct nvbios *bios)
5251{
5252 struct drm_device *dev = bios->dev;
7f245b20 5253 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5254 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5255 int header_len = gpio_table[1],
5256 entries = gpio_table[2],
5257 entry_len = gpio_table[3];
5258 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5259 int i;
5260
7f245b20 5261 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5262 if (gpio_table_ptr && entry_len != 4) {
5263 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5264 return;
5265 }
5266
5267 parse_entry = parse_dcb40_gpio_entry;
5268
7f245b20 5269 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5270 if (gpio_table_ptr && entry_len != 2) {
5271 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5272 return;
5273 }
5274
5275 parse_entry = parse_dcb30_gpio_entry;
5276
7f245b20 5277 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5278 /*
5279 * DCBs older than v3.0 don't really have a GPIO
5280 * table, instead they keep some GPIO info at fixed
5281 * locations.
5282 */
5283 uint16_t dcbptr = ROM16(bios->data[0x36]);
5284 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5285
5286 if (tvdac_gpio[0] & 1) {
5287 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5288
5289 gpio->tag = DCB_GPIO_TVDAC0;
5290 gpio->line = tvdac_gpio[1] >> 4;
5291 gpio->invert = tvdac_gpio[0] & 2;
5292 }
5293 }
5294
5295 if (!gpio_table_ptr)
5296 return;
5297
5298 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5299 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5300 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5301 }
5302
5303 for (i = 0; i < entries; i++)
5304 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5305}
5306
5307struct dcb_connector_table_entry *
5308nouveau_bios_connector_entry(struct drm_device *dev, int index)
5309{
5310 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5311 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5312 struct dcb_connector_table_entry *cte;
5313
7f245b20 5314 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5315 return NULL;
5316
7f245b20 5317 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5318 if (cte->type == 0xff)
5319 return NULL;
5320
5321 return cte;
5322}
5323
f66fa771
BS		 5324static enum dcb_connector_type
5325divine_connector_type(struct nvbios *bios, int index)
5326{
5327 struct dcb_table *dcb = &bios->dcb;
5328 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5329 int i;
5330
5331 for (i = 0; i < dcb->entries; i++) {
5332 if (dcb->entry[i].connector == index)
5333 encoders |= (1 << dcb->entry[i].type);
5334 }
5335
5336 if (encoders & (1 << OUTPUT_DP)) {
5337 if (encoders & (1 << OUTPUT_TMDS))
5338 type = DCB_CONNECTOR_DP;
5339 else
5340 type = DCB_CONNECTOR_eDP;
5341 } else
5342 if (encoders & (1 << OUTPUT_TMDS)) {
5343 if (encoders & (1 << OUTPUT_ANALOG))
5344 type = DCB_CONNECTOR_DVI_I;
5345 else
5346 type = DCB_CONNECTOR_DVI_D;
5347 } else
5348 if (encoders & (1 << OUTPUT_ANALOG)) {
5349 type = DCB_CONNECTOR_VGA;
5350 } else
5351 if (encoders & (1 << OUTPUT_LVDS)) {
5352 type = DCB_CONNECTOR_LVDS;
5353 } else
5354 if (encoders & (1 << OUTPUT_TV)) {
5355 type = DCB_CONNECTOR_TV_0;
5356 }
5357
5358 return type;
5359}
5360
53c44c3a
BS		 5361static void
5362apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5363{
5364 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5365 struct drm_device *dev = bios->dev;
5366
5367 /* Gigabyte NX85T */
5368 if ((dev->pdev->device == 0x0421) &&
5369 (dev->pdev->subsystem_vendor == 0x1458) &&
5370 (dev->pdev->subsystem_device == 0x344c)) {
5371 if (cte->type == DCB_CONNECTOR_HDMI_1)
5372 cte->type = DCB_CONNECTOR_DVI_I;
5373 }
5374}
5375
6ee73861
BS		 5376static void
5377parse_dcb_connector_table(struct nvbios *bios)
5378{
5379 struct drm_device *dev = bios->dev;
7f245b20 5380 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5381 struct dcb_connector_table_entry *cte;
7f245b20 5382 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5383 uint8_t *entry;
5384 int i;
5385
7f245b20 5386 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5387 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5388 return;
5389 }
5390
5391 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5392 conntab[0], conntab[1], conntab[2], conntab[3]);
5393 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5394 (conntab[3] != 2 && conntab[3] != 4)) {
5395 NV_ERROR(dev, " Unknown! Please report.\n");
5396 return;
5397 }
5398
5399 ct->entries = conntab[2];
5400
5401 entry = conntab + conntab[1];
5402 cte = &ct->entry[0];
5403 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5404 cte->index = i;
6ee73861
BS		 5405 if (conntab[3] == 2)
5406 cte->entry = ROM16(entry[0]);
5407 else
5408 cte->entry = ROM32(entry[0]);
f66fa771 5409
6ee73861 5410 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5411 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5412 switch (cte->entry & 0x00033000) {
5413 case 0x00001000:
5414 cte->gpio_tag = 0x07;
5415 break;
5416 case 0x00002000:
5417 cte->gpio_tag = 0x08;
5418 break;
5419 case 0x00010000:
5420 cte->gpio_tag = 0x51;
5421 break;
5422 case 0x00020000:
5423 cte->gpio_tag = 0x52;
5424 break;
5425 default:
5426 cte->gpio_tag = 0xff;
5427 break;
5428 }
5429
5430 if (cte->type == 0xff)
5431 continue;
5432
53c44c3a
BS		 5433 apply_dcb_connector_quirks(bios, i);
5434
6ee73861
BS		 5435 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5436 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5437
5438 /* check for known types, fallback to guessing the type
5439 * from attached encoders if we hit an unknown.
5440 */
5441 switch (cte->type) {
5442 case DCB_CONNECTOR_VGA:
5443 case DCB_CONNECTOR_TV_0:
5444 case DCB_CONNECTOR_TV_1:
5445 case DCB_CONNECTOR_TV_3:
5446 case DCB_CONNECTOR_DVI_I:
5447 case DCB_CONNECTOR_DVI_D:
5448 case DCB_CONNECTOR_LVDS:
5449 case DCB_CONNECTOR_DP:
5450 case DCB_CONNECTOR_eDP:
5451 case DCB_CONNECTOR_HDMI_0:
5452 case DCB_CONNECTOR_HDMI_1:
5453 break;
5454 default:
5455 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5456 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5457 break;
5458 }
5459
da647d5b
BS		 5460 if (nouveau_override_conntype) {
5461 int type = divine_connector_type(bios, cte->index);
5462 if (type != cte->type)
5463 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5464 }
5465
6ee73861
BS		 5466 }
5467}
5468
7f245b20 5469static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5470{
5471 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5472
5473 memset(entry, 0, sizeof(struct dcb_entry));
5474 entry->index = dcb->entries++;
5475
5476 return entry;
5477}
5478
7f245b20 5479static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5480{
5481 struct dcb_entry *entry = new_dcb_entry(dcb);
5482
5483 entry->type = 0;
5484 entry->i2c_index = i2c;
5485 entry->heads = heads;
5486 entry->location = DCB_LOC_ON_CHIP;
5487 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5488}
5489
7f245b20 5490static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5491{
5492 struct dcb_entry *entry = new_dcb_entry(dcb);
5493
5494 entry->type = 2;
5495 entry->i2c_index = LEGACY_I2C_PANEL;
5496 entry->heads = twoHeads ? 3 : 1;
5497 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5498 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5499 entry->duallink_possible = false; /* SiI164 and co. are single link */
5500
5501#if 0
5502 /*
5503 * For dvi-a either crtc probably works, but my card appears to only
5504 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5505 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5506 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5507 * the monitor picks up the mode res ok and lights up, but no pixel
5508 * data appears, so the board manufacturer probably connected up the
5509 * sync lines, but missed the video traces / components
5510 *
5511 * with this introduction, dvi-a left as an exercise for the reader.
5512 */
5513 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5514#endif
5515}
5516
7f245b20 5517static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5518{
5519 struct dcb_entry *entry = new_dcb_entry(dcb);
5520
5521 entry->type = 1;
5522 entry->i2c_index = LEGACY_I2C_TV;
5523 entry->heads = twoHeads ? 3 : 1;
5524 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5525}
5526
5527static bool
7f245b20 5528parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5529 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5530{
5531 entry->type = conn & 0xf;
5532 entry->i2c_index = (conn >> 4) & 0xf;
5533 entry->heads = (conn >> 8) & 0xf;
7f245b20 5534 if (dcb->version >= 0x40)
6ee73861
BS		 5535 entry->connector = (conn >> 12) & 0xf;
5536 entry->bus = (conn >> 16) & 0xf;
5537 entry->location = (conn >> 20) & 0x3;
5538 entry->or = (conn >> 24) & 0xf;
5539 /*
5540 * Normal entries consist of a single bit, but dual link has the
5541 * next most significant bit set too
5542 */
5543 entry->duallink_possible =
5544 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5545
5546 switch (entry->type) {
5547 case OUTPUT_ANALOG:
5548 /*
5549 * Although the rest of a CRT conf dword is usually
5550 * zeros, mac biosen have stuff there so we must mask
5551 */
7f245b20 5552 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5553 (conf & 0xffff) * 10 :
5554 (conf & 0xff) * 10000;
5555 break;
5556 case OUTPUT_LVDS:
5557 {
5558 uint32_t mask;
5559 if (conf & 0x1)
5560 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5561 if (dcb->version < 0x22) {
6ee73861
BS		 5562 mask = ~0xd;
5563 /*
5564 * The laptop in bug 14567 lies and claims to not use
5565 * straps when it does, so assume all DCB 2.0 laptops
5566 * use straps, until a broken EDID using one is produced
5567 */
5568 entry->lvdsconf.use_straps_for_mode = true;
5569 /*
5570 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5571 * mean the same thing (probably wrong, but might work)
5572 */
5573 if (conf & 0x4 || conf & 0x8)
5574 entry->lvdsconf.use_power_scripts = true;
5575 } else {
5576 mask = ~0x5;
5577 if (conf & 0x4)
5578 entry->lvdsconf.use_power_scripts = true;
5579 }
5580 if (conf & mask) {
5581 /*
5582 * Until we even try to use these on G8x, it's
5583 * useless reporting unknown bits. They all are.
5584 */
7f245b20 5585 if (dcb->version >= 0x40)
6ee73861
BS		 5586 break;
5587
5588 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5589 "please report\n");
5590 }
5591 break;
5592 }
5593 case OUTPUT_TV:
5594 {
7f245b20 5595 if (dcb->version >= 0x30)
6ee73861
BS		 5596 entry->tvconf.has_component_output = conf & (0x8 << 4);
5597 else
5598 entry->tvconf.has_component_output = false;
5599
5600 break;
5601 }
5602 case OUTPUT_DP:
5603 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5604 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5605 switch ((conf & 0x0f000000) >> 24) {
5606 case 0xf:
5607 entry->dpconf.link_nr = 4;
5608 break;
5609 case 0x3:
5610 entry->dpconf.link_nr = 2;
5611 break;
5612 default:
5613 entry->dpconf.link_nr = 1;
5614 break;
5615 }
5616 break;
5617 case OUTPUT_TMDS:
5618 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5619 break;
5620 case 0xe:
5621 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5622 dcb->entries--;
6ee73861 5623 return false;
e7cc51c5
BS		 5624 default:
5625 break;
6ee73861
BS		 5626 }
5627
5628 /* unsure what DCB version introduces this, 3.0? */
5629 if (conf & 0x100000)
5630 entry->i2c_upper_default = true;
5631
5632 return true;
5633}
5634
5635static bool
7f245b20 5636parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5637 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5638{
b0d2de86
BS		 5639 switch (conn & 0x0000000f) {
5640 case 0:
5641 entry->type = OUTPUT_ANALOG;
5642 break;
5643 case 1:
5644 entry->type = OUTPUT_TV;
5645 break;
5646 case 2:
5647 case 3:
6ee73861 5648 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5649 break;
5650 case 4:
5651 switch ((conn & 0x000000f0) >> 4) {
5652 case 0:
6ee73861 5653 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5654 break;
5655 case 1:
5656 entry->type = OUTPUT_LVDS;
5657 break;
5658 default:
5659 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5660 (conn & 0x000000f0) >> 4);
5661 return false;
5662 }
5663 break;
5664 default:
5665 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5666 return false;
6ee73861 5667 }
b0d2de86
BS		 5668
5669 entry->i2c_index = (conn & 0x0003c000) >> 14;
5670 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5671 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5672 entry->location = (conn & 0x01e00000) >> 21;
5673 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5674 entry->duallink_possible = false;
5675
5676 switch (entry->type) {
5677 case OUTPUT_ANALOG:
5678 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5679 break;
b0d2de86
BS		 5680 case OUTPUT_TV:
5681 entry->tvconf.has_component_output = false;
6ee73861
BS		 5682 break;
5683 case OUTPUT_TMDS:
5684 /*
5685 * Invent a DVI-A output, by copying the fields of the DVI-D
5686 * output; reported to work by math_b on an NV20(!).
5687 */
5688 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5689 break;
b0d2de86
BS		 5690 case OUTPUT_LVDS:
5691 if ((conn & 0x00003f00) != 0x10)
5692 entry->lvdsconf.use_straps_for_mode = true;
5693 entry->lvdsconf.use_power_scripts = true;
5694 break;
5695 default:
6ee73861
BS		 5696 break;
5697 }
5698
5699 return true;
5700}
5701
7f245b20 5702static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5703 uint32_t conn, uint32_t conf)
5704{
7f245b20 5705 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5706 bool ret;
5707
7f245b20
BS		 5708 if (dcb->version >= 0x20)
5709 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5710 else
7f245b20 5711 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5712 if (!ret)
5713 return ret;
5714
7f245b20
BS		 5715 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5716 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5717
5718 return true;
5719}
5720
5721static
7f245b20 5722void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5723{
5724 /*
5725 * DCB v2.0 lists each output combination separately.
5726 * Here we merge compatible entries to have fewer outputs, with
5727 * more options
5728 */
5729
5730 int i, newentries = 0;
5731
5732 for (i = 0; i < dcb->entries; i++) {
5733 struct dcb_entry *ient = &dcb->entry[i];
5734 int j;
5735
5736 for (j = i + 1; j < dcb->entries; j++) {
5737 struct dcb_entry *jent = &dcb->entry[j];
5738
5739 if (jent->type == 100) /* already merged entry */
5740 continue;
5741
5742 /* merge heads field when all other fields the same */
5743 if (jent->i2c_index == ient->i2c_index &&
5744 jent->type == ient->type &&
5745 jent->location == ient->location &&
5746 jent->or == ient->or) {
5747 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5748 i, j);
5749 ient->heads |= jent->heads;
5750 jent->type = 100; /* dummy value */
5751 }
5752 }
5753 }
5754
5755 /* Compact entries merged into others out of dcb */
5756 for (i = 0; i < dcb->entries; i++) {
5757 if (dcb->entry[i].type == 100)
5758 continue;
5759
5760 if (newentries != i) {
5761 dcb->entry[newentries] = dcb->entry[i];
5762 dcb->entry[newentries].index = newentries;
5763 }
5764 newentries++;
5765 }
5766
5767 dcb->entries = newentries;
5768}
5769
ed42f824
BS		 5770static int
5771parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5772{
ed42f824 5773 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5774 struct dcb_table *dcb = &bios->dcb;
ed42f824 5775 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5776 uint8_t *dcbtable;
5777 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5778 bool configblock = true;
5779 int recordlength = 8, confofs = 4;
5780 int i;
5781
6ee73861 5782 /* get the offset from 0x36 */
ed42f824
BS		 5783 if (dev_priv->card_type > NV_04) {
5784 dcbptr = ROM16(bios->data[0x36]);
5785 if (dcbptr == 0x0000)
5786 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5787 }
6ee73861 5788
ed42f824 5789 /* this situation likely means a really old card, pre DCB */
6ee73861 5790 if (dcbptr == 0x0) {
ed42f824 5791 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5792 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5793
ed42f824 5794 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5795 fabricate_tv_output(dcb, twoHeads);
5796
5797 return 0;
5798 }
5799
5800 dcbtable = &bios->data[dcbptr];
5801
5802 /* get DCB version */
7f245b20 5803 dcb->version = dcbtable[0];
6ee73861 5804 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5805 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5806
7f245b20 5807 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5808 uint32_t sig;
5809
7f245b20 5810 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5811 headerlen = dcbtable[1];
5812 entries = dcbtable[2];
5813 recordlength = dcbtable[3];
5814 i2ctabptr = ROM16(dcbtable[4]);
5815 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5816 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5817 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5818 } else {
5819 i2ctabptr = ROM16(dcbtable[2]);
5820 sig = ROM32(dcbtable[4]);
5821 headerlen = 8;
5822 }
5823
5824 if (sig != 0x4edcbdcb) {
5825 NV_ERROR(dev, "Bad Display Configuration Block "
5826 "signature (%08X)\n", sig);
5827 return -EINVAL;
5828 }
7f245b20 5829 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5830 char sig[8] = { 0 };
5831
5832 strncpy(sig, (char *)&dcbtable[-7], 7);
5833 i2ctabptr = ROM16(dcbtable[2]);
5834 recordlength = 10;
5835 confofs = 6;
5836
5837 if (strcmp(sig, "DEV_REC")) {
5838 NV_ERROR(dev, "Bad Display Configuration Block "
5839 "signature (%s)\n", sig);
5840 return -EINVAL;
5841 }
5842 } else {
5843 /*
5844 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5845 * has the same single (crt) entry, even when tv-out present, so
5846 * the conclusion is this version cannot really be used.
5847 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5848 * 5 entries, which are not specific to the card and so no use.
5849 * v1.2 does have an I2C table that read_dcb_i2c_table can
5850 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5851 * pointer, so use the indices parsed in parse_bmp_structure.
5852 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5853 */
5854 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5855 "adding all possible outputs\n");
5856 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5857
5858 /*
5859 * Attempt to detect TV before DVI because the test
5860 * for the former is more accurate and it rules the
5861 * latter out.
5862 */
5863 if (nv04_tv_identify(dev,
5864 bios->legacy.i2c_indices.tv) >= 0)
5865 fabricate_tv_output(dcb, twoHeads);
5866
5867 else if (bios->tmds.output0_script_ptr ||
5868 bios->tmds.output1_script_ptr)
5869 fabricate_dvi_i_output(dcb, twoHeads);
5870
5871 return 0;
5872 }
5873
5874 if (!i2ctabptr)
5875 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5876 else {
7f245b20
BS		 5877 dcb->i2c_table = &bios->data[i2ctabptr];
5878 if (dcb->version >= 0x30)
5879 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5880 }
5881
6ee73861
BS		 5882 if (entries > DCB_MAX_NUM_ENTRIES)
5883 entries = DCB_MAX_NUM_ENTRIES;
5884
5885 for (i = 0; i < entries; i++) {
5886 uint32_t connection, config = 0;
5887
5888 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5889 if (configblock)
5890 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5891
5892 /* seen on an NV11 with DCB v1.5 */
5893 if (connection == 0x00000000)
5894 break;
5895
5896 /* seen on an NV17 with DCB v2.0 */
5897 if (connection == 0xffffffff)
5898 break;
5899
5900 if ((connection & 0x0000000f) == 0x0000000f)
5901 continue;
5902
5903 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5904 dcb->entries, connection, config);
5905
7f245b20 5906 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5907 break;
5908 }
5909
5910 /*
5911 * apart for v2.1+ not being known for requiring merging, this
5912 * guarantees dcbent->index is the index of the entry in the rom image
5913 */
7f245b20 5914 if (dcb->version < 0x21)
6ee73861
BS		 5915 merge_like_dcb_entries(dev, dcb);
5916
54abb5dd
BS		 5917 if (!dcb->entries)
5918 return -ENXIO;
5919
5920 parse_dcb_gpio_table(bios);
5921 parse_dcb_connector_table(bios);
5922 return 0;
6ee73861
BS		 5923}
5924
5925static void
5926fixup_legacy_connector(struct nvbios *bios)
5927{
7f245b20 5928 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5929 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5930
5931 /*
5932 * DCB 3.0 also has the table in most cases, but there are some cards
5933 * where the table is filled with stub entries, and the DCB entriy
5934 * indices are all 0. We don't need the connector indices on pre-G80
5935 * chips (yet?) so limit the use to DCB 4.0 and above.
5936 */
7f245b20 5937 if (dcb->version >= 0x40)
6ee73861
BS		 5938 return;
5939
dc5bc4ed
BS		 5940 dcb->connector.entries = 0;
5941
6ee73861
BS		 5942 /*
5943 * No known connector info before v3.0, so make it up. the rule here
5944 * is: anything on the same i2c bus is considered to be on the same
5945 * connector. any output without an associated i2c bus is assigned
5946 * its own unique connector index.
5947 */
5948 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5949 /*
5950 * Ignore the I2C index for on-chip TV-out, as there
5951 * are cards with bogus values (nv31m in bug 23212),
5952 * and it's otherwise useless.
5953 */
5954 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5955 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5956 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5957 i2c = dcb->entry[i].i2c_index;
5958
5959 if (i2c_conn[i2c]) {
5960 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5961 continue;
5962 }
5963
dc5bc4ed
BS		 5964 dcb->entry[i].connector = dcb->connector.entries++;
5965 if (i2c != 0xf)
5966 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5967 }
5968
dc5bc4ed
BS		 5969 /* Fake the connector table as well as just connector indices */
5970 for (i = 0; i < dcb->connector.entries; i++) {
5971 dcb->connector.entry[i].index = i;
5972 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5973 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 5974 }
5975}
5976
5977static void
5978fixup_legacy_i2c(struct nvbios *bios)
5979{
7f245b20 5980 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 5981 int i;
5982
5983 for (i = 0; i < dcb->entries; i++) {
5984 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5985 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5986 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5987 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5988 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5989 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5990 }
5991}
5992
5993static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5994{
5995 /*
5996 * The header following the "HWSQ" signature has the number of entries,
5997 * and the entry size
5998 *
5999 * An entry consists of a dword to write to the sequencer control reg
6000 * (0x00001304), followed by the ucode bytes, written sequentially,
6001 * starting at reg 0x00001400
6002 */
6003
6004 uint8_t bytes_to_write;
6005 uint16_t hwsq_entry_offset;
6006 int i;
6007
6008 if (bios->data[hwsq_offset] <= entry) {
6009 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6010 "requested entry\n");
6011 return -ENOENT;
6012 }
6013
6014 bytes_to_write = bios->data[hwsq_offset + 1];
6015
6016 if (bytes_to_write != 36) {
6017 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6018 return -EINVAL;
6019 }
6020
6021 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6022
6023 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6024
6025 /* set sequencer control */
6026 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6027 bytes_to_write -= 4;
6028
6029 /* write ucode */
6030 for (i = 0; i < bytes_to_write; i += 4)
6031 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6032
6033 /* twiddle NV_PBUS_DEBUG_4 */
6034 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6035
6036 return 0;
6037}
6038
6039static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6040 struct nvbios *bios)
6041{
6042 /*
6043 * BMP based cards, from NV17, need a microcode loading to correctly
6044 * control the GPIO etc for LVDS panels
6045 *
6046 * BIT based cards seem to do this directly in the init scripts
6047 *
6048 * The microcode entries are found by the "HWSQ" signature.
6049 */
6050
6051 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6052 const int sz = sizeof(hwsq_signature);
6053 int hwsq_offset;
6054
6055 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6056 if (!hwsq_offset)
6057 return 0;
6058
6059 /* always use entry 0? */
6060 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6061}
6062
6063uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6064{
6065 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6066 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6067 const uint8_t edid_sig[] = {
6068 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6069 uint16_t offset = 0;
6070 uint16_t newoffset;
6071 int searchlen = NV_PROM_SIZE;
6072
6073 if (bios->fp.edid)
6074 return bios->fp.edid;
6075
6076 while (searchlen) {
6077 newoffset = findstr(&bios->data[offset], searchlen,
6078 edid_sig, 8);
6079 if (!newoffset)
6080 return NULL;
6081 offset += newoffset;
6082 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6083 break;
6084
6085 searchlen -= offset;
6086 offset++;
6087 }
6088
6089 NV_TRACE(dev, "Found EDID in BIOS\n");
6090
6091 return bios->fp.edid = &bios->data[offset];
6092}
6093
6094void
6095nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6096 struct dcb_entry *dcbent)
6097{
6098 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6099 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6100 struct init_exec iexec = { true, false };
6101
d9184fa9 6102 mutex_lock(&bios->lock);
6ee73861
BS		 6103 bios->display.output = dcbent;
6104 parse_init_table(bios, table, &iexec);
6105 bios->display.output = NULL;
d9184fa9 6106 mutex_unlock(&bios->lock);
6ee73861
BS		 6107}
6108
6109static bool NVInitVBIOS(struct drm_device *dev)
6110{
6111 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6112 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6113
6114 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6115 mutex_init(&bios->lock);
6ee73861
BS		 6116 bios->dev = dev;
6117
6118 if (!NVShadowVBIOS(dev, bios->data))
6119 return false;
6120
6121 bios->length = NV_PROM_SIZE;
6122 return true;
6123}
6124
6125static int nouveau_parse_vbios_struct(struct drm_device *dev)
6126{
6127 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6128 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6129 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6130 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6131 int offset;
6132
6133 offset = findstr(bios->data, bios->length,
6134 bit_signature, sizeof(bit_signature));
6135 if (offset) {
6136 NV_TRACE(dev, "BIT BIOS found\n");
6137 return parse_bit_structure(bios, offset + 6);
6138 }
6139
6140 offset = findstr(bios->data, bios->length,
6141 bmp_signature, sizeof(bmp_signature));
6142 if (offset) {
6143 NV_TRACE(dev, "BMP BIOS found\n");
6144 return parse_bmp_structure(dev, bios, offset);
6145 }
6146
6147 NV_ERROR(dev, "No known BIOS signature found\n");
6148 return -ENODEV;
6149}
6150
6151int
6152nouveau_run_vbios_init(struct drm_device *dev)
6153{
6154 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6155 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6156 int i, ret = 0;
6157
6158 NVLockVgaCrtcs(dev, false);
6159 if (nv_two_heads(dev))
6160 NVSetOwner(dev, bios->state.crtchead);
6161
6162 if (bios->major_version < 5) /* BMP only */
6163 load_nv17_hw_sequencer_ucode(dev, bios);
6164
6165 if (bios->execute) {
6166 bios->fp.last_script_invoc = 0;
6167 bios->fp.lvds_init_run = false;
6168 }
6169
6170 parse_init_tables(bios);
6171
6172 /*
6173 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6174 * parser will run this right after the init tables, the binary
6175 * driver appears to run it at some point later.
6176 */
6177 if (bios->some_script_ptr) {
6178 struct init_exec iexec = {true, false};
6179
6180 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6181 bios->some_script_ptr);
6182 parse_init_table(bios, bios->some_script_ptr, &iexec);
6183 }
6184
6185 if (dev_priv->card_type >= NV_50) {
7f245b20 6186 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6187 nouveau_bios_run_display_table(dev,
7f245b20 6188 &bios->dcb.entry[i],
6ee73861
BS		 6189 0, 0);
6190 }
6191 }
6192
6193 NVLockVgaCrtcs(dev, true);
6194
6195 return ret;
6196}
6197
6198static void
6199nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6200{
6201 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6202 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6203 struct dcb_i2c_entry *entry;
6204 int i;
6205
7f245b20 6206 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6207 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6208 nouveau_i2c_fini(dev, entry);
6209}
6210
d13102c6
BS		 6211static bool
6212nouveau_bios_posted(struct drm_device *dev)
6213{
6214 struct drm_nouveau_private *dev_priv = dev->dev_private;
6215 bool was_locked;
6216 unsigned htotal;
6217
6218 if (dev_priv->chipset >= NV_50) {
6219 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6220 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6221 return false;
6222 return true;
6223 }
6224
6225 was_locked = NVLockVgaCrtcs(dev, false);
6226 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6227 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6228 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6229 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6230 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6231 NVLockVgaCrtcs(dev, was_locked);
6232 return (htotal != 0);
6233}
6234
6ee73861
BS		 6235int
6236nouveau_bios_init(struct drm_device *dev)
6237{
6238 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6239 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6240 uint32_t saved_nv_pextdev_boot_0;
6241 bool was_locked;
6242 int ret;
6243
6ee73861
BS		 6244 if (!NVInitVBIOS(dev))
6245 return -ENODEV;
6246
6247 ret = nouveau_parse_vbios_struct(dev);
6248 if (ret)
6249 return ret;
6250
6251 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6252 if (ret)
6253 return ret;
6254
6255 fixup_legacy_i2c(bios);
6256 fixup_legacy_connector(bios);
6257
6258 if (!bios->major_version) /* we don't run version 0 bios */
6259 return 0;
6260
6261 /* these will need remembering across a suspend */
6262 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6263 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6264
6265 /* init script execution disabled */
6266 bios->execute = false;
6267
6268 /* ... unless card isn't POSTed already */
d13102c6 6269 if (!nouveau_bios_posted(dev)) {
6ee73861 6270 NV_INFO(dev, "Adaptor not initialised\n");
f50c0b91 6271 if (dev_priv->card_type < NV_40) {
6ee73861
BS		 6272 NV_ERROR(dev, "Unable to POST this chipset\n");
6273 return -ENODEV;
6274 }
6275
6276 NV_INFO(dev, "Running VBIOS init tables\n");
6277 bios->execute = true;
6278 }
6279
6280 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6281
6282 ret = nouveau_run_vbios_init(dev);
04a39c57 6283 if (ret)
6ee73861 6284 return ret;
6ee73861
BS		 6285
6286 /* feature_byte on BMP is poor, but init always sets CR4B */
6287 was_locked = NVLockVgaCrtcs(dev, false);
6288 if (bios->major_version < 5)
6289 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6290
6291 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6292 if (bios->is_mobile || bios->major_version >= 5)
6293 ret = parse_fp_mode_table(dev, bios);
6294 NVLockVgaCrtcs(dev, was_locked);
6295
6296 /* allow subsequent scripts to execute */
6297 bios->execute = true;
6298
6299 return 0;
6300}
6301
6302void
6303nouveau_bios_takedown(struct drm_device *dev)
6304{
6305 nouveau_bios_i2c_devices_takedown(dev);
6306}
Michael's Linux tree.