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CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
c5fd936e 26#include <linux/delay.h>
94580299
BS
27#include <linux/module.h>
28#include <linux/pci.h>
5addcf0a
DA
29#include <linux/pm_runtime.h>
30#include <linux/vga_switcheroo.h>
fdb751ef 31
ae95621b
MY
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
fdb751ef 34
ebb945a9 35#include <core/gpuobj.h>
c33e05a1 36#include <core/option.h>
7974dd1b
BS
37#include <core/pci.h>
38#include <core/tegra.h>
94580299 39
04b88677 40#include <nvif/driver.h>
a7cf0180 41#include <nvif/fifo.h>
04b88677 42
923bc416 43#include <nvif/class.h>
845f2725 44#include <nvif/cl0002.h>
8ed1730c 45#include <nvif/cla06f.h>
538b269b
BS
46#include <nvif/if0004.h>
47
4dc28134 48#include "nouveau_drv.h"
ebb945a9 49#include "nouveau_dma.h"
77145f1c
BS
50#include "nouveau_ttm.h"
51#include "nouveau_gem.h"
77145f1c 52#include "nouveau_vga.h"
8d021d71 53#include "nouveau_led.h"
b9ed919f 54#include "nouveau_hwmon.h"
77145f1c
BS
55#include "nouveau_acpi.h"
56#include "nouveau_bios.h"
57#include "nouveau_ioctl.h"
ebb945a9
BS
58#include "nouveau_abi16.h"
59#include "nouveau_fbcon.h"
60#include "nouveau_fence.h"
33b903e8 61#include "nouveau_debugfs.h"
27111a23 62#include "nouveau_usif.h"
703fa264 63#include "nouveau_connector.h"
055a65d5 64#include "nouveau_platform.h"
ebb945a9 65
94580299
BS
66MODULE_PARM_DESC(config, "option string to pass to driver core");
67static char *nouveau_config;
68module_param_named(config, nouveau_config, charp, 0400);
69
70MODULE_PARM_DESC(debug, "debug string to pass to driver core");
71static char *nouveau_debug;
72module_param_named(debug, nouveau_debug, charp, 0400);
73
ebb945a9
BS
74MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
75static int nouveau_noaccel = 0;
76module_param_named(noaccel, nouveau_noaccel, int, 0400);
77
9430738d
BS
78MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
79 "0 = disabled, 1 = enabled, 2 = headless)");
80int nouveau_modeset = -1;
77145f1c
BS
81module_param_named(modeset, nouveau_modeset, int, 0400);
82
5addcf0a 83MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
321f5c5f 84static int nouveau_runtime_pm = -1;
5addcf0a
DA
85module_param_named(runpm, nouveau_runtime_pm, int, 0400);
86
915b4d11
DH
87static struct drm_driver driver_stub;
88static struct drm_driver driver_pci;
89static struct drm_driver driver_platform;
77145f1c 90
94580299 91static u64
420b9469 92nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
93{
94 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
95 name |= pdev->bus->number << 16;
96 name |= PCI_SLOT(pdev->devfn) << 8;
97 return name | PCI_FUNC(pdev->devfn);
98}
99
420b9469
AC
100static u64
101nouveau_platform_name(struct platform_device *platformdev)
102{
103 return platformdev->id;
104}
105
106static u64
107nouveau_name(struct drm_device *dev)
108{
109 if (dev->pdev)
110 return nouveau_pci_name(dev->pdev);
111 else
76adb460 112 return nouveau_platform_name(to_platform_device(dev->dev));
420b9469
AC
113}
114
814a2324 115static inline bool
11e451e7 116nouveau_cli_work_ready(struct dma_fence *fence)
814a2324 117{
11e451e7
BS
118 if (!dma_fence_is_signaled(fence))
119 return false;
814a2324
BS
120 dma_fence_put(fence);
121 return true;
122}
123
124static void
11e451e7 125nouveau_cli_work(struct work_struct *w)
814a2324 126{
11e451e7 127 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
814a2324
BS
128 struct nouveau_cli_work *work, *wtmp;
129 mutex_lock(&cli->lock);
130 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
11e451e7 131 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
814a2324
BS
132 list_del(&work->head);
133 work->func(work);
134 }
135 }
136 mutex_unlock(&cli->lock);
137}
138
139static void
140nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
141{
142 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
143 schedule_work(&work->cli->work);
144}
145
146void
147nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
148 struct nouveau_cli_work *work)
149{
150 work->fence = dma_fence_get(fence);
151 work->cli = cli;
152 mutex_lock(&cli->lock);
153 list_add_tail(&work->head, &cli->worker);
814a2324
BS
154 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
155 nouveau_cli_work_fence(fence, &work->cb);
b26a2319 156 mutex_unlock(&cli->lock);
814a2324
BS
157}
158
20d8a88e
BS
159static void
160nouveau_cli_fini(struct nouveau_cli *cli)
161{
11e451e7
BS
162 /* All our channels are dead now, which means all the fences they
163 * own are signalled, and all callback functions have been called.
164 *
165 * So, after flushing the workqueue, there should be nothing left.
166 */
167 flush_work(&cli->work);
168 WARN_ON(!list_empty(&cli->worker));
169
20d8a88e 170 usif_client_fini(cli);
24e8375b 171 nouveau_vmm_fini(&cli->vmm);
01670a79 172 nvif_mmu_fini(&cli->mmu);
1167c6bc 173 nvif_device_fini(&cli->device);
cb7e88e7 174 mutex_lock(&cli->drm->master.lock);
20d8a88e 175 nvif_client_fini(&cli->base);
cb7e88e7 176 mutex_unlock(&cli->drm->master.lock);
20d8a88e
BS
177}
178
94580299 179static int
20d8a88e
BS
180nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
181 struct nouveau_cli *cli)
94580299 182{
7f507624
BS
183 static const struct nvif_mclass
184 mems[] = {
185 { NVIF_CLASS_MEM_GF100, -1 },
186 { NVIF_CLASS_MEM_NV50 , -1 },
187 { NVIF_CLASS_MEM_NV04 , -1 },
188 {}
189 };
01670a79
BS
190 static const struct nvif_mclass
191 mmus[] = {
192 { NVIF_CLASS_MMU_GF100, -1 },
193 { NVIF_CLASS_MMU_NV50 , -1 },
194 { NVIF_CLASS_MMU_NV04 , -1 },
195 {}
196 };
96da0bcd
BS
197 static const struct nvif_mclass
198 vmms[] = {
199 { NVIF_CLASS_VMM_GP100, -1 },
200 { NVIF_CLASS_VMM_GM200, -1 },
201 { NVIF_CLASS_VMM_GF100, -1 },
202 { NVIF_CLASS_VMM_NV50 , -1 },
203 { NVIF_CLASS_VMM_NV04 , -1 },
204 {}
205 };
20d8a88e 206 u64 device = nouveau_name(drm->dev);
9ad97ede 207 int ret;
9ad97ede 208
20d8a88e 209 snprintf(cli->name, sizeof(cli->name), "%s", sname);
e75c091b 210 cli->drm = drm;
20d8a88e
BS
211 mutex_init(&cli->mutex);
212 usif_client_init(cli);
213
814a2324
BS
214 INIT_WORK(&cli->work, nouveau_cli_work);
215 INIT_LIST_HEAD(&cli->worker);
cb7e88e7
BS
216 mutex_init(&cli->lock);
217
218 if (cli == &drm->master) {
80e60973
BS
219 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
220 cli->name, device, &cli->base);
221 } else {
cb7e88e7
BS
222 mutex_lock(&drm->master.lock);
223 ret = nvif_client_init(&drm->master.base, cli->name, device,
9ad97ede 224 &cli->base);
cb7e88e7 225 mutex_unlock(&drm->master.lock);
dd5700ea 226 }
20d8a88e
BS
227 if (ret) {
228 NV_ERROR(drm, "Client allocation failed: %d\n", ret);
229 goto done;
dd5700ea 230 }
94580299 231
1167c6bc
BS
232 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
233 &(struct nv_device_v0) {
234 .device = ~0,
235 }, sizeof(struct nv_device_v0),
236 &cli->device);
237 if (ret) {
238 NV_ERROR(drm, "Device allocation failed: %d\n", ret);
239 goto done;
240 }
241
01670a79
BS
242 ret = nvif_mclass(&cli->device.object, mmus);
243 if (ret < 0) {
244 NV_ERROR(drm, "No supported MMU class\n");
245 goto done;
246 }
247
248 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
249 if (ret) {
250 NV_ERROR(drm, "MMU allocation failed: %d\n", ret);
251 goto done;
252 }
253
96da0bcd
BS
254 ret = nvif_mclass(&cli->mmu.object, vmms);
255 if (ret < 0) {
256 NV_ERROR(drm, "No supported VMM class\n");
257 goto done;
258 }
259
260 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
261 if (ret) {
262 NV_ERROR(drm, "VMM allocation failed: %d\n", ret);
263 goto done;
264 }
265
7f507624
BS
266 ret = nvif_mclass(&cli->mmu.object, mems);
267 if (ret < 0) {
268 NV_ERROR(drm, "No supported MEM class\n");
269 goto done;
270 }
271
272 cli->mem = &mems[ret];
7f507624 273 return 0;
20d8a88e
BS
274done:
275 if (ret)
276 nouveau_cli_fini(cli);
277 return ret;
94580299
BS
278}
279
ebb945a9
BS
280static void
281nouveau_accel_fini(struct nouveau_drm *drm)
282{
fbd58ebd 283 nouveau_channel_idle(drm->channel);
0ad72863 284 nvif_object_fini(&drm->ntfy);
f027f491 285 nvkm_gpuobj_del(&drm->notify);
fbd58ebd 286 nvif_notify_fini(&drm->flip);
0ad72863 287 nvif_object_fini(&drm->nvsw);
fbd58ebd
BS
288 nouveau_channel_del(&drm->channel);
289
290 nouveau_channel_idle(drm->cechan);
0ad72863 291 nvif_object_fini(&drm->ttm.copy);
fbd58ebd
BS
292 nouveau_channel_del(&drm->cechan);
293
ebb945a9
BS
294 if (drm->fence)
295 nouveau_fence(drm)->dtor(drm);
296}
297
298static void
299nouveau_accel_init(struct nouveau_drm *drm)
300{
1167c6bc 301 struct nvif_device *device = &drm->client.device;
41a63406 302 struct nvif_sclass *sclass;
49981046 303 u32 arg0, arg1;
41a63406 304 int ret, i, n;
ebb945a9 305
967e7bde 306 if (nouveau_noaccel)
ebb945a9
BS
307 return;
308
eb47db4f
BS
309 ret = nouveau_channels_init(drm);
310 if (ret)
311 return;
312
ebb945a9 313 /* initialise synchronisation routines */
967e7bde
BS
314 /*XXX: this is crap, but the fence/channel stuff is a little
315 * backwards in some places. this will be fixed.
316 */
41a63406 317 ret = n = nvif_object_sclass_get(&device->object, &sclass);
967e7bde
BS
318 if (ret < 0)
319 return;
320
41a63406
BS
321 for (ret = -ENOSYS, i = 0; i < n; i++) {
322 switch (sclass[i].oclass) {
bbf8906b 323 case NV03_CHANNEL_DMA:
967e7bde
BS
324 ret = nv04_fence_create(drm);
325 break;
bbf8906b 326 case NV10_CHANNEL_DMA:
967e7bde
BS
327 ret = nv10_fence_create(drm);
328 break;
bbf8906b
BS
329 case NV17_CHANNEL_DMA:
330 case NV40_CHANNEL_DMA:
967e7bde
BS
331 ret = nv17_fence_create(drm);
332 break;
bbf8906b 333 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
334 ret = nv50_fence_create(drm);
335 break;
bbf8906b 336 case G82_CHANNEL_GPFIFO:
967e7bde
BS
337 ret = nv84_fence_create(drm);
338 break;
bbf8906b
BS
339 case FERMI_CHANNEL_GPFIFO:
340 case KEPLER_CHANNEL_GPFIFO_A:
63f8c9b7 341 case KEPLER_CHANNEL_GPFIFO_B:
a1020afe 342 case MAXWELL_CHANNEL_GPFIFO_A:
e8ff9794 343 case PASCAL_CHANNEL_GPFIFO_A:
967e7bde
BS
344 ret = nvc0_fence_create(drm);
345 break;
346 default:
347 break;
348 }
349 }
350
41a63406 351 nvif_object_sclass_put(&sclass);
ebb945a9
BS
352 if (ret) {
353 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
354 nouveau_accel_fini(drm);
355 return;
356 }
357
967e7bde 358 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
1167c6bc 359 ret = nouveau_channel_new(drm, &drm->client.device,
a7cf0180
BS
360 nvif_fifo_runlist_ce(device), 0,
361 &drm->cechan);
49981046
BS
362 if (ret)
363 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
364
a7cf0180 365 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
49469800 366 arg1 = 1;
00fc6f6f 367 } else
967e7bde
BS
368 if (device->info.chipset >= 0xa3 &&
369 device->info.chipset != 0xaa &&
370 device->info.chipset != 0xac) {
1167c6bc 371 ret = nouveau_channel_new(drm, &drm->client.device,
0ad72863 372 NvDmaFB, NvDmaTT, &drm->cechan);
00fc6f6f
BS
373 if (ret)
374 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
375
376 arg0 = NvDmaFB;
377 arg1 = NvDmaTT;
49981046
BS
378 } else {
379 arg0 = NvDmaFB;
380 arg1 = NvDmaTT;
381 }
382
1167c6bc
BS
383 ret = nouveau_channel_new(drm, &drm->client.device,
384 arg0, arg1, &drm->channel);
ebb945a9
BS
385 if (ret) {
386 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
387 nouveau_accel_fini(drm);
388 return;
389 }
390
512fa0b8
BS
391 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
392 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
393 nouveau_abi16_swclass(drm), NULL, 0,
394 &drm->nvsw);
69a6146d 395 if (ret == 0) {
512fa0b8
BS
396 ret = RING_SPACE(drm->channel, 2);
397 if (ret == 0) {
69a6146d 398 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
512fa0b8
BS
399 OUT_RING (drm->channel, drm->nvsw.handle);
400 }
401
402 ret = nvif_notify_init(&drm->nvsw,
403 nouveau_flip_complete,
404 false, NV04_NVSW_NTFY_UEVENT,
405 NULL, 0, 0, &drm->flip);
406 if (ret == 0)
407 ret = nvif_notify_get(&drm->flip);
408 if (ret) {
409 nouveau_accel_fini(drm);
410 return;
69a6146d
BS
411 }
412 }
898a2b32 413
898a2b32 414 if (ret) {
512fa0b8 415 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
898a2b32
BS
416 nouveau_accel_fini(drm);
417 return;
418 }
69a6146d
BS
419 }
420
967e7bde 421 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
1167c6bc
BS
422 ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0,
423 false, NULL, &drm->notify);
ebb945a9
BS
424 if (ret) {
425 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
426 nouveau_accel_fini(drm);
427 return;
428 }
429
a01ca78c 430 ret = nvif_object_init(&drm->channel->user, NvNotify0,
4acfd707
BS
431 NV_DMA_IN_MEMORY,
432 &(struct nv_dma_v0) {
433 .target = NV_DMA_V0_TARGET_VRAM,
434 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
435 .start = drm->notify->addr,
436 .limit = drm->notify->addr + 31
4acfd707 437 }, sizeof(struct nv_dma_v0),
0ad72863 438 &drm->ntfy);
ebb945a9
BS
439 if (ret) {
440 nouveau_accel_fini(drm);
441 return;
442 }
443 }
444
445
49981046 446 nouveau_bo_move_init(drm);
ebb945a9
BS
447}
448
56550d94
GKH
449static int nouveau_drm_probe(struct pci_dev *pdev,
450 const struct pci_device_id *pent)
94580299 451{
be83cd4e 452 struct nvkm_device *device;
ebb945a9
BS
453 struct apertures_struct *aper;
454 bool boot = false;
94580299
BS
455 int ret;
456
b00e5334 457 if (vga_switcheroo_client_probe_defer(pdev))
98b3a340
LW
458 return -EPROBE_DEFER;
459
0e67bed2
BS
460 /* We need to check that the chipset is supported before booting
461 * fbdev off the hardware, as there's no way to put it back.
462 */
463 ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
464 if (ret)
465 return ret;
466
467 nvkm_device_del(&device);
468
469 /* Remove conflicting drivers (vesafb, efifb etc). */
ebb945a9
BS
470 aper = alloc_apertures(3);
471 if (!aper)
472 return -ENOMEM;
473
474 aper->ranges[0].base = pci_resource_start(pdev, 1);
475 aper->ranges[0].size = pci_resource_len(pdev, 1);
476 aper->count = 1;
477
478 if (pci_resource_len(pdev, 2)) {
479 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
480 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
481 aper->count++;
482 }
483
484 if (pci_resource_len(pdev, 3)) {
485 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
486 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
487 aper->count++;
488 }
489
490#ifdef CONFIG_X86
491 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
492#endif
771fa0e4 493 if (nouveau_modeset != 2)
44adece5 494 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
83ef7777 495 kfree(aper);
ebb945a9 496
7974dd1b
BS
497 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
498 true, true, ~0ULL, &device);
94580299
BS
499 if (ret)
500 return ret;
501
502 pci_set_master(pdev);
503
915b4d11 504 ret = drm_get_pci_dev(pdev, pent, &driver_pci);
94580299 505 if (ret) {
e781dc8f 506 nvkm_device_del(&device);
94580299
BS
507 return ret;
508 }
509
510 return 0;
511}
512
5b8a43ae 513static int
94580299
BS
514nouveau_drm_load(struct drm_device *dev, unsigned long flags)
515{
94580299
BS
516 struct nouveau_drm *drm;
517 int ret;
518
20d8a88e
BS
519 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
520 return -ENOMEM;
521 dev->dev_private = drm;
522 drm->dev = dev;
523
cb7e88e7
BS
524 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
525 if (ret)
526 return ret;
527
20d8a88e 528 ret = nouveau_cli_init(drm, "DRM", &drm->client);
94580299
BS
529 if (ret)
530 return ret;
531
1167c6bc
BS
532 dev->irq_enabled = true;
533
989aa5b7 534 nvxx_client(&drm->client.base)->debug =
be83cd4e 535 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 536
94580299 537 INIT_LIST_HEAD(&drm->clients);
ebb945a9 538 spin_lock_init(&drm->tile.lock);
94580299 539
77145f1c
BS
540 /* workaround an odd issue on nvc1 by disabling the device's
541 * nosnoop capability. hopefully won't cause issues until a
542 * better fix is found - assuming there is one...
543 */
1167c6bc
BS
544 if (drm->client.device.info.chipset == 0xc1)
545 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 546
77145f1c 547 nouveau_vga_init(drm);
cb75d97e 548
ebb945a9 549 ret = nouveau_ttm_init(drm);
94580299 550 if (ret)
77145f1c
BS
551 goto fail_ttm;
552
553 ret = nouveau_bios_init(dev);
554 if (ret)
555 goto fail_bios;
556
77145f1c 557 ret = nouveau_display_create(dev);
ebb945a9 558 if (ret)
77145f1c
BS
559 goto fail_dispctor;
560
561 if (dev->mode_config.num_crtc) {
562 ret = nouveau_display_init(dev);
563 if (ret)
564 goto fail_dispinit;
565 }
566
b126a200 567 nouveau_debugfs_init(drm);
b9ed919f 568 nouveau_hwmon_init(dev);
ebb945a9
BS
569 nouveau_accel_init(drm);
570 nouveau_fbcon_init(dev);
8d021d71 571 nouveau_led_init(dev);
5addcf0a 572
8fa4338a 573 if (nouveau_pmops_runtime()) {
5addcf0a
DA
574 pm_runtime_use_autosuspend(dev->dev);
575 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
576 pm_runtime_set_active(dev->dev);
577 pm_runtime_allow(dev->dev);
578 pm_runtime_mark_last_busy(dev->dev);
579 pm_runtime_put(dev->dev);
9a2eba33
PU
580 } else {
581 /* enable polling for external displays */
582 drm_kms_helper_poll_enable(dev);
5addcf0a 583 }
94580299
BS
584 return 0;
585
77145f1c
BS
586fail_dispinit:
587 nouveau_display_destroy(dev);
588fail_dispctor:
77145f1c
BS
589 nouveau_bios_takedown(dev);
590fail_bios:
ebb945a9 591 nouveau_ttm_fini(drm);
77145f1c 592fail_ttm:
77145f1c 593 nouveau_vga_fini(drm);
20d8a88e 594 nouveau_cli_fini(&drm->client);
cb7e88e7 595 nouveau_cli_fini(&drm->master);
20d8a88e 596 kfree(drm);
94580299
BS
597 return ret;
598}
599
11b3c20b 600static void
94580299
BS
601nouveau_drm_unload(struct drm_device *dev)
602{
77145f1c 603 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 604
8fa4338a 605 if (nouveau_pmops_runtime()) {
c1b16b45 606 pm_runtime_get_sync(dev->dev);
55c868a3 607 pm_runtime_forbid(dev->dev);
c1b16b45
LW
608 }
609
8d021d71 610 nouveau_led_fini(dev);
ebb945a9
BS
611 nouveau_fbcon_fini(dev);
612 nouveau_accel_fini(drm);
b9ed919f 613 nouveau_hwmon_fini(dev);
b126a200 614 nouveau_debugfs_fini(drm);
77145f1c 615
9430738d 616 if (dev->mode_config.num_crtc)
3b4c0abb 617 nouveau_display_fini(dev, false);
77145f1c
BS
618 nouveau_display_destroy(dev);
619
77145f1c 620 nouveau_bios_takedown(dev);
94580299 621
ebb945a9 622 nouveau_ttm_fini(drm);
77145f1c 623 nouveau_vga_fini(drm);
cb75d97e 624
20d8a88e 625 nouveau_cli_fini(&drm->client);
cb7e88e7 626 nouveau_cli_fini(&drm->master);
20d8a88e 627 kfree(drm);
94580299
BS
628}
629
8ba9ff11
AC
630void
631nouveau_drm_device_remove(struct drm_device *dev)
94580299 632{
77145f1c 633 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e 634 struct nvkm_client *client;
76ecea5b 635 struct nvkm_device *device;
77145f1c 636
7d3428cd 637 dev->irq_enabled = false;
989aa5b7 638 client = nvxx_client(&drm->client.base);
4e7e62d6 639 device = nvkm_device_find(client->device);
77145f1c
BS
640 drm_put_dev(dev);
641
e781dc8f 642 nvkm_device_del(&device);
94580299 643}
8ba9ff11
AC
644
645static void
646nouveau_drm_remove(struct pci_dev *pdev)
647{
648 struct drm_device *dev = pci_get_drvdata(pdev);
649
650 nouveau_drm_device_remove(dev);
651}
94580299 652
cd897837 653static int
05c63c2f 654nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 655{
77145f1c 656 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
657 int ret;
658
8d021d71
MP
659 nouveau_led_suspend(dev);
660
6fbb702e 661 if (dev->mode_config.num_crtc) {
2d38a535 662 NV_DEBUG(drm, "suspending console...\n");
6fbb702e 663 nouveau_fbcon_set_suspend(dev, 1);
2d38a535 664 NV_DEBUG(drm, "suspending display...\n");
6fbb702e 665 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
666 if (ret)
667 return ret;
668 }
94580299 669
2d38a535 670 NV_DEBUG(drm, "evicting buffers...\n");
ebb945a9
BS
671 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
672
2d38a535 673 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
674 if (drm->cechan) {
675 ret = nouveau_channel_idle(drm->cechan);
676 if (ret)
f3980dc5 677 goto fail_display;
81dff21b
BS
678 }
679
680 if (drm->channel) {
681 ret = nouveau_channel_idle(drm->channel);
682 if (ret)
f3980dc5 683 goto fail_display;
81dff21b
BS
684 }
685
2d38a535 686 NV_DEBUG(drm, "suspending fence...\n");
ebb945a9 687 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
688 if (!nouveau_fence(drm)->suspend(drm)) {
689 ret = -ENOMEM;
690 goto fail_display;
691 }
ebb945a9
BS
692 }
693
2d38a535 694 NV_DEBUG(drm, "suspending object tree...\n");
cb7e88e7 695 ret = nvif_client_suspend(&drm->master.base);
94580299
BS
696 if (ret)
697 goto fail_client;
698
94580299
BS
699 return 0;
700
701fail_client:
f3980dc5
IM
702 if (drm->fence && nouveau_fence(drm)->resume)
703 nouveau_fence(drm)->resume(drm);
704
705fail_display:
9430738d 706 if (dev->mode_config.num_crtc) {
2d38a535 707 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 708 nouveau_display_resume(dev, runtime);
9430738d 709 }
94580299
BS
710 return ret;
711}
712
cd897837 713static int
6fbb702e 714nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb
DA
715{
716 struct nouveau_drm *drm = nouveau_drm(dev);
2d8b9ccb 717
2d38a535 718 NV_DEBUG(drm, "resuming object tree...\n");
cb7e88e7 719 nvif_client_resume(&drm->master.base);
94580299 720
2d38a535 721 NV_DEBUG(drm, "resuming fence...\n");
81dff21b
BS
722 if (drm->fence && nouveau_fence(drm)->resume)
723 nouveau_fence(drm)->resume(drm);
724
77145f1c 725 nouveau_run_vbios_init(dev);
77145f1c 726
9430738d 727 if (dev->mode_config.num_crtc) {
2d38a535 728 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 729 nouveau_display_resume(dev, runtime);
2d38a535 730 NV_DEBUG(drm, "resuming console...\n");
6fbb702e 731 nouveau_fbcon_set_suspend(dev, 0);
9430738d 732 }
5addcf0a 733
8d021d71
MP
734 nouveau_led_resume(dev);
735
77145f1c 736 return 0;
94580299
BS
737}
738
7bb6d442
BS
739int
740nouveau_pmops_suspend(struct device *dev)
741{
742 struct pci_dev *pdev = to_pci_dev(dev);
743 struct drm_device *drm_dev = pci_get_drvdata(pdev);
744 int ret;
745
746 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
747 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
748 return 0;
749
750 ret = nouveau_do_suspend(drm_dev, false);
751 if (ret)
752 return ret;
753
754 pci_save_state(pdev);
755 pci_disable_device(pdev);
7bb6d442 756 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 757 udelay(200);
7bb6d442
BS
758 return 0;
759}
760
761int
762nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
763{
764 struct pci_dev *pdev = to_pci_dev(dev);
765 struct drm_device *drm_dev = pci_get_drvdata(pdev);
766 int ret;
767
5addcf0a
DA
768 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
769 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
770 return 0;
771
772 pci_set_power_state(pdev, PCI_D0);
773 pci_restore_state(pdev);
774 ret = pci_enable_device(pdev);
775 if (ret)
776 return ret;
777 pci_set_master(pdev);
778
0b2fe659
HG
779 ret = nouveau_do_resume(drm_dev, false);
780
781 /* Monitors may have been connected / disconnected during suspend */
782 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
783
784 return ret;
2d8b9ccb
DA
785}
786
7bb6d442
BS
787static int
788nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
789{
790 struct pci_dev *pdev = to_pci_dev(dev);
791 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 792 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
793}
794
7bb6d442
BS
795static int
796nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
797{
798 struct pci_dev *pdev = to_pci_dev(dev);
799 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 800 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
801}
802
321f5c5f 803bool
5499473c 804nouveau_pmops_runtime(void)
321f5c5f
BS
805{
806 if (nouveau_runtime_pm == -1)
807 return nouveau_is_optimus() || nouveau_is_v1_dsm();
808 return nouveau_runtime_pm == 1;
809}
810
7bb6d442
BS
811static int
812nouveau_pmops_runtime_suspend(struct device *dev)
813{
814 struct pci_dev *pdev = to_pci_dev(dev);
815 struct drm_device *drm_dev = pci_get_drvdata(pdev);
816 int ret;
817
321f5c5f 818 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
819 pm_runtime_forbid(dev);
820 return -EBUSY;
821 }
822
7bb6d442 823 drm_kms_helper_poll_disable(drm_dev);
7bb6d442
BS
824 nouveau_switcheroo_optimus_dsm();
825 ret = nouveau_do_suspend(drm_dev, true);
826 pci_save_state(pdev);
827 pci_disable_device(pdev);
8c863944 828 pci_ignore_hotplug(pdev);
7bb6d442
BS
829 pci_set_power_state(pdev, PCI_D3cold);
830 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
831 return ret;
832}
833
834static int
835nouveau_pmops_runtime_resume(struct device *dev)
836{
837 struct pci_dev *pdev = to_pci_dev(dev);
838 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1167c6bc 839 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
7bb6d442
BS
840 int ret;
841
321f5c5f
BS
842 if (!nouveau_pmops_runtime()) {
843 pm_runtime_forbid(dev);
844 return -EBUSY;
845 }
7bb6d442
BS
846
847 pci_set_power_state(pdev, PCI_D0);
848 pci_restore_state(pdev);
849 ret = pci_enable_device(pdev);
850 if (ret)
851 return ret;
852 pci_set_master(pdev);
853
854 ret = nouveau_do_resume(drm_dev, true);
cae9ff03 855
7bb6d442 856 /* do magic */
a01ca78c 857 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
7bb6d442 858 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
0b2fe659
HG
859
860 /* Monitors may have been connected / disconnected during suspend */
861 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
862
7bb6d442
BS
863 return ret;
864}
865
866static int
867nouveau_pmops_runtime_idle(struct device *dev)
868{
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct drm_device *drm_dev = pci_get_drvdata(pdev);
871 struct nouveau_drm *drm = nouveau_drm(drm_dev);
872 struct drm_crtc *crtc;
873
321f5c5f 874 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
875 pm_runtime_forbid(dev);
876 return -EBUSY;
877 }
878
7bb6d442
BS
879 list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
880 if (crtc->enabled) {
881 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
882 return -EBUSY;
883 }
884 }
885 pm_runtime_mark_last_busy(dev);
886 pm_runtime_autosuspend(dev);
887 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
888 return 1;
889}
2d8b9ccb 890
5b8a43ae 891static int
ebb945a9
BS
892nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
893{
ebb945a9
BS
894 struct nouveau_drm *drm = nouveau_drm(dev);
895 struct nouveau_cli *cli;
a2896ced 896 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
897 int ret;
898
5addcf0a
DA
899 /* need to bring up power immediately if opening device */
900 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 901 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
902 return ret;
903
a2896ced
MS
904 get_task_comm(tmpname, current);
905 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 906
20d8a88e
BS
907 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL)))
908 return ret;
420b9469 909
20d8a88e 910 ret = nouveau_cli_init(drm, name, cli);
ebb945a9 911 if (ret)
20d8a88e 912 goto done;
ebb945a9 913
0ad72863
BS
914 cli->base.super = false;
915
ebb945a9
BS
916 fpriv->driver_priv = cli;
917
918 mutex_lock(&drm->client.mutex);
919 list_add(&cli->head, &drm->clients);
920 mutex_unlock(&drm->client.mutex);
5addcf0a 921
20d8a88e
BS
922done:
923 if (ret && cli) {
924 nouveau_cli_fini(cli);
925 kfree(cli);
926 }
927
5addcf0a
DA
928 pm_runtime_mark_last_busy(dev->dev);
929 pm_runtime_put_autosuspend(dev->dev);
5addcf0a 930 return ret;
ebb945a9
BS
931}
932
5b8a43ae 933static void
f0e73ff3 934nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
ebb945a9
BS
935{
936 struct nouveau_cli *cli = nouveau_cli(fpriv);
937 struct nouveau_drm *drm = nouveau_drm(dev);
938
5addcf0a
DA
939 pm_runtime_get_sync(dev->dev);
940
ac8c7930 941 mutex_lock(&cli->mutex);
ebb945a9
BS
942 if (cli->abi16)
943 nouveau_abi16_fini(cli->abi16);
ac8c7930 944 mutex_unlock(&cli->mutex);
ebb945a9
BS
945
946 mutex_lock(&drm->client.mutex);
947 list_del(&cli->head);
948 mutex_unlock(&drm->client.mutex);
5addcf0a 949
20d8a88e
BS
950 nouveau_cli_fini(cli);
951 kfree(cli);
5addcf0a
DA
952 pm_runtime_mark_last_busy(dev->dev);
953 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
954}
955
baa70943 956static const struct drm_ioctl_desc
77145f1c 957nouveau_ioctls[] = {
f8c47144
DV
958 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
960 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
963 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
967 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
969 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
970};
971
27111a23
BS
972long
973nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 974{
27111a23
BS
975 struct drm_file *filp = file->private_data;
976 struct drm_device *dev = filp->minor->dev;
5addcf0a 977 long ret;
5addcf0a
DA
978
979 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 980 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
981 return ret;
982
27111a23
BS
983 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
984 case DRM_NOUVEAU_NVIF:
985 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
986 break;
987 default:
988 ret = drm_ioctl(file, cmd, arg);
989 break;
990 }
5addcf0a
DA
991
992 pm_runtime_mark_last_busy(dev->dev);
993 pm_runtime_put_autosuspend(dev->dev);
994 return ret;
995}
27111a23 996
77145f1c
BS
997static const struct file_operations
998nouveau_driver_fops = {
999 .owner = THIS_MODULE,
1000 .open = drm_open,
1001 .release = drm_release,
5addcf0a 1002 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
1003 .mmap = nouveau_ttm_mmap,
1004 .poll = drm_poll,
77145f1c
BS
1005 .read = drm_read,
1006#if defined(CONFIG_COMPAT)
1007 .compat_ioctl = nouveau_compat_ioctl,
1008#endif
1009 .llseek = noop_llseek,
1010};
1011
1012static struct drm_driver
915b4d11 1013driver_stub = {
77145f1c 1014 .driver_features =
0e975980
PA
1015 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
1016 DRIVER_KMS_LEGACY_CONTEXT,
77145f1c
BS
1017
1018 .load = nouveau_drm_load,
1019 .unload = nouveau_drm_unload,
1020 .open = nouveau_drm_open,
77145f1c
BS
1021 .postclose = nouveau_drm_postclose,
1022 .lastclose = nouveau_vga_lastclose,
1023
33b903e8 1024#if defined(CONFIG_DEBUG_FS)
56c101af 1025 .debugfs_init = nouveau_drm_debugfs_init,
33b903e8
MS
1026#endif
1027
51cb4b39
BS
1028 .enable_vblank = nouveau_display_vblank_enable,
1029 .disable_vblank = nouveau_display_vblank_disable,
d83ef853 1030 .get_scanout_position = nouveau_display_scanoutpos,
1bf6ad62 1031 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
77145f1c
BS
1032
1033 .ioctls = nouveau_ioctls,
baa70943 1034 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
1035 .fops = &nouveau_driver_fops,
1036
1037 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1038 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
1039 .gem_prime_export = drm_gem_prime_export,
1040 .gem_prime_import = drm_gem_prime_import,
1041 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 1042 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 1043 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
1044 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1045 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1046 .gem_prime_vmap = nouveau_gem_prime_vmap,
1047 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 1048
a51e6ac4 1049 .gem_free_object_unlocked = nouveau_gem_object_del,
77145f1c
BS
1050 .gem_open_object = nouveau_gem_object_open,
1051 .gem_close_object = nouveau_gem_object_close,
1052
1053 .dumb_create = nouveau_display_dumb_create,
1054 .dumb_map_offset = nouveau_display_dumb_map_offset,
77145f1c
BS
1055
1056 .name = DRIVER_NAME,
1057 .desc = DRIVER_DESC,
1058#ifdef GIT_REVISION
1059 .date = GIT_REVISION,
1060#else
1061 .date = DRIVER_DATE,
1062#endif
1063 .major = DRIVER_MAJOR,
1064 .minor = DRIVER_MINOR,
1065 .patchlevel = DRIVER_PATCHLEVEL,
1066};
1067
94580299
BS
1068static struct pci_device_id
1069nouveau_drm_pci_table[] = {
1070 {
1071 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1072 .class = PCI_BASE_CLASS_DISPLAY << 16,
1073 .class_mask = 0xff << 16,
1074 },
1075 {
1076 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1077 .class = PCI_BASE_CLASS_DISPLAY << 16,
1078 .class_mask = 0xff << 16,
1079 },
1080 {}
1081};
1082
703fa264
PM
1083static void nouveau_display_options(void)
1084{
1085 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1086
1087 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1088 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1089 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1090 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1091 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1092 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1093 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1094 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1095 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1096 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
f3a8b664 1097 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
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1098}
1099
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DA
1100static const struct dev_pm_ops nouveau_pm_ops = {
1101 .suspend = nouveau_pmops_suspend,
1102 .resume = nouveau_pmops_resume,
1103 .freeze = nouveau_pmops_freeze,
1104 .thaw = nouveau_pmops_thaw,
1105 .poweroff = nouveau_pmops_freeze,
1106 .restore = nouveau_pmops_resume,
5addcf0a
DA
1107 .runtime_suspend = nouveau_pmops_runtime_suspend,
1108 .runtime_resume = nouveau_pmops_runtime_resume,
1109 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1110};
1111
94580299
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1112static struct pci_driver
1113nouveau_drm_pci_driver = {
1114 .name = "nouveau",
1115 .id_table = nouveau_drm_pci_table,
1116 .probe = nouveau_drm_probe,
1117 .remove = nouveau_drm_remove,
2d8b9ccb 1118 .driver.pm = &nouveau_pm_ops,
94580299
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1119};
1120
8ba9ff11 1121struct drm_device *
e396ecd1
AC
1122nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1123 struct platform_device *pdev,
47b2505e 1124 struct nvkm_device **pdevice)
420b9469 1125{
8ba9ff11
AC
1126 struct drm_device *drm;
1127 int err;
420b9469 1128
e396ecd1 1129 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
7974dd1b 1130 true, true, ~0ULL, pdevice);
8ba9ff11 1131 if (err)
e781dc8f 1132 goto err_free;
8ba9ff11 1133
915b4d11 1134 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
0f288605
TG
1135 if (IS_ERR(drm)) {
1136 err = PTR_ERR(drm);
8ba9ff11 1137 goto err_free;
420b9469
AC
1138 }
1139
8ba9ff11
AC
1140 platform_set_drvdata(pdev, drm);
1141
1142 return drm;
1143
1144err_free:
e781dc8f 1145 nvkm_device_del(pdevice);
8ba9ff11
AC
1146
1147 return ERR_PTR(err);
420b9469
AC
1148}
1149
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1150static int __init
1151nouveau_drm_init(void)
1152{
915b4d11 1153 driver_pci = driver_stub;
915b4d11 1154 driver_platform = driver_stub;
915b4d11 1155
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1156 nouveau_display_options();
1157
77145f1c 1158 if (nouveau_modeset == -1) {
77145f1c
BS
1159 if (vgacon_text_force())
1160 nouveau_modeset = 0;
77145f1c
BS
1161 }
1162
1163 if (!nouveau_modeset)
1164 return 0;
1165
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AC
1166#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1167 platform_driver_register(&nouveau_platform_driver);
1168#endif
1169
77145f1c 1170 nouveau_register_dsm_handler();
db1a0ae2 1171 nouveau_backlight_ctor();
10631d72
DV
1172
1173#ifdef CONFIG_PCI
1174 return pci_register_driver(&nouveau_drm_pci_driver);
1175#else
1176 return 0;
1177#endif
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1178}
1179
1180static void __exit
1181nouveau_drm_exit(void)
1182{
77145f1c
BS
1183 if (!nouveau_modeset)
1184 return;
1185
10631d72
DV
1186#ifdef CONFIG_PCI
1187 pci_unregister_driver(&nouveau_drm_pci_driver);
1188#endif
db1a0ae2 1189 nouveau_backlight_dtor();
77145f1c 1190 nouveau_unregister_dsm_handler();
055a65d5
AC
1191
1192#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1193 platform_driver_unregister(&nouveau_platform_driver);
1194#endif
94580299
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1195}
1196
1197module_init(nouveau_drm_init);
1198module_exit(nouveau_drm_exit);
1199
1200MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1201MODULE_AUTHOR(DRIVER_AUTHOR);
1202MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1203MODULE_LICENSE("GPL and additional rights");