]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/gpu/drm/omapdrm/dss/hdmi4.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
[thirdparty/linux.git] / drivers / gpu / drm / omapdrm / dss / hdmi4.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
c3198a5e 2/*
ef26958a 3 * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
bb5cdf8d 4 *
c3198a5e
M
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
c3198a5e
M
8 */
9
10#define DSS_SUBSYS_NAME "HDMI"
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/interrupt.h>
17#include <linux/mutex.h>
18#include <linux/delay.h>
19#include <linux/string.h>
24e6289c 20#include <linux/platform_device.h>
4fbafaf3
TV
21#include <linux/pm_runtime.h>
22#include <linux/clk.h>
cca35017 23#include <linux/gpio.h>
17486943 24#include <linux/regulator/consumer.h>
736e60dd 25#include <linux/component.h>
d9e32ecd 26#include <linux/of.h>
09bffa6e 27#include <linux/of_graph.h>
4d594dff 28#include <sound/omap-hdmi-audio.h>
1897e1a3 29#include <media/cec.h>
c3198a5e 30
32043da7 31#include "omapdss.h"
ef26958a 32#include "hdmi4_core.h"
1897e1a3 33#include "hdmi4_cec.h"
c3198a5e 34#include "dss.h"
945514b5 35#include "hdmi.h"
c3198a5e 36
ac767456 37static int hdmi_runtime_get(struct omap_hdmi *hdmi)
4fbafaf3
TV
38{
39 int r;
40
41 DSSDBG("hdmi_runtime_get\n");
42
ac767456 43 r = pm_runtime_get_sync(&hdmi->pdev->dev);
4fbafaf3 44 WARN_ON(r < 0);
a247ce78 45 if (r < 0)
852f0838 46 return r;
a247ce78
AT
47
48 return 0;
4fbafaf3
TV
49}
50
ac767456 51static void hdmi_runtime_put(struct omap_hdmi *hdmi)
4fbafaf3
TV
52{
53 int r;
54
55 DSSDBG("hdmi_runtime_put\n");
56
ac767456 57 r = pm_runtime_put_sync(&hdmi->pdev->dev);
5be3aebd 58 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV
59}
60
dcf5f729
TV
61static irqreturn_t hdmi_irq_handler(int irq, void *data)
62{
f3096a4a
HV
63 struct omap_hdmi *hdmi = data;
64 struct hdmi_wp_data *wp = &hdmi->wp;
dcf5f729
TV
65 u32 irqstatus;
66
67 irqstatus = hdmi_wp_get_irqstatus(wp);
68 hdmi_wp_set_irqstatus(wp, irqstatus);
69
70 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
71 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
72 /*
73 * If we get both connect and disconnect interrupts at the same
74 * time, turn off the PHY, clear interrupts, and restart, which
75 * raises connect interrupt if a cable is connected, or nothing
76 * if cable is not connected.
77 */
78 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
79
80 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
81 HDMI_IRQ_LINK_DISCONNECT);
82
83 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
84 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
85 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
86 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
87 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
88 }
1897e1a3
HV
89 if (irqstatus & HDMI_IRQ_CORE) {
90 u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4);
91
92 hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4);
93 if (intr4 & 8)
94 hdmi4_cec_irq(&hdmi->core);
95 }
dcf5f729
TV
96
97 return IRQ_HANDLED;
98}
99
ac767456 100static int hdmi_power_on_core(struct omap_hdmi *hdmi)
c3198a5e 101{
46095b2d 102 int r;
c3198a5e 103
ac767456 104 if (hdmi->core.core_pwr_cnt++)
a141a296
HV
105 return 0;
106
ac767456 107 r = regulator_enable(hdmi->vdda_reg);
17486943 108 if (r)
a141a296 109 goto err_reg_enable;
17486943 110
ac767456 111 r = hdmi_runtime_get(hdmi);
4fbafaf3 112 if (r)
cca35017 113 goto err_runtime_get;
c3198a5e 114
ac767456 115 hdmi4_core_powerdown_disable(&hdmi->core);
1d54ecf2 116
bb426fc9 117 /* Make selection of HDMI in DSS */
ac767456 118 dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
bb426fc9 119
ac767456 120 hdmi->core_enabled = true;
0b450c31 121
bb426fc9
TV
122 return 0;
123
124err_runtime_get:
ac767456 125 regulator_disable(hdmi->vdda_reg);
a141a296 126err_reg_enable:
ac767456 127 hdmi->core.core_pwr_cnt--;
164ebdd1 128
bb426fc9
TV
129 return r;
130}
131
ac767456 132static void hdmi_power_off_core(struct omap_hdmi *hdmi)
bb426fc9 133{
ac767456 134 if (--hdmi->core.core_pwr_cnt)
a141a296
HV
135 return;
136
ac767456 137 hdmi->core_enabled = false;
0b450c31 138
ac767456
LP
139 hdmi_runtime_put(hdmi);
140 regulator_disable(hdmi->vdda_reg);
bb426fc9
TV
141}
142
ac767456 143static int hdmi_power_on_full(struct omap_hdmi *hdmi)
bb426fc9
TV
144{
145 int r;
95e472da 146 const struct videomode *vm;
ac767456 147 struct hdmi_wp_data *wp = &hdmi->wp;
c84c3a5b 148 struct dss_pll_clock_info hdmi_cinfo = { 0 };
d11e5c82 149 unsigned int pc;
bb426fc9 150
ac767456 151 r = hdmi_power_on_core(hdmi);
bb426fc9
TV
152 if (r)
153 return r;
154
dcf5f729 155 /* disable and clear irqs */
f3096a4a
HV
156 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);
157 hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);
dcf5f729 158
ac767456 159 vm = &hdmi->cfg.vm;
c3198a5e 160
da11bbbb
PU
161 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
162 vm->vactive);
c3198a5e 163
da11bbbb
PU
164 pc = vm->pixelclock;
165 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
67d8ffdd
TV
166 pc *= 2;
167
c107751d
TV
168 /* DSS_HDMI_TCLK is bitclk / 10 */
169 pc *= 10;
170
ac767456 171 dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
c17dc0e3 172 pc, &hdmi_cinfo);
c3198a5e 173
ac767456 174 r = dss_pll_enable(&hdmi->pll.pll);
c3198a5e 175 if (r) {
c2fbd061 176 DSSERR("Failed to enable PLL\n");
cca35017 177 goto err_pll_enable;
c3198a5e
M
178 }
179
ac767456 180 r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
c2fbd061
TV
181 if (r) {
182 DSSERR("Failed to configure PLL\n");
183 goto err_pll_cfg;
184 }
185
ac767456 186 r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
c84c3a5b 187 hdmi_cinfo.clkout[0]);
c3198a5e 188 if (r) {
dcf5f729
TV
189 DSSDBG("Failed to configure PHY\n");
190 goto err_phy_cfg;
c3198a5e
M
191 }
192
dcf5f729
TV
193 r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
194 if (r)
195 goto err_phy_pwr;
196
ac767456 197 hdmi4_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
c3198a5e 198
ac767456 199 r = dss_mgr_enable(&hdmi->output);
33ca237f
TV
200 if (r)
201 goto err_mgr_enable;
3870c909 202
ac767456 203 r = hdmi_wp_video_start(&hdmi->wp);
4e4b53ce
TV
204 if (r)
205 goto err_vid_enable;
206
dcf5f729
TV
207 hdmi_wp_set_irqenable(wp,
208 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
209
c3198a5e 210 return 0;
33ca237f 211
c0456be3 212err_vid_enable:
ac767456 213 dss_mgr_disable(&hdmi->output);
4e4b53ce 214err_mgr_enable:
ac767456 215 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
dcf5f729 216err_phy_pwr:
9bba13f0 217err_phy_cfg:
c2fbd061 218err_pll_cfg:
ac767456 219 dss_pll_disable(&hdmi->pll.pll);
cca35017 220err_pll_enable:
ac767456 221 hdmi_power_off_core(hdmi);
c3198a5e
M
222 return -EIO;
223}
224
ac767456 225static void hdmi_power_off_full(struct omap_hdmi *hdmi)
c3198a5e 226{
ac767456 227 hdmi_wp_clear_irqenable(&hdmi->wp, ~HDMI_IRQ_CORE);
dcf5f729 228
ac767456 229 hdmi_wp_video_stop(&hdmi->wp);
dcf5f729 230
ac767456 231 dss_mgr_disable(&hdmi->output);
4e4b53ce 232
ac767456 233 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
dcf5f729 234
ac767456 235 dss_pll_disable(&hdmi->pll.pll);
17486943 236
ac767456 237 hdmi_power_off_core(hdmi);
c3198a5e
M
238}
239
ec68cd5a 240static void hdmi_display_set_timings(struct omap_dss_device *dssdev,
41322aa6 241 const struct drm_display_mode *mode)
c3198a5e 242{
ac767456 243 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
ed1aa900 244
ac767456 245 mutex_lock(&hdmi->lock);
5391e87d 246
41322aa6 247 drm_display_mode_to_videomode(mode, &hdmi->cfg.vm);
1e676248 248
41322aa6 249 dispc_set_tv_pclk(hdmi->dss->dispc, mode->clock * 1000);
ac767456
LP
250
251 mutex_unlock(&hdmi->lock);
c3198a5e
M
252}
253
f33656e1 254static int hdmi_dump_regs(struct seq_file *s, void *p)
162874d5 255{
ac767456
LP
256 struct omap_hdmi *hdmi = s->private;
257
258 mutex_lock(&hdmi->lock);
162874d5 259
ac767456
LP
260 if (hdmi_runtime_get(hdmi)) {
261 mutex_unlock(&hdmi->lock);
f33656e1 262 return 0;
f8fb7d7b 263 }
162874d5 264
ac767456
LP
265 hdmi_wp_dump(&hdmi->wp, s);
266 hdmi_pll_dump(&hdmi->pll, s);
267 hdmi_phy_dump(&hdmi->phy, s);
268 hdmi4_core_dump(&hdmi->core, s);
162874d5 269
ac767456
LP
270 hdmi_runtime_put(hdmi);
271 mutex_unlock(&hdmi->lock);
f33656e1 272 return 0;
162874d5
M
273}
274
ac767456 275static int read_edid(struct omap_hdmi *hdmi, u8 *buf, int len)
47024565
TV
276{
277 int r;
278
ac767456 279 mutex_lock(&hdmi->lock);
47024565 280
ac767456 281 r = hdmi_runtime_get(hdmi);
47024565
TV
282 BUG_ON(r);
283
ac767456 284 r = hdmi4_read_edid(&hdmi->core, buf, len);
47024565 285
ac767456
LP
286 hdmi_runtime_put(hdmi);
287 mutex_unlock(&hdmi->lock);
47024565
TV
288
289 return r;
290}
291
8a9d4626
JS
292static void hdmi_start_audio_stream(struct omap_hdmi *hd)
293{
294 hdmi_wp_audio_enable(&hd->wp, true);
295 hdmi4_audio_start(&hd->core, &hd->wp);
296}
297
298static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
299{
300 hdmi4_audio_stop(&hd->core, &hd->wp);
301 hdmi_wp_audio_enable(&hd->wp, false);
302}
303
19b4200d 304static void hdmi_display_enable(struct omap_dss_device *dssdev)
c3198a5e 305{
ac767456 306 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626 307 unsigned long flags;
19b4200d 308 int r;
c3198a5e
M
309
310 DSSDBG("ENTER hdmi_display_enable\n");
311
ac767456 312 mutex_lock(&hdmi->lock);
c3198a5e 313
ac767456 314 r = hdmi_power_on_full(hdmi);
c3198a5e
M
315 if (r) {
316 DSSERR("failed to power on device\n");
19b4200d 317 goto done;
c3198a5e
M
318 }
319
ac767456
LP
320 if (hdmi->audio_configured) {
321 r = hdmi4_audio_config(&hdmi->core, &hdmi->wp,
322 &hdmi->audio_config,
323 hdmi->cfg.vm.pixelclock);
8a9d4626
JS
324 if (r) {
325 DSSERR("Error restoring audio configuration: %d", r);
ac767456
LP
326 hdmi->audio_abort_cb(&hdmi->pdev->dev);
327 hdmi->audio_configured = false;
8a9d4626
JS
328 }
329 }
330
ac767456
LP
331 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
332 if (hdmi->audio_configured && hdmi->audio_playing)
333 hdmi_start_audio_stream(hdmi);
334 hdmi->display_enabled = true;
335 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
4d594dff 336
19b4200d 337done:
ac767456 338 mutex_unlock(&hdmi->lock);
c3198a5e
M
339}
340
164ebdd1 341static void hdmi_display_disable(struct omap_dss_device *dssdev)
c3198a5e 342{
ac767456 343 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626
JS
344 unsigned long flags;
345
c3198a5e
M
346 DSSDBG("Enter hdmi_display_disable\n");
347
ac767456 348 mutex_lock(&hdmi->lock);
c3198a5e 349
ac767456
LP
350 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
351 hdmi_stop_audio_stream(hdmi);
352 hdmi->display_enabled = false;
353 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
4d594dff 354
ac767456 355 hdmi_power_off_full(hdmi);
c3198a5e 356
ac767456 357 mutex_unlock(&hdmi->lock);
c3198a5e
M
358}
359
ac767456 360int hdmi4_core_enable(struct hdmi_core_data *core)
4489823c 361{
ac767456 362 struct omap_hdmi *hdmi = container_of(core, struct omap_hdmi, core);
4489823c
TV
363 int r = 0;
364
5bebbbfe 365 DSSDBG("ENTER omapdss_hdmi4_core_enable\n");
4489823c 366
ac767456 367 mutex_lock(&hdmi->lock);
4489823c 368
ac767456 369 r = hdmi_power_on_core(hdmi);
4489823c
TV
370 if (r) {
371 DSSERR("failed to power on device\n");
372 goto err0;
373 }
374
ac767456 375 mutex_unlock(&hdmi->lock);
4489823c
TV
376 return 0;
377
378err0:
ac767456 379 mutex_unlock(&hdmi->lock);
4489823c
TV
380 return r;
381}
382
ac767456 383void hdmi4_core_disable(struct hdmi_core_data *core)
4489823c 384{
ac767456
LP
385 struct omap_hdmi *hdmi = container_of(core, struct omap_hdmi, core);
386
5bebbbfe 387 DSSDBG("Enter omapdss_hdmi4_core_disable\n");
4489823c 388
ac767456 389 mutex_lock(&hdmi->lock);
4489823c 390
ac767456 391 hdmi_power_off_core(hdmi);
4489823c 392
ac767456 393 mutex_unlock(&hdmi->lock);
4489823c
TV
394}
395
511afb44
LP
396static int hdmi_connect(struct omap_dss_device *src,
397 struct omap_dss_device *dst)
0b450c31 398{
f8a8eabb 399 return omapdss_device_connect(dst->dss, dst, dst->next);
0b450c31
TV
400}
401
511afb44
LP
402static void hdmi_disconnect(struct omap_dss_device *src,
403 struct omap_dss_device *dst)
0b450c31 404{
511afb44 405 omapdss_device_disconnect(dst, dst->next);
0b450c31
TV
406}
407
408static int hdmi_read_edid(struct omap_dss_device *dssdev,
409 u8 *edid, int len)
410{
ac767456 411 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
0b450c31
TV
412 bool need_enable;
413 int r;
414
ac767456 415 need_enable = hdmi->core_enabled == false;
0b450c31
TV
416
417 if (need_enable) {
ac767456 418 r = hdmi4_core_enable(&hdmi->core);
0b450c31
TV
419 if (r)
420 return r;
421 }
422
ac767456 423 r = read_edid(hdmi, edid, len);
1897e1a3 424 if (r >= 256)
ac767456 425 hdmi4_cec_set_phys_addr(&hdmi->core,
1897e1a3
HV
426 cec_get_edid_phys_addr(edid, r, NULL));
427 else
ac767456 428 hdmi4_cec_set_phys_addr(&hdmi->core, CEC_PHYS_ADDR_INVALID);
0b450c31 429 if (need_enable)
ac767456 430 hdmi4_core_disable(&hdmi->core);
0b450c31
TV
431
432 return r;
433}
434
019114ef
HV
435static void hdmi_lost_hotplug(struct omap_dss_device *dssdev)
436{
ac767456
LP
437 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
438
439 hdmi4_cec_set_phys_addr(&hdmi->core, CEC_PHYS_ADDR_INVALID);
019114ef
HV
440}
441
ab0aee95
TV
442static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
443 const struct hdmi_avi_infoframe *avi)
444{
ac767456
LP
445 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
446
447 hdmi->cfg.infoframe = *avi;
ab0aee95
TV
448 return 0;
449}
450
451static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
452 bool hdmi_mode)
453{
ac767456
LP
454 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
455
456 hdmi->cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
ab0aee95
TV
457 return 0;
458}
459
b93109d7 460static const struct omap_dss_device_ops hdmi_ops = {
0b450c31
TV
461 .connect = hdmi_connect,
462 .disconnect = hdmi_disconnect,
463
164ebdd1
TV
464 .enable = hdmi_display_enable,
465 .disable = hdmi_display_disable,
0b450c31 466
ec68cd5a 467 .set_timings = hdmi_display_set_timings,
0b450c31 468
83910ad3
LP
469 .read_edid = hdmi_read_edid,
470
b93109d7 471 .hdmi = {
b93109d7
LP
472 .lost_hotplug = hdmi_lost_hotplug,
473 .set_infoframe = hdmi_set_infoframe,
474 .set_hdmi_mode = hdmi_set_hdmi_mode,
475 },
0b450c31
TV
476};
477
5fc15d98
LP
478/* -----------------------------------------------------------------------------
479 * Audio Callbacks
480 */
2f5dc676 481
4d594dff
JS
482static int hdmi_audio_startup(struct device *dev,
483 void (*abort_cb)(struct device *dev))
484{
485 struct omap_hdmi *hd = dev_get_drvdata(dev);
4d594dff
JS
486
487 mutex_lock(&hd->lock);
488
c1899cb3 489 WARN_ON(hd->audio_abort_cb != NULL);
4d594dff
JS
490
491 hd->audio_abort_cb = abort_cb;
492
4d594dff
JS
493 mutex_unlock(&hd->lock);
494
c1899cb3 495 return 0;
4d594dff
JS
496}
497
498static int hdmi_audio_shutdown(struct device *dev)
499{
500 struct omap_hdmi *hd = dev_get_drvdata(dev);
501
502 mutex_lock(&hd->lock);
503 hd->audio_abort_cb = NULL;
8a9d4626
JS
504 hd->audio_configured = false;
505 hd->audio_playing = false;
4d594dff
JS
506 mutex_unlock(&hd->lock);
507
508 return 0;
509}
510
511static int hdmi_audio_start(struct device *dev)
512{
513 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 514 unsigned long flags;
4d594dff 515
8a9d4626
JS
516 spin_lock_irqsave(&hd->audio_playing_lock, flags);
517
c1899cb3
JS
518 if (hd->display_enabled) {
519 if (!hdmi_mode_has_audio(&hd->cfg))
520 DSSERR("%s: Video mode does not support audio\n",
521 __func__);
8a9d4626 522 hdmi_start_audio_stream(hd);
c1899cb3 523 }
8a9d4626 524 hd->audio_playing = true;
4d594dff 525
8a9d4626 526 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
527 return 0;
528}
529
530static void hdmi_audio_stop(struct device *dev)
531{
532 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 533 unsigned long flags;
4d594dff
JS
534
535 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
4d594dff 536
8a9d4626
JS
537 spin_lock_irqsave(&hd->audio_playing_lock, flags);
538
539 if (hd->display_enabled)
540 hdmi_stop_audio_stream(hd);
541 hd->audio_playing = false;
542
543 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
544}
545
546static int hdmi_audio_config(struct device *dev,
547 struct omap_dss_audio *dss_audio)
548{
549 struct omap_hdmi *hd = dev_get_drvdata(dev);
77eeac24 550 int ret = 0;
4d594dff
JS
551
552 mutex_lock(&hd->lock);
553
c1899cb3
JS
554 if (hd->display_enabled) {
555 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
556 hd->cfg.vm.pixelclock);
557 if (ret)
558 goto out;
4d594dff
JS
559 }
560
c1899cb3
JS
561 hd->audio_configured = true;
562 hd->audio_config = *dss_audio;
4d594dff
JS
563out:
564 mutex_unlock(&hd->lock);
565
566 return ret;
567}
568
569static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
570 .audio_startup = hdmi_audio_startup,
571 .audio_shutdown = hdmi_audio_shutdown,
572 .audio_start = hdmi_audio_start,
573 .audio_stop = hdmi_audio_stop,
574 .audio_config = hdmi_audio_config,
575};
576
ac767456 577static int hdmi_audio_register(struct omap_hdmi *hdmi)
4d594dff
JS
578{
579 struct omap_hdmi_audio_pdata pdata = {
ac767456 580 .dev = &hdmi->pdev->dev,
d20fa5a0 581 .version = 4,
ac767456 582 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
4d594dff
JS
583 .ops = &hdmi_audio_ops,
584 };
585
ac767456
LP
586 hdmi->audio_pdev = platform_device_register_data(
587 &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
4d594dff
JS
588 &pdata, sizeof(pdata));
589
ac767456
LP
590 if (IS_ERR(hdmi->audio_pdev))
591 return PTR_ERR(hdmi->audio_pdev);
4d594dff
JS
592
593 return 0;
594}
595
5fc15d98
LP
596/* -----------------------------------------------------------------------------
597 * Component Bind & Unbind
598 */
599
736e60dd 600static int hdmi4_bind(struct device *dev, struct device *master, void *data)
c3198a5e 601{
7b295257 602 struct dss_device *dss = dss_get_device(master);
5fc15d98 603 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
38f3daf6 604 int r;
5fc15d98
LP
605
606 hdmi->dss = dss;
607
f8523b64 608 r = hdmi_runtime_get(hdmi);
5fc15d98
LP
609 if (r)
610 return r;
611
f8523b64
LP
612 r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
613 if (r)
614 goto err_runtime_put;
615
5fc15d98
LP
616 r = hdmi4_cec_init(hdmi->pdev, &hdmi->core, &hdmi->wp);
617 if (r)
618 goto err_pll_uninit;
619
620 r = hdmi_audio_register(hdmi);
621 if (r) {
622 DSSERR("Registering HDMI audio failed\n");
623 goto err_cec_uninit;
624 }
625
626 hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
627 hdmi);
628
f8523b64
LP
629 hdmi_runtime_put(hdmi);
630
5fc15d98
LP
631 return 0;
632
633err_cec_uninit:
634 hdmi4_cec_uninit(&hdmi->core);
635err_pll_uninit:
636 hdmi_pll_uninit(&hdmi->pll);
f8523b64
LP
637err_runtime_put:
638 hdmi_runtime_put(hdmi);
5fc15d98
LP
639 return r;
640}
641
642static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
643{
644 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
645
646 dss_debugfs_remove_file(hdmi->debugfs);
647
648 if (hdmi->audio_pdev)
649 platform_device_unregister(hdmi->audio_pdev);
650
651 hdmi4_cec_uninit(&hdmi->core);
652 hdmi_pll_uninit(&hdmi->pll);
653}
654
655static const struct component_ops hdmi4_component_ops = {
656 .bind = hdmi4_bind,
657 .unbind = hdmi4_unbind,
658};
659
660/* -----------------------------------------------------------------------------
661 * Probe & Remove, Suspend & Resume
662 */
663
27d62452 664static int hdmi4_init_output(struct omap_hdmi *hdmi)
5fc15d98
LP
665{
666 struct omap_dss_device *out = &hdmi->output;
71316556 667 int r;
5fc15d98
LP
668
669 out->dev = &hdmi->pdev->dev;
670 out->id = OMAP_DSS_OUTPUT_HDMI;
0dbfc396 671 out->type = OMAP_DISPLAY_TYPE_HDMI;
5fc15d98
LP
672 out->name = "hdmi.0";
673 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
674 out->ops = &hdmi_ops;
675 out->owner = THIS_MODULE;
676 out->of_ports = BIT(0);
90279e95 677 out->ops_flags = OMAP_DSS_DEVICE_OP_EDID;
5fc15d98 678
d17eb453
LP
679 r = omapdss_device_init_output(out);
680 if (r < 0)
71316556 681 return r;
71316556 682
5fc15d98 683 omapdss_device_register(out);
27d62452
LP
684
685 return 0;
5fc15d98
LP
686}
687
688static void hdmi4_uninit_output(struct omap_hdmi *hdmi)
689{
690 struct omap_dss_device *out = &hdmi->output;
691
692 omapdss_device_unregister(out);
d17eb453 693 omapdss_device_cleanup_output(out);
5fc15d98
LP
694}
695
696static int hdmi4_probe_of(struct omap_hdmi *hdmi)
697{
698 struct platform_device *pdev = hdmi->pdev;
699 struct device_node *node = pdev->dev.of_node;
700 struct device_node *ep;
701 int r;
702
703 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
704 if (!ep)
705 return 0;
706
707 r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
708 of_node_put(ep);
709 return r;
710}
711
712static int hdmi4_probe(struct platform_device *pdev)
713{
714 struct omap_hdmi *hdmi;
dcf5f729 715 int irq;
5fc15d98 716 int r;
c3198a5e 717
ac767456
LP
718 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
719 if (!hdmi)
720 return -ENOMEM;
721
722 hdmi->pdev = pdev;
5fc15d98 723
ac767456 724 dev_set_drvdata(&pdev->dev, hdmi);
c3198a5e 725
ac767456
LP
726 mutex_init(&hdmi->lock);
727 spin_lock_init(&hdmi->audio_playing_lock);
c3198a5e 728
5fc15d98 729 r = hdmi4_probe_of(hdmi);
1dff212c 730 if (r)
ac767456 731 goto err_free;
2f5dc676 732
ac767456 733 r = hdmi_wp_init(pdev, &hdmi->wp, 4);
f382d9eb 734 if (r)
ac767456 735 goto err_free;
c3198a5e 736
ac767456 737 r = hdmi_phy_init(pdev, &hdmi->phy, 4);
5cac5aee 738 if (r)
5fc15d98 739 goto err_free;
ddb1d5ca 740
ac767456 741 r = hdmi4_core_init(pdev, &hdmi->core);
425f02fd 742 if (r)
5fc15d98 743 goto err_free;
1897e1a3 744
dcf5f729
TV
745 irq = platform_get_irq(pdev, 0);
746 if (irq < 0) {
747 DSSERR("platform_get_irq failed\n");
c84c3a5b 748 r = -ENODEV;
5fc15d98 749 goto err_free;
dcf5f729
TV
750 }
751
752 r = devm_request_threaded_irq(&pdev->dev, irq,
753 NULL, hdmi_irq_handler,
ac767456 754 IRQF_ONESHOT, "OMAP HDMI", hdmi);
dcf5f729
TV
755 if (r) {
756 DSSERR("HDMI IRQ request failed\n");
5fc15d98 757 goto err_free;
dcf5f729
TV
758 }
759
8a36357a
LP
760 hdmi->vdda_reg = devm_regulator_get(&pdev->dev, "vdda");
761 if (IS_ERR(hdmi->vdda_reg)) {
762 r = PTR_ERR(hdmi->vdda_reg);
763 if (r != -EPROBE_DEFER)
764 DSSERR("can't get VDDA regulator\n");
765 goto err_free;
766 }
767
4fbafaf3
TV
768 pm_runtime_enable(&pdev->dev);
769
27d62452
LP
770 r = hdmi4_init_output(hdmi);
771 if (r)
772 goto err_pm_disable;
002d368d 773
5fc15d98
LP
774 r = component_add(&pdev->dev, &hdmi4_component_ops);
775 if (r)
66aacfe2 776 goto err_uninit_output;
e40402cf 777
cca35017 778 return 0;
ac767456 779
66aacfe2 780err_uninit_output:
5fc15d98 781 hdmi4_uninit_output(hdmi);
27d62452 782err_pm_disable:
66aacfe2 783 pm_runtime_disable(&pdev->dev);
ac767456
LP
784err_free:
785 kfree(hdmi);
c84c3a5b 786 return r;
cca35017
TV
787}
788
5fc15d98 789static int hdmi4_remove(struct platform_device *pdev)
c3198a5e 790{
5fc15d98 791 struct omap_hdmi *hdmi = platform_get_drvdata(pdev);
ac767456 792
5fc15d98 793 component_del(&pdev->dev, &hdmi4_component_ops);
81b87f51 794
5fc15d98 795 hdmi4_uninit_output(hdmi);
1897e1a3 796
5fc15d98 797 pm_runtime_disable(&pdev->dev);
c84c3a5b 798
ac767456 799 kfree(hdmi);
c3198a5e
M
800 return 0;
801}
802
0465616d
TV
803static const struct of_device_id hdmi_of_match[] = {
804 { .compatible = "ti,omap4-hdmi", },
805 {},
806};
807
d66c36a3 808struct platform_driver omapdss_hdmi4hw_driver = {
736e60dd
TV
809 .probe = hdmi4_probe,
810 .remove = hdmi4_remove,
c3198a5e
M
811 .driver = {
812 .name = "omapdss_hdmi",
0465616d 813 .of_match_table = hdmi_of_match,
422ccbd5 814 .suppress_bind_attrs = true,
c3198a5e
M
815 },
816};