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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
[thirdparty/linux.git] / drivers / gpu / drm / omapdrm / dss / venc.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
b2886273 2/*
b2886273 3 * Copyright (C) 2009 Nokia Corporation
6505d75c 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
b2886273
TV		 5 *
6 * VENC settings from TI's DSS driver
b2886273
TV		 7 */
8
9#define DSS_SUBSYS_NAME "VENC"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/mutex.h>
17#include <linux/completion.h>
18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/seq_file.h>
21#include <linux/platform_device.h>
22#include <linux/regulator/consumer.h>
4fbafaf3 23#include <linux/pm_runtime.h>
a2207021 24#include <linux/of.h>
09bffa6e 25#include <linux/of_graph.h>
736e60dd 26#include <linux/component.h>
34dfb85f 27#include <linux/sys_soc.h>
b2886273 28
32043da7 29#include "omapdss.h"
b2886273
TV		 30#include "dss.h"
31
b2886273
TV		 32/* Venc registers */
33#define VENC_REV_ID 0x00
34#define VENC_STATUS 0x04
35#define VENC_F_CONTROL 0x08
36#define VENC_VIDOUT_CTRL 0x10
37#define VENC_SYNC_CTRL 0x14
38#define VENC_LLEN 0x1C
39#define VENC_FLENS 0x20
40#define VENC_HFLTR_CTRL 0x24
41#define VENC_CC_CARR_WSS_CARR 0x28
42#define VENC_C_PHASE 0x2C
43#define VENC_GAIN_U 0x30
44#define VENC_GAIN_V 0x34
45#define VENC_GAIN_Y 0x38
46#define VENC_BLACK_LEVEL 0x3C
47#define VENC_BLANK_LEVEL 0x40
48#define VENC_X_COLOR 0x44
49#define VENC_M_CONTROL 0x48
50#define VENC_BSTAMP_WSS_DATA 0x4C
51#define VENC_S_CARR 0x50
52#define VENC_LINE21 0x54
53#define VENC_LN_SEL 0x58
54#define VENC_L21__WC_CTL 0x5C
55#define VENC_HTRIGGER_VTRIGGER 0x60
56#define VENC_SAVID__EAVID 0x64
57#define VENC_FLEN__FAL 0x68
58#define VENC_LAL__PHASE_RESET 0x6C
59#define VENC_HS_INT_START_STOP_X 0x70
60#define VENC_HS_EXT_START_STOP_X 0x74
61#define VENC_VS_INT_START_X 0x78
62#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
63#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
64#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
65#define VENC_VS_EXT_STOP_Y 0x88
66#define VENC_AVID_START_STOP_X 0x90
67#define VENC_AVID_START_STOP_Y 0x94
68#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
69#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
70#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
71#define VENC_TVDETGP_INT_START_STOP_X 0xB0
72#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
73#define VENC_GEN_CTRL 0xB8
74#define VENC_OUTPUT_CONTROL 0xC4
75#define VENC_OUTPUT_TEST 0xC8
76#define VENC_DAC_B__DAC_C 0xC8
77
78struct venc_config {
79 u32 f_control;
80 u32 vidout_ctrl;
81 u32 sync_ctrl;
82 u32 llen;
83 u32 flens;
84 u32 hfltr_ctrl;
85 u32 cc_carr_wss_carr;
86 u32 c_phase;
87 u32 gain_u;
88 u32 gain_v;
89 u32 gain_y;
90 u32 black_level;
91 u32 blank_level;
92 u32 x_color;
93 u32 m_control;
94 u32 bstamp_wss_data;
95 u32 s_carr;
96 u32 line21;
97 u32 ln_sel;
98 u32 l21__wc_ctl;
99 u32 htrigger_vtrigger;
100 u32 savid__eavid;
101 u32 flen__fal;
102 u32 lal__phase_reset;
103 u32 hs_int_start_stop_x;
104 u32 hs_ext_start_stop_x;
105 u32 vs_int_start_x;
106 u32 vs_int_stop_x__vs_int_start_y;
107 u32 vs_int_stop_y__vs_ext_start_x;
108 u32 vs_ext_stop_x__vs_ext_start_y;
109 u32 vs_ext_stop_y;
110 u32 avid_start_stop_x;
111 u32 avid_start_stop_y;
112 u32 fid_int_start_x__fid_int_start_y;
113 u32 fid_int_offset_y__fid_ext_start_x;
114 u32 fid_ext_start_y__fid_ext_offset_y;
115 u32 tvdetgp_int_start_stop_x;
116 u32 tvdetgp_int_start_stop_y;
117 u32 gen_ctrl;
118};
119
120/* from TRM */
121static const struct venc_config venc_config_pal_trm = {
122 .f_control = 0,
123 .vidout_ctrl = 1,
124 .sync_ctrl = 0x40,
125 .llen = 0x35F, /* 863 */
126 .flens = 0x270, /* 624 */
127 .hfltr_ctrl = 0,
128 .cc_carr_wss_carr = 0x2F7225ED,
129 .c_phase = 0,
130 .gain_u = 0x111,
131 .gain_v = 0x181,
132 .gain_y = 0x140,
133 .black_level = 0x3B,
134 .blank_level = 0x3B,
135 .x_color = 0x7,
136 .m_control = 0x2,
137 .bstamp_wss_data = 0x3F,
138 .s_carr = 0x2A098ACB,
139 .line21 = 0,
140 .ln_sel = 0x01290015,
141 .l21__wc_ctl = 0x0000F603,
142 .htrigger_vtrigger = 0,
143
144 .savid__eavid = 0x06A70108,
145 .flen__fal = 0x00180270,
146 .lal__phase_reset = 0x00040135,
147 .hs_int_start_stop_x = 0x00880358,
148 .hs_ext_start_stop_x = 0x000F035F,
149 .vs_int_start_x = 0x01A70000,
150 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
151 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
152 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
153 .vs_ext_stop_y = 0x00000025,
154 .avid_start_stop_x = 0x03530083,
155 .avid_start_stop_y = 0x026C002E,
156 .fid_int_start_x__fid_int_start_y = 0x0001008A,
157 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
158 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
159
160 .tvdetgp_int_start_stop_x = 0x00140001,
161 .tvdetgp_int_start_stop_y = 0x00010001,
162 .gen_ctrl = 0x00FF0000,
163};
164
165/* from TRM */
166static const struct venc_config venc_config_ntsc_trm = {
167 .f_control = 0,
168 .vidout_ctrl = 1,
169 .sync_ctrl = 0x8040,
170 .llen = 0x359,
171 .flens = 0x20C,
172 .hfltr_ctrl = 0,
173 .cc_carr_wss_carr = 0x043F2631,
174 .c_phase = 0,
175 .gain_u = 0x102,
176 .gain_v = 0x16C,
177 .gain_y = 0x12F,
178 .black_level = 0x43,
179 .blank_level = 0x38,
180 .x_color = 0x7,
181 .m_control = 0x1,
182 .bstamp_wss_data = 0x38,
183 .s_carr = 0x21F07C1F,
184 .line21 = 0,
185 .ln_sel = 0x01310011,
186 .l21__wc_ctl = 0x0000F003,
187 .htrigger_vtrigger = 0,
188
189 .savid__eavid = 0x069300F4,
190 .flen__fal = 0x0016020C,
191 .lal__phase_reset = 0x00060107,
192 .hs_int_start_stop_x = 0x008E0350,
193 .hs_ext_start_stop_x = 0x000F0359,
194 .vs_int_start_x = 0x01A00000,
195 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
196 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
197 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
198 .vs_ext_stop_y = 0x00000006,
199 .avid_start_stop_x = 0x03480078,
200 .avid_start_stop_y = 0x02060024,
201 .fid_int_start_x__fid_int_start_y = 0x0001008A,
202 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
203 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
204
205 .tvdetgp_int_start_stop_x = 0x00140001,
206 .tvdetgp_int_start_stop_y = 0x00010001,
207 .gen_ctrl = 0x00F90000,
208};
209
210static const struct venc_config venc_config_pal_bdghi = {
211 .f_control = 0,
212 .vidout_ctrl = 0,
213 .sync_ctrl = 0,
214 .hfltr_ctrl = 0,
215 .x_color = 0,
216 .line21 = 0,
217 .ln_sel = 21,
218 .htrigger_vtrigger = 0,
219 .tvdetgp_int_start_stop_x = 0x00140001,
220 .tvdetgp_int_start_stop_y = 0x00010001,
221 .gen_ctrl = 0x00FB0000,
222
223 .llen = 864-1,
224 .flens = 625-1,
225 .cc_carr_wss_carr = 0x2F7625ED,
226 .c_phase = 0xDF,
227 .gain_u = 0x111,
228 .gain_v = 0x181,
229 .gain_y = 0x140,
230 .black_level = 0x3e,
231 .blank_level = 0x3e,
232 .m_control = 0<<2 | 1<<1,
233 .bstamp_wss_data = 0x42,
234 .s_carr = 0x2a098acb,
235 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
236 .savid__eavid = 0x06A70108,
237 .flen__fal = 23<<16 | 624<<0,
238 .lal__phase_reset = 2<<17 | 310<<0,
239 .hs_int_start_stop_x = 0x00920358,
240 .hs_ext_start_stop_x = 0x000F035F,
241 .vs_int_start_x = 0x1a7<<16,
242 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
243 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
244 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
245 .vs_ext_stop_y = 0x05,
246 .avid_start_stop_x = 0x03530082,
247 .avid_start_stop_y = 0x0270002E,
248 .fid_int_start_x__fid_int_start_y = 0x0005008A,
249 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
250 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
251};
252
beea6214
TV		 253enum venc_videomode {
254 VENC_MODE_UNKNOWN,
255 VENC_MODE_PAL,
256 VENC_MODE_NTSC,
257};
258
b08644a2
LP		 259static const struct drm_display_mode omap_dss_pal_mode = {
260 .hdisplay = 720,
261 .hsync_start = 732,
262 .hsync_end = 796,
263 .htotal = 864,
264 .vdisplay = 574,
265 .vsync_start = 579,
266 .vsync_end = 584,
267 .vtotal = 625,
268 .clock = 13500,
269
270 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
271 DRM_MODE_FLAG_NVSYNC,
b2886273 272};
b2886273 273
b08644a2
LP		 274static const struct drm_display_mode omap_dss_ntsc_mode = {
275 .hdisplay = 720,
276 .hsync_start = 736,
277 .hsync_end = 800,
278 .htotal = 858,
279 .vdisplay = 482,
280 .vsync_start = 488,
281 .vsync_end = 494,
282 .vtotal = 525,
283 .clock = 13500,
284
285 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
286 DRM_MODE_FLAG_NVSYNC,
b2886273 287};
b2886273 288
663ac57b 289struct venc_device {
30ea50c9 290 struct platform_device *pdev;
b2886273
TV		 291 void __iomem *base;
292 struct mutex venc_lock;
b2886273 293 struct regulator *vdda_dac_reg;
1ef904e1 294 struct dss_device *dss;
4fbafaf3 295
f33656e1
LP		 296 struct dss_debugfs_entry *debugfs;
297
4fbafaf3 298 struct clk *tv_dac_clk;
a5abf472 299
d60dfaba 300 const struct venc_config *config;
febe2905 301 enum omap_dss_venc_type type;
89e71956 302 bool invert_polarity;
34dfb85f 303 bool requires_tv_dac_clk;
81b87f51 304
1f68d9c4 305 struct omap_dss_device output;
663ac57b
LP		 306};
307
308#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
b2886273 309
663ac57b 310static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
b2886273 311{
663ac57b 312 __raw_writel(val, venc->base + idx);
b2886273
TV		 313}
314
663ac57b 315static inline u32 venc_read_reg(struct venc_device *venc, int idx)
b2886273 316{
663ac57b 317 u32 l = __raw_readl(venc->base + idx);
b2886273
TV		 318 return l;
319}
320
663ac57b
LP		 321static void venc_write_config(struct venc_device *venc,
322 const struct venc_config *config)
b2886273
TV		 323{
324 DSSDBG("write venc conf\n");
325
663ac57b
LP		 326 venc_write_reg(venc, VENC_LLEN, config->llen);
327 venc_write_reg(venc, VENC_FLENS, config->flens);
328 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
329 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
330 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
331 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
332 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
333 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
334 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
335 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
d79bd6b4 336 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
663ac57b
LP		 337 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
338 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
339 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
340 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
341 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
342 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
343 config->hs_int_start_stop_x);
344 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
345 config->hs_ext_start_stop_x);
346 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
347 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
b2886273 348 config->vs_int_stop_x__vs_int_start_y);
663ac57b 349 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
b2886273 350 config->vs_int_stop_y__vs_ext_start_x);
663ac57b 351 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
b2886273 352 config->vs_ext_stop_x__vs_ext_start_y);
663ac57b
LP		 353 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
354 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
355 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
356 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
b2886273 357 config->fid_int_start_x__fid_int_start_y);
663ac57b 358 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
b2886273 359 config->fid_int_offset_y__fid_ext_start_x);
663ac57b 360 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
b2886273
TV		 361 config->fid_ext_start_y__fid_ext_offset_y);
362
663ac57b
LP		 363 venc_write_reg(venc, VENC_DAC_B__DAC_C,
364 venc_read_reg(venc, VENC_DAC_B__DAC_C));
365 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
366 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
367 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
368 venc_write_reg(venc, VENC_LINE21, config->line21);
369 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
370 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
371 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
b2886273 372 config->tvdetgp_int_start_stop_x);
663ac57b 373 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
b2886273 374 config->tvdetgp_int_start_stop_y);
663ac57b
LP		 375 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
376 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
377 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
b2886273
TV		 378}
379
663ac57b 380static void venc_reset(struct venc_device *venc)
b2886273
TV		 381{
382 int t = 1000;
383
663ac57b
LP		 384 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
385 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
b2886273
TV		 386 if (--t == 0) {
387 DSSERR("Failed to reset venc\n");
388 return;
389 }
390 }
391
c6f65e1a 392#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
b2886273 393 /* the magical sleep that makes things work */
c6f65e1a 394 /* XXX more info? What bug this circumvents? */
b2886273 395 msleep(20);
c6f65e1a 396#endif
b2886273
TV		 397}
398
663ac57b 399static int venc_runtime_get(struct venc_device *venc)
b2886273 400{
4fbafaf3
TV		 401 int r;
402
403 DSSDBG("venc_runtime_get\n");
404
663ac57b 405 r = pm_runtime_get_sync(&venc->pdev->dev);
4fbafaf3
TV		 406 WARN_ON(r < 0);
407 return r < 0 ? r : 0;
408}
409
663ac57b 410static void venc_runtime_put(struct venc_device *venc)
4fbafaf3
TV		 411{
412 int r;
413
414 DSSDBG("venc_runtime_put\n");
415
663ac57b 416 r = pm_runtime_put_sync(&venc->pdev->dev);
5be3aebd 417 WARN_ON(r < 0 && r != -ENOSYS);
b2886273
TV		 418}
419
663ac57b 420static int venc_power_on(struct venc_device *venc)
37ac60e4
TV		 421{
422 u32 l;
33ca237f 423 int r;
37ac60e4 424
663ac57b 425 r = venc_runtime_get(venc);
156fd99e
AT		 426 if (r)
427 goto err0;
428
663ac57b 429 venc_reset(venc);
d60dfaba 430 venc_write_config(venc, venc->config);
37ac60e4 431
663ac57b
LP		 432 dss_set_venc_output(venc->dss, venc->type);
433 dss_set_dac_pwrdn_bgz(venc->dss, 1);
37ac60e4
TV		 434
435 l = 0;
436
663ac57b 437 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
37ac60e4
TV		 438 l |= 1 << 1;
439 else /* S-Video */
440 l |= (1 << 0) | (1 << 2);
441
663ac57b 442 if (venc->invert_polarity == false)
37ac60e4
TV		 443 l |= 1 << 3;
444
663ac57b 445 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
37ac60e4 446
663ac57b 447 r = regulator_enable(venc->vdda_dac_reg);
ec874107 448 if (r)
156fd99e 449 goto err1;
37ac60e4 450
663ac57b 451 r = dss_mgr_enable(&venc->output);
33ca237f 452 if (r)
156fd99e 453 goto err2;
33ca237f
TV		 454
455 return 0;
456
156fd99e 457err2:
663ac57b 458 regulator_disable(venc->vdda_dac_reg);
156fd99e 459err1:
663ac57b
LP		 460 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
461 dss_set_dac_pwrdn_bgz(venc->dss, 0);
33ca237f 462
663ac57b 463 venc_runtime_put(venc);
156fd99e 464err0:
33ca237f 465 return r;
37ac60e4
TV		 466}
467
663ac57b 468static void venc_power_off(struct venc_device *venc)
37ac60e4 469{
663ac57b
LP		 470 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
471 dss_set_dac_pwrdn_bgz(venc->dss, 0);
37ac60e4 472
663ac57b 473 dss_mgr_disable(&venc->output);
37ac60e4 474
663ac57b 475 regulator_disable(venc->vdda_dac_reg);
156fd99e 476
663ac57b 477 venc_runtime_put(venc);
37ac60e4
TV		 478}
479
19b4200d 480static void venc_display_enable(struct omap_dss_device *dssdev)
0aca3c63 481{
663ac57b 482 struct venc_device *venc = dssdev_to_venc(dssdev);
0aca3c63 483
156fd99e 484 DSSDBG("venc_display_enable\n");
0aca3c63 485
663ac57b 486 mutex_lock(&venc->venc_lock);
0aca3c63 487
19b4200d 488 venc_power_on(venc);
156fd99e 489
663ac57b 490 mutex_unlock(&venc->venc_lock);
b2886273
TV		 491}
492
09d2e7cd 493static void venc_display_disable(struct omap_dss_device *dssdev)
b2886273 494{
663ac57b
LP		 495 struct venc_device *venc = dssdev_to_venc(dssdev);
496
156fd99e 497 DSSDBG("venc_display_disable\n");
b2886273 498
663ac57b 499 mutex_lock(&venc->venc_lock);
37ac60e4 500
663ac57b 501 venc_power_off(venc);
37ac60e4 502
663ac57b 503 mutex_unlock(&venc->venc_lock);
b2886273
TV		 504}
505
870e19d5
LP		 506static int venc_get_modes(struct omap_dss_device *dssdev,
507 struct drm_connector *connector)
35d944cb 508{
b08644a2
LP		 509 static const struct drm_display_mode *modes[] = {
510 &omap_dss_pal_mode,
511 &omap_dss_ntsc_mode,
40e5f937
LP		 512 };
513 unsigned int i;
35d944cb 514
40e5f937
LP		 515 for (i = 0; i < ARRAY_SIZE(modes); ++i) {
516 struct drm_display_mode *mode;
870e19d5 517
b08644a2 518 mode = drm_mode_duplicate(connector->dev, modes[i]);
40e5f937
LP		 519 if (!mode)
520 return i;
521
40e5f937
LP		 522 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
523 drm_mode_set_name(mode);
524 drm_mode_probed_add(connector, mode);
525 }
526
527 return ARRAY_SIZE(modes);
35d944cb
LP		 528}
529
41322aa6 530static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode)
d60dfaba 531{
41322aa6 532 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
d60dfaba
LP		 533 return VENC_MODE_UNKNOWN;
534
b08644a2
LP		 535 if (mode->clock == omap_dss_pal_mode.clock &&
536 mode->hdisplay == omap_dss_pal_mode.hdisplay &&
537 mode->vdisplay == omap_dss_pal_mode.vdisplay)
d60dfaba
LP		 538 return VENC_MODE_PAL;
539
b08644a2
LP		 540 if (mode->clock == omap_dss_ntsc_mode.clock &&
541 mode->hdisplay == omap_dss_ntsc_mode.hdisplay &&
542 mode->vdisplay == omap_dss_ntsc_mode.vdisplay)
d60dfaba
LP		 543 return VENC_MODE_NTSC;
544
545 return VENC_MODE_UNKNOWN;
546}
547
09d2e7cd 548static void venc_set_timings(struct omap_dss_device *dssdev,
41322aa6 549 const struct drm_display_mode *mode)
69b2048f 550{
663ac57b 551 struct venc_device *venc = dssdev_to_venc(dssdev);
41322aa6 552 enum venc_videomode venc_mode = venc_get_videomode(mode);
beea6214 553
69b2048f
TV		 554 DSSDBG("venc_set_timings\n");
555
663ac57b 556 mutex_lock(&venc->venc_lock);
156fd99e 557
d60dfaba
LP		 558 switch (venc_mode) {
559 default:
560 WARN_ON_ONCE(1);
561 /* Fall-through */
562 case VENC_MODE_PAL:
563 venc->config = &venc_config_pal_trm;
564 break;
565
566 case VENC_MODE_NTSC:
567 venc->config = &venc_config_ntsc_trm;
568 break;
569 }
156fd99e 570
663ac57b 571 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
5391e87d 572
663ac57b 573 mutex_unlock(&venc->venc_lock);
69b2048f
TV		 574}
575
09d2e7cd 576static int venc_check_timings(struct omap_dss_device *dssdev,
41322aa6 577 struct drm_display_mode *mode)
69b2048f
TV		 578{
579 DSSDBG("venc_check_timings\n");
580
41322aa6 581 switch (venc_get_videomode(mode)) {
beea6214 582 case VENC_MODE_PAL:
b08644a2
LP		 583 drm_mode_copy(mode, &omap_dss_pal_mode);
584 break;
a730ce99 585
beea6214 586 case VENC_MODE_NTSC:
b08644a2
LP		 587 drm_mode_copy(mode, &omap_dss_ntsc_mode);
588 break;
a730ce99 589
beea6214
TV		 590 default:
591 return -EINVAL;
592 }
b08644a2
LP		 593
594 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
595 drm_mode_set_name(mode);
596 return 0;
69b2048f
TV		 597}
598
f33656e1 599static int venc_dump_regs(struct seq_file *s, void *p)
b2886273 600{
663ac57b
LP		 601 struct venc_device *venc = s->private;
602
603#define DUMPREG(venc, r) \
604 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
b2886273 605
663ac57b 606 if (venc_runtime_get(venc))
f33656e1 607 return 0;
b2886273 608
663ac57b
LP		 609 DUMPREG(venc, VENC_F_CONTROL);
610 DUMPREG(venc, VENC_VIDOUT_CTRL);
611 DUMPREG(venc, VENC_SYNC_CTRL);
612 DUMPREG(venc, VENC_LLEN);
613 DUMPREG(venc, VENC_FLENS);
614 DUMPREG(venc, VENC_HFLTR_CTRL);
615 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
616 DUMPREG(venc, VENC_C_PHASE);
617 DUMPREG(venc, VENC_GAIN_U);
618 DUMPREG(venc, VENC_GAIN_V);
619 DUMPREG(venc, VENC_GAIN_Y);
620 DUMPREG(venc, VENC_BLACK_LEVEL);
621 DUMPREG(venc, VENC_BLANK_LEVEL);
622 DUMPREG(venc, VENC_X_COLOR);
623 DUMPREG(venc, VENC_M_CONTROL);
624 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
625 DUMPREG(venc, VENC_S_CARR);
626 DUMPREG(venc, VENC_LINE21);
627 DUMPREG(venc, VENC_LN_SEL);
628 DUMPREG(venc, VENC_L21__WC_CTL);
629 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
630 DUMPREG(venc, VENC_SAVID__EAVID);
631 DUMPREG(venc, VENC_FLEN__FAL);
632 DUMPREG(venc, VENC_LAL__PHASE_RESET);
633 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
634 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
635 DUMPREG(venc, VENC_VS_INT_START_X);
636 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
637 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
638 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
639 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
640 DUMPREG(venc, VENC_AVID_START_STOP_X);
641 DUMPREG(venc, VENC_AVID_START_STOP_Y);
642 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
643 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
644 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
645 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
646 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
647 DUMPREG(venc, VENC_GEN_CTRL);
648 DUMPREG(venc, VENC_OUTPUT_CONTROL);
649 DUMPREG(venc, VENC_OUTPUT_TEST);
650
651 venc_runtime_put(venc);
b2886273
TV		 652
653#undef DUMPREG
f33656e1 654 return 0;
b2886273 655}
30ea50c9 656
663ac57b 657static int venc_get_clocks(struct venc_device *venc)
4fbafaf3
TV		 658{
659 struct clk *clk;
660
663ac57b
LP		 661 if (venc->requires_tv_dac_clk) {
662 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
4fbafaf3
TV		 663 if (IS_ERR(clk)) {
664 DSSERR("can't get tv_dac_clk\n");
4fbafaf3
TV		 665 return PTR_ERR(clk);
666 }
667 } else {
668 clk = NULL;
669 }
670
663ac57b 671 venc->tv_dac_clk = clk;
4fbafaf3
TV		 672
673 return 0;
674}
675
511afb44
LP		 676static int venc_connect(struct omap_dss_device *src,
677 struct omap_dss_device *dst)
fb8efa49 678{
f8a8eabb 679 return omapdss_device_connect(dst->dss, dst, dst->next);
fb8efa49
TV		 680}
681
511afb44
LP		 682static void venc_disconnect(struct omap_dss_device *src,
683 struct omap_dss_device *dst)
fb8efa49 684{
511afb44 685 omapdss_device_disconnect(dst, dst->next);
fb8efa49
TV		 686}
687
b93109d7 688static const struct omap_dss_device_ops venc_ops = {
fb8efa49
TV		 689 .connect = venc_connect,
690 .disconnect = venc_disconnect,
691
09d2e7cd
TV		 692 .enable = venc_display_enable,
693 .disable = venc_display_disable,
fb8efa49 694
09d2e7cd
TV		 695 .check_timings = venc_check_timings,
696 .set_timings = venc_set_timings,
870e19d5
LP		 697
698 .get_modes = venc_get_modes,
fb8efa49
TV		 699};
700
c8719326
LP		 701/* -----------------------------------------------------------------------------
702 * Component Bind & Unbind
703 */
704
705static int venc_bind(struct device *dev, struct device *master, void *data)
706{
707 struct dss_device *dss = dss_get_device(master);
708 struct venc_device *venc = dev_get_drvdata(dev);
709 u8 rev_id;
710 int r;
711
712 venc->dss = dss;
713
714 r = venc_runtime_get(venc);
715 if (r)
716 return r;
717
718 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
719 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
720
721 venc_runtime_put(venc);
722
723 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
724 venc);
725
726 return 0;
727}
728
729static void venc_unbind(struct device *dev, struct device *master, void *data)
730{
731 struct venc_device *venc = dev_get_drvdata(dev);
732
733 dss_debugfs_remove_file(venc->debugfs);
734}
735
736static const struct component_ops venc_component_ops = {
737 .bind = venc_bind,
738 .unbind = venc_unbind,
739};
740
741/* -----------------------------------------------------------------------------
742 * Probe & Remove, Suspend & Resume
743 */
744
27d62452 745static int venc_init_output(struct venc_device *venc)
81b87f51 746{
663ac57b 747 struct omap_dss_device *out = &venc->output;
71316556 748 int r;
81b87f51 749
663ac57b 750 out->dev = &venc->pdev->dev;
81b87f51 751 out->id = OMAP_DSS_OUTPUT_VENC;
0dbfc396 752 out->type = OMAP_DISPLAY_TYPE_VENC;
7286a08f 753 out->name = "venc.0";
2eea5ae6 754 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
b93109d7 755 out->ops = &venc_ops;
b7328e14 756 out->owner = THIS_MODULE;
4e20bda6 757 out->of_ports = BIT(0);
46b3847d 758 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
81b87f51 759
d17eb453
LP		 760 r = omapdss_device_init_output(out);
761 if (r < 0)
71316556 762 return r;
71316556 763
de57e9db 764 omapdss_device_register(out);
27d62452
LP		 765
766 return 0;
81b87f51
AT		 767}
768
663ac57b 769static void venc_uninit_output(struct venc_device *venc)
81b87f51 770{
de57e9db 771 omapdss_device_unregister(&venc->output);
d17eb453 772 omapdss_device_cleanup_output(&venc->output);
81b87f51
AT		 773}
774
663ac57b 775static int venc_probe_of(struct venc_device *venc)
a2207021 776{
663ac57b 777 struct device_node *node = venc->pdev->dev.of_node;
a2207021
TV		 778 struct device_node *ep;
779 u32 channels;
780 int r;
781
09bffa6e 782 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
a2207021
TV		 783 if (!ep)
784 return 0;
785
663ac57b 786 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
a2207021
TV		 787
788 r = of_property_read_u32(ep, "ti,channels", &channels);
789 if (r) {
663ac57b 790 dev_err(&venc->pdev->dev,
a2207021
TV		 791 "failed to read property 'ti,channels': %d\n", r);
792 goto err;
793 }
794
795 switch (channels) {
796 case 1:
663ac57b 797 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
a2207021
TV		 798 break;
799 case 2:
663ac57b 800 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
a2207021
TV		 801 break;
802 default:
663ac57b
LP		 803 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
804 channels);
a2207021
TV		 805 r = -EINVAL;
806 goto err;
807 }
808
809 of_node_put(ep);
810
811 return 0;
18cbe723 812
a2207021
TV		 813err:
814 of_node_put(ep);
18cbe723 815 return r;
a2207021
TV		 816}
817
34dfb85f
LP		 818static const struct soc_device_attribute venc_soc_devices[] = {
819 { .machine = "OMAP3[45]*" },
820 { .machine = "AM35*" },
821 { /* sentinel */ }
822};
823
c8719326 824static int venc_probe(struct platform_device *pdev)
30ea50c9 825{
663ac57b 826 struct venc_device *venc;
ea9da36a 827 struct resource *venc_mem;
38f3daf6 828 int r;
ea9da36a 829
663ac57b
LP		 830 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
831 if (!venc)
832 return -ENOMEM;
833
834 venc->pdev = pdev;
c8719326
LP		 835
836 platform_set_drvdata(pdev, venc);
30ea50c9 837
34dfb85f
LP		 838 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
839 if (soc_device_match(venc_soc_devices))
663ac57b 840 venc->requires_tv_dac_clk = true;
34dfb85f 841
663ac57b 842 mutex_init(&venc->venc_lock);
30ea50c9 843
d60dfaba 844 venc->config = &venc_config_pal_trm;
30ea50c9 845
663ac57b
LP		 846 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
847 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
848 if (IS_ERR(venc->base)) {
849 r = PTR_ERR(venc->base);
850 goto err_free;
851 }
30ea50c9 852
8a36357a
LP		 853 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
854 if (IS_ERR(venc->vdda_dac_reg)) {
855 r = PTR_ERR(venc->vdda_dac_reg);
856 if (r != -EPROBE_DEFER)
857 DSSERR("can't get VDDA_DAC regulator\n");
858 goto err_free;
859 }
860
663ac57b 861 r = venc_get_clocks(venc);
4fbafaf3 862 if (r)
663ac57b 863 goto err_free;
4fbafaf3 864
663ac57b 865 r = venc_probe_of(venc);
c8719326
LP		 866 if (r)
867 goto err_free;
a2207021 868
c8719326 869 pm_runtime_enable(&pdev->dev);
e40402cf 870
27d62452
LP		 871 r = venc_init_output(venc);
872 if (r)
873 goto err_pm_disable;
81b87f51 874
c8719326
LP		 875 r = component_add(&pdev->dev, &venc_component_ops);
876 if (r)
877 goto err_uninit_output;
878
cd3b3449 879 return 0;
4fbafaf3 880
c8719326
LP		 881err_uninit_output:
882 venc_uninit_output(venc);
27d62452 883err_pm_disable:
4fbafaf3 884 pm_runtime_disable(&pdev->dev);
663ac57b
LP		 885err_free:
886 kfree(venc);
4fbafaf3 887 return r;
30ea50c9
SG		 888}
889
c8719326 890static int venc_remove(struct platform_device *pdev)
30ea50c9 891{
c8719326 892 struct venc_device *venc = platform_get_drvdata(pdev);
736e60dd 893
c8719326 894 component_del(&pdev->dev, &venc_component_ops);
f33656e1 895
663ac57b 896 venc_uninit_output(venc);
81b87f51 897
c8719326 898 pm_runtime_disable(&pdev->dev);
663ac57b
LP		 899
900 kfree(venc);
30ea50c9
SG		 901 return 0;
902}
903
4fbafaf3
TV		 904static int venc_runtime_suspend(struct device *dev)
905{
663ac57b
LP		 906 struct venc_device *venc = dev_get_drvdata(dev);
907
908 if (venc->tv_dac_clk)
909 clk_disable_unprepare(venc->tv_dac_clk);
4fbafaf3 910
4fbafaf3
TV		 911 return 0;
912}
913
914static int venc_runtime_resume(struct device *dev)
915{
663ac57b 916 struct venc_device *venc = dev_get_drvdata(dev);
4fbafaf3 917
663ac57b
LP		 918 if (venc->tv_dac_clk)
919 clk_prepare_enable(venc->tv_dac_clk);
4fbafaf3
TV		 920
921 return 0;
4fbafaf3
TV		 922}
923
924static const struct dev_pm_ops venc_pm_ops = {
925 .runtime_suspend = venc_runtime_suspend,
926 .runtime_resume = venc_runtime_resume,
927};
928
a2207021
TV		 929static const struct of_device_id venc_of_match[] = {
930 { .compatible = "ti,omap2-venc", },
931 { .compatible = "ti,omap3-venc", },
932 { .compatible = "ti,omap4-venc", },
933 {},
934};
935
d66c36a3 936struct platform_driver omap_venchw_driver = {
736e60dd
TV		 937 .probe = venc_probe,
938 .remove = venc_remove,
30ea50c9
SG		 939 .driver = {
940 .name = "omapdss_venc",
4fbafaf3 941 .pm = &venc_pm_ops,
a2207021 942 .of_match_table = venc_of_match,
422ccbd5 943 .suppress_bind_attrs = true,
30ea50c9
SG		 944 },
945};
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