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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f5f9454c | 2 | /* |
bb5cdf8d | 3 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
f5f9454c | 4 | * Author: Rob Clark <rob.clark@linaro.org> |
f5f9454c RC |
5 | */ |
6 | ||
7 | #include "omap_drv.h" | |
8 | ||
80f91bff LP |
9 | struct omap_irq_wait { |
10 | struct list_head node; | |
84e1d457 | 11 | wait_queue_head_t wq; |
dfe9cfcc | 12 | u32 irqmask; |
80f91bff LP |
13 | int count; |
14 | }; | |
15 | ||
84e1d457 | 16 | /* call with wait_lock and dispc runtime held */ |
f5f9454c RC |
17 | static void omap_irq_update(struct drm_device *dev) |
18 | { | |
19 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 20 | struct omap_irq_wait *wait; |
dfe9cfcc | 21 | u32 irqmask = priv->irq_mask; |
f5f9454c | 22 | |
84e1d457 | 23 | assert_spin_locked(&priv->wait_lock); |
f5f9454c | 24 | |
80f91bff LP |
25 | list_for_each_entry(wait, &priv->wait_list, node) |
26 | irqmask |= wait->irqmask; | |
f5f9454c RC |
27 | |
28 | DBG("irqmask=%08x", irqmask); | |
29 | ||
50638ae5 | 30 | priv->dispc_ops->write_irqenable(priv->dispc, irqmask); |
f5f9454c RC |
31 | } |
32 | ||
80f91bff | 33 | static void omap_irq_wait_handler(struct omap_irq_wait *wait) |
f5f9454c | 34 | { |
f5f9454c | 35 | wait->count--; |
84e1d457 | 36 | wake_up(&wait->wq); |
f5f9454c RC |
37 | } |
38 | ||
39 | struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, | |
dfe9cfcc | 40 | u32 irqmask, int count) |
f5f9454c | 41 | { |
80f91bff | 42 | struct omap_drm_private *priv = dev->dev_private; |
f5f9454c | 43 | struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); |
80f91bff LP |
44 | unsigned long flags; |
45 | ||
84e1d457 | 46 | init_waitqueue_head(&wait->wq); |
80f91bff | 47 | wait->irqmask = irqmask; |
f5f9454c | 48 | wait->count = count; |
80f91bff | 49 | |
84e1d457 | 50 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
51 | list_add(&wait->node, &priv->wait_list); |
52 | omap_irq_update(dev); | |
84e1d457 | 53 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 54 | |
f5f9454c RC |
55 | return wait; |
56 | } | |
57 | ||
58 | int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |
59 | unsigned long timeout) | |
60 | { | |
84e1d457 | 61 | struct omap_drm_private *priv = dev->dev_private; |
80f91bff | 62 | unsigned long flags; |
84e1d457 LP |
63 | int ret; |
64 | ||
65 | ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout); | |
80f91bff | 66 | |
84e1d457 | 67 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
68 | list_del(&wait->node); |
69 | omap_irq_update(dev); | |
84e1d457 | 70 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 71 | |
f5f9454c | 72 | kfree(wait); |
80f91bff LP |
73 | |
74 | return ret == 0 ? -1 : 0; | |
f5f9454c RC |
75 | } |
76 | ||
77 | /** | |
78 | * enable_vblank - enable vblank interrupt events | |
79 | * @dev: DRM device | |
88e72717 | 80 | * @pipe: which irq to enable |
f5f9454c RC |
81 | * |
82 | * Enable vblank interrupts for @crtc. If the device doesn't have | |
83 | * a hardware vblank counter, this routine should be a no-op, since | |
84 | * interrupts will have to stay on to keep the count accurate. | |
85 | * | |
86 | * RETURNS | |
87 | * Zero on success, appropriate errno if the given @crtc's vblank | |
88 | * interrupt cannot be enabled. | |
89 | */ | |
0396162a | 90 | int omap_irq_enable_vblank(struct drm_crtc *crtc) |
f5f9454c | 91 | { |
0396162a | 92 | struct drm_device *dev = crtc->dev; |
f5f9454c RC |
93 | struct omap_drm_private *priv = dev->dev_private; |
94 | unsigned long flags; | |
0396162a | 95 | enum omap_channel channel = omap_crtc_channel(crtc); |
f5f9454c | 96 | |
0396162a | 97 | DBG("dev=%p, crtc=%u", dev, channel); |
f5f9454c | 98 | |
84e1d457 | 99 | spin_lock_irqsave(&priv->wait_lock, flags); |
50638ae5 LP |
100 | priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, |
101 | channel); | |
f5f9454c | 102 | omap_irq_update(dev); |
84e1d457 | 103 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
108 | /** | |
109 | * disable_vblank - disable vblank interrupt events | |
110 | * @dev: DRM device | |
88e72717 | 111 | * @pipe: which irq to enable |
f5f9454c RC |
112 | * |
113 | * Disable vblank interrupts for @crtc. If the device doesn't have | |
114 | * a hardware vblank counter, this routine should be a no-op, since | |
115 | * interrupts will have to stay on to keep the count accurate. | |
116 | */ | |
0396162a | 117 | void omap_irq_disable_vblank(struct drm_crtc *crtc) |
f5f9454c | 118 | { |
0396162a | 119 | struct drm_device *dev = crtc->dev; |
f5f9454c RC |
120 | struct omap_drm_private *priv = dev->dev_private; |
121 | unsigned long flags; | |
0396162a | 122 | enum omap_channel channel = omap_crtc_channel(crtc); |
f5f9454c | 123 | |
0396162a | 124 | DBG("dev=%p, crtc=%u", dev, channel); |
f5f9454c | 125 | |
84e1d457 | 126 | spin_lock_irqsave(&priv->wait_lock, flags); |
50638ae5 LP |
127 | priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, |
128 | channel); | |
f5f9454c | 129 | omap_irq_update(dev); |
84e1d457 | 130 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
131 | } |
132 | ||
728ae8dd LP |
133 | static void omap_irq_fifo_underflow(struct omap_drm_private *priv, |
134 | u32 irqstatus) | |
135 | { | |
136 | static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, | |
137 | DEFAULT_RATELIMIT_BURST); | |
138 | static const struct { | |
139 | const char *name; | |
140 | u32 mask; | |
141 | } sources[] = { | |
142 | { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, | |
143 | { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, | |
144 | { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, | |
145 | { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, | |
146 | }; | |
147 | ||
148 | const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | |
149 | | DISPC_IRQ_VID1_FIFO_UNDERFLOW | |
150 | | DISPC_IRQ_VID2_FIFO_UNDERFLOW | |
151 | | DISPC_IRQ_VID3_FIFO_UNDERFLOW; | |
152 | unsigned int i; | |
153 | ||
84e1d457 | 154 | spin_lock(&priv->wait_lock); |
728ae8dd | 155 | irqstatus &= priv->irq_mask & mask; |
84e1d457 | 156 | spin_unlock(&priv->wait_lock); |
728ae8dd LP |
157 | |
158 | if (!irqstatus) | |
159 | return; | |
160 | ||
161 | if (!__ratelimit(&_rs)) | |
162 | return; | |
163 | ||
164 | DRM_ERROR("FIFO underflow on "); | |
165 | ||
166 | for (i = 0; i < ARRAY_SIZE(sources); ++i) { | |
167 | if (sources[i].mask & irqstatus) | |
168 | pr_cont("%s ", sources[i].name); | |
169 | } | |
170 | ||
171 | pr_cont("(0x%08x)\n", irqstatus); | |
172 | } | |
173 | ||
dc50be89 TV |
174 | static void omap_irq_ocp_error_handler(struct drm_device *dev, |
175 | u32 irqstatus) | |
6b5538d4 LP |
176 | { |
177 | if (!(irqstatus & DISPC_IRQ_OCP_ERR)) | |
178 | return; | |
179 | ||
dc50be89 | 180 | dev_err_ratelimited(dev->dev, "OCP error\n"); |
6b5538d4 LP |
181 | } |
182 | ||
f13ab005 | 183 | static irqreturn_t omap_irq_handler(int irq, void *arg) |
f5f9454c RC |
184 | { |
185 | struct drm_device *dev = (struct drm_device *) arg; | |
186 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 187 | struct omap_irq_wait *wait, *n; |
f5f9454c RC |
188 | unsigned long flags; |
189 | unsigned int id; | |
190 | u32 irqstatus; | |
191 | ||
50638ae5 LP |
192 | irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); |
193 | priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); | |
194 | priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ | |
f5f9454c RC |
195 | |
196 | VERB("irqs: %08x", irqstatus); | |
197 | ||
2ee76792 LP |
198 | for (id = 0; id < priv->num_pipes; id++) { |
199 | struct drm_crtc *crtc = priv->pipes[id].crtc; | |
e0519af7 | 200 | enum omap_channel channel = omap_crtc_channel(crtc); |
0d8f371f | 201 | |
50638ae5 | 202 | if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { |
f5f9454c | 203 | drm_handle_vblank(dev, id); |
14389a37 LP |
204 | omap_crtc_vblank_irq(crtc); |
205 | } | |
e0519af7 | 206 | |
50638ae5 | 207 | if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) |
e0519af7 | 208 | omap_crtc_error_irq(crtc, irqstatus); |
0d8f371f | 209 | } |
f5f9454c | 210 | |
dc50be89 | 211 | omap_irq_ocp_error_handler(dev, irqstatus); |
728ae8dd LP |
212 | omap_irq_fifo_underflow(priv, irqstatus); |
213 | ||
84e1d457 | 214 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
215 | list_for_each_entry_safe(wait, n, &priv->wait_list, node) { |
216 | if (wait->irqmask & irqstatus) | |
217 | omap_irq_wait_handler(wait); | |
f5f9454c | 218 | } |
84e1d457 | 219 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
220 | |
221 | return IRQ_HANDLED; | |
222 | } | |
223 | ||
728ae8dd LP |
224 | static const u32 omap_underflow_irqs[] = { |
225 | [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, | |
226 | [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW, | |
227 | [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW, | |
228 | [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW, | |
229 | }; | |
230 | ||
f13ab005 LP |
231 | /* |
232 | * We need a special version, instead of just using drm_irq_install(), | |
233 | * because we need to register the irq via omapdss. Once omapdss and | |
234 | * omapdrm are merged together we can assign the dispc hwmod data to | |
235 | * ourselves and drop these and just use drm_irq_{install,uninstall}() | |
236 | */ | |
f5f9454c | 237 | |
f13ab005 | 238 | int omap_drm_irq_install(struct drm_device *dev) |
f5f9454c RC |
239 | { |
240 | struct omap_drm_private *priv = dev->dev_private; | |
50638ae5 | 241 | unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); |
728ae8dd LP |
242 | unsigned int max_planes; |
243 | unsigned int i; | |
f13ab005 | 244 | int ret; |
f5f9454c | 245 | |
84e1d457 | 246 | spin_lock_init(&priv->wait_lock); |
80f91bff | 247 | INIT_LIST_HEAD(&priv->wait_list); |
f5f9454c | 248 | |
6b5538d4 | 249 | priv->irq_mask = DISPC_IRQ_OCP_ERR; |
728ae8dd LP |
250 | |
251 | max_planes = min(ARRAY_SIZE(priv->planes), | |
252 | ARRAY_SIZE(omap_underflow_irqs)); | |
253 | for (i = 0; i < max_planes; ++i) { | |
254 | if (priv->planes[i]) | |
255 | priv->irq_mask |= omap_underflow_irqs[i]; | |
256 | } | |
257 | ||
e0519af7 | 258 | for (i = 0; i < num_mgrs; ++i) |
50638ae5 | 259 | priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i); |
e0519af7 | 260 | |
50638ae5 LP |
261 | priv->dispc_ops->runtime_get(priv->dispc); |
262 | priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff); | |
263 | priv->dispc_ops->runtime_put(priv->dispc); | |
f13ab005 | 264 | |
50638ae5 | 265 | ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev); |
f13ab005 LP |
266 | if (ret < 0) |
267 | return ret; | |
268 | ||
4423843c | 269 | dev->irq_enabled = true; |
f5f9454c | 270 | |
f13ab005 | 271 | return 0; |
f5f9454c RC |
272 | } |
273 | ||
f13ab005 | 274 | void omap_drm_irq_uninstall(struct drm_device *dev) |
f5f9454c | 275 | { |
9f759225 | 276 | struct omap_drm_private *priv = dev->dev_private; |
f5f9454c | 277 | |
f13ab005 LP |
278 | if (!dev->irq_enabled) |
279 | return; | |
280 | ||
4423843c | 281 | dev->irq_enabled = false; |
f5f9454c | 282 | |
50638ae5 | 283 | priv->dispc_ops->free_irq(priv->dispc, dev); |
f5f9454c | 284 | } |