projects / thirdparty / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 37e9b6a6 | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 49 | |
| 771fe6b9 | 50 | /* |
| 44ca7478 | 51 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 52 | */ |
| 2b497502 DV |
53 | struct r100_mc_save { |
| 54 | u32 GENMO_WT; | |
| 55 | u32 CRTC_EXT_CNTL; | |
| 56 | u32 CRTC_GEN_CNTL; | |
| 57 | u32 CRTC2_GEN_CNTL; | |
| 58 | u32 CUR_OFFSET; | |
| 59 | u32 CUR2_OFFSET; | |
| 60 | }; | |
| 61 | int r100_init(struct radeon_device *rdev); | |
| 62 | void r100_fini(struct radeon_device *rdev); | |
| 63 | int r100_suspend(struct radeon_device *rdev); | |
| 64 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 65 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| e32eb50d | 66 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 71fe2899 | 67 | int r100_asic_reset(struct radeon_device *rdev, bool hard); |
| 7ed220d7 | 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 | 69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| cb658906 | 70 | uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); |
| 7f90fc96 | 71 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, |
| cb658906 | 72 | uint64_t entry); |
| f712812e | 73 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 771fe6b9 JG |
74 | int r100_irq_set(struct radeon_device *rdev); |
| 75 | int r100_irq_process(struct radeon_device *rdev); | |
| 76 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 77 | struct radeon_fence *fence); | |
| 1654b817 | 78 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 79 | struct radeon_ring *cp, |
| 15d3332f | 80 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 81 | bool emit_wait); |
| 771fe6b9 JG |
82 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 83 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 84 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 57d20a43 CK |
85 | struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, |
| 86 | uint64_t src_offset, | |
| 87 | uint64_t dst_offset, | |
| 88 | unsigned num_gpu_pages, | |
| 52791eee | 89 | struct dma_resv *resv); |
| e024e110 DA |
90 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 91 | uint32_t tiling_flags, uint32_t pitch, | |
| 92 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 93 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 94 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 95 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 96 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 429770b3 AD |
97 | void r100_hpd_init(struct radeon_device *rdev); |
| 98 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 99 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 100 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 101 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
102 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 103 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 104 | void r100_cp_disable(struct radeon_device *rdev); | |
| 105 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 106 | void r100_cp_fini(struct radeon_device *rdev); | |
| 107 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 108 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 109 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 110 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 111 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 112 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| f712812e | 113 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 2b497502 DV |
114 | void r100_irq_disable(struct radeon_device *rdev); |
| 115 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 116 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 117 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
118 | int r100_cp_reset(struct radeon_device *rdev); |
| 119 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 120 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
121 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 122 | struct radeon_cs_packet *pkt, | |
| 123 | struct radeon_bo *robj); | |
| 124 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 125 | struct radeon_cs_packet *pkt, | |
| 126 | const unsigned *auth, unsigned n, | |
| 127 | radeon_packet0_check_t check); | |
| 128 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 129 | struct radeon_cs_packet *pkt, | |
| 130 | unsigned idx); | |
| 131 | void r100_enable_bm(struct radeon_device *rdev); | |
| 132 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 133 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 134 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
135 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 136 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 137 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
138 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 139 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 157fa14d | 140 | extern void r100_page_flip(struct radeon_device *rdev, int crtc, |
| c63dd758 | 141 | u64 crtc_base, bool async); |
| 157fa14d | 142 | extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); |
| 3ae19b75 | 143 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 144 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| bae6b562 | 145 | |
| ea31bf69 AD |
146 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
| 147 | struct radeon_ring *ring); | |
| 148 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, | |
| 149 | struct radeon_ring *ring); | |
| 150 | void r100_gfx_set_wptr(struct radeon_device *rdev, | |
| 151 | struct radeon_ring *ring); | |
| 897eba82 | 152 | |
| 44ca7478 PN |
153 | /* |
| 154 | * r200,rv250,rs300,rv280 | |
| 155 | */ | |
| 57d20a43 CK |
156 | struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, |
| 157 | uint64_t src_offset, | |
| 158 | uint64_t dst_offset, | |
| 159 | unsigned num_gpu_pages, | |
| 52791eee | 160 | struct dma_resv *resv); |
| 187f3da3 | 161 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
162 | |
| 163 | /* | |
| 164 | * r300,r350,rv350,rv380 | |
| 165 | */ | |
| 207bf9e9 JG |
166 | extern int r300_init(struct radeon_device *rdev); |
| 167 | extern void r300_fini(struct radeon_device *rdev); | |
| 168 | extern int r300_suspend(struct radeon_device *rdev); | |
| 169 | extern int r300_resume(struct radeon_device *rdev); | |
| 71fe2899 | 170 | extern int r300_asic_reset(struct radeon_device *rdev, bool hard); |
| f712812e | 171 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 207bf9e9 JG |
172 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 173 | struct radeon_fence *fence); | |
| 174 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 175 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| cb658906 | 176 | extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); |
| 7f90fc96 | 177 | extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, |
| cb658906 | 178 | uint64_t entry); |
| 207bf9e9 | 179 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 180 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
181 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 182 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 183 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 184 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 185 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 186 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 187 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 188 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 189 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 89e5181f | 190 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 44ca7478 | 191 | |
| 771fe6b9 JG |
192 | /* |
| 193 | * r420,r423,rv410 | |
| 194 | */ | |
| 9f022ddf JG |
195 | extern int r420_init(struct radeon_device *rdev); |
| 196 | extern void r420_fini(struct radeon_device *rdev); | |
| 197 | extern int r420_suspend(struct radeon_device *rdev); | |
| 198 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 199 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
200 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 201 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 202 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 203 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
204 | |
| 205 | /* | |
| 206 | * rs400,rs480 | |
| 207 | */ | |
| ca6ffc64 JG |
208 | extern int rs400_init(struct radeon_device *rdev); |
| 209 | extern void rs400_fini(struct radeon_device *rdev); | |
| 210 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 211 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 212 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| cb658906 | 213 | uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); |
| 7f90fc96 | 214 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, |
| cb658906 | 215 | uint64_t entry); |
| 771fe6b9 JG |
216 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 217 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
218 | int rs400_gart_init(struct radeon_device *rdev); |
| 219 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 220 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 221 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 222 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 89e5181f | 223 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
| 187f3da3 | 224 | |
| 771fe6b9 JG |
225 | /* |
| 226 | * rs600. | |
| 227 | */ | |
| 71fe2899 | 228 | extern int rs600_asic_reset(struct radeon_device *rdev, bool hard); |
| c010f800 JG |
229 | extern int rs600_init(struct radeon_device *rdev); |
| 230 | extern void rs600_fini(struct radeon_device *rdev); | |
| 231 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 232 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 233 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 234 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 235 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 236 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 | 237 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| cb658906 | 238 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); |
| 7f90fc96 | 239 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
| cb658906 | 240 | uint64_t entry); |
| 771fe6b9 JG |
241 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 242 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 243 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
244 | void rs600_hpd_init(struct radeon_device *rdev); |
| 245 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 246 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 247 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 248 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
249 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 250 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 251 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 157fa14d | 252 | extern void rs600_page_flip(struct radeon_device *rdev, int crtc, |
| c63dd758 | 253 | u64 crtc_base, bool async); |
| 157fa14d | 254 | extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); |
| 187f3da3 | 255 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 3ae19b75 | 256 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 257 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| 429770b3 | 258 | |
| 771fe6b9 JG |
259 | /* |
| 260 | * rs690,rs740 | |
| 261 | */ | |
| 3bc68535 JG |
262 | int rs690_init(struct radeon_device *rdev); |
| 263 | void rs690_fini(struct radeon_device *rdev); | |
| 264 | int rs690_resume(struct radeon_device *rdev); | |
| 265 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
266 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 267 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 268 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
269 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 270 | struct drm_display_mode *mode1, | |
| 271 | struct drm_display_mode *mode2); | |
| 89e5181f | 272 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
273 | |
| 274 | /* | |
| 275 | * rv515 | |
| 276 | */ | |
| 187f3da3 | 277 | struct rv515_mc_save { |
| 187f3da3 DV |
278 | u32 vga_render_control; |
| 279 | u32 vga_hdp_control; | |
| 6253e4c7 | 280 | bool crtc_enabled[2]; |
| 187f3da3 | 281 | }; |
| 81ee8fb6 | 282 | |
| 068a117c | 283 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 284 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
285 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 286 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| f712812e | 287 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| c93bb85b | 288 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
289 | int rv515_resume(struct radeon_device *rdev); |
| 290 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
291 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 292 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 293 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 294 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 295 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 296 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 297 | void rv515_debugfs(struct radeon_device *rdev); | |
| 89e5181f | 298 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
299 | |
| 300 | /* | |
| 301 | * r520,rv530,rv560,rv570,r580 | |
| 302 | */ | |
| d39c3b89 | 303 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 304 | int r520_resume(struct radeon_device *rdev); |
| 89e5181f | 305 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
306 | |
| 307 | /* | |
| 3ce0a23d | 308 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 309 | */ |
| 3ce0a23d JG |
310 | int r600_init(struct radeon_device *rdev); |
| 311 | void r600_fini(struct radeon_device *rdev); | |
| 312 | int r600_suspend(struct radeon_device *rdev); | |
| 313 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 314 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
315 | int r600_wb_init(struct radeon_device *rdev); |
| 316 | void r600_wb_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 317 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 771fe6b9 JG |
318 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 319 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d | 320 | int r600_cs_parse(struct radeon_cs_parser *p); |
| cf4ccd01 | 321 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
| 3ce0a23d JG |
322 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 323 | struct radeon_fence *fence); | |
| 1654b817 | 324 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 325 | struct radeon_ring *cp, |
| 15d3332f | 326 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 327 | bool emit_wait); |
| 4d75658b AD |
328 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
| 329 | struct radeon_fence *fence); | |
| 1654b817 | 330 | bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
| 4d75658b AD |
331 | struct radeon_ring *ring, |
| 332 | struct radeon_semaphore *semaphore, | |
| 333 | bool emit_wait); | |
| 334 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 335 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 123bc183 | 336 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 71fe2899 | 337 | int r600_asic_reset(struct radeon_device *rdev, bool hard); |
| 3ce0a23d JG |
338 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 339 | uint32_t tiling_flags, uint32_t pitch, | |
| 340 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 341 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| f712812e | 342 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 4d75658b | 343 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d | 344 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 345 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 4d75658b | 346 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 57d20a43 CK |
347 | struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, |
| 348 | uint64_t src_offset, uint64_t dst_offset, | |
| 349 | unsigned num_gpu_pages, | |
| 52791eee | 350 | struct dma_resv *resv); |
| 57d20a43 CK |
351 | struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, |
| 352 | uint64_t src_offset, uint64_t dst_offset, | |
| 353 | unsigned num_gpu_pages, | |
| 52791eee | 354 | struct dma_resv *resv); |
| 429770b3 AD |
355 | void r600_hpd_init(struct radeon_device *rdev); |
| 356 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 357 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 358 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 359 | enum radeon_hpd_id hpd); | |
| 124764f1 | 360 | extern void r600_mmio_hdp_flush(struct radeon_device *rdev); |
| def9ba9c | 361 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 362 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
363 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 364 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 65337e60 SL |
365 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 366 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| ce8f5370 | 367 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
| 3313e3d4 AD |
368 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 369 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
370 | bool r600_card_posted(struct radeon_device *rdev); |
| 371 | void r600_cp_stop(struct radeon_device *rdev); | |
| 372 | int r600_cp_start(struct radeon_device *rdev); | |
| e32eb50d | 373 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
| 3574dda4 DV |
374 | int r600_cp_resume(struct radeon_device *rdev); |
| 375 | void r600_cp_fini(struct radeon_device *rdev); | |
| 376 | int r600_count_pipe_bits(uint32_t val); | |
| 377 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 378 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 379 | void r600_scratch_init(struct radeon_device *rdev); | |
| 3574dda4 | 380 | int r600_init_microcode(struct radeon_device *rdev); |
| ea31bf69 AD |
381 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
| 382 | struct radeon_ring *ring); | |
| 383 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, | |
| 384 | struct radeon_ring *ring); | |
| 385 | void r600_gfx_set_wptr(struct radeon_device *rdev, | |
| 386 | struct radeon_ring *ring); | |
| c6d2ac2c AD |
387 | int r600_get_allowed_info_register(struct radeon_device *rdev, |
| 388 | u32 reg, u32 *val); | |
| 3574dda4 DV |
389 | /* r600 irq */ |
| 390 | int r600_irq_process(struct radeon_device *rdev); | |
| 391 | int r600_irq_init(struct radeon_device *rdev); | |
| 392 | void r600_irq_fini(struct radeon_device *rdev); | |
| 393 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 394 | int r600_irq_set(struct radeon_device *rdev); | |
| 395 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 396 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 397 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 398 | /* r600 audio */ | |
| 3574dda4 | 399 | void r600_audio_fini(struct radeon_device *rdev); |
| 8f33a156 RM |
400 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); |
| 401 | void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, | |
| 402 | size_t size); | |
| 403 | void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); | |
| 404 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder); | |
| 3574dda4 DV |
405 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| 406 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| 89e5181f | 407 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 454d2e2a | 408 | u32 r600_get_xclk(struct radeon_device *rdev); |
| d0418894 | 409 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
| 6bd1c385 | 410 | int rv6xx_get_temp(struct radeon_device *rdev); |
| 1b9ba70a | 411 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 98243917 AD |
412 | int r600_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 413 | void r600_dpm_post_set_power_state(struct radeon_device *rdev); | |
| a4643ba3 | 414 | int r600_dpm_late_enable(struct radeon_device *rdev); |
| 2e1e6dad CK |
415 | /* r600 dma */ |
| 416 | uint32_t r600_dma_get_rptr(struct radeon_device *rdev, | |
| 417 | struct radeon_ring *ring); | |
| 418 | uint32_t r600_dma_get_wptr(struct radeon_device *rdev, | |
| 419 | struct radeon_ring *ring); | |
| 420 | void r600_dma_set_wptr(struct radeon_device *rdev, | |
| 421 | struct radeon_ring *ring); | |
| 4a6369e9 AD |
422 | /* rv6xx dpm */ |
| 423 | int rv6xx_dpm_init(struct radeon_device *rdev); | |
| 424 | int rv6xx_dpm_enable(struct radeon_device *rdev); | |
| 425 | void rv6xx_dpm_disable(struct radeon_device *rdev); | |
| 426 | int rv6xx_dpm_set_power_state(struct radeon_device *rdev); | |
| 427 | void rv6xx_setup_asic(struct radeon_device *rdev); | |
| 428 | void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 429 | void rv6xx_dpm_fini(struct radeon_device *rdev); | |
| 430 | u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 431 | u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 432 | void rv6xx_dpm_print_power_state(struct radeon_device *rdev, | |
| 433 | struct radeon_ps *ps); | |
| 242916a5 AD |
434 | void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 435 | struct seq_file *m); | |
| f4f85a8c AD |
436 | int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, |
| 437 | enum radeon_dpm_forced_level level); | |
| d0a04d3b AD |
438 | u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev); |
| 439 | u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 9d67006e AD |
440 | /* rs780 dpm */ |
| 441 | int rs780_dpm_init(struct radeon_device *rdev); | |
| 442 | int rs780_dpm_enable(struct radeon_device *rdev); | |
| 443 | void rs780_dpm_disable(struct radeon_device *rdev); | |
| 444 | int rs780_dpm_set_power_state(struct radeon_device *rdev); | |
| 445 | void rs780_dpm_setup_asic(struct radeon_device *rdev); | |
| 446 | void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 447 | void rs780_dpm_fini(struct radeon_device *rdev); | |
| 448 | u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 449 | u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 450 | void rs780_dpm_print_power_state(struct radeon_device *rdev, | |
| 451 | struct radeon_ps *ps); | |
| 444bddc4 AD |
452 | void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 453 | struct seq_file *m); | |
| 63580c3e AB |
454 | int rs780_dpm_force_performance_level(struct radeon_device *rdev, |
| 455 | enum radeon_dpm_forced_level level); | |
| 3c94566c AD |
456 | u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev); |
| 457 | u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 3ce0a23d | 458 | |
| 3ce0a23d JG |
459 | /* |
| 460 | * rv770,rv730,rv710,rv740 | |
| 461 | */ | |
| 462 | int rv770_init(struct radeon_device *rdev); | |
| 463 | void rv770_fini(struct radeon_device *rdev); | |
| 464 | int rv770_suspend(struct radeon_device *rdev); | |
| 465 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 | 466 | void rv770_pm_misc(struct radeon_device *rdev); |
| c63dd758 MD |
467 | void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base, |
| 468 | bool async); | |
| 157fa14d | 469 | bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); |
| 3574dda4 DV |
470 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
| 471 | void r700_cp_stop(struct radeon_device *rdev); | |
| 472 | void r700_cp_fini(struct radeon_device *rdev); | |
| 57d20a43 CK |
473 | struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, |
| 474 | uint64_t src_offset, uint64_t dst_offset, | |
| 475 | unsigned num_gpu_pages, | |
| 52791eee | 476 | struct dma_resv *resv); |
| 454d2e2a | 477 | u32 rv770_get_xclk(struct radeon_device *rdev); |
| ef0e6e65 | 478 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6bd1c385 | 479 | int rv770_get_temp(struct radeon_device *rdev); |
| 66229b20 AD |
480 | /* rv7xx pm */ |
| 481 | int rv770_dpm_init(struct radeon_device *rdev); | |
| 482 | int rv770_dpm_enable(struct radeon_device *rdev); | |
| a3f11245 | 483 | int rv770_dpm_late_enable(struct radeon_device *rdev); |
| 66229b20 AD |
484 | void rv770_dpm_disable(struct radeon_device *rdev); |
| 485 | int rv770_dpm_set_power_state(struct radeon_device *rdev); | |
| 486 | void rv770_dpm_setup_asic(struct radeon_device *rdev); | |
| 487 | void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 488 | void rv770_dpm_fini(struct radeon_device *rdev); | |
| 489 | u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 490 | u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 491 | void rv770_dpm_print_power_state(struct radeon_device *rdev, | |
| 492 | struct radeon_ps *ps); | |
| bd210d11 AD |
493 | void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 494 | struct seq_file *m); | |
| 8b5e6b7f AD |
495 | int rv770_dpm_force_performance_level(struct radeon_device *rdev, |
| 496 | enum radeon_dpm_forced_level level); | |
| b06195d9 | 497 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); |
| 296deb71 AD |
498 | u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev); |
| 499 | u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 3ce0a23d | 500 | |
| bcc1c2a1 AD |
501 | /* |
| 502 | * evergreen | |
| 503 | */ | |
| 3574dda4 | 504 | struct evergreen_mc_save { |
| 3574dda4 DV |
505 | u32 vga_render_control; |
| 506 | u32 vga_hdp_control; | |
| 62444b74 | 507 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
| 3574dda4 | 508 | }; |
| 81ee8fb6 | 509 | |
| 0fcdb61e | 510 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
511 | int evergreen_init(struct radeon_device *rdev); |
| 512 | void evergreen_fini(struct radeon_device *rdev); | |
| 513 | int evergreen_suspend(struct radeon_device *rdev); | |
| 514 | int evergreen_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
515 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 516 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 71fe2899 | 517 | int evergreen_asic_reset(struct radeon_device *rdev, bool hard); |
| bcc1c2a1 | 518 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 519 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
520 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 521 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 522 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 523 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 524 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
525 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 526 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 527 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 528 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| d2ead3ea | 529 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
530 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 531 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 532 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 533 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 27810fb2 | 534 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
| 23d33ba3 | 535 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| a8b4925c | 536 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 157fa14d | 537 | extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, |
| c63dd758 | 538 | u64 crtc_base, bool async); |
| 157fa14d | 539 | extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); |
| 3ae19b75 | 540 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 3574dda4 | 541 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 89e5181f | 542 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 233d1ad5 AD |
543 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
| 544 | struct radeon_fence *fence); | |
| 545 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, | |
| 546 | struct radeon_ib *ib); | |
| 57d20a43 CK |
547 | struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, |
| 548 | uint64_t src_offset, uint64_t dst_offset, | |
| 549 | unsigned num_gpu_pages, | |
| 52791eee | 550 | struct dma_resv *resv); |
| 6bd1c385 | 551 | int evergreen_get_temp(struct radeon_device *rdev); |
| ff609975 AD |
552 | int evergreen_get_allowed_info_register(struct radeon_device *rdev, |
| 553 | u32 reg, u32 *val); | |
| 6bd1c385 | 554 | int sumo_get_temp(struct radeon_device *rdev); |
| 29a15221 | 555 | int tn_get_temp(struct radeon_device *rdev); |
| dc50ba7f AD |
556 | int cypress_dpm_init(struct radeon_device *rdev); |
| 557 | void cypress_dpm_setup_asic(struct radeon_device *rdev); | |
| 558 | int cypress_dpm_enable(struct radeon_device *rdev); | |
| 559 | void cypress_dpm_disable(struct radeon_device *rdev); | |
| 560 | int cypress_dpm_set_power_state(struct radeon_device *rdev); | |
| 561 | void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 562 | void cypress_dpm_fini(struct radeon_device *rdev); | |
| d0b54bdc | 563 | bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); |
| 6596afd4 AD |
564 | int btc_dpm_init(struct radeon_device *rdev); |
| 565 | void btc_dpm_setup_asic(struct radeon_device *rdev); | |
| 566 | int btc_dpm_enable(struct radeon_device *rdev); | |
| 567 | void btc_dpm_disable(struct radeon_device *rdev); | |
| e8a9539f | 568 | int btc_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 6596afd4 | 569 | int btc_dpm_set_power_state(struct radeon_device *rdev); |
| e8a9539f | 570 | void btc_dpm_post_set_power_state(struct radeon_device *rdev); |
| 6596afd4 | 571 | void btc_dpm_fini(struct radeon_device *rdev); |
| e8a9539f AD |
572 | u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); |
| 573 | u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| a84301c6 | 574 | bool btc_dpm_vblank_too_short(struct radeon_device *rdev); |
| 9f3f63f2 AD |
575 | void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 576 | struct seq_file *m); | |
| 99550ee9 AD |
577 | u32 btc_dpm_get_current_sclk(struct radeon_device *rdev); |
| 578 | u32 btc_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 80ea2c12 AD |
579 | int sumo_dpm_init(struct radeon_device *rdev); |
| 580 | int sumo_dpm_enable(struct radeon_device *rdev); | |
| 14ec9fab | 581 | int sumo_dpm_late_enable(struct radeon_device *rdev); |
| 80ea2c12 | 582 | void sumo_dpm_disable(struct radeon_device *rdev); |
| 422a56bc | 583 | int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 80ea2c12 | 584 | int sumo_dpm_set_power_state(struct radeon_device *rdev); |
| 422a56bc | 585 | void sumo_dpm_post_set_power_state(struct radeon_device *rdev); |
| 80ea2c12 AD |
586 | void sumo_dpm_setup_asic(struct radeon_device *rdev); |
| 587 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 588 | void sumo_dpm_fini(struct radeon_device *rdev); | |
| 589 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 590 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 591 | void sumo_dpm_print_power_state(struct radeon_device *rdev, | |
| 592 | struct radeon_ps *ps); | |
| fb70160c AD |
593 | void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 594 | struct seq_file *m); | |
| 5d5e5591 AD |
595 | int sumo_dpm_force_performance_level(struct radeon_device *rdev, |
| 596 | enum radeon_dpm_forced_level level); | |
| 2f8e1eb7 AD |
597 | u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev); |
| 598 | u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 4546b2c1 | 599 | |
| e3487629 AD |
600 | /* |
| 601 | * cayman | |
| 602 | */ | |
| b40e7e16 AD |
603 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 604 | struct radeon_fence *fence); | |
| e3487629 AD |
605 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 606 | int cayman_init(struct radeon_device *rdev); | |
| 607 | void cayman_fini(struct radeon_device *rdev); | |
| 608 | int cayman_suspend(struct radeon_device *rdev); | |
| 609 | int cayman_resume(struct radeon_device *rdev); | |
| 71fe2899 | 610 | int cayman_asic_reset(struct radeon_device *rdev, bool hard); |
| 721604a1 JG |
611 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 612 | int cayman_vm_init(struct radeon_device *rdev); | |
| 613 | void cayman_vm_fini(struct radeon_device *rdev); | |
| faffaf62 CK |
614 | void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 615 | unsigned vm_id, uint64_t pd_addr); | |
| 089a786e | 616 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
| 721604a1 | 617 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| cd459e52 | 618 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| f60cbd11 AD |
619 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
| 620 | struct radeon_ib *ib); | |
| 123bc183 | 621 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| f60cbd11 | 622 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| 03f62abd CK |
623 | |
| 624 | void cayman_dma_vm_copy_pages(struct radeon_device *rdev, | |
| 625 | struct radeon_ib *ib, | |
| 626 | uint64_t pe, uint64_t src, | |
| 627 | unsigned count); | |
| 628 | void cayman_dma_vm_write_pages(struct radeon_device *rdev, | |
| 629 | struct radeon_ib *ib, | |
| 630 | uint64_t pe, | |
| 631 | uint64_t addr, unsigned count, | |
| 632 | uint32_t incr, uint32_t flags); | |
| 633 | void cayman_dma_vm_set_pages(struct radeon_device *rdev, | |
| 634 | struct radeon_ib *ib, | |
| 635 | uint64_t pe, | |
| 636 | uint64_t addr, unsigned count, | |
| 637 | uint32_t incr, uint32_t flags); | |
| 638 | void cayman_dma_vm_pad_ib(struct radeon_ib *ib); | |
| 24c16439 | 639 | |
| faffaf62 CK |
640 | void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 641 | unsigned vm_id, uint64_t pd_addr); | |
| 45f9a39b | 642 | |
| ea31bf69 AD |
643 | u32 cayman_gfx_get_rptr(struct radeon_device *rdev, |
| 644 | struct radeon_ring *ring); | |
| 645 | u32 cayman_gfx_get_wptr(struct radeon_device *rdev, | |
| 646 | struct radeon_ring *ring); | |
| 647 | void cayman_gfx_set_wptr(struct radeon_device *rdev, | |
| 648 | struct radeon_ring *ring); | |
| 649 | uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, | |
| 650 | struct radeon_ring *ring); | |
| 651 | uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, | |
| 652 | struct radeon_ring *ring); | |
| 653 | void cayman_dma_set_wptr(struct radeon_device *rdev, | |
| 654 | struct radeon_ring *ring); | |
| e66582f9 AD |
655 | int cayman_get_allowed_info_register(struct radeon_device *rdev, |
| 656 | u32 reg, u32 *val); | |
| ea31bf69 | 657 | |
| 69e0b57a AD |
658 | int ni_dpm_init(struct radeon_device *rdev); |
| 659 | void ni_dpm_setup_asic(struct radeon_device *rdev); | |
| 660 | int ni_dpm_enable(struct radeon_device *rdev); | |
| 661 | void ni_dpm_disable(struct radeon_device *rdev); | |
| fee3d744 | 662 | int ni_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 69e0b57a | 663 | int ni_dpm_set_power_state(struct radeon_device *rdev); |
| fee3d744 | 664 | void ni_dpm_post_set_power_state(struct radeon_device *rdev); |
| 69e0b57a AD |
665 | void ni_dpm_fini(struct radeon_device *rdev); |
| 666 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 667 | u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 668 | void ni_dpm_print_power_state(struct radeon_device *rdev, | |
| 669 | struct radeon_ps *ps); | |
| bdf0c4f0 AD |
670 | void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 671 | struct seq_file *m); | |
| 170a47f0 AD |
672 | int ni_dpm_force_performance_level(struct radeon_device *rdev, |
| 673 | enum radeon_dpm_forced_level level); | |
| 76ad73e5 | 674 | bool ni_dpm_vblank_too_short(struct radeon_device *rdev); |
| 1d633e3a AD |
675 | u32 ni_dpm_get_current_sclk(struct radeon_device *rdev); |
| 676 | u32 ni_dpm_get_current_mclk(struct radeon_device *rdev); | |
| d70229f7 AD |
677 | int trinity_dpm_init(struct radeon_device *rdev); |
| 678 | int trinity_dpm_enable(struct radeon_device *rdev); | |
| bda44c1a | 679 | int trinity_dpm_late_enable(struct radeon_device *rdev); |
| d70229f7 | 680 | void trinity_dpm_disable(struct radeon_device *rdev); |
| a284c48a | 681 | int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); |
| d70229f7 | 682 | int trinity_dpm_set_power_state(struct radeon_device *rdev); |
| a284c48a | 683 | void trinity_dpm_post_set_power_state(struct radeon_device *rdev); |
| d70229f7 AD |
684 | void trinity_dpm_setup_asic(struct radeon_device *rdev); |
| 685 | void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 686 | void trinity_dpm_fini(struct radeon_device *rdev); | |
| 687 | u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 688 | u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 689 | void trinity_dpm_print_power_state(struct radeon_device *rdev, | |
| 690 | struct radeon_ps *ps); | |
| 490ab931 AD |
691 | void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 692 | struct seq_file *m); | |
| 9b5de596 AD |
693 | int trinity_dpm_force_performance_level(struct radeon_device *rdev, |
| 694 | enum radeon_dpm_forced_level level); | |
| 11877060 | 695 | void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
| 7ce9cdae AD |
696 | u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); |
| 697 | u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 0fda42ac | 698 | int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
| d70229f7 | 699 | |
| 43b3cd99 AD |
700 | /* DCE6 - SI */ |
| 701 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
| b530602f | 702 | void dce6_audio_fini(struct radeon_device *rdev); |
| 43b3cd99 | 703 | |
| 02779c08 AD |
704 | /* |
| 705 | * si | |
| 706 | */ | |
| 707 | void si_fence_ring_emit(struct radeon_device *rdev, | |
| 708 | struct radeon_fence *fence); | |
| 709 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 710 | int si_init(struct radeon_device *rdev); | |
| 711 | void si_fini(struct radeon_device *rdev); | |
| 712 | int si_suspend(struct radeon_device *rdev); | |
| 713 | int si_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
714 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 715 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 71fe2899 | 716 | int si_asic_reset(struct radeon_device *rdev, bool hard); |
| 02779c08 AD |
717 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 718 | int si_irq_set(struct radeon_device *rdev); | |
| 719 | int si_irq_process(struct radeon_device *rdev); | |
| 720 | int si_vm_init(struct radeon_device *rdev); | |
| 721 | void si_vm_fini(struct radeon_device *rdev); | |
| faffaf62 CK |
722 | void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 723 | unsigned vm_id, uint64_t pd_addr); | |
| 02779c08 | 724 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 57d20a43 CK |
725 | struct radeon_fence *si_copy_dma(struct radeon_device *rdev, |
| 726 | uint64_t src_offset, uint64_t dst_offset, | |
| 727 | unsigned num_gpu_pages, | |
| 52791eee | 728 | struct dma_resv *resv); |
| 03f62abd CK |
729 | |
| 730 | void si_dma_vm_copy_pages(struct radeon_device *rdev, | |
| 731 | struct radeon_ib *ib, | |
| 732 | uint64_t pe, uint64_t src, | |
| 733 | unsigned count); | |
| 734 | void si_dma_vm_write_pages(struct radeon_device *rdev, | |
| 735 | struct radeon_ib *ib, | |
| 736 | uint64_t pe, | |
| 737 | uint64_t addr, unsigned count, | |
| 738 | uint32_t incr, uint32_t flags); | |
| 739 | void si_dma_vm_set_pages(struct radeon_device *rdev, | |
| 740 | struct radeon_ib *ib, | |
| 741 | uint64_t pe, | |
| 742 | uint64_t addr, unsigned count, | |
| 743 | uint32_t incr, uint32_t flags); | |
| 744 | ||
| faffaf62 CK |
745 | void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 746 | unsigned vm_id, uint64_t pd_addr); | |
| 454d2e2a | 747 | u32 si_get_xclk(struct radeon_device *rdev); |
| d0418894 | 748 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
| 2539eb02 | 749 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| b7af630c | 750 | int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
| 6bd1c385 | 751 | int si_get_temp(struct radeon_device *rdev); |
| 4af692f6 AD |
752 | int si_get_allowed_info_register(struct radeon_device *rdev, |
| 753 | u32 reg, u32 *val); | |
| a9e61410 AD |
754 | int si_dpm_init(struct radeon_device *rdev); |
| 755 | void si_dpm_setup_asic(struct radeon_device *rdev); | |
| 756 | int si_dpm_enable(struct radeon_device *rdev); | |
| 963c115d | 757 | int si_dpm_late_enable(struct radeon_device *rdev); |
| a9e61410 AD |
758 | void si_dpm_disable(struct radeon_device *rdev); |
| 759 | int si_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 760 | int si_dpm_set_power_state(struct radeon_device *rdev); | |
| 761 | void si_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 762 | void si_dpm_fini(struct radeon_device *rdev); | |
| 763 | void si_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 7982128c AD |
764 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 765 | struct seq_file *m); | |
| a160a6a3 AD |
766 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
| 767 | enum radeon_dpm_forced_level level); | |
| 5e8150a6 AD |
768 | int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
| 769 | u32 *speed); | |
| 770 | int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, | |
| 771 | u32 speed); | |
| 772 | u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); | |
| 773 | void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); | |
| ca1110bc AD |
774 | u32 si_dpm_get_current_sclk(struct radeon_device *rdev); |
| 775 | u32 si_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 02779c08 | 776 | |
| 0672e27b AD |
777 | /* DCE8 - CIK */ |
| 778 | void dce8_bandwidth_update(struct radeon_device *rdev); | |
| 779 | ||
| 44fa346f AD |
780 | /* |
| 781 | * cik | |
| 782 | */ | |
| 783 | uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); | |
| 2c67912c | 784 | u32 cik_get_xclk(struct radeon_device *rdev); |
| 6e2c3c0a AD |
785 | uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 786 | void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 87167bb1 | 787 | int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 5ad6bf91 | 788 | int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
| 0672e27b AD |
789 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
| 790 | struct radeon_fence *fence); | |
| 1654b817 | 791 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
| 0672e27b AD |
792 | struct radeon_ring *ring, |
| 793 | struct radeon_semaphore *semaphore, | |
| 794 | bool emit_wait); | |
| 795 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 57d20a43 CK |
796 | struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, |
| 797 | uint64_t src_offset, uint64_t dst_offset, | |
| 798 | unsigned num_gpu_pages, | |
| 52791eee | 799 | struct dma_resv *resv); |
| 57d20a43 CK |
800 | struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, |
| 801 | uint64_t src_offset, uint64_t dst_offset, | |
| 802 | unsigned num_gpu_pages, | |
| 52791eee | 803 | struct dma_resv *resv); |
| 0672e27b AD |
804 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 805 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 806 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 807 | void cik_fence_gfx_ring_emit(struct radeon_device *rdev, | |
| 808 | struct radeon_fence *fence); | |
| 809 | void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |
| 810 | struct radeon_fence *fence); | |
| 1654b817 | 811 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
| 0672e27b AD |
812 | struct radeon_ring *cp, |
| 813 | struct radeon_semaphore *semaphore, | |
| 814 | bool emit_wait); | |
| 815 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 816 | int cik_init(struct radeon_device *rdev); | |
| 817 | void cik_fini(struct radeon_device *rdev); | |
| 818 | int cik_suspend(struct radeon_device *rdev); | |
| 819 | int cik_resume(struct radeon_device *rdev); | |
| 820 | bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 71fe2899 | 821 | int cik_asic_reset(struct radeon_device *rdev, bool hard); |
| 0672e27b AD |
822 | void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 823 | int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 824 | int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 825 | int cik_irq_set(struct radeon_device *rdev); | |
| 826 | int cik_irq_process(struct radeon_device *rdev); | |
| 827 | int cik_vm_init(struct radeon_device *rdev); | |
| 828 | void cik_vm_fini(struct radeon_device *rdev); | |
| faffaf62 CK |
829 | void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 830 | unsigned vm_id, uint64_t pd_addr); | |
| 03f62abd CK |
831 | |
| 832 | void cik_sdma_vm_copy_pages(struct radeon_device *rdev, | |
| 833 | struct radeon_ib *ib, | |
| 834 | uint64_t pe, uint64_t src, | |
| 835 | unsigned count); | |
| 836 | void cik_sdma_vm_write_pages(struct radeon_device *rdev, | |
| 837 | struct radeon_ib *ib, | |
| 838 | uint64_t pe, | |
| 839 | uint64_t addr, unsigned count, | |
| 840 | uint32_t incr, uint32_t flags); | |
| 841 | void cik_sdma_vm_set_pages(struct radeon_device *rdev, | |
| 842 | struct radeon_ib *ib, | |
| 843 | uint64_t pe, | |
| 844 | uint64_t addr, unsigned count, | |
| 845 | uint32_t incr, uint32_t flags); | |
| 846 | void cik_sdma_vm_pad_ib(struct radeon_ib *ib); | |
| 847 | ||
| faffaf62 CK |
848 | void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 849 | unsigned vm_id, uint64_t pd_addr); | |
| 0672e27b | 850 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| ea31bf69 AD |
851 | u32 cik_gfx_get_rptr(struct radeon_device *rdev, |
| 852 | struct radeon_ring *ring); | |
| 853 | u32 cik_gfx_get_wptr(struct radeon_device *rdev, | |
| 854 | struct radeon_ring *ring); | |
| 855 | void cik_gfx_set_wptr(struct radeon_device *rdev, | |
| 856 | struct radeon_ring *ring); | |
| 857 | u32 cik_compute_get_rptr(struct radeon_device *rdev, | |
| 858 | struct radeon_ring *ring); | |
| 859 | u32 cik_compute_get_wptr(struct radeon_device *rdev, | |
| 860 | struct radeon_ring *ring); | |
| 861 | void cik_compute_set_wptr(struct radeon_device *rdev, | |
| 862 | struct radeon_ring *ring); | |
| 863 | u32 cik_sdma_get_rptr(struct radeon_device *rdev, | |
| 864 | struct radeon_ring *ring); | |
| 865 | u32 cik_sdma_get_wptr(struct radeon_device *rdev, | |
| 866 | struct radeon_ring *ring); | |
| 867 | void cik_sdma_set_wptr(struct radeon_device *rdev, | |
| 868 | struct radeon_ring *ring); | |
| 286d9cc6 AD |
869 | int ci_get_temp(struct radeon_device *rdev); |
| 870 | int kv_get_temp(struct radeon_device *rdev); | |
| 353eec2a AD |
871 | int cik_get_allowed_info_register(struct radeon_device *rdev, |
| 872 | u32 reg, u32 *val); | |
| 44fa346f | 873 | |
| cc8dbbb4 AD |
874 | int ci_dpm_init(struct radeon_device *rdev); |
| 875 | int ci_dpm_enable(struct radeon_device *rdev); | |
| 90208427 | 876 | int ci_dpm_late_enable(struct radeon_device *rdev); |
| cc8dbbb4 AD |
877 | void ci_dpm_disable(struct radeon_device *rdev); |
| 878 | int ci_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 879 | int ci_dpm_set_power_state(struct radeon_device *rdev); | |
| 880 | void ci_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 881 | void ci_dpm_setup_asic(struct radeon_device *rdev); | |
| 882 | void ci_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 883 | void ci_dpm_fini(struct radeon_device *rdev); | |
| 884 | u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 885 | u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 886 | void ci_dpm_print_power_state(struct radeon_device *rdev, | |
| 887 | struct radeon_ps *ps); | |
| 94b4adc5 AD |
888 | void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 889 | struct seq_file *m); | |
| 89536fd6 AD |
890 | int ci_dpm_force_performance_level(struct radeon_device *rdev, |
| 891 | enum radeon_dpm_forced_level level); | |
| 5496131e | 892 | bool ci_dpm_vblank_too_short(struct radeon_device *rdev); |
| 942bdf7f | 893 | void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
| dbbd3c81 AD |
894 | u32 ci_dpm_get_current_sclk(struct radeon_device *rdev); |
| 895 | u32 ci_dpm_get_current_mclk(struct radeon_device *rdev); | |
| cc8dbbb4 | 896 | |
| 36689e57 OC |
897 | int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
| 898 | u32 *speed); | |
| 899 | int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, | |
| 900 | u32 speed); | |
| 901 | u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev); | |
| 902 | void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); | |
| 903 | ||
| 41a524ab AD |
904 | int kv_dpm_init(struct radeon_device *rdev); |
| 905 | int kv_dpm_enable(struct radeon_device *rdev); | |
| d8852c34 | 906 | int kv_dpm_late_enable(struct radeon_device *rdev); |
| 41a524ab AD |
907 | void kv_dpm_disable(struct radeon_device *rdev); |
| 908 | int kv_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 909 | int kv_dpm_set_power_state(struct radeon_device *rdev); | |
| 910 | void kv_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 911 | void kv_dpm_setup_asic(struct radeon_device *rdev); | |
| 912 | void kv_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 913 | void kv_dpm_fini(struct radeon_device *rdev); | |
| 914 | u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 915 | u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 916 | void kv_dpm_print_power_state(struct radeon_device *rdev, | |
| 917 | struct radeon_ps *ps); | |
| ae3e40e8 AD |
918 | void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 919 | struct seq_file *m); | |
| 2b4c8022 AD |
920 | int kv_dpm_force_performance_level(struct radeon_device *rdev, |
| 921 | enum radeon_dpm_forced_level level); | |
| 77df508a | 922 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
| b7a5ae97 | 923 | void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
| 9b23bad0 AD |
924 | u32 kv_dpm_get_current_sclk(struct radeon_device *rdev); |
| 925 | u32 kv_dpm_get_current_mclk(struct radeon_device *rdev); | |
| 41a524ab | 926 | |
| e409b128 CK |
927 | /* uvd v1.0 */ |
| 928 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, | |
| 929 | struct radeon_ring *ring); | |
| 930 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, | |
| 931 | struct radeon_ring *ring); | |
| 932 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, | |
| 933 | struct radeon_ring *ring); | |
| 856754c3 | 934 | int uvd_v1_0_resume(struct radeon_device *rdev); |
| e409b128 CK |
935 | |
| 936 | int uvd_v1_0_init(struct radeon_device *rdev); | |
| 937 | void uvd_v1_0_fini(struct radeon_device *rdev); | |
| 938 | int uvd_v1_0_start(struct radeon_device *rdev); | |
| 939 | void uvd_v1_0_stop(struct radeon_device *rdev); | |
| 940 | ||
| 941 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 856754c3 CK |
942 | void uvd_v1_0_fence_emit(struct radeon_device *rdev, |
| 943 | struct radeon_fence *fence); | |
| e409b128 | 944 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1654b817 | 945 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
| e409b128 CK |
946 | struct radeon_ring *ring, |
| 947 | struct radeon_semaphore *semaphore, | |
| 948 | bool emit_wait); | |
| 949 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 950 | ||
| 951 | /* uvd v2.2 */ | |
| 952 | int uvd_v2_2_resume(struct radeon_device *rdev); | |
| 953 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, | |
| 954 | struct radeon_fence *fence); | |
| 013ead48 CK |
955 | bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, |
| 956 | struct radeon_ring *ring, | |
| 957 | struct radeon_semaphore *semaphore, | |
| 958 | bool emit_wait); | |
| e409b128 CK |
959 | |
| 960 | /* uvd v3.1 */ | |
| 1654b817 | 961 | bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, |
| e409b128 CK |
962 | struct radeon_ring *ring, |
| 963 | struct radeon_semaphore *semaphore, | |
| 964 | bool emit_wait); | |
| 965 | ||
| 966 | /* uvd v4.2 */ | |
| 967 | int uvd_v4_2_resume(struct radeon_device *rdev); | |
| 968 | ||
| d93f7937 CK |
969 | /* vce v1.0 */ |
| 970 | uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, | |
| 971 | struct radeon_ring *ring); | |
| 972 | uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, | |
| 973 | struct radeon_ring *ring); | |
| 974 | void vce_v1_0_set_wptr(struct radeon_device *rdev, | |
| 975 | struct radeon_ring *ring); | |
| a918efab CK |
976 | int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); |
| 977 | unsigned vce_v1_0_bo_size(struct radeon_device *rdev); | |
| 978 | int vce_v1_0_resume(struct radeon_device *rdev); | |
| d93f7937 CK |
979 | int vce_v1_0_init(struct radeon_device *rdev); |
| 980 | int vce_v1_0_start(struct radeon_device *rdev); | |
| 981 | ||
| 982 | /* vce v2.0 */ | |
| fa0cf2f2 | 983 | unsigned vce_v2_0_bo_size(struct radeon_device *rdev); |
| d93f7937 CK |
984 | int vce_v2_0_resume(struct radeon_device *rdev); |
| 985 | ||
| 771fe6b9 | 986 | #endif |