[thirdparty/linux.git] / drivers / gpu / drm / radeon / radeon_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/radeon_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "radeon.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */
/**
 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 * Returns 0 for success, -ENOMEM for failure.
 */
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
{
	void *ptr;

	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
				   &rdev->gart.table_addr);
	if (ptr == NULL) {
		return -ENOMEM;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_uc((unsigned long)ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	rdev->gart.ptr = ptr;
	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
	return 0;
}

/**
 * radeon_gart_table_ram_free - free system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Free system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 */
void radeon_gart_table_ram_free(struct radeon_device *rdev)
{
	if (rdev->gart.ptr == NULL) {
		return;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_wb((unsigned long)rdev->gart.ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
			    (void *)rdev->gart.ptr,
			    rdev->gart.table_addr);
	rdev->gart.ptr = NULL;
	rdev->gart.table_addr = 0;
}

/**
 * radeon_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		r = radeon_bo_create(rdev, rdev->gart.table_size,
				     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
				     0, NULL, NULL, &rdev->gart.robj);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * radeon_gart_table_vram_pin - pin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_pin(struct radeon_device *rdev)
{
	uint64_t gpu_addr;
	int r;

	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->gart.robj,
				RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->gart.robj);
		return r;
	}
	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
	if (r)
		radeon_bo_unpin(rdev->gart.robj);
	radeon_bo_unreserve(rdev->gart.robj);
	rdev->gart.table_addr = gpu_addr;

	if (!r) {
		int i;

		/* We might have dropped some GART table updates while it wasn't
		 * mapped, restore all entries
		 */
		for (i = 0; i < rdev->gart.num_gpu_pages; i++)
			radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
		mb();
		radeon_gart_tlb_flush(rdev);
	}

	return r;
}

/**
 * radeon_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		return;
	}
	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (likely(r == 0)) {
		radeon_bo_kunmap(rdev->gart.robj);
		radeon_bo_unpin(rdev->gart.robj);
		radeon_bo_unreserve(rdev->gart.robj);
		rdev->gart.ptr = NULL;
	}
}

/**
 * radeon_gart_table_vram_free - free gart page table vram
 *
 * @rdev: radeon_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void radeon_gart_table_vram_free(struct radeon_device *rdev)
{
	if (rdev->gart.robj == NULL) {
		return;
	}
	radeon_bo_unref(&rdev->gart.robj);
}

/*
 * Common gart functions.
 */
/**
 * radeon_gart_unbind - unbind pages from the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 */
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
	for (i = 0; i < pages; i++, p++) {
		if (rdev->gart.pages[p]) {
			rdev->gart.pages[p] = NULL;
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
				rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
				if (rdev->gart.ptr) {
					radeon_gart_set_page(rdev, t,
							     rdev->dummy_page.entry);
				}
			}
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
}

/**
 * radeon_gart_bind - bind pages into the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: RADEON_GART_PAGE_* flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint32_t flags)
{
	unsigned t;
	unsigned p;
	uint64_t page_base, page_entry;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);

	for (i = 0; i < pages; i++, p++) {
		rdev->gart.pages[p] = pagelist[i];
		page_base = dma_addr[i];
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
			page_entry = radeon_gart_get_page_entry(page_base, flags);
			rdev->gart.pages_entry[t] = page_entry;
			if (rdev->gart.ptr) {
				radeon_gart_set_page(rdev, t, page_entry);
			}
			page_base += RADEON_GPU_PAGE_SIZE;
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
	return 0;
}

/**
 * radeon_gart_init - init the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int radeon_gart_init(struct radeon_device *rdev)
{
	int r, i;

	if (rdev->gart.pages) {
		return 0;
	}
	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	/* Compute table size */
	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	/* Allocate pages table */
	rdev->gart.pages = vzalloc(array_size(sizeof(void *),
				   rdev->gart.num_cpu_pages));
	if (rdev->gart.pages == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t),
						    rdev->gart.num_gpu_pages));
	if (rdev->gart.pages_entry == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	/* set GART entry to point to the dummy page by default */
	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
		rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
	return 0;
}

/**
 * radeon_gart_fini - tear down the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the gart driver info and free the dummy page (all asics).
 */
void radeon_gart_fini(struct radeon_device *rdev)
{
	if (rdev->gart.ready) {
		/* unbind pages */
		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	}
	rdev->gart.ready = false;
	vfree(rdev->gart.pages);
	vfree(rdev->gart.pages_entry);
	rdev->gart.pages = NULL;
	rdev->gart.pages_entry = NULL;

	radeon_dummy_page_fini(rdev);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
f9183127	28
2ef79416	29	#include <linux/pci.h>
f9183127 SR	30	#include <linux/vmalloc.h>
f9183127 SR	31
760285e7	32	#include <drm/radeon_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
771fe6b9	36	#include "radeon.h"
771fe6b9	37
03eec93b AD	38	/*
	39	* GART
	40	* The GART (Graphics Aperture Remapping Table) is an aperture
	41	* in the GPU's address space. System pages can be mapped into
	42	* the aperture and look like contiguous pages from the GPU's
	43	* perspective. A page table maps the pages in the aperture
	44	* to the actual backing pages in system memory.
	45	*
	46	* Radeon GPUs support both an internal GART, as described above,
	47	* and AGP. AGP works similarly, but the GART table is configured
	48	* and maintained by the northbridge rather than the driver.
	49	* Radeon hw has a separate AGP aperture that is programmed to
	50	* point to the AGP aperture provided by the northbridge and the
	51	* requests are passed through to the northbridge aperture.
	52	* Both AGP and internal GART can be used at the same time, however
	53	* that is not currently supported by the driver.
	54	*
	55	* This file handles the common internal GART management.
	56	*/
	57
771fe6b9 JG	58	/*
	59	* Common GART table functions.
	60	*/
03eec93b AD	61	/**
	62	* radeon_gart_table_ram_alloc - allocate system ram for gart page table
	63	*
	64	* @rdev: radeon_device pointer
	65	*
	66	* Allocate system memory for GART page table
	67	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	68	* gart table to be in system memory.
	69	* Returns 0 for success, -ENOMEM for failure.
	70	*/
771fe6b9 JG	71	int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
	72	{
	73	void *ptr;
	74
	75	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
	76	&rdev->gart.table_addr);
	77	if (ptr == NULL) {
	78	return -ENOMEM;
	79	}
	80	#ifdef CONFIG_X86
	81	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	82	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
	83	set_memory_uc((unsigned long)ptr,
	84	rdev->gart.table_size >> PAGE_SHIFT);
	85	}
	86	#endif
c9a1be96 JG	87	rdev->gart.ptr = ptr;
c9a1be96 JG	88	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
771fe6b9 JG	89	return 0;
	90	}
	91
03eec93b AD	92	/**
	93	* radeon_gart_table_ram_free - free system ram for gart page table
	94	*
	95	* @rdev: radeon_device pointer
	96	*
	97	* Free system memory for GART page table
	98	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	99	* gart table to be in system memory.
	100	*/
771fe6b9 JG	101	void radeon_gart_table_ram_free(struct radeon_device *rdev)
771fe6b9 JG	102	{
c9a1be96	103	if (rdev->gart.ptr == NULL) {
771fe6b9 JG	104	return;
	105	}
	106	#ifdef CONFIG_X86
	107	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	108	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
c9a1be96	109	set_memory_wb((unsigned long)rdev->gart.ptr,
771fe6b9 JG	110	rdev->gart.table_size >> PAGE_SHIFT);
	111	}
	112	#endif
	113	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
c9a1be96	114	(void *)rdev->gart.ptr,
771fe6b9	115	rdev->gart.table_addr);
c9a1be96	116	rdev->gart.ptr = NULL;
771fe6b9 JG	117	rdev->gart.table_addr = 0;
	118	}
	119
03eec93b AD	120	/**
	121	* radeon_gart_table_vram_alloc - allocate vram for gart page table
	122	*
	123	* @rdev: radeon_device pointer
	124	*
	125	* Allocate video memory for GART page table
	126	* (pcie r4xx, r5xx+). These asics require the
	127	* gart table to be in video memory.
	128	* Returns 0 for success, error for failure.
	129	*/
771fe6b9 JG	130	int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
771fe6b9 JG	131	{
771fe6b9 JG	132	int r;
771fe6b9 JG	133
c9a1be96	134	if (rdev->gart.robj == NULL) {
441921d5	135	r = radeon_bo_create(rdev, rdev->gart.table_size,
268b2510	136	PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
831b6966	137	0, NULL, NULL, &rdev->gart.robj);
771fe6b9 JG	138	if (r) {
	139	return r;
	140	}
	141	}
4aac0473 JG	142	return 0;
	143	}
	144
03eec93b AD	145	/**
	146	* radeon_gart_table_vram_pin - pin gart page table in vram
	147	*
	148	* @rdev: radeon_device pointer
	149	*
	150	* Pin the GART page table in vram so it will not be moved
	151	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	152	* gart table to be in video memory.
	153	* Returns 0 for success, error for failure.
	154	*/
4aac0473 JG	155	int radeon_gart_table_vram_pin(struct radeon_device *rdev)
	156	{
	157	uint64_t gpu_addr;
	158	int r;
	159
c9a1be96	160	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	161	if (unlikely(r != 0))
771fe6b9	162	return r;
c9a1be96	163	r = radeon_bo_pin(rdev->gart.robj,
4c788679	164	RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
771fe6b9	165	if (r) {
c9a1be96	166	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9 JG	167	return r;
771fe6b9 JG	168	}
c9a1be96	169	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
4c788679	170	if (r)
c9a1be96 JG	171	radeon_bo_unpin(rdev->gart.robj);
c9a1be96 JG	172	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9	173	rdev->gart.table_addr = gpu_addr;
5636d2f8 MD	174
	175	if (!r) {
	176	int i;
	177
	178	/* We might have dropped some GART table updates while it wasn't
	179	* mapped, restore all entries
	180	*/
	181	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
	182	radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
	183	mb();
	184	radeon_gart_tlb_flush(rdev);
	185	}
	186
4c788679	187	return r;
771fe6b9 JG	188	}
771fe6b9 JG	189
03eec93b AD	190	/**
	191	* radeon_gart_table_vram_unpin - unpin gart page table in vram
	192	*
	193	* @rdev: radeon_device pointer
	194	*
	195	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	196	* These asics require the gart table to be in video memory.
	197	*/
c9a1be96	198	void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
771fe6b9	199	{
4c788679 JG	200	int r;
4c788679 JG	201
c9a1be96	202	if (rdev->gart.robj == NULL) {
771fe6b9 JG	203	return;
771fe6b9 JG	204	}
c9a1be96	205	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	206	if (likely(r == 0)) {
c9a1be96 JG	207	radeon_bo_kunmap(rdev->gart.robj);
	208	radeon_bo_unpin(rdev->gart.robj);
	209	radeon_bo_unreserve(rdev->gart.robj);
	210	rdev->gart.ptr = NULL;
	211	}
	212	}
	213
03eec93b AD	214	/**
	215	* radeon_gart_table_vram_free - free gart page table vram
	216	*
	217	* @rdev: radeon_device pointer
	218	*
	219	* Free the video memory used for the GART page table
	220	* (pcie r4xx, r5xx+). These asics require the gart table to
	221	* be in video memory.
	222	*/
c9a1be96 JG	223	void radeon_gart_table_vram_free(struct radeon_device *rdev)
	224	{
	225	if (rdev->gart.robj == NULL) {
	226	return;
4c788679	227	}
c9a1be96	228	radeon_bo_unref(&rdev->gart.robj);
771fe6b9 JG	229	}
771fe6b9 JG	230
771fe6b9 JG	231	/*
	232	* Common gart functions.
	233	*/
03eec93b AD	234	/**
	235	* radeon_gart_unbind - unbind pages from the gart page table
	236	*
	237	* @rdev: radeon_device pointer
	238	* @offset: offset into the GPU's gart aperture
	239	* @pages: number of pages to unbind
	240	*
	241	* Unbinds the requested pages from the gart page table and
	242	* replaces them with the dummy page (all asics).
	243	*/
771fe6b9 JG	244	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
	245	int pages)
	246	{
	247	unsigned t;
	248	unsigned p;
	249	int i, j;
	250
	251	if (!rdev->gart.ready) {
fcf4de5a	252	WARN(1, "trying to unbind memory from uninitialized GART !\n");
771fe6b9 JG	253	return;
771fe6b9 JG	254	}
a77f1718 MT	255	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	256	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	257	for (i = 0; i < pages; i++, p++) {
771fe6b9 JG	258	if (rdev->gart.pages[p]) {
771fe6b9	259	rdev->gart.pages[p] = NULL;
a77f1718	260	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
cb658906	261	rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
c9a1be96	262	if (rdev->gart.ptr) {
cb658906 MD	263	radeon_gart_set_page(rdev, t,
cb658906 MD	264	rdev->dummy_page.entry);
c9a1be96	265	}
771fe6b9 JG	266	}
	267	}
	268	}
233709d2 MD	269	if (rdev->gart.ptr) {
	270	mb();
	271	radeon_gart_tlb_flush(rdev);
	272	}
771fe6b9 JG	273	}
771fe6b9 JG	274
03eec93b AD	275	/**
	276	* radeon_gart_bind - bind pages into the gart page table
	277	*
	278	* @rdev: radeon_device pointer
	279	* @offset: offset into the GPU's gart aperture
	280	* @pages: number of pages to bind
	281	* @pagelist: pages to bind
	282	* @dma_addr: DMA addresses of pages
77497f27	283	* @flags: RADEON_GART_PAGE_* flags
03eec93b AD	284	*
	285	* Binds the requested pages to the gart page table
	286	* (all asics).
	287	* Returns 0 for success, -EINVAL for failure.
	288	*/
771fe6b9	289	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
77497f27 MD	290	int pages, struct page *pagelist, dma_addr_t dma_addr,
77497f27 MD	291	uint32_t flags)
771fe6b9 JG	292	{
	293	unsigned t;
	294	unsigned p;
cb658906	295	uint64_t page_base, page_entry;
771fe6b9 JG	296	int i, j;
	297
	298	if (!rdev->gart.ready) {
fcf4de5a	299	WARN(1, "trying to bind memory to uninitialized GART !\n");
771fe6b9 JG	300	return -EINVAL;
771fe6b9 JG	301	}
a77f1718 MT	302	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	303	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	304
771fe6b9 JG	305	for (i = 0; i < pages; i++, p++) {
771fe6b9	306	rdev->gart.pages[p] = pagelist[i];
cb658906 MD	307	page_base = dma_addr[i];
	308	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
	309	page_entry = radeon_gart_get_page_entry(page_base, flags);
	310	rdev->gart.pages_entry[t] = page_entry;
	311	if (rdev->gart.ptr) {
	312	radeon_gart_set_page(rdev, t, page_entry);
c9a1be96	313	}
cb658906	314	page_base += RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	315	}
771fe6b9 JG	316	}
233709d2 MD	317	if (rdev->gart.ptr) {
	318	mb();
	319	radeon_gart_tlb_flush(rdev);
	320	}
771fe6b9 JG	321	return 0;
	322	}
	323
03eec93b AD	324	/**
	325	* radeon_gart_init - init the driver info for managing the gart
	326	*
	327	* @rdev: radeon_device pointer
	328	*
	329	* Allocate the dummy page and init the gart driver info (all asics).
	330	* Returns 0 for success, error for failure.
	331	*/
771fe6b9 JG	332	int radeon_gart_init(struct radeon_device *rdev)
771fe6b9 JG	333	{
82568565 DA	334	int r, i;
82568565 DA	335
771fe6b9 JG	336	if (rdev->gart.pages) {
	337	return 0;
	338	}
a77f1718 MT	339	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
a77f1718 MT	340	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
771fe6b9 JG	341	DRM_ERROR("Page size is smaller than GPU page size!\n");
	342	return -EINVAL;
	343	}
82568565 DA	344	r = radeon_dummy_page_init(rdev);
	345	if (r)
	346	return r;
771fe6b9 JG	347	/* Compute table size */
771fe6b9 JG	348	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
a77f1718	349	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	350	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
	351	rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	352	/* Allocate pages table */
fad953ce KC	353	rdev->gart.pages = vzalloc(array_size(sizeof(void *),
fad953ce KC	354	rdev->gart.num_cpu_pages));
771fe6b9 JG	355	if (rdev->gart.pages == NULL) {
	356	radeon_gart_fini(rdev);
	357	return -ENOMEM;
	358	}
42bc47b3 KC	359	rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t),
42bc47b3 KC	360	rdev->gart.num_gpu_pages));
cb658906 MD	361	if (rdev->gart.pages_entry == NULL) {
	362	radeon_gart_fini(rdev);
	363	return -ENOMEM;
	364	}
82568565	365	/* set GART entry to point to the dummy page by default */
cb658906 MD	366	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
cb658906 MD	367	rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
771fe6b9 JG	368	return 0;
	369	}
	370
03eec93b AD	371	/**
	372	* radeon_gart_fini - tear down the driver info for managing the gart
	373	*
	374	* @rdev: radeon_device pointer
	375	*
	376	* Tear down the gart driver info and free the dummy page (all asics).
	377	*/
771fe6b9 JG	378	void radeon_gart_fini(struct radeon_device *rdev)
771fe6b9 JG	379	{
cb658906	380	if (rdev->gart.ready) {
771fe6b9 JG	381	/* unbind pages */
	382	radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	383	}
	384	rdev->gart.ready = false;
59240ee3	385	vfree(rdev->gart.pages);
cb658906	386	vfree(rdev->gart.pages_entry);
771fe6b9	387	rdev->gart.pages = NULL;
cb658906	388	rdev->gart.pages_entry = NULL;
92656d70 AD	389
92656d70 AD	390	radeon_dummy_page_fini(rdev);
771fe6b9	391	}