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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
64a9dfc4 MY |
32 | #include <drm/ttm/ttm_bo_api.h> |
33 | #include <drm/ttm/ttm_bo_driver.h> | |
34 | #include <drm/ttm/ttm_placement.h> | |
35 | #include <drm/ttm/ttm_module.h> | |
36 | #include <drm/ttm/ttm_page_alloc.h> | |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
4cfe7629 | 41 | #include <linux/swiotlb.h> |
f72a113a CK |
42 | #include <linux/swap.h> |
43 | #include <linux/pagemap.h> | |
2014b569 | 44 | #include <linux/debugfs.h> |
771fe6b9 JG |
45 | #include "radeon_reg.h" |
46 | #include "radeon.h" | |
47 | ||
fa8a1238 | 48 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 49 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 50 | |
771fe6b9 JG |
51 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
52 | { | |
53 | struct radeon_mman *mman; | |
54 | struct radeon_device *rdev; | |
55 | ||
56 | mman = container_of(bdev, struct radeon_mman, bdev); | |
57 | rdev = container_of(mman, struct radeon_device, mman); | |
58 | return rdev; | |
59 | } | |
60 | ||
771fe6b9 JG |
61 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
62 | { | |
63 | return 0; | |
64 | } | |
65 | ||
66 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
67 | struct ttm_mem_type_manager *man) | |
68 | { | |
69 | struct radeon_device *rdev; | |
70 | ||
71 | rdev = radeon_get_rdev(bdev); | |
72 | ||
73 | switch (type) { | |
74 | case TTM_PL_SYSTEM: | |
75 | /* System memory */ | |
76 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
77 | man->available_caching = TTM_PL_MASK_CACHING; | |
78 | man->default_caching = TTM_PL_FLAG_CACHED; | |
79 | break; | |
80 | case TTM_PL_TT: | |
d961db75 | 81 | man->func = &ttm_bo_manager_func; |
d594e46a | 82 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
83 | man->available_caching = TTM_PL_MASK_CACHING; |
84 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 85 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
a7fb8a23 | 86 | #if IS_ENABLED(CONFIG_AGP) |
771fe6b9 | 87 | if (rdev->flags & RADEON_IS_AGP) { |
d9906753 | 88 | if (!rdev->ddev->agp) { |
771fe6b9 JG |
89 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
90 | (unsigned)type); | |
91 | return -EINVAL; | |
92 | } | |
55c93278 | 93 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 94 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
95 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
96 | TTM_PL_FLAG_WC; | |
97 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 98 | } |
0c321c79 | 99 | #endif |
771fe6b9 JG |
100 | break; |
101 | case TTM_PL_VRAM: | |
102 | /* "On-card" video ram */ | |
d961db75 | 103 | man->func = &ttm_bo_manager_func; |
d594e46a | 104 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 105 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
106 | TTM_MEMTYPE_FLAG_MAPPABLE; |
107 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
108 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
109 | break; |
110 | default: | |
111 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
112 | return -EINVAL; | |
113 | } | |
114 | return 0; | |
115 | } | |
116 | ||
312ea8da JG |
117 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
118 | struct ttm_placement *placement) | |
771fe6b9 | 119 | { |
46886dbf | 120 | static const struct ttm_place placements = { |
f1217ed0 CK |
121 | .fpfn = 0, |
122 | .lpfn = 0, | |
123 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | |
124 | }; | |
125 | ||
d03d8589 | 126 | struct radeon_bo *rbo; |
d03d8589 JG |
127 | |
128 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
d03d8589 JG |
129 | placement->placement = &placements; |
130 | placement->busy_placement = &placements; | |
131 | placement->num_placement = 1; | |
132 | placement->num_busy_placement = 1; | |
133 | return; | |
134 | } | |
135 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 136 | switch (bo->mem.mem_type) { |
312ea8da | 137 | case TTM_PL_VRAM: |
5e5c21ca | 138 | if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) |
9270eb1b | 139 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
2a85aedd MD |
140 | else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && |
141 | bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { | |
142 | unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
143 | int i; | |
144 | ||
145 | /* Try evicting to the CPU inaccessible part of VRAM | |
146 | * first, but only set GTT as busy placement, so this | |
147 | * BO will be evicted to GTT rather than causing other | |
148 | * BOs to be evicted from VRAM | |
149 | */ | |
150 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | | |
151 | RADEON_GEM_DOMAIN_GTT); | |
152 | rbo->placement.num_busy_placement = 0; | |
153 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
154 | if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { | |
ce4b4f22 MD |
155 | if (rbo->placements[i].fpfn < fpfn) |
156 | rbo->placements[i].fpfn = fpfn; | |
2a85aedd MD |
157 | } else { |
158 | rbo->placement.busy_placement = | |
159 | &rbo->placements[i]; | |
160 | rbo->placement.num_busy_placement = 1; | |
161 | } | |
162 | } | |
163 | } else | |
9270eb1b | 164 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
312ea8da JG |
165 | break; |
166 | case TTM_PL_TT: | |
771fe6b9 | 167 | default: |
312ea8da | 168 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 169 | } |
eaa5fd1a | 170 | *placement = rbo->placement; |
771fe6b9 JG |
171 | } |
172 | ||
173 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
174 | { | |
acb46527 DH |
175 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
176 | ||
b5dcec69 JG |
177 | if (radeon_ttm_tt_has_userptr(bo->ttm)) |
178 | return -EPERM; | |
d9a1f0b4 DH |
179 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, |
180 | filp->private_data); | |
771fe6b9 JG |
181 | } |
182 | ||
183 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
184 | struct ttm_mem_reg *new_mem) | |
185 | { | |
186 | struct ttm_mem_reg *old_mem = &bo->mem; | |
187 | ||
188 | BUG_ON(old_mem->mm_node != NULL); | |
189 | *old_mem = *new_mem; | |
190 | new_mem->mm_node = NULL; | |
191 | } | |
192 | ||
193 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
97a875cb | 194 | bool evict, bool no_wait_gpu, |
9d87fa21 JG |
195 | struct ttm_mem_reg *new_mem, |
196 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
197 | { |
198 | struct radeon_device *rdev; | |
199 | uint64_t old_start, new_start; | |
876dc9f3 | 200 | struct radeon_fence *fence; |
57d20a43 | 201 | unsigned num_pages; |
876dc9f3 | 202 | int r, ridx; |
771fe6b9 JG |
203 | |
204 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 205 | ridx = radeon_copy_ring_index(rdev); |
13f479b9 CK |
206 | old_start = (u64)old_mem->start << PAGE_SHIFT; |
207 | new_start = (u64)new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
208 | |
209 | switch (old_mem->mem_type) { | |
210 | case TTM_PL_VRAM: | |
d594e46a | 211 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
212 | break; |
213 | case TTM_PL_TT: | |
d594e46a | 214 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
215 | break; |
216 | default: | |
217 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
218 | return -EINVAL; | |
219 | } | |
220 | switch (new_mem->mem_type) { | |
221 | case TTM_PL_VRAM: | |
d594e46a | 222 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
223 | break; |
224 | case TTM_PL_TT: | |
d594e46a | 225 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
226 | break; |
227 | default: | |
228 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
229 | return -EINVAL; | |
230 | } | |
876dc9f3 | 231 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 232 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
233 | return -EINVAL; |
234 | } | |
003cefe0 AD |
235 | |
236 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
237 | ||
57d20a43 CK |
238 | num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
239 | fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv); | |
240 | if (IS_ERR(fence)) | |
241 | return PTR_ERR(fence); | |
242 | ||
74561cd4 | 243 | r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); |
771fe6b9 JG |
244 | radeon_fence_unref(&fence); |
245 | return r; | |
246 | } | |
247 | ||
248 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 249 | bool evict, bool interruptible, |
97a875cb | 250 | bool no_wait_gpu, |
771fe6b9 JG |
251 | struct ttm_mem_reg *new_mem) |
252 | { | |
c13c55d6 | 253 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
254 | struct radeon_device *rdev; |
255 | struct ttm_mem_reg *old_mem = &bo->mem; | |
256 | struct ttm_mem_reg tmp_mem; | |
f1217ed0 | 257 | struct ttm_place placements; |
312ea8da | 258 | struct ttm_placement placement; |
771fe6b9 JG |
259 | int r; |
260 | ||
261 | rdev = radeon_get_rdev(bo->bdev); | |
262 | tmp_mem = *new_mem; | |
263 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
264 | placement.num_placement = 1; |
265 | placement.placement = &placements; | |
266 | placement.num_busy_placement = 1; | |
267 | placement.busy_placement = &placements; | |
f1217ed0 CK |
268 | placements.fpfn = 0; |
269 | placements.lpfn = 0; | |
270 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 271 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
272 | if (unlikely(r)) { |
273 | return r; | |
274 | } | |
df67bed9 DA |
275 | |
276 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
277 | if (unlikely(r)) { | |
278 | goto out_cleanup; | |
279 | } | |
280 | ||
993baf15 | 281 | r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); |
771fe6b9 JG |
282 | if (unlikely(r)) { |
283 | goto out_cleanup; | |
284 | } | |
97a875cb | 285 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
286 | if (unlikely(r)) { |
287 | goto out_cleanup; | |
288 | } | |
3e98d829 | 289 | r = ttm_bo_move_ttm(bo, &ctx, new_mem); |
771fe6b9 | 290 | out_cleanup: |
42311ff9 | 291 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
292 | return r; |
293 | } | |
294 | ||
295 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 296 | bool evict, bool interruptible, |
97a875cb | 297 | bool no_wait_gpu, |
771fe6b9 JG |
298 | struct ttm_mem_reg *new_mem) |
299 | { | |
c13c55d6 | 300 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
301 | struct radeon_device *rdev; |
302 | struct ttm_mem_reg *old_mem = &bo->mem; | |
303 | struct ttm_mem_reg tmp_mem; | |
312ea8da | 304 | struct ttm_placement placement; |
f1217ed0 | 305 | struct ttm_place placements; |
771fe6b9 JG |
306 | int r; |
307 | ||
308 | rdev = radeon_get_rdev(bo->bdev); | |
309 | tmp_mem = *new_mem; | |
310 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
311 | placement.num_placement = 1; |
312 | placement.placement = &placements; | |
313 | placement.num_busy_placement = 1; | |
314 | placement.busy_placement = &placements; | |
f1217ed0 CK |
315 | placements.fpfn = 0; |
316 | placements.lpfn = 0; | |
317 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 318 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
319 | if (unlikely(r)) { |
320 | return r; | |
321 | } | |
3e98d829 | 322 | r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); |
771fe6b9 JG |
323 | if (unlikely(r)) { |
324 | goto out_cleanup; | |
325 | } | |
97a875cb | 326 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
327 | if (unlikely(r)) { |
328 | goto out_cleanup; | |
329 | } | |
330 | out_cleanup: | |
42311ff9 | 331 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
332 | return r; |
333 | } | |
334 | ||
2823f4f0 CK |
335 | static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, |
336 | struct ttm_operation_ctx *ctx, | |
337 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
338 | { |
339 | struct radeon_device *rdev; | |
e1a575ad | 340 | struct radeon_bo *rbo; |
771fe6b9 JG |
341 | struct ttm_mem_reg *old_mem = &bo->mem; |
342 | int r; | |
343 | ||
2823f4f0 | 344 | r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); |
88932a7b CK |
345 | if (r) |
346 | return r; | |
347 | ||
e1a575ad MD |
348 | /* Can't move a pinned BO */ |
349 | rbo = container_of(bo, struct radeon_bo, tbo); | |
350 | if (WARN_ON_ONCE(rbo->pin_count > 0)) | |
351 | return -EINVAL; | |
352 | ||
771fe6b9 JG |
353 | rdev = radeon_get_rdev(bo->bdev); |
354 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
355 | radeon_move_null(bo, new_mem); | |
356 | return 0; | |
357 | } | |
358 | if ((old_mem->mem_type == TTM_PL_TT && | |
359 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
360 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
361 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 362 | /* bind is enough */ |
771fe6b9 JG |
363 | radeon_move_null(bo, new_mem); |
364 | return 0; | |
365 | } | |
27cd7769 AD |
366 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
367 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 368 | /* use memcpy */ |
1ab2e105 | 369 | goto memcpy; |
771fe6b9 JG |
370 | } |
371 | ||
372 | if (old_mem->mem_type == TTM_PL_VRAM && | |
373 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
2823f4f0 CK |
374 | r = radeon_move_vram_ram(bo, evict, ctx->interruptible, |
375 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 JG |
376 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
377 | new_mem->mem_type == TTM_PL_VRAM) { | |
2823f4f0 CK |
378 | r = radeon_move_ram_vram(bo, evict, ctx->interruptible, |
379 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 | 380 | } else { |
2823f4f0 CK |
381 | r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, |
382 | new_mem, old_mem); | |
771fe6b9 | 383 | } |
1ab2e105 MD |
384 | |
385 | if (r) { | |
386 | memcpy: | |
3e98d829 | 387 | r = ttm_bo_move_memcpy(bo, ctx, new_mem); |
67e8e3f9 MO |
388 | if (r) { |
389 | return r; | |
390 | } | |
1ab2e105 | 391 | } |
67e8e3f9 MO |
392 | |
393 | /* update statistics */ | |
394 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
395 | return 0; | |
771fe6b9 JG |
396 | } |
397 | ||
0a2d50e3 JG |
398 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
399 | { | |
400 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
401 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
402 | ||
403 | mem->bus.addr = NULL; | |
404 | mem->bus.offset = 0; | |
405 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
406 | mem->bus.base = 0; | |
407 | mem->bus.is_iomem = false; | |
408 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
409 | return -EINVAL; | |
410 | switch (mem->mem_type) { | |
411 | case TTM_PL_SYSTEM: | |
412 | /* system memory */ | |
413 | return 0; | |
414 | case TTM_PL_TT: | |
a7fb8a23 | 415 | #if IS_ENABLED(CONFIG_AGP) |
0a2d50e3 JG |
416 | if (rdev->flags & RADEON_IS_AGP) { |
417 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 418 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 419 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 420 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
421 | } |
422 | #endif | |
423 | break; | |
424 | case TTM_PL_VRAM: | |
d961db75 | 425 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
426 | /* check if it's visible */ |
427 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
428 | return -EINVAL; | |
429 | mem->bus.base = rdev->mc.aper_base; | |
430 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
431 | #ifdef __alpha__ |
432 | /* | |
433 | * Alpha: use bus.addr to hold the ioremap() return, | |
434 | * so we can modify bus.base below. | |
435 | */ | |
436 | if (mem->placement & TTM_PL_FLAG_WC) | |
437 | mem->bus.addr = | |
438 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
439 | mem->bus.size); | |
440 | else | |
441 | mem->bus.addr = | |
442 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
443 | mem->bus.size); | |
3b2c6932 AY |
444 | if (!mem->bus.addr) |
445 | return -ENOMEM; | |
ffb57c4b JE |
446 | |
447 | /* | |
448 | * Alpha: Use just the bus offset plus | |
449 | * the hose/domain memory base for bus.base. | |
450 | * It then can be used to build PTEs for VRAM | |
451 | * access, as done in ttm_bo_vm_fault(). | |
452 | */ | |
453 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
454 | rdev->ddev->hose->dense_mem_base; | |
455 | #endif | |
0a2d50e3 JG |
456 | break; |
457 | default: | |
458 | return -EINVAL; | |
459 | } | |
460 | return 0; | |
461 | } | |
462 | ||
463 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
464 | { | |
465 | } | |
466 | ||
649bf3ca JG |
467 | /* |
468 | * TTM backend functions. | |
469 | */ | |
470 | struct radeon_ttm_tt { | |
8e7e7052 | 471 | struct ttm_dma_tt ttm; |
649bf3ca JG |
472 | struct radeon_device *rdev; |
473 | u64 offset; | |
f72a113a CK |
474 | |
475 | uint64_t userptr; | |
476 | struct mm_struct *usermm; | |
477 | uint32_t userflags; | |
649bf3ca JG |
478 | }; |
479 | ||
f72a113a CK |
480 | /* prepare the sg table with the user pages */ |
481 | static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) | |
482 | { | |
483 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
484 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
485 | unsigned pinned = 0, nents; | |
486 | int r; | |
487 | ||
488 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
489 | enum dma_data_direction direction = write ? | |
490 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
491 | ||
492 | if (current->mm != gtt->usermm) | |
493 | return -EPERM; | |
494 | ||
ddd00e33 CK |
495 | if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { |
496 | /* check that we only pin down anonymous memory | |
497 | to prevent problems with writeback */ | |
498 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; | |
499 | struct vm_area_struct *vma; | |
500 | vma = find_vma(gtt->usermm, gtt->userptr); | |
501 | if (!vma || vma->vm_file || vma->vm_end < end) | |
502 | return -EPERM; | |
503 | } | |
504 | ||
f72a113a CK |
505 | do { |
506 | unsigned num_pages = ttm->num_pages - pinned; | |
507 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
508 | struct page **pages = ttm->pages + pinned; | |
509 | ||
768ae309 LS |
510 | r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, |
511 | pages, NULL); | |
f72a113a CK |
512 | if (r < 0) |
513 | goto release_pages; | |
514 | ||
515 | pinned += r; | |
516 | ||
517 | } while (pinned < ttm->num_pages); | |
518 | ||
519 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, | |
520 | ttm->num_pages << PAGE_SHIFT, | |
521 | GFP_KERNEL); | |
522 | if (r) | |
523 | goto release_sg; | |
524 | ||
525 | r = -ENOMEM; | |
526 | nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
527 | if (nents != ttm->sg->nents) | |
528 | goto release_sg; | |
529 | ||
530 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
531 | gtt->ttm.dma_address, ttm->num_pages); | |
532 | ||
533 | return 0; | |
534 | ||
535 | release_sg: | |
536 | kfree(ttm->sg); | |
537 | ||
538 | release_pages: | |
c6f92f9f | 539 | release_pages(ttm->pages, pinned); |
f72a113a CK |
540 | return r; |
541 | } | |
542 | ||
543 | static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |
544 | { | |
545 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
546 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
db12973c | 547 | struct sg_page_iter sg_iter; |
f72a113a CK |
548 | |
549 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
550 | enum dma_data_direction direction = write ? | |
551 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
552 | ||
863653fe CK |
553 | /* double check that we don't free the table twice */ |
554 | if (!ttm->sg->sgl) | |
555 | return; | |
556 | ||
f72a113a CK |
557 | /* free the sg table and pages again */ |
558 | dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
559 | ||
db12973c | 560 | for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { |
561 | struct page *page = sg_page_iter_page(&sg_iter); | |
f72a113a CK |
562 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) |
563 | set_page_dirty(page); | |
564 | ||
565 | mark_page_accessed(page); | |
09cbfeaf | 566 | put_page(page); |
f72a113a CK |
567 | } |
568 | ||
569 | sg_free_table(ttm->sg); | |
570 | } | |
571 | ||
649bf3ca JG |
572 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
573 | struct ttm_mem_reg *bo_mem) | |
574 | { | |
8e7e7052 | 575 | struct radeon_ttm_tt *gtt = (void*)ttm; |
77497f27 MD |
576 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
577 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
578 | int r; |
579 | ||
f72a113a CK |
580 | if (gtt->userptr) { |
581 | radeon_ttm_tt_pin_userptr(ttm); | |
582 | flags &= ~RADEON_GART_PAGE_WRITE; | |
583 | } | |
584 | ||
649bf3ca JG |
585 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
586 | if (!ttm->num_pages) { | |
587 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
588 | ttm->num_pages, bo_mem, ttm); | |
589 | } | |
77497f27 MD |
590 | if (ttm->caching_state == tt_cached) |
591 | flags |= RADEON_GART_PAGE_SNOOP; | |
592 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, | |
593 | ttm->pages, gtt->ttm.dma_address, flags); | |
649bf3ca JG |
594 | if (r) { |
595 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
596 | ttm->num_pages, (unsigned)gtt->offset); | |
597 | return r; | |
598 | } | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
603 | { | |
8e7e7052 | 604 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 605 | |
649bf3ca | 606 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
f72a113a CK |
607 | |
608 | if (gtt->userptr) | |
609 | radeon_ttm_tt_unpin_userptr(ttm); | |
610 | ||
649bf3ca JG |
611 | return 0; |
612 | } | |
613 | ||
614 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
615 | { | |
8e7e7052 | 616 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 617 | |
8e7e7052 | 618 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
619 | kfree(gtt); |
620 | } | |
621 | ||
622 | static struct ttm_backend_func radeon_backend_func = { | |
623 | .bind = &radeon_ttm_backend_bind, | |
624 | .unbind = &radeon_ttm_backend_unbind, | |
625 | .destroy = &radeon_ttm_backend_destroy, | |
626 | }; | |
627 | ||
dde5da23 CK |
628 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, |
629 | uint32_t page_flags) | |
649bf3ca JG |
630 | { |
631 | struct radeon_device *rdev; | |
632 | struct radeon_ttm_tt *gtt; | |
633 | ||
dde5da23 | 634 | rdev = radeon_get_rdev(bo->bdev); |
a7fb8a23 | 635 | #if IS_ENABLED(CONFIG_AGP) |
649bf3ca | 636 | if (rdev->flags & RADEON_IS_AGP) { |
dde5da23 CK |
637 | return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, |
638 | page_flags); | |
649bf3ca JG |
639 | } |
640 | #endif | |
641 | ||
642 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
643 | if (gtt == NULL) { | |
644 | return NULL; | |
645 | } | |
8e7e7052 | 646 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 647 | gtt->rdev = rdev; |
dde5da23 | 648 | if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { |
8e7e7052 | 649 | kfree(gtt); |
649bf3ca JG |
650 | return NULL; |
651 | } | |
8e7e7052 | 652 | return >t->ttm.ttm; |
649bf3ca JG |
653 | } |
654 | ||
3840a656 CK |
655 | static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) |
656 | { | |
657 | if (!ttm || ttm->func != &radeon_backend_func) | |
658 | return NULL; | |
659 | return (struct radeon_ttm_tt *)ttm; | |
660 | } | |
661 | ||
d0cef9fa RH |
662 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm, |
663 | struct ttm_operation_ctx *ctx) | |
c52494f6 | 664 | { |
3840a656 | 665 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
c52494f6 | 666 | struct radeon_device *rdev; |
40f5cf99 | 667 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 | 668 | |
3840a656 | 669 | if (gtt && gtt->userptr) { |
69ee2410 | 670 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
f72a113a CK |
671 | if (!ttm->sg) |
672 | return -ENOMEM; | |
673 | ||
674 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
675 | ttm->state = tt_unbound; | |
676 | return 0; | |
677 | } | |
678 | ||
40f5cf99 AD |
679 | if (slave && ttm->sg) { |
680 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
681 | gtt->ttm.dma_address, ttm->num_pages); | |
682 | ttm->state = tt_unbound; | |
683 | return 0; | |
684 | } | |
685 | ||
c52494f6 | 686 | rdev = radeon_get_rdev(ttm->bdev); |
a7fb8a23 | 687 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac | 688 | if (rdev->flags & RADEON_IS_AGP) { |
d0cef9fa | 689 | return ttm_agp_tt_populate(ttm, ctx); |
dea7e0ac JG |
690 | } |
691 | #endif | |
c52494f6 KRW |
692 | |
693 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 694 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
d0cef9fa | 695 | return ttm_dma_populate(>t->ttm, rdev->dev, ctx); |
c52494f6 KRW |
696 | } |
697 | #endif | |
698 | ||
d0cef9fa | 699 | return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); |
c52494f6 KRW |
700 | } |
701 | ||
702 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
703 | { | |
704 | struct radeon_device *rdev; | |
3840a656 | 705 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
40f5cf99 AD |
706 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
707 | ||
3840a656 | 708 | if (gtt && gtt->userptr) { |
f72a113a CK |
709 | kfree(ttm->sg); |
710 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
711 | return; | |
712 | } | |
713 | ||
40f5cf99 AD |
714 | if (slave) |
715 | return; | |
c52494f6 KRW |
716 | |
717 | rdev = radeon_get_rdev(ttm->bdev); | |
a7fb8a23 | 718 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac JG |
719 | if (rdev->flags & RADEON_IS_AGP) { |
720 | ttm_agp_tt_unpopulate(ttm); | |
721 | return; | |
722 | } | |
723 | #endif | |
c52494f6 KRW |
724 | |
725 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 726 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
8e7e7052 | 727 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
728 | return; |
729 | } | |
730 | #endif | |
731 | ||
f7871fd1 | 732 | ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); |
c52494f6 | 733 | } |
649bf3ca | 734 | |
f72a113a CK |
735 | int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
736 | uint32_t flags) | |
737 | { | |
3840a656 | 738 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
739 | |
740 | if (gtt == NULL) | |
741 | return -EINVAL; | |
742 | ||
743 | gtt->userptr = addr; | |
744 | gtt->usermm = current->mm; | |
745 | gtt->userflags = flags; | |
746 | return 0; | |
747 | } | |
748 | ||
749 | bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) | |
750 | { | |
3840a656 | 751 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
752 | |
753 | if (gtt == NULL) | |
754 | return false; | |
755 | ||
756 | return !!gtt->userptr; | |
757 | } | |
758 | ||
759 | bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) | |
760 | { | |
3840a656 | 761 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
762 | |
763 | if (gtt == NULL) | |
764 | return false; | |
765 | ||
766 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
767 | } | |
768 | ||
771fe6b9 | 769 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 770 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
771 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
772 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
771fe6b9 JG |
773 | .invalidate_caches = &radeon_invalidate_caches, |
774 | .init_mem_type = &radeon_init_mem_type, | |
a2ab19fe | 775 | .eviction_valuable = ttm_bo_eviction_valuable, |
771fe6b9 JG |
776 | .evict_flags = &radeon_evict_flags, |
777 | .move = &radeon_bo_move, | |
778 | .verify_access = &radeon_verify_access, | |
e024e110 DA |
779 | .move_notify = &radeon_bo_move_notify, |
780 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
781 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
782 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
783 | }; |
784 | ||
785 | int radeon_ttm_init(struct radeon_device *rdev) | |
786 | { | |
787 | int r; | |
788 | ||
771fe6b9 JG |
789 | /* No others user of address space so set it to 0 */ |
790 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
44d847b7 DH |
791 | &radeon_bo_driver, |
792 | rdev->ddev->anon_inode->i_mapping, | |
ad49f501 | 793 | rdev->need_dma32); |
771fe6b9 JG |
794 | if (r) { |
795 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
796 | return r; | |
797 | } | |
0a0c7596 | 798 | rdev->mman.initialized = true; |
4c788679 | 799 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 800 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
801 | if (r) { |
802 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
803 | return r; | |
804 | } | |
14eedc32 LK |
805 | /* Change the size here instead of the init above so only lpfn is affected */ |
806 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
807 | ||
441921d5 | 808 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
831b6966 | 809 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
4aa5b92f | 810 | NULL, &rdev->stolen_vga_memory); |
771fe6b9 JG |
811 | if (r) { |
812 | return r; | |
813 | } | |
4aa5b92f | 814 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); |
4c788679 JG |
815 | if (r) |
816 | return r; | |
4aa5b92f KR |
817 | r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
818 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
771fe6b9 | 819 | if (r) { |
4aa5b92f | 820 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
821 | return r; |
822 | } | |
823 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 824 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
4c788679 | 825 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 826 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
827 | if (r) { |
828 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
829 | return r; | |
830 | } | |
831 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 832 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
833 | |
834 | r = radeon_ttm_debugfs_init(rdev); | |
835 | if (r) { | |
836 | DRM_ERROR("Failed to init debugfs\n"); | |
837 | return r; | |
838 | } | |
771fe6b9 JG |
839 | return 0; |
840 | } | |
841 | ||
842 | void radeon_ttm_fini(struct radeon_device *rdev) | |
843 | { | |
4c788679 JG |
844 | int r; |
845 | ||
0a0c7596 JG |
846 | if (!rdev->mman.initialized) |
847 | return; | |
2014b569 | 848 | radeon_ttm_debugfs_fini(rdev); |
4aa5b92f KR |
849 | if (rdev->stolen_vga_memory) { |
850 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); | |
4c788679 | 851 | if (r == 0) { |
4aa5b92f KR |
852 | radeon_bo_unpin(rdev->stolen_vga_memory); |
853 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
4c788679 | 854 | } |
4aa5b92f | 855 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
856 | } |
857 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
858 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
859 | ttm_bo_device_release(&rdev->mman.bdev); | |
860 | radeon_gart_fini(rdev); | |
0a0c7596 | 861 | rdev->mman.initialized = false; |
771fe6b9 JG |
862 | DRM_INFO("radeon: ttm finalized\n"); |
863 | } | |
864 | ||
53595338 DA |
865 | /* this should only be called at bootup or when userspace |
866 | * isn't running */ | |
867 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
868 | { | |
869 | struct ttm_mem_type_manager *man; | |
870 | ||
871 | if (!rdev->mman.initialized) | |
872 | return; | |
873 | ||
874 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
875 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
876 | man->size = size >> PAGE_SHIFT; | |
877 | } | |
878 | ||
771fe6b9 | 879 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 880 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 | 881 | |
2bfb0b67 | 882 | static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) |
771fe6b9 JG |
883 | { |
884 | struct ttm_buffer_object *bo; | |
5876dd24 | 885 | struct radeon_device *rdev; |
2bfb0b67 | 886 | vm_fault_t ret; |
771fe6b9 | 887 | |
11bac800 | 888 | bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; |
771fe6b9 JG |
889 | if (bo == NULL) { |
890 | return VM_FAULT_NOPAGE; | |
891 | } | |
5876dd24 | 892 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 893 | down_read(&rdev->pm.mclk_lock); |
2bfb0b67 | 894 | ret = ttm_vm_ops->fault(vmf); |
db7fce39 | 895 | up_read(&rdev->pm.mclk_lock); |
2bfb0b67 | 896 | return ret; |
771fe6b9 JG |
897 | } |
898 | ||
899 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
900 | { | |
771fe6b9 | 901 | int r; |
bed2dd84 TZ |
902 | struct drm_file *file_priv = filp->private_data; |
903 | struct radeon_device *rdev = file_priv->minor->dev->dev_private; | |
771fe6b9 | 904 | |
771fe6b9 JG |
905 | if (rdev == NULL) { |
906 | return -EINVAL; | |
907 | } | |
908 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
909 | if (unlikely(r != 0)) { | |
910 | return r; | |
911 | } | |
912 | if (unlikely(ttm_vm_ops == NULL)) { | |
913 | ttm_vm_ops = vma->vm_ops; | |
914 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
915 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
916 | } | |
917 | vma->vm_ops = &radeon_ttm_vm_ops; | |
918 | return 0; | |
919 | } | |
920 | ||
fa8a1238 | 921 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 922 | |
fa8a1238 DA |
923 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
924 | { | |
925 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
bbbb29ef | 926 | unsigned ttm_pl = *(int*)node->info_ent->data; |
fa8a1238 DA |
927 | struct drm_device *dev = node->minor->dev; |
928 | struct radeon_device *rdev = dev->dev_private; | |
bbbb29ef | 929 | struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; |
b5c3714f | 930 | struct drm_printer p = drm_seq_file_printer(m); |
fa8a1238 | 931 | |
bbbb29ef | 932 | man->func->debug(man, &p); |
b5c3714f | 933 | return 0; |
fa8a1238 | 934 | } |
893d6e6e | 935 | |
bbbb29ef | 936 | |
893d6e6e CK |
937 | static int ttm_pl_vram = TTM_PL_VRAM; |
938 | static int ttm_pl_tt = TTM_PL_TT; | |
939 | ||
940 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
941 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
942 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
943 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
944 | #ifdef CONFIG_SWIOTLB | |
945 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
946 | #endif | |
947 | }; | |
948 | ||
2014b569 CK |
949 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
950 | { | |
951 | struct radeon_device *rdev = inode->i_private; | |
952 | i_size_write(inode, rdev->mc.mc_vram_size); | |
953 | filep->private_data = inode->i_private; | |
954 | return 0; | |
955 | } | |
956 | ||
957 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
958 | size_t size, loff_t *pos) | |
959 | { | |
960 | struct radeon_device *rdev = f->private_data; | |
961 | ssize_t result = 0; | |
962 | int r; | |
963 | ||
964 | if (size & 0x3 || *pos & 0x3) | |
965 | return -EINVAL; | |
966 | ||
967 | while (size) { | |
968 | unsigned long flags; | |
969 | uint32_t value; | |
970 | ||
971 | if (*pos >= rdev->mc.mc_vram_size) | |
972 | return result; | |
973 | ||
974 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
975 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
976 | if (rdev->family >= CHIP_CEDAR) | |
977 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
978 | value = RREG32(RADEON_MM_DATA); | |
979 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
980 | ||
981 | r = put_user(value, (uint32_t *)buf); | |
982 | if (r) | |
983 | return r; | |
984 | ||
985 | result += 4; | |
986 | buf += 4; | |
987 | *pos += 4; | |
988 | size -= 4; | |
989 | } | |
990 | ||
991 | return result; | |
992 | } | |
993 | ||
994 | static const struct file_operations radeon_ttm_vram_fops = { | |
995 | .owner = THIS_MODULE, | |
996 | .open = radeon_ttm_vram_open, | |
997 | .read = radeon_ttm_vram_read, | |
998 | .llseek = default_llseek | |
999 | }; | |
1000 | ||
dd66d20e CK |
1001 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
1002 | { | |
1003 | struct radeon_device *rdev = inode->i_private; | |
1004 | i_size_write(inode, rdev->mc.gtt_size); | |
1005 | filep->private_data = inode->i_private; | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
1010 | size_t size, loff_t *pos) | |
1011 | { | |
1012 | struct radeon_device *rdev = f->private_data; | |
1013 | ssize_t result = 0; | |
1014 | int r; | |
1015 | ||
1016 | while (size) { | |
1017 | loff_t p = *pos / PAGE_SIZE; | |
1018 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 1019 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
1020 | struct page *page; |
1021 | void *ptr; | |
1022 | ||
1023 | if (p >= rdev->gart.num_cpu_pages) | |
1024 | return result; | |
1025 | ||
1026 | page = rdev->gart.pages[p]; | |
1027 | if (page) { | |
1028 | ptr = kmap(page); | |
1029 | ptr += off; | |
1030 | ||
1031 | r = copy_to_user(buf, ptr, cur_size); | |
1032 | kunmap(rdev->gart.pages[p]); | |
1033 | } else | |
1034 | r = clear_user(buf, cur_size); | |
1035 | ||
1036 | if (r) | |
1037 | return -EFAULT; | |
1038 | ||
1039 | result += cur_size; | |
1040 | buf += cur_size; | |
1041 | *pos += cur_size; | |
1042 | size -= cur_size; | |
1043 | } | |
1044 | ||
1045 | return result; | |
1046 | } | |
1047 | ||
1048 | static const struct file_operations radeon_ttm_gtt_fops = { | |
1049 | .owner = THIS_MODULE, | |
1050 | .open = radeon_ttm_gtt_open, | |
1051 | .read = radeon_ttm_gtt_read, | |
1052 | .llseek = default_llseek | |
1053 | }; | |
1054 | ||
fa8a1238 DA |
1055 | #endif |
1056 | ||
1057 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
1058 | { | |
f4e45d02 | 1059 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
1060 | unsigned count; |
1061 | ||
1062 | struct drm_minor *minor = rdev->ddev->primary; | |
1063 | struct dentry *ent, *root = minor->debugfs_root; | |
1064 | ||
1065 | ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, | |
1066 | rdev, &radeon_ttm_vram_fops); | |
1067 | if (IS_ERR(ent)) | |
1068 | return PTR_ERR(ent); | |
1069 | rdev->mman.vram = ent; | |
1070 | ||
dd66d20e CK |
1071 | ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, |
1072 | rdev, &radeon_ttm_gtt_fops); | |
1073 | if (IS_ERR(ent)) | |
1074 | return PTR_ERR(ent); | |
1075 | rdev->mman.gtt = ent; | |
1076 | ||
2014b569 | 1077 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1078 | |
c52494f6 | 1079 | #ifdef CONFIG_SWIOTLB |
1bc3d3cc | 1080 | if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) |
893d6e6e | 1081 | --count; |
c52494f6 | 1082 | #endif |
fa8a1238 | 1083 | |
893d6e6e CK |
1084 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1085 | #else | |
1086 | ||
fa8a1238 | 1087 | return 0; |
893d6e6e | 1088 | #endif |
fa8a1238 | 1089 | } |
2014b569 CK |
1090 | |
1091 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1092 | { | |
1093 | #if defined(CONFIG_DEBUG_FS) | |
1094 | ||
1095 | debugfs_remove(rdev->mman.vram); | |
1096 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1097 | |
1098 | debugfs_remove(rdev->mman.gtt); | |
1099 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1100 | #endif |
1101 | } |