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Commit | Line | Data |
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0bbce9eb | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
4bf8e196 LP |
2 | /* |
3 | * rcar_du_drv.h -- R-Car Display Unit DRM driver | |
4 | * | |
2427b303 | 5 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
4bf8e196 LP |
6 | * |
7 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
4bf8e196 LP |
8 | */ |
9 | ||
10 | #ifndef __RCAR_DU_DRV_H__ | |
11 | #define __RCAR_DU_DRV_H__ | |
12 | ||
13 | #include <linux/kernel.h> | |
8d3f9b22 | 14 | #include <linux/wait.h> |
4bf8e196 LP |
15 | |
16 | #include "rcar_du_crtc.h" | |
cb2025d2 | 17 | #include "rcar_du_group.h" |
6d62ef3a | 18 | #include "rcar_du_vsp.h" |
4bf8e196 LP |
19 | |
20 | struct clk; | |
21 | struct device; | |
22 | struct drm_device; | |
9a47db8e | 23 | struct drm_property; |
cb2025d2 | 24 | struct rcar_du_device; |
a6cc417d | 25 | struct rcar_du_encoder; |
4bf8e196 | 26 | |
c14f63ab | 27 | #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */ |
cef0d9cf LP |
28 | #define RCAR_DU_FEATURE_VSP1_SOURCE BIT(1) /* Has inputs from VSP1 */ |
29 | #define RCAR_DU_FEATURE_INTERLACED BIT(2) /* HW supports interlaced */ | |
30 | #define RCAR_DU_FEATURE_TVM_SYNC BIT(3) /* Has TV switch/sync modes */ | |
e8355e0d | 31 | |
c14f63ab | 32 | #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ |
f66ee304 | 33 | |
ef67a902 LP |
34 | /* |
35 | * struct rcar_du_output_routing - Output routing specification | |
36 | * @possible_crtcs: bitmask of possible CRTCs for the output | |
96c02691 | 37 | * @port: device tree port number corresponding to this output route |
ef67a902 LP |
38 | * |
39 | * The DU has 5 possible outputs (DPAD0/1, LVDS0/1, TCON). Output routing data | |
40 | * specify the valid SoC outputs, which CRTCs can drive the output, and the type | |
41 | * of in-SoC encoder for the output. | |
42 | */ | |
43 | struct rcar_du_output_routing { | |
44 | unsigned int possible_crtcs; | |
96c02691 | 45 | unsigned int port; |
ef67a902 LP |
46 | }; |
47 | ||
481d342e LP |
48 | /* |
49 | * struct rcar_du_device_info - DU model-specific information | |
2427b303 | 50 | * @gen: device generation (2 or 3) |
481d342e | 51 | * @features: device features (RCAR_DU_FEATURE_*) |
e8355e0d | 52 | * @quirks: device quirks (RCAR_DU_QUIRK_*) |
5361cc7f | 53 | * @channels_mask: bit mask of available DU channels |
ef67a902 | 54 | * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*) |
90374b5c | 55 | * @num_lvds: number of internal LVDS encoders |
9fe50e64 | 56 | * @dpll_mask: bit mask of DU channels equipped with a DPLL |
b4734f43 | 57 | * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock |
481d342e LP |
58 | */ |
59 | struct rcar_du_device_info { | |
2427b303 | 60 | unsigned int gen; |
481d342e | 61 | unsigned int features; |
e8355e0d | 62 | unsigned int quirks; |
5361cc7f | 63 | unsigned int channels_mask; |
ef67a902 | 64 | struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX]; |
90374b5c | 65 | unsigned int num_lvds; |
9fe50e64 | 66 | unsigned int dpll_mask; |
b4734f43 | 67 | unsigned int lvds_clk_mask; |
481d342e LP |
68 | }; |
69 | ||
6a8c49fc | 70 | #define RCAR_DU_MAX_CRTCS 4 |
a64b9c7e | 71 | #define RCAR_DU_MAX_GROUPS DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2) |
6d62ef3a | 72 | #define RCAR_DU_MAX_VSPS 4 |
a64b9c7e | 73 | |
4bf8e196 LP |
74 | struct rcar_du_device { |
75 | struct device *dev; | |
481d342e | 76 | const struct rcar_du_device_info *info; |
4bf8e196 LP |
77 | |
78 | void __iomem *mmio; | |
4bf8e196 LP |
79 | |
80 | struct drm_device *ddev; | |
81 | ||
a64b9c7e | 82 | struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; |
4bf8e196 LP |
83 | unsigned int num_crtcs; |
84 | ||
a6cc417d LP |
85 | struct rcar_du_encoder *encoders[RCAR_DU_OUTPUT_MAX]; |
86 | ||
a64b9c7e | 87 | struct rcar_du_group groups[RCAR_DU_MAX_GROUPS]; |
6d62ef3a | 88 | struct rcar_du_vsp vsps[RCAR_DU_MAX_VSPS]; |
7cbc05cb | 89 | |
9f6aee95 | 90 | struct { |
9f6aee95 | 91 | struct drm_property *colorkey; |
9f6aee95 LP |
92 | } props; |
93 | ||
7cbc05cb | 94 | unsigned int dpad0_source; |
b8a43032 | 95 | unsigned int dpad1_source; |
34a04f2b | 96 | unsigned int vspd1_sink; |
4bf8e196 LP |
97 | }; |
98 | ||
481d342e LP |
99 | static inline bool rcar_du_has(struct rcar_du_device *rcdu, |
100 | unsigned int feature) | |
101 | { | |
102 | return rcdu->info->features & feature; | |
103 | } | |
104 | ||
e8355e0d LP |
105 | static inline bool rcar_du_needs(struct rcar_du_device *rcdu, |
106 | unsigned int quirk) | |
107 | { | |
108 | return rcdu->info->quirks & quirk; | |
109 | } | |
110 | ||
4bf8e196 LP |
111 | static inline u32 rcar_du_read(struct rcar_du_device *rcdu, u32 reg) |
112 | { | |
113 | return ioread32(rcdu->mmio + reg); | |
114 | } | |
115 | ||
116 | static inline void rcar_du_write(struct rcar_du_device *rcdu, u32 reg, u32 data) | |
117 | { | |
118 | iowrite32(data, rcdu->mmio + reg); | |
119 | } | |
120 | ||
121 | #endif /* __RCAR_DU_DRV_H__ */ |