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9026e0d1 MR |
1 | /* |
2 | * Copyright (C) 2015 Free Electrons | |
3 | * Copyright (C) 2015 NextThing Co | |
4 | * | |
5 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <drm/drmP.h> | |
96180dde | 14 | #include <drm/drm_atomic.h> |
9026e0d1 MR |
15 | #include <drm/drm_atomic_helper.h> |
16 | #include <drm/drm_crtc.h> | |
9026e0d1 MR |
17 | #include <drm/drm_fb_cma_helper.h> |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | #include <drm/drm_plane_helper.h> | |
fcd70cd3 | 20 | #include <drm/drm_probe_helper.h> |
9026e0d1 MR |
21 | |
22 | #include <linux/component.h> | |
80a58240 | 23 | #include <linux/list.h> |
f55c83d3 | 24 | #include <linux/of_device.h> |
da3a1c30 | 25 | #include <linux/of_graph.h> |
9026e0d1 MR |
26 | #include <linux/reset.h> |
27 | ||
28 | #include "sun4i_backend.h" | |
29 | #include "sun4i_drv.h" | |
ca07b210 | 30 | #include "sun4i_frontend.h" |
87969338 IZ |
31 | #include "sun4i_layer.h" |
32 | #include "sunxi_engine.h" | |
9026e0d1 | 33 | |
f55c83d3 CYT |
34 | struct sun4i_backend_quirks { |
35 | /* backend <-> TCON muxing selection done in backend */ | |
36 | bool needs_output_muxing; | |
dcf496a6 PK |
37 | |
38 | /* alpha at the lowest z position is not always supported */ | |
39 | bool supports_lowest_plane_alpha; | |
f55c83d3 CYT |
40 | }; |
41 | ||
a6fbffb0 | 42 | static const u32 sunxi_rgb2yuv_coef[12] = { |
9026e0d1 MR |
43 | 0x00000107, 0x00000204, 0x00000064, 0x00000108, |
44 | 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808, | |
45 | 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808 | |
46 | }; | |
47 | ||
87969338 | 48 | static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) |
9026e0d1 MR |
49 | { |
50 | int i; | |
51 | ||
52 | DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n"); | |
53 | ||
54 | /* Set color correction */ | |
87969338 | 55 | regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, |
9026e0d1 MR |
56 | SUN4I_BACKEND_OCCTL_ENABLE); |
57 | ||
58 | for (i = 0; i < 12; i++) | |
87969338 | 59 | regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), |
9026e0d1 MR |
60 | sunxi_rgb2yuv_coef[i]); |
61 | } | |
9026e0d1 | 62 | |
87969338 | 63 | static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) |
9026e0d1 MR |
64 | { |
65 | DRM_DEBUG_DRIVER("Disabling color correction\n"); | |
66 | ||
67 | /* Disable color correction */ | |
87969338 | 68 | regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, |
9026e0d1 MR |
69 | SUN4I_BACKEND_OCCTL_ENABLE, 0); |
70 | } | |
9026e0d1 | 71 | |
87969338 | 72 | static void sun4i_backend_commit(struct sunxi_engine *engine) |
9026e0d1 MR |
73 | { |
74 | DRM_DEBUG_DRIVER("Committing changes\n"); | |
75 | ||
87969338 | 76 | regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, |
9026e0d1 MR |
77 | SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS | |
78 | SUN4I_BACKEND_REGBUFFCTL_LOADCTL); | |
79 | } | |
9026e0d1 MR |
80 | |
81 | void sun4i_backend_layer_enable(struct sun4i_backend *backend, | |
82 | int layer, bool enable) | |
83 | { | |
84 | u32 val; | |
85 | ||
cf80aeef CYT |
86 | DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis", |
87 | layer); | |
9026e0d1 MR |
88 | |
89 | if (enable) | |
90 | val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); | |
91 | else | |
92 | val = 0; | |
93 | ||
87969338 | 94 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
95 | SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); |
96 | } | |
9026e0d1 | 97 | |
35152d11 | 98 | static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode) |
9026e0d1 MR |
99 | { |
100 | switch (format) { | |
101 | case DRM_FORMAT_ARGB8888: | |
102 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888; | |
103 | break; | |
104 | ||
47d7fbb3 MR |
105 | case DRM_FORMAT_ARGB4444: |
106 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444; | |
107 | break; | |
108 | ||
109 | case DRM_FORMAT_ARGB1555: | |
110 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555; | |
111 | break; | |
112 | ||
113 | case DRM_FORMAT_RGBA5551: | |
114 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551; | |
115 | break; | |
116 | ||
117 | case DRM_FORMAT_RGBA4444: | |
118 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444; | |
119 | break; | |
120 | ||
9026e0d1 MR |
121 | case DRM_FORMAT_XRGB8888: |
122 | *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888; | |
123 | break; | |
124 | ||
125 | case DRM_FORMAT_RGB888: | |
126 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888; | |
127 | break; | |
128 | ||
47d7fbb3 MR |
129 | case DRM_FORMAT_RGB565: |
130 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565; | |
131 | break; | |
132 | ||
9026e0d1 MR |
133 | default: |
134 | return -EINVAL; | |
135 | } | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
3d4265f8 PK |
140 | static const uint32_t sun4i_backend_formats[] = { |
141 | DRM_FORMAT_ARGB1555, | |
142 | DRM_FORMAT_ARGB4444, | |
143 | DRM_FORMAT_ARGB8888, | |
3d4265f8 PK |
144 | DRM_FORMAT_RGB565, |
145 | DRM_FORMAT_RGB888, | |
146 | DRM_FORMAT_RGBA4444, | |
147 | DRM_FORMAT_RGBA5551, | |
148 | DRM_FORMAT_UYVY, | |
149 | DRM_FORMAT_VYUY, | |
150 | DRM_FORMAT_XRGB8888, | |
151 | DRM_FORMAT_YUYV, | |
152 | DRM_FORMAT_YVYU, | |
153 | }; | |
154 | ||
02a3ce3c | 155 | bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier) |
3d4265f8 PK |
156 | { |
157 | unsigned int i; | |
158 | ||
02a3ce3c PK |
159 | if (modifier != DRM_FORMAT_MOD_LINEAR) |
160 | return false; | |
161 | ||
3d4265f8 PK |
162 | for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++) |
163 | if (sun4i_backend_formats[i] == fmt) | |
164 | return true; | |
165 | ||
166 | return false; | |
167 | } | |
168 | ||
9026e0d1 MR |
169 | int sun4i_backend_update_layer_coord(struct sun4i_backend *backend, |
170 | int layer, struct drm_plane *plane) | |
171 | { | |
172 | struct drm_plane_state *state = plane->state; | |
9026e0d1 MR |
173 | |
174 | DRM_DEBUG_DRIVER("Updating layer %d\n", layer); | |
175 | ||
176 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) { | |
177 | DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", | |
178 | state->crtc_w, state->crtc_h); | |
87969338 | 179 | regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG, |
9026e0d1 MR |
180 | SUN4I_BACKEND_DISSIZE(state->crtc_w, |
181 | state->crtc_h)); | |
182 | } | |
183 | ||
9026e0d1 MR |
184 | /* Set height and width */ |
185 | DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", | |
186 | state->crtc_w, state->crtc_h); | |
87969338 | 187 | regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), |
9026e0d1 MR |
188 | SUN4I_BACKEND_LAYSIZE(state->crtc_w, |
189 | state->crtc_h)); | |
190 | ||
191 | /* Set base coordinates */ | |
192 | DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n", | |
193 | state->crtc_x, state->crtc_y); | |
87969338 | 194 | regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), |
9026e0d1 MR |
195 | SUN4I_BACKEND_LAYCOOR(state->crtc_x, |
196 | state->crtc_y)); | |
197 | ||
198 | return 0; | |
199 | } | |
9026e0d1 | 200 | |
ddc389f5 MR |
201 | static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend, |
202 | int layer, struct drm_plane *plane) | |
203 | { | |
204 | struct drm_plane_state *state = plane->state; | |
205 | struct drm_framebuffer *fb = state->fb; | |
2aafafab AKH |
206 | const struct drm_format_info *format = fb->format; |
207 | const uint32_t fmt = format->format; | |
ddc389f5 MR |
208 | u32 val = SUN4I_BACKEND_IYUVCTL_EN; |
209 | int i; | |
210 | ||
211 | for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++) | |
212 | regmap_write(backend->engine.regs, | |
213 | SUN4I_BACKEND_YGCOEF_REG(i), | |
214 | sunxi_bt601_yuv2rgb_coef[i]); | |
215 | ||
216 | /* | |
217 | * We should do that only for a single plane, but the | |
218 | * framebuffer's atomic_check has our back on this. | |
219 | */ | |
220 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), | |
221 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, | |
222 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN); | |
223 | ||
224 | /* TODO: Add support for the multi-planar YUV formats */ | |
0fff724a PK |
225 | if (drm_format_info_is_yuv_packed(format) && |
226 | drm_format_info_is_yuv_sampling_422(format)) | |
ddc389f5 MR |
227 | val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; |
228 | else | |
2aafafab | 229 | DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt); |
ddc389f5 MR |
230 | |
231 | /* | |
232 | * Allwinner seems to list the pixel sequence from right to left, while | |
233 | * DRM lists it from left to right. | |
234 | */ | |
2aafafab | 235 | switch (fmt) { |
ddc389f5 MR |
236 | case DRM_FORMAT_YUYV: |
237 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY; | |
238 | break; | |
239 | case DRM_FORMAT_YVYU: | |
240 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY; | |
241 | break; | |
242 | case DRM_FORMAT_UYVY: | |
243 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU; | |
244 | break; | |
245 | case DRM_FORMAT_VYUY: | |
246 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV; | |
247 | break; | |
248 | default: | |
249 | DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n", | |
2aafafab | 250 | fmt); |
ddc389f5 MR |
251 | } |
252 | ||
253 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
9026e0d1 MR |
258 | int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, |
259 | int layer, struct drm_plane *plane) | |
260 | { | |
261 | struct drm_plane_state *state = plane->state; | |
262 | struct drm_framebuffer *fb = state->fb; | |
263 | bool interlaced = false; | |
264 | u32 val; | |
265 | int ret; | |
266 | ||
ddc389f5 MR |
267 | /* Clear the YUV mode */ |
268 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), | |
269 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); | |
270 | ||
9026e0d1 MR |
271 | if (plane->state->crtc) |
272 | interlaced = plane->state->crtc->state->adjusted_mode.flags | |
273 | & DRM_MODE_FLAG_INTERLACE; | |
274 | ||
87969338 | 275 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
276 | SUN4I_BACKEND_MODCTL_ITLMOD_EN, |
277 | interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); | |
278 | ||
279 | DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", | |
280 | interlaced ? "on" : "off"); | |
281 | ||
d99008aa MR |
282 | val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); |
283 | if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) | |
284 | val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; | |
285 | regmap_update_bits(backend->engine.regs, | |
286 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
287 | SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK | | |
288 | SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN, | |
289 | val); | |
290 | ||
979c11ef | 291 | if (fb->format->is_yuv) |
ddc389f5 MR |
292 | return sun4i_backend_update_yuv_format(backend, layer, plane); |
293 | ||
35152d11 | 294 | ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val); |
9026e0d1 MR |
295 | if (ret) { |
296 | DRM_DEBUG_DRIVER("Invalid format\n"); | |
0f0861e3 | 297 | return ret; |
9026e0d1 MR |
298 | } |
299 | ||
87969338 IZ |
300 | regmap_update_bits(backend->engine.regs, |
301 | SUN4I_BACKEND_ATTCTL_REG1(layer), | |
9026e0d1 MR |
302 | SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); |
303 | ||
304 | return 0; | |
305 | } | |
9026e0d1 | 306 | |
ca07b210 MR |
307 | int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, |
308 | int layer, uint32_t fmt) | |
309 | { | |
310 | u32 val; | |
311 | int ret; | |
312 | ||
35152d11 | 313 | ret = sun4i_backend_drm_format_to_layer(fmt, &val); |
ca07b210 MR |
314 | if (ret) { |
315 | DRM_DEBUG_DRIVER("Invalid format\n"); | |
316 | return ret; | |
317 | } | |
318 | ||
319 | regmap_update_bits(backend->engine.regs, | |
320 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
321 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN, | |
322 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN); | |
323 | ||
324 | regmap_update_bits(backend->engine.regs, | |
325 | SUN4I_BACKEND_ATTCTL_REG1(layer), | |
326 | SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
ddc389f5 MR |
331 | static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend, |
332 | struct drm_framebuffer *fb, | |
333 | dma_addr_t paddr) | |
334 | { | |
335 | /* TODO: Add support for the multi-planar YUV formats */ | |
336 | DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr); | |
337 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr); | |
338 | ||
339 | DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); | |
340 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0), | |
341 | fb->pitches[0] * 8); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
9026e0d1 MR |
346 | int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, |
347 | int layer, struct drm_plane *plane) | |
348 | { | |
349 | struct drm_plane_state *state = plane->state; | |
350 | struct drm_framebuffer *fb = state->fb; | |
9026e0d1 MR |
351 | u32 lo_paddr, hi_paddr; |
352 | dma_addr_t paddr; | |
9026e0d1 | 353 | |
f5870879 MR |
354 | /* Set the line width */ |
355 | DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); | |
356 | regmap_write(backend->engine.regs, | |
357 | SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), | |
358 | fb->pitches[0] * 8); | |
359 | ||
cff2192f CYT |
360 | /* Get the start of the displayed memory */ |
361 | paddr = drm_fb_cma_get_gem_addr(fb, state, 0); | |
f1b78f0e | 362 | DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); |
9026e0d1 | 363 | |
4690803b CYT |
364 | /* |
365 | * backend DMA accesses DRAM directly, bypassing the system | |
366 | * bus. As such, the address range is different and the buffer | |
367 | * address needs to be corrected. | |
368 | */ | |
369 | paddr -= PHYS_OFFSET; | |
370 | ||
979c11ef | 371 | if (fb->format->is_yuv) |
ddc389f5 MR |
372 | return sun4i_backend_update_yuv_buffer(backend, fb, paddr); |
373 | ||
9026e0d1 MR |
374 | /* Write the 32 lower bits of the address (in bits) */ |
375 | lo_paddr = paddr << 3; | |
376 | DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr); | |
87969338 IZ |
377 | regmap_write(backend->engine.regs, |
378 | SUN4I_BACKEND_LAYFB_L32ADD_REG(layer), | |
9026e0d1 MR |
379 | lo_paddr); |
380 | ||
381 | /* And the upper bits */ | |
382 | hi_paddr = paddr >> 29; | |
383 | DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr); | |
87969338 | 384 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG, |
9026e0d1 MR |
385 | SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer), |
386 | SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr)); | |
387 | ||
388 | return 0; | |
389 | } | |
9026e0d1 | 390 | |
47a05f4a MR |
391 | int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, |
392 | struct drm_plane *plane) | |
393 | { | |
394 | struct drm_plane_state *state = plane->state; | |
8f1f2553 | 395 | struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state); |
47a05f4a | 396 | unsigned int priority = state->normalized_zpos; |
8f1f2553 | 397 | unsigned int pipe = p_state->pipe; |
47a05f4a | 398 | |
8f1f2553 MR |
399 | DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n", |
400 | layer, priority, pipe); | |
47a05f4a | 401 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), |
8f1f2553 | 402 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK | |
47a05f4a | 403 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, |
8f1f2553 | 404 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) | |
47a05f4a MR |
405 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
686d2638 PK |
410 | void sun4i_backend_cleanup_layer(struct sun4i_backend *backend, |
411 | int layer) | |
412 | { | |
413 | regmap_update_bits(backend->engine.regs, | |
414 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
415 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN | | |
416 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); | |
417 | } | |
418 | ||
96180dde MR |
419 | static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state) |
420 | { | |
421 | u16 src_h = state->src_h >> 16; | |
422 | u16 src_w = state->src_w >> 16; | |
423 | ||
424 | DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n", | |
425 | src_w, src_h, state->crtc_w, state->crtc_h); | |
426 | ||
427 | if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) | |
428 | return true; | |
429 | ||
430 | return false; | |
431 | } | |
432 | ||
433 | static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state) | |
434 | { | |
435 | struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); | |
436 | struct sun4i_backend *backend = layer->backend; | |
aaf3880b | 437 | uint32_t format = state->fb->format->format; |
02a3ce3c | 438 | uint64_t modifier = state->fb->modifier; |
96180dde MR |
439 | |
440 | if (IS_ERR(backend->frontend)) | |
441 | return false; | |
442 | ||
02a3ce3c | 443 | if (!sun4i_frontend_format_is_supported(format, modifier)) |
aaf3880b PK |
444 | return false; |
445 | ||
02a3ce3c | 446 | if (!sun4i_backend_format_is_supported(format, modifier)) |
aaf3880b PK |
447 | return true; |
448 | ||
ad25d073 PK |
449 | /* |
450 | * TODO: The backend alone allows 2x and 4x integer scaling, including | |
451 | * support for an alpha component (which the frontend doesn't support). | |
aaf3880b PK |
452 | * Use the backend directly instead of the frontend in this case, with |
453 | * another test to return false. | |
454 | */ | |
455 | ||
456 | if (sun4i_backend_plane_uses_scaler(state)) | |
457 | return true; | |
458 | ||
459 | /* | |
460 | * Here the format is supported by both the frontend and the backend | |
461 | * and no frontend scaling is required, so use the backend directly. | |
ad25d073 | 462 | */ |
aaf3880b | 463 | return false; |
96180dde MR |
464 | } |
465 | ||
ab698510 PK |
466 | static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state, |
467 | bool *uses_frontend) | |
468 | { | |
469 | if (sun4i_backend_plane_uses_frontend(state)) { | |
470 | *uses_frontend = true; | |
471 | return true; | |
472 | } | |
473 | ||
474 | *uses_frontend = false; | |
475 | ||
476 | /* Scaling is not supported without the frontend. */ | |
477 | if (sun4i_backend_plane_uses_scaler(state)) | |
478 | return false; | |
479 | ||
480 | return true; | |
481 | } | |
482 | ||
dd63250c MR |
483 | static void sun4i_backend_atomic_begin(struct sunxi_engine *engine, |
484 | struct drm_crtc_state *old_state) | |
485 | { | |
486 | u32 val; | |
487 | ||
488 | WARN_ON(regmap_read_poll_timeout(engine->regs, | |
489 | SUN4I_BACKEND_REGBUFFCTL_REG, | |
490 | val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL), | |
491 | 100, 50000)); | |
492 | } | |
493 | ||
96180dde MR |
494 | static int sun4i_backend_atomic_check(struct sunxi_engine *engine, |
495 | struct drm_crtc_state *crtc_state) | |
496 | { | |
8f1f2553 | 497 | struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; |
dcf496a6 | 498 | struct sun4i_backend *backend = engine_to_sun4i_backend(engine); |
96180dde MR |
499 | struct drm_atomic_state *state = crtc_state->state; |
500 | struct drm_device *drm = state->dev; | |
501 | struct drm_plane *plane; | |
65f7fa3a MR |
502 | unsigned int num_planes = 0; |
503 | unsigned int num_alpha_planes = 0; | |
96180dde | 504 | unsigned int num_frontend_planes = 0; |
dcf496a6 | 505 | unsigned int num_alpha_planes_max = 1; |
32463556 | 506 | unsigned int num_yuv_planes = 0; |
8f1f2553 MR |
507 | unsigned int current_pipe = 0; |
508 | unsigned int i; | |
96180dde MR |
509 | |
510 | DRM_DEBUG_DRIVER("Starting checking our planes\n"); | |
511 | ||
512 | if (!crtc_state->planes_changed) | |
513 | return 0; | |
514 | ||
515 | drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { | |
516 | struct drm_plane_state *plane_state = | |
517 | drm_atomic_get_plane_state(state, plane); | |
518 | struct sun4i_layer_state *layer_state = | |
519 | state_to_sun4i_layer_state(plane_state); | |
65f7fa3a MR |
520 | struct drm_framebuffer *fb = plane_state->fb; |
521 | struct drm_format_name_buf format_name; | |
96180dde | 522 | |
ab698510 PK |
523 | if (!sun4i_backend_plane_is_supported(plane_state, |
524 | &layer_state->uses_frontend)) | |
525 | return -EINVAL; | |
526 | ||
527 | if (layer_state->uses_frontend) { | |
96180dde MR |
528 | DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", |
529 | plane->index); | |
96180dde | 530 | num_frontend_planes++; |
ae56bfbd PK |
531 | } else { |
532 | if (fb->format->is_yuv) { | |
533 | DRM_DEBUG_DRIVER("Plane FB format is YUV\n"); | |
534 | num_yuv_planes++; | |
535 | } | |
96180dde | 536 | } |
65f7fa3a MR |
537 | |
538 | DRM_DEBUG_DRIVER("Plane FB format is %s\n", | |
539 | drm_get_format_name(fb->format->format, | |
540 | &format_name)); | |
d99008aa | 541 | if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) |
65f7fa3a MR |
542 | num_alpha_planes++; |
543 | ||
8f1f2553 MR |
544 | DRM_DEBUG_DRIVER("Plane zpos is %d\n", |
545 | plane_state->normalized_zpos); | |
546 | ||
547 | /* Sort our planes by Zpos */ | |
548 | plane_states[plane_state->normalized_zpos] = plane_state; | |
549 | ||
65f7fa3a MR |
550 | num_planes++; |
551 | } | |
552 | ||
8f1f2553 MR |
553 | /* All our planes were disabled, bail out */ |
554 | if (!num_planes) | |
555 | return 0; | |
556 | ||
65f7fa3a MR |
557 | /* |
558 | * The hardware is a bit unusual here. | |
559 | * | |
560 | * Even though it supports 4 layers, it does the composition | |
561 | * in two separate steps. | |
562 | * | |
563 | * The first one is assigning a layer to one of its two | |
564 | * pipes. If more that 1 layer is assigned to the same pipe, | |
565 | * and if pixels overlaps, the pipe will take the pixel from | |
566 | * the layer with the highest priority. | |
567 | * | |
568 | * The second step is the actual alpha blending, that takes | |
dcf496a6 | 569 | * the two pipes as input, and uses the potential alpha |
65f7fa3a MR |
570 | * component to do the transparency between the two. |
571 | * | |
dcf496a6 | 572 | * This two-step scenario makes us unable to guarantee a |
65f7fa3a MR |
573 | * robust alpha blending between the 4 layers in all |
574 | * situations, since this means that we need to have one layer | |
575 | * with alpha at the lowest position of our two pipes. | |
576 | * | |
dcf496a6 PK |
577 | * However, we cannot even do that on every platform, since |
578 | * the hardware has a bug where the lowest plane of the lowest | |
579 | * pipe (pipe 0, priority 0), if it has any alpha, will | |
580 | * discard the pixel data entirely and just display the pixels | |
581 | * in the background color (black by default). | |
65f7fa3a | 582 | * |
dcf496a6 PK |
583 | * This means that on the affected platforms, we effectively |
584 | * have only three valid configurations with alpha, all of | |
585 | * them with the alpha being on pipe1 with the lowest | |
586 | * position, which can be 1, 2 or 3 depending on the number of | |
587 | * planes and their zpos. | |
65f7fa3a | 588 | */ |
dcf496a6 PK |
589 | |
590 | /* For platforms that are not affected by the issue described above. */ | |
591 | if (backend->quirks->supports_lowest_plane_alpha) | |
592 | num_alpha_planes_max++; | |
593 | ||
594 | if (num_alpha_planes > num_alpha_planes_max) { | |
65f7fa3a MR |
595 | DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); |
596 | return -EINVAL; | |
96180dde MR |
597 | } |
598 | ||
8f1f2553 | 599 | /* We can't have an alpha plane at the lowest position */ |
dcf496a6 PK |
600 | if (!backend->quirks->supports_lowest_plane_alpha && |
601 | (plane_states[0]->fb->format->has_alpha || | |
602 | (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) | |
8f1f2553 MR |
603 | return -EINVAL; |
604 | ||
605 | for (i = 1; i < num_planes; i++) { | |
606 | struct drm_plane_state *p_state = plane_states[i]; | |
607 | struct drm_framebuffer *fb = p_state->fb; | |
608 | struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); | |
609 | ||
610 | /* | |
611 | * The only alpha position is the lowest plane of the | |
612 | * second pipe. | |
613 | */ | |
d99008aa | 614 | if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) |
8f1f2553 MR |
615 | current_pipe++; |
616 | ||
617 | s_state->pipe = current_pipe; | |
618 | } | |
619 | ||
32463556 MR |
620 | /* We can only have a single YUV plane at a time */ |
621 | if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) { | |
622 | DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
96180dde MR |
626 | if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { |
627 | DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); | |
628 | return -EINVAL; | |
629 | } | |
630 | ||
32463556 MR |
631 | DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n", |
632 | num_planes, num_alpha_planes, num_frontend_planes, | |
633 | num_yuv_planes); | |
65f7fa3a | 634 | |
96180dde MR |
635 | return 0; |
636 | } | |
637 | ||
ca07b210 MR |
638 | static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine) |
639 | { | |
640 | struct sun4i_backend *backend = engine_to_sun4i_backend(engine); | |
641 | struct sun4i_frontend *frontend = backend->frontend; | |
642 | ||
643 | if (!frontend) | |
644 | return; | |
645 | ||
646 | /* | |
647 | * In a teardown scenario with the frontend involved, we have | |
648 | * to keep the frontend enabled until the next vblank, and | |
649 | * only then disable it. | |
650 | * | |
651 | * This is due to the fact that the backend will not take into | |
652 | * account the new configuration (with the plane that used to | |
653 | * be fed by the frontend now disabled) until we write to the | |
654 | * commit bit and the hardware fetches the new configuration | |
655 | * during the next vblank. | |
656 | * | |
657 | * So we keep the frontend around in order to prevent any | |
658 | * visual artifacts. | |
659 | */ | |
660 | spin_lock(&backend->frontend_lock); | |
661 | if (backend->frontend_teardown) { | |
662 | sun4i_frontend_exit(frontend); | |
663 | backend->frontend_teardown = false; | |
664 | } | |
665 | spin_unlock(&backend->frontend_lock); | |
666 | }; | |
667 | ||
440d2c7b MR |
668 | static int sun4i_backend_init_sat(struct device *dev) { |
669 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
670 | int ret; | |
671 | ||
672 | backend->sat_reset = devm_reset_control_get(dev, "sat"); | |
673 | if (IS_ERR(backend->sat_reset)) { | |
674 | dev_err(dev, "Couldn't get the SAT reset line\n"); | |
675 | return PTR_ERR(backend->sat_reset); | |
676 | } | |
677 | ||
678 | ret = reset_control_deassert(backend->sat_reset); | |
679 | if (ret) { | |
680 | dev_err(dev, "Couldn't deassert the SAT reset line\n"); | |
681 | return ret; | |
682 | } | |
683 | ||
684 | backend->sat_clk = devm_clk_get(dev, "sat"); | |
685 | if (IS_ERR(backend->sat_clk)) { | |
686 | dev_err(dev, "Couldn't get our SAT clock\n"); | |
687 | ret = PTR_ERR(backend->sat_clk); | |
688 | goto err_assert_reset; | |
689 | } | |
690 | ||
691 | ret = clk_prepare_enable(backend->sat_clk); | |
692 | if (ret) { | |
693 | dev_err(dev, "Couldn't enable the SAT clock\n"); | |
694 | return ret; | |
695 | } | |
696 | ||
697 | return 0; | |
698 | ||
699 | err_assert_reset: | |
700 | reset_control_assert(backend->sat_reset); | |
701 | return ret; | |
702 | } | |
703 | ||
704 | static int sun4i_backend_free_sat(struct device *dev) { | |
705 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
706 | ||
707 | clk_disable_unprepare(backend->sat_clk); | |
708 | reset_control_assert(backend->sat_reset); | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
da3a1c30 CYT |
713 | /* |
714 | * The display backend can take video output from the display frontend, or | |
715 | * the display enhancement unit on the A80, as input for one it its layers. | |
716 | * This relationship within the display pipeline is encoded in the device | |
717 | * tree with of_graph, and we use it here to figure out which backend, if | |
718 | * there are 2 or more, we are currently probing. The number would be in | |
719 | * the "reg" property of the upstream output port endpoint. | |
720 | */ | |
721 | static int sun4i_backend_of_get_id(struct device_node *node) | |
722 | { | |
723 | struct device_node *port, *ep; | |
724 | int ret = -EINVAL; | |
725 | ||
726 | /* input is port 0 */ | |
727 | port = of_graph_get_port_by_id(node, 0); | |
728 | if (!port) | |
729 | return -EINVAL; | |
730 | ||
731 | /* try finding an upstream endpoint */ | |
732 | for_each_available_child_of_node(port, ep) { | |
733 | struct device_node *remote; | |
734 | u32 reg; | |
735 | ||
0bd46d70 | 736 | remote = of_graph_get_remote_endpoint(ep); |
da3a1c30 CYT |
737 | if (!remote) |
738 | continue; | |
739 | ||
740 | ret = of_property_read_u32(remote, "reg", ®); | |
741 | if (ret) | |
742 | continue; | |
743 | ||
744 | ret = reg; | |
745 | } | |
746 | ||
747 | of_node_put(port); | |
748 | ||
749 | return ret; | |
750 | } | |
751 | ||
ca07b210 MR |
752 | /* TODO: This needs to take multiple pipelines into account */ |
753 | static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv, | |
754 | struct device_node *node) | |
755 | { | |
756 | struct device_node *port, *ep, *remote; | |
757 | struct sun4i_frontend *frontend; | |
758 | ||
759 | port = of_graph_get_port_by_id(node, 0); | |
760 | if (!port) | |
761 | return ERR_PTR(-EINVAL); | |
762 | ||
763 | for_each_available_child_of_node(port, ep) { | |
764 | remote = of_graph_get_remote_port_parent(ep); | |
765 | if (!remote) | |
766 | continue; | |
767 | ||
768 | /* does this node match any registered engines? */ | |
769 | list_for_each_entry(frontend, &drv->frontend_list, list) { | |
770 | if (remote == frontend->node) { | |
771 | of_node_put(remote); | |
772 | of_node_put(port); | |
773 | return frontend; | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
778 | return ERR_PTR(-EINVAL); | |
779 | } | |
780 | ||
87969338 | 781 | static const struct sunxi_engine_ops sun4i_backend_engine_ops = { |
dd63250c | 782 | .atomic_begin = sun4i_backend_atomic_begin, |
96180dde | 783 | .atomic_check = sun4i_backend_atomic_check, |
87969338 IZ |
784 | .commit = sun4i_backend_commit, |
785 | .layers_init = sun4i_layers_init, | |
786 | .apply_color_correction = sun4i_backend_apply_color_correction, | |
787 | .disable_color_correction = sun4i_backend_disable_color_correction, | |
ca07b210 | 788 | .vblank_quirk = sun4i_backend_vblank_quirk, |
87969338 IZ |
789 | }; |
790 | ||
9026e0d1 MR |
791 | static struct regmap_config sun4i_backend_regmap_config = { |
792 | .reg_bits = 32, | |
793 | .val_bits = 32, | |
794 | .reg_stride = 4, | |
795 | .max_register = 0x5800, | |
796 | }; | |
797 | ||
798 | static int sun4i_backend_bind(struct device *dev, struct device *master, | |
799 | void *data) | |
800 | { | |
801 | struct platform_device *pdev = to_platform_device(dev); | |
802 | struct drm_device *drm = data; | |
803 | struct sun4i_drv *drv = drm->dev_private; | |
804 | struct sun4i_backend *backend; | |
f55c83d3 | 805 | const struct sun4i_backend_quirks *quirks; |
9026e0d1 MR |
806 | struct resource *res; |
807 | void __iomem *regs; | |
808 | int i, ret; | |
809 | ||
810 | backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL); | |
811 | if (!backend) | |
812 | return -ENOMEM; | |
813 | dev_set_drvdata(dev, backend); | |
ca07b210 | 814 | spin_lock_init(&backend->frontend_lock); |
9026e0d1 | 815 | |
87969338 IZ |
816 | backend->engine.node = dev->of_node; |
817 | backend->engine.ops = &sun4i_backend_engine_ops; | |
818 | backend->engine.id = sun4i_backend_of_get_id(dev->of_node); | |
819 | if (backend->engine.id < 0) | |
820 | return backend->engine.id; | |
da3a1c30 | 821 | |
ca07b210 MR |
822 | backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node); |
823 | if (IS_ERR(backend->frontend)) | |
824 | dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n"); | |
825 | ||
9026e0d1 MR |
826 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
827 | regs = devm_ioremap_resource(dev, res); | |
9a8aa939 | 828 | if (IS_ERR(regs)) |
9026e0d1 | 829 | return PTR_ERR(regs); |
9026e0d1 | 830 | |
9026e0d1 MR |
831 | backend->reset = devm_reset_control_get(dev, NULL); |
832 | if (IS_ERR(backend->reset)) { | |
833 | dev_err(dev, "Couldn't get our reset line\n"); | |
834 | return PTR_ERR(backend->reset); | |
835 | } | |
836 | ||
837 | ret = reset_control_deassert(backend->reset); | |
838 | if (ret) { | |
839 | dev_err(dev, "Couldn't deassert our reset line\n"); | |
840 | return ret; | |
841 | } | |
842 | ||
843 | backend->bus_clk = devm_clk_get(dev, "ahb"); | |
844 | if (IS_ERR(backend->bus_clk)) { | |
845 | dev_err(dev, "Couldn't get the backend bus clock\n"); | |
846 | ret = PTR_ERR(backend->bus_clk); | |
847 | goto err_assert_reset; | |
848 | } | |
849 | clk_prepare_enable(backend->bus_clk); | |
850 | ||
851 | backend->mod_clk = devm_clk_get(dev, "mod"); | |
852 | if (IS_ERR(backend->mod_clk)) { | |
853 | dev_err(dev, "Couldn't get the backend module clock\n"); | |
854 | ret = PTR_ERR(backend->mod_clk); | |
855 | goto err_disable_bus_clk; | |
856 | } | |
857 | clk_prepare_enable(backend->mod_clk); | |
858 | ||
859 | backend->ram_clk = devm_clk_get(dev, "ram"); | |
860 | if (IS_ERR(backend->ram_clk)) { | |
861 | dev_err(dev, "Couldn't get the backend RAM clock\n"); | |
862 | ret = PTR_ERR(backend->ram_clk); | |
863 | goto err_disable_mod_clk; | |
864 | } | |
865 | clk_prepare_enable(backend->ram_clk); | |
866 | ||
440d2c7b MR |
867 | if (of_device_is_compatible(dev->of_node, |
868 | "allwinner,sun8i-a33-display-backend")) { | |
869 | ret = sun4i_backend_init_sat(dev); | |
870 | if (ret) { | |
871 | dev_err(dev, "Couldn't init SAT resources\n"); | |
872 | goto err_disable_ram_clk; | |
873 | } | |
874 | } | |
875 | ||
8270249f CYT |
876 | backend->engine.regs = devm_regmap_init_mmio(dev, regs, |
877 | &sun4i_backend_regmap_config); | |
878 | if (IS_ERR(backend->engine.regs)) { | |
879 | dev_err(dev, "Couldn't create the backend regmap\n"); | |
880 | return PTR_ERR(backend->engine.regs); | |
881 | } | |
882 | ||
87969338 | 883 | list_add_tail(&backend->engine.list, &drv->engine_list); |
80a58240 | 884 | |
936598d1 CYT |
885 | /* |
886 | * Many of the backend's layer configuration registers have | |
887 | * undefined default values. This poses a risk as we use | |
888 | * regmap_update_bits in some places, and don't overwrite | |
889 | * the whole register. | |
890 | * | |
891 | * Clear the registers here to have something predictable. | |
892 | */ | |
9026e0d1 | 893 | for (i = 0x800; i < 0x1000; i += 4) |
87969338 | 894 | regmap_write(backend->engine.regs, i, 0); |
9026e0d1 MR |
895 | |
896 | /* Disable registers autoloading */ | |
87969338 | 897 | regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG, |
9026e0d1 MR |
898 | SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS); |
899 | ||
900 | /* Enable the backend */ | |
87969338 | 901 | regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
902 | SUN4I_BACKEND_MODCTL_DEBE_EN | |
903 | SUN4I_BACKEND_MODCTL_START_CTL); | |
904 | ||
f55c83d3 CYT |
905 | /* Set output selection if needed */ |
906 | quirks = of_device_get_match_data(dev); | |
907 | if (quirks->needs_output_muxing) { | |
908 | /* | |
909 | * We assume there is no dynamic muxing of backends | |
910 | * and TCONs, so we select the backend with same ID. | |
911 | * | |
912 | * While dynamic selection might be interesting, since | |
913 | * the CRTC is tied to the TCON, while the layers are | |
914 | * tied to the backends, this means, we will need to | |
915 | * switch between groups of layers. There might not be | |
916 | * a way to represent this constraint in DRM. | |
917 | */ | |
918 | regmap_update_bits(backend->engine.regs, | |
919 | SUN4I_BACKEND_MODCTL_REG, | |
920 | SUN4I_BACKEND_MODCTL_OUT_SEL, | |
921 | (backend->engine.id | |
922 | ? SUN4I_BACKEND_MODCTL_OUT_LCD1 | |
923 | : SUN4I_BACKEND_MODCTL_OUT_LCD0)); | |
924 | } | |
925 | ||
e527cd9e PK |
926 | backend->quirks = quirks; |
927 | ||
9026e0d1 MR |
928 | return 0; |
929 | ||
440d2c7b MR |
930 | err_disable_ram_clk: |
931 | clk_disable_unprepare(backend->ram_clk); | |
9026e0d1 MR |
932 | err_disable_mod_clk: |
933 | clk_disable_unprepare(backend->mod_clk); | |
934 | err_disable_bus_clk: | |
935 | clk_disable_unprepare(backend->bus_clk); | |
936 | err_assert_reset: | |
937 | reset_control_assert(backend->reset); | |
938 | return ret; | |
939 | } | |
940 | ||
941 | static void sun4i_backend_unbind(struct device *dev, struct device *master, | |
942 | void *data) | |
943 | { | |
944 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
945 | ||
87969338 | 946 | list_del(&backend->engine.list); |
80a58240 | 947 | |
440d2c7b MR |
948 | if (of_device_is_compatible(dev->of_node, |
949 | "allwinner,sun8i-a33-display-backend")) | |
950 | sun4i_backend_free_sat(dev); | |
951 | ||
9026e0d1 MR |
952 | clk_disable_unprepare(backend->ram_clk); |
953 | clk_disable_unprepare(backend->mod_clk); | |
954 | clk_disable_unprepare(backend->bus_clk); | |
955 | reset_control_assert(backend->reset); | |
956 | } | |
957 | ||
dfeb693d | 958 | static const struct component_ops sun4i_backend_ops = { |
9026e0d1 MR |
959 | .bind = sun4i_backend_bind, |
960 | .unbind = sun4i_backend_unbind, | |
961 | }; | |
962 | ||
963 | static int sun4i_backend_probe(struct platform_device *pdev) | |
964 | { | |
965 | return component_add(&pdev->dev, &sun4i_backend_ops); | |
966 | } | |
967 | ||
968 | static int sun4i_backend_remove(struct platform_device *pdev) | |
969 | { | |
970 | component_del(&pdev->dev, &sun4i_backend_ops); | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
9a8187c0 CYT |
975 | static const struct sun4i_backend_quirks sun4i_backend_quirks = { |
976 | .needs_output_muxing = true, | |
977 | }; | |
978 | ||
f55c83d3 CYT |
979 | static const struct sun4i_backend_quirks sun5i_backend_quirks = { |
980 | }; | |
981 | ||
982 | static const struct sun4i_backend_quirks sun6i_backend_quirks = { | |
983 | }; | |
984 | ||
aaddb6d2 JL |
985 | static const struct sun4i_backend_quirks sun7i_backend_quirks = { |
986 | .needs_output_muxing = true, | |
dcf496a6 | 987 | .supports_lowest_plane_alpha = true, |
aaddb6d2 JL |
988 | }; |
989 | ||
f55c83d3 | 990 | static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = { |
dcf496a6 | 991 | .supports_lowest_plane_alpha = true, |
f55c83d3 CYT |
992 | }; |
993 | ||
33478959 CYT |
994 | static const struct sun4i_backend_quirks sun9i_backend_quirks = { |
995 | }; | |
996 | ||
9026e0d1 | 997 | static const struct of_device_id sun4i_backend_of_table[] = { |
9a8187c0 CYT |
998 | { |
999 | .compatible = "allwinner,sun4i-a10-display-backend", | |
1000 | .data = &sun4i_backend_quirks, | |
1001 | }, | |
f55c83d3 CYT |
1002 | { |
1003 | .compatible = "allwinner,sun5i-a13-display-backend", | |
1004 | .data = &sun5i_backend_quirks, | |
1005 | }, | |
1006 | { | |
1007 | .compatible = "allwinner,sun6i-a31-display-backend", | |
1008 | .data = &sun6i_backend_quirks, | |
1009 | }, | |
aaddb6d2 JL |
1010 | { |
1011 | .compatible = "allwinner,sun7i-a20-display-backend", | |
1012 | .data = &sun7i_backend_quirks, | |
1013 | }, | |
d0ec0a3e CYT |
1014 | { |
1015 | .compatible = "allwinner,sun8i-a23-display-backend", | |
1016 | .data = &sun8i_a33_backend_quirks, | |
1017 | }, | |
f55c83d3 CYT |
1018 | { |
1019 | .compatible = "allwinner,sun8i-a33-display-backend", | |
1020 | .data = &sun8i_a33_backend_quirks, | |
1021 | }, | |
33478959 CYT |
1022 | { |
1023 | .compatible = "allwinner,sun9i-a80-display-backend", | |
1024 | .data = &sun9i_backend_quirks, | |
1025 | }, | |
9026e0d1 MR |
1026 | { } |
1027 | }; | |
1028 | MODULE_DEVICE_TABLE(of, sun4i_backend_of_table); | |
1029 | ||
1030 | static struct platform_driver sun4i_backend_platform_driver = { | |
1031 | .probe = sun4i_backend_probe, | |
1032 | .remove = sun4i_backend_remove, | |
1033 | .driver = { | |
1034 | .name = "sun4i-backend", | |
1035 | .of_match_table = sun4i_backend_of_table, | |
1036 | }, | |
1037 | }; | |
1038 | module_platform_driver(sun4i_backend_platform_driver); | |
1039 | ||
1040 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
1041 | MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver"); | |
1042 | MODULE_LICENSE("GPL"); |