[thirdparty/kernel/stable.git] / drivers / gpu / drm / sun4i / sun4i_tv.c

/*
 * Copyright (C) 2015 Free Electrons
 * Copyright (C) 2015 NextThing Co
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/component.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>

#include "sun4i_crtc.h"
#include "sun4i_drv.h"
#include "sunxi_engine.h"

#define SUN4I_TVE_EN_REG		0x000
#define SUN4I_TVE_EN_DAC_MAP_MASK		GENMASK(19, 4)
#define SUN4I_TVE_EN_DAC_MAP(dac, out)		(((out) & 0xf) << (dac + 1) * 4)
#define SUN4I_TVE_EN_ENABLE			BIT(0)

#define SUN4I_TVE_CFG0_REG		0x004
#define SUN4I_TVE_CFG0_DAC_CONTROL_54M		BIT(26)
#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M	BIT(25)
#define SUN4I_TVE_CFG0_CORE_CONTROL_54M		BIT(24)
#define SUN4I_TVE_CFG0_YC_EN			BIT(17)
#define SUN4I_TVE_CFG0_COMP_EN			BIT(16)
#define SUN4I_TVE_CFG0_RES(x)			((x) & 0xf)
#define SUN4I_TVE_CFG0_RES_480i			SUN4I_TVE_CFG0_RES(0)
#define SUN4I_TVE_CFG0_RES_576i			SUN4I_TVE_CFG0_RES(1)

#define SUN4I_TVE_DAC0_REG		0x008
#define SUN4I_TVE_DAC0_CLOCK_INVERT		BIT(24)
#define SUN4I_TVE_DAC0_LUMA(x)			(((x) & 3) << 20)
#define SUN4I_TVE_DAC0_LUMA_0_4			SUN4I_TVE_DAC0_LUMA(3)
#define SUN4I_TVE_DAC0_CHROMA(x)		(((x) & 3) << 18)
#define SUN4I_TVE_DAC0_CHROMA_0_75		SUN4I_TVE_DAC0_CHROMA(3)
#define SUN4I_TVE_DAC0_INTERNAL_DAC(x)		(((x) & 3) << 16)
#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS	SUN4I_TVE_DAC0_INTERNAL_DAC(3)
#define SUN4I_TVE_DAC0_DAC_EN(dac)		BIT(dac)

#define SUN4I_TVE_NOTCH_REG		0x00c
#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x)	((4 - (x)) << (dac * 3))

#define SUN4I_TVE_CHROMA_FREQ_REG	0x010

#define SUN4I_TVE_PORCH_REG		0x014
#define SUN4I_TVE_PORCH_BACK(x)			((x) << 16)
#define SUN4I_TVE_PORCH_FRONT(x)		(x)

#define SUN4I_TVE_LINE_REG		0x01c
#define SUN4I_TVE_LINE_FIRST(x)			((x) << 16)
#define SUN4I_TVE_LINE_NUMBER(x)		(x)

#define SUN4I_TVE_LEVEL_REG		0x020
#define SUN4I_TVE_LEVEL_BLANK(x)		((x) << 16)
#define SUN4I_TVE_LEVEL_BLACK(x)		(x)

#define SUN4I_TVE_DAC1_REG		0x024
#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x)	((x) << (dac * 8))

#define SUN4I_TVE_DETECT_STA_REG	0x038
#define SUN4I_TVE_DETECT_STA_DAC(dac)		BIT((dac * 8))
#define SUN4I_TVE_DETECT_STA_UNCONNECTED		0
#define SUN4I_TVE_DETECT_STA_CONNECTED			1
#define SUN4I_TVE_DETECT_STA_GROUND			2

#define SUN4I_TVE_CB_CR_LVL_REG		0x10c
#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x)		((x) << 8)
#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x)		(x)

#define SUN4I_TVE_TINT_BURST_PHASE_REG	0x110
#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x)	(x)

#define SUN4I_TVE_BURST_WIDTH_REG	0x114
#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x)	((x) << 16)
#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x)	((x) << 8)
#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x)	(x)

#define SUN4I_TVE_CB_CR_GAIN_REG	0x118
#define SUN4I_TVE_CB_CR_GAIN_CR(x)		((x) << 8)
#define SUN4I_TVE_CB_CR_GAIN_CB(x)		(x)

#define SUN4I_TVE_SYNC_VBI_REG		0x11c
#define SUN4I_TVE_SYNC_VBI_SYNC(x)		((x) << 16)
#define SUN4I_TVE_SYNC_VBI_VBLANK(x)		(x)

#define SUN4I_TVE_ACTIVE_LINE_REG	0x124
#define SUN4I_TVE_ACTIVE_LINE(x)		(x)

#define SUN4I_TVE_CHROMA_REG		0x128
#define SUN4I_TVE_CHROMA_COMP_GAIN(x)		((x) & 3)
#define SUN4I_TVE_CHROMA_COMP_GAIN_50		SUN4I_TVE_CHROMA_COMP_GAIN(2)

#define SUN4I_TVE_12C_REG		0x12c
#define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE		BIT(8)
#define SUN4I_TVE_12C_COMP_YUV_EN		BIT(0)

#define SUN4I_TVE_RESYNC_REG		0x130
#define SUN4I_TVE_RESYNC_FIELD			BIT(31)
#define SUN4I_TVE_RESYNC_LINE(x)		((x) << 16)
#define SUN4I_TVE_RESYNC_PIXEL(x)		(x)

#define SUN4I_TVE_SLAVE_REG		0x134

#define SUN4I_TVE_WSS_DATA2_REG		0x244

struct color_gains {
	u16	cb;
	u16	cr;
};

struct burst_levels {
	u16	cb;
	u16	cr;
};

struct video_levels {
	u16	black;
	u16	blank;
};

struct resync_parameters {
	bool	field;
	u16	line;
	u16	pixel;
};

struct tv_mode {
	char		*name;

	u32		mode;
	u32		chroma_freq;
	u16		back_porch;
	u16		front_porch;
	u16		line_number;
	u16		vblank_level;

	u32		hdisplay;
	u16		hfront_porch;
	u16		hsync_len;
	u16		hback_porch;

	u32		vdisplay;
	u16		vfront_porch;
	u16		vsync_len;
	u16		vback_porch;

	bool		yc_en;
	bool		dac3_en;
	bool		dac_bit25_en;

	const struct color_gains	*color_gains;
	const struct burst_levels	*burst_levels;
	const struct video_levels	*video_levels;
	const struct resync_parameters	*resync_params;
};

struct sun4i_tv {
	struct drm_connector	connector;
	struct drm_encoder	encoder;

	struct clk		*clk;
	struct regmap		*regs;
	struct reset_control	*reset;

	struct sun4i_drv	*drv;
};

static const struct video_levels ntsc_video_levels = {
	.black = 282,	.blank = 240,
};

static const struct video_levels pal_video_levels = {
	.black = 252,	.blank = 252,
};

static const struct burst_levels ntsc_burst_levels = {
	.cb = 79,	.cr = 0,
};

static const struct burst_levels pal_burst_levels = {
	.cb = 40,	.cr = 40,
};

static const struct color_gains ntsc_color_gains = {
	.cb = 160,	.cr = 160,
};

static const struct color_gains pal_color_gains = {
	.cb = 224,	.cr = 224,
};

static const struct resync_parameters ntsc_resync_parameters = {
	.field = false,	.line = 14,	.pixel = 12,
};

static const struct resync_parameters pal_resync_parameters = {
	.field = true,	.line = 13,	.pixel = 12,
};

static const struct tv_mode tv_modes[] = {
	{
		.name		= "NTSC",
		.mode		= SUN4I_TVE_CFG0_RES_480i,
		.chroma_freq	= 0x21f07c1f,
		.yc_en		= true,
		.dac3_en	= true,
		.dac_bit25_en	= true,

		.back_porch	= 118,
		.front_porch	= 32,
		.line_number	= 525,

		.hdisplay	= 720,
		.hfront_porch	= 18,
		.hsync_len	= 2,
		.hback_porch	= 118,

		.vdisplay	= 480,
		.vfront_porch	= 26,
		.vsync_len	= 2,
		.vback_porch	= 17,

		.vblank_level	= 240,

		.color_gains	= &ntsc_color_gains,
		.burst_levels	= &ntsc_burst_levels,
		.video_levels	= &ntsc_video_levels,
		.resync_params	= &ntsc_resync_parameters,
	},
	{
		.name		= "PAL",
		.mode		= SUN4I_TVE_CFG0_RES_576i,
		.chroma_freq	= 0x2a098acb,

		.back_porch	= 138,
		.front_porch	= 24,
		.line_number	= 625,

		.hdisplay	= 720,
		.hfront_porch	= 3,
		.hsync_len	= 2,
		.hback_porch	= 139,

		.vdisplay	= 576,
		.vfront_porch	= 28,
		.vsync_len	= 2,
		.vback_porch	= 19,

		.vblank_level	= 252,

		.color_gains	= &pal_color_gains,
		.burst_levels	= &pal_burst_levels,
		.video_levels	= &pal_video_levels,
		.resync_params	= &pal_resync_parameters,
	},
};

static inline struct sun4i_tv *
drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
{
	return container_of(encoder, struct sun4i_tv,
			    encoder);
}

static inline struct sun4i_tv *
drm_connector_to_sun4i_tv(struct drm_connector *connector)
{
	return container_of(connector, struct sun4i_tv,
			    connector);
}

/*
 * FIXME: If only the drm_display_mode private field was usable, this
 * could go away...
 *
 * So far, it doesn't seem to be preserved when the mode is passed by
 * to mode_set for some reason.
 */
static const struct tv_mode *sun4i_tv_find_tv_by_mode(const struct drm_display_mode *mode)
{
	int i;

	/* First try to identify the mode by name */
	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
		const struct tv_mode *tv_mode = &tv_modes[i];

		DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
				 mode->name, tv_mode->name);

		if (!strcmp(mode->name, tv_mode->name))
			return tv_mode;
	}

	/* Then by number of lines */
	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
		const struct tv_mode *tv_mode = &tv_modes[i];

		DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
				 mode->name, tv_mode->name,
				 mode->vdisplay, tv_mode->vdisplay);

		if (mode->vdisplay == tv_mode->vdisplay)
			return tv_mode;
	}

	return NULL;
}

static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
				      struct drm_display_mode *mode)
{
	DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);

	mode->type = DRM_MODE_TYPE_DRIVER;
	mode->clock = 13500;
	mode->flags = DRM_MODE_FLAG_INTERLACE;

	mode->hdisplay = tv_mode->hdisplay;
	mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
	mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
	mode->htotal = mode->hsync_end  + tv_mode->hback_porch;

	mode->vdisplay = tv_mode->vdisplay;
	mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
	mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
	mode->vtotal = mode->vsync_end  + tv_mode->vback_porch;
}

static void sun4i_tv_disable(struct drm_encoder *encoder)
{
	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);

	DRM_DEBUG_DRIVER("Disabling the TV Output\n");

	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
			   SUN4I_TVE_EN_ENABLE,
			   0);

	sunxi_engine_disable_color_correction(crtc->engine);
}

static void sun4i_tv_enable(struct drm_encoder *encoder)
{
	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);

	DRM_DEBUG_DRIVER("Enabling the TV Output\n");

	sunxi_engine_apply_color_correction(crtc->engine);

	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
			   SUN4I_TVE_EN_ENABLE,
			   SUN4I_TVE_EN_ENABLE);
}

static void sun4i_tv_mode_set(struct drm_encoder *encoder,
			      struct drm_display_mode *mode,
			      struct drm_display_mode *adjusted_mode)
{
	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
	const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);

	/* Enable and map the DAC to the output */
	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
			   SUN4I_TVE_EN_DAC_MAP_MASK,
			   SUN4I_TVE_EN_DAC_MAP(0, 1) |
			   SUN4I_TVE_EN_DAC_MAP(1, 2) |
			   SUN4I_TVE_EN_DAC_MAP(2, 3) |
			   SUN4I_TVE_EN_DAC_MAP(3, 4));

	/* Set PAL settings */
	regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
		     tv_mode->mode |
		     (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
		     SUN4I_TVE_CFG0_COMP_EN |
		     SUN4I_TVE_CFG0_DAC_CONTROL_54M |
		     SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
		     SUN4I_TVE_CFG0_CORE_CONTROL_54M);

	/* Configure the DAC for a composite output */
	regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
		     SUN4I_TVE_DAC0_DAC_EN(0) |
		     (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
		     SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
		     SUN4I_TVE_DAC0_CHROMA_0_75 |
		     SUN4I_TVE_DAC0_LUMA_0_4 |
		     SUN4I_TVE_DAC0_CLOCK_INVERT |
		     (tv_mode->dac_bit25_en ? BIT(25) : 0) |
		     BIT(30));

	/* Configure the sample delay between DAC0 and the other DAC */
	regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
		     SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
		     SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));

	regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
		     tv_mode->chroma_freq);

	/* Set the front and back porch */
	regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
		     SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
		     SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));

	/* Set the lines setup */
	regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
		     SUN4I_TVE_LINE_FIRST(22) |
		     SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));

	regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
		     SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
		     SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));

	regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
		     SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
		     SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
		     SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
		     SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));

	regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
		     SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
		     SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));

	/* Set burst width for a composite output */
	regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
		     SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
		     SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
		     SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));

	regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
		     SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
		     SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));

	regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
		     SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
		     SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));

	regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
		     SUN4I_TVE_ACTIVE_LINE(1440));

	/* Set composite chroma gain to 50 % */
	regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
		     SUN4I_TVE_CHROMA_COMP_GAIN_50);

	regmap_write(tv->regs, SUN4I_TVE_12C_REG,
		     SUN4I_TVE_12C_COMP_YUV_EN |
		     SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);

	regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
		     SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
		     SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
		     (tv_mode->resync_params->field ?
		      SUN4I_TVE_RESYNC_FIELD : 0));

	regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
}

static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
	.disable	= sun4i_tv_disable,
	.enable		= sun4i_tv_enable,
	.mode_set	= sun4i_tv_mode_set,
};

static void sun4i_tv_destroy(struct drm_encoder *encoder)
{
	drm_encoder_cleanup(encoder);
}

static struct drm_encoder_funcs sun4i_tv_funcs = {
	.destroy	= sun4i_tv_destroy,
};

static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
		struct drm_display_mode *mode;
		const struct tv_mode *tv_mode = &tv_modes[i];

		mode = drm_mode_create(connector->dev);
		if (!mode) {
			DRM_ERROR("Failed to create a new display mode\n");
			return 0;
		}

		strcpy(mode->name, tv_mode->name);

		sun4i_tv_mode_to_drm_mode(tv_mode, mode);
		drm_mode_probed_add(connector, mode);
	}

	return i;
}

static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
				    struct drm_display_mode *mode)
{
	/* TODO */
	return MODE_OK;
}

static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
	.get_modes	= sun4i_tv_comp_get_modes,
	.mode_valid	= sun4i_tv_comp_mode_valid,
};

static void
sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
}

static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
	.fill_modes		= drm_helper_probe_single_connector_modes,
	.destroy		= sun4i_tv_comp_connector_destroy,
	.reset			= drm_atomic_helper_connector_reset,
	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
};

static struct regmap_config sun4i_tv_regmap_config = {
	.reg_bits	= 32,
	.val_bits	= 32,
	.reg_stride	= 4,
	.max_register	= SUN4I_TVE_WSS_DATA2_REG,
	.name		= "tv-encoder",
};

static int sun4i_tv_bind(struct device *dev, struct device *master,
			 void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct drm_device *drm = data;
	struct sun4i_drv *drv = drm->dev_private;
	struct sun4i_tv *tv;
	struct resource *res;
	void __iomem *regs;
	int ret;

	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
	if (!tv)
		return -ENOMEM;
	tv->drv = drv;
	dev_set_drvdata(dev, tv);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(regs)) {
		dev_err(dev, "Couldn't map the TV encoder registers\n");
		return PTR_ERR(regs);
	}

	tv->regs = devm_regmap_init_mmio(dev, regs,
					 &sun4i_tv_regmap_config);
	if (IS_ERR(tv->regs)) {
		dev_err(dev, "Couldn't create the TV encoder regmap\n");
		return PTR_ERR(tv->regs);
	}

	tv->reset = devm_reset_control_get(dev, NULL);
	if (IS_ERR(tv->reset)) {
		dev_err(dev, "Couldn't get our reset line\n");
		return PTR_ERR(tv->reset);
	}

	ret = reset_control_deassert(tv->reset);
	if (ret) {
		dev_err(dev, "Couldn't deassert our reset line\n");
		return ret;
	}

	tv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(tv->clk)) {
		dev_err(dev, "Couldn't get the TV encoder clock\n");
		ret = PTR_ERR(tv->clk);
		goto err_assert_reset;
	}
	clk_prepare_enable(tv->clk);

	drm_encoder_helper_add(&tv->encoder,
			       &sun4i_tv_helper_funcs);
	ret = drm_encoder_init(drm,
			       &tv->encoder,
			       &sun4i_tv_funcs,
			       DRM_MODE_ENCODER_TVDAC,
			       NULL);
	if (ret) {
		dev_err(dev, "Couldn't initialise the TV encoder\n");
		goto err_disable_clk;
	}

	tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
								dev->of_node);
	if (!tv->encoder.possible_crtcs) {
		ret = -EPROBE_DEFER;
		goto err_disable_clk;
	}

	drm_connector_helper_add(&tv->connector,
				 &sun4i_tv_comp_connector_helper_funcs);
	ret = drm_connector_init(drm, &tv->connector,
				 &sun4i_tv_comp_connector_funcs,
				 DRM_MODE_CONNECTOR_Composite);
	if (ret) {
		dev_err(dev,
			"Couldn't initialise the Composite connector\n");
		goto err_cleanup_connector;
	}
	tv->connector.interlace_allowed = true;

	drm_connector_attach_encoder(&tv->connector, &tv->encoder);

	return 0;

err_cleanup_connector:
	drm_encoder_cleanup(&tv->encoder);
err_disable_clk:
	clk_disable_unprepare(tv->clk);
err_assert_reset:
	reset_control_assert(tv->reset);
	return ret;
}

static void sun4i_tv_unbind(struct device *dev, struct device *master,
			    void *data)
{
	struct sun4i_tv *tv = dev_get_drvdata(dev);

	drm_connector_cleanup(&tv->connector);
	drm_encoder_cleanup(&tv->encoder);
	clk_disable_unprepare(tv->clk);
}

static const struct component_ops sun4i_tv_ops = {
	.bind	= sun4i_tv_bind,
	.unbind	= sun4i_tv_unbind,
};

static int sun4i_tv_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &sun4i_tv_ops);
}

static int sun4i_tv_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &sun4i_tv_ops);

	return 0;
}

static const struct of_device_id sun4i_tv_of_table[] = {
	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
	{ }
};
MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);

static struct platform_driver sun4i_tv_platform_driver = {
	.probe		= sun4i_tv_probe,
	.remove		= sun4i_tv_remove,
	.driver		= {
		.name		= "sun4i-tve",
		.of_match_table	= sun4i_tv_of_table,
	},
};
module_platform_driver(sun4i_tv_platform_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
03c4c71d MR	1	/*
	2	* Copyright (C) 2015 Free Electrons
	3	* Copyright (C) 2015 NextThing Co
	4	*
	5	* Maxime Ripard <maxime.ripard@free-electrons.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/component.h>
	15	#include <linux/of_address.h>
	16	#include <linux/regmap.h>
	17	#include <linux/reset.h>
	18
	19	#include <drm/drmP.h>
	20	#include <drm/drm_atomic_helper.h>
78428d67	21	#include <drm/drm_of.h>
03c4c71d	22	#include <drm/drm_panel.h>
fcd70cd3	23	#include <drm/drm_probe_helper.h>
03c4c71d	24
279156a3	25	#include "sun4i_crtc.h"
03c4c71d	26	#include "sun4i_drv.h"
87969338	27	#include "sunxi_engine.h"
03c4c71d MR	28
	29	#define SUN4I_TVE_EN_REG 0x000
	30	#define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)
	31	#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
	32	#define SUN4I_TVE_EN_ENABLE BIT(0)
	33
	34	#define SUN4I_TVE_CFG0_REG 0x004
	35	#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
	36	#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25)
	37	#define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24)
	38	#define SUN4I_TVE_CFG0_YC_EN BIT(17)
	39	#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
	40	#define SUN4I_TVE_CFG0_RES(x) ((x) & 0xf)
	41	#define SUN4I_TVE_CFG0_RES_480i SUN4I_TVE_CFG0_RES(0)
	42	#define SUN4I_TVE_CFG0_RES_576i SUN4I_TVE_CFG0_RES(1)
	43
	44	#define SUN4I_TVE_DAC0_REG 0x008
	45	#define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24)
	46	#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
	47	#define SUN4I_TVE_DAC0_LUMA_0_4 SUN4I_TVE_DAC0_LUMA(3)
	48	#define SUN4I_TVE_DAC0_CHROMA(x) (((x) & 3) << 18)
	49	#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
	50	#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
	51	#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS SUN4I_TVE_DAC0_INTERNAL_DAC(3)
	52	#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
	53
	54	#define SUN4I_TVE_NOTCH_REG 0x00c
	55	#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
	56
	57	#define SUN4I_TVE_CHROMA_FREQ_REG 0x010
	58
	59	#define SUN4I_TVE_PORCH_REG 0x014
	60	#define SUN4I_TVE_PORCH_BACK(x) ((x) << 16)
	61	#define SUN4I_TVE_PORCH_FRONT(x) (x)
	62
	63	#define SUN4I_TVE_LINE_REG 0x01c
	64	#define SUN4I_TVE_LINE_FIRST(x) ((x) << 16)
	65	#define SUN4I_TVE_LINE_NUMBER(x) (x)
	66
	67	#define SUN4I_TVE_LEVEL_REG 0x020
	68	#define SUN4I_TVE_LEVEL_BLANK(x) ((x) << 16)
	69	#define SUN4I_TVE_LEVEL_BLACK(x) (x)
	70
	71	#define SUN4I_TVE_DAC1_REG 0x024
	72	#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x) ((x) << (dac * 8))
	73
	74	#define SUN4I_TVE_DETECT_STA_REG 0x038
	75	#define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8))
	76	#define SUN4I_TVE_DETECT_STA_UNCONNECTED 0
	77	#define SUN4I_TVE_DETECT_STA_CONNECTED 1
	78	#define SUN4I_TVE_DETECT_STA_GROUND 2
	79
	80	#define SUN4I_TVE_CB_CR_LVL_REG 0x10c
	81	#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x) ((x) << 8)
	82	#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x) (x)
	83
	84	#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
	85	#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x) (x)
	86
	87	#define SUN4I_TVE_BURST_WIDTH_REG 0x114
	88	#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
	89	#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x) ((x) << 8)
	90	#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x) (x)
	91
92	#define SUN4I_TVE_CB_CR_GAIN_REG 0x118
93	#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
94	#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
95
96	#define SUN4I_TVE_SYNC_VBI_REG 0x11c
97	#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
98	#define SUN4I_TVE_SYNC_VBI_VBLANK(x) (x)
99
100	#define SUN4I_TVE_ACTIVE_LINE_REG 0x124
101	#define SUN4I_TVE_ACTIVE_LINE(x) (x)
102
103	#define SUN4I_TVE_CHROMA_REG 0x128
104	#define SUN4I_TVE_CHROMA_COMP_GAIN(x) ((x) & 3)
105	#define SUN4I_TVE_CHROMA_COMP_GAIN_50 SUN4I_TVE_CHROMA_COMP_GAIN(2)
106
107	#define SUN4I_TVE_12C_REG 0x12c
108	#define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8)
109	#define SUN4I_TVE_12C_COMP_YUV_EN BIT(0)
110
111	#define SUN4I_TVE_RESYNC_REG 0x130
112	#define SUN4I_TVE_RESYNC_FIELD BIT(31)
113	#define SUN4I_TVE_RESYNC_LINE(x) ((x) << 16)
114	#define SUN4I_TVE_RESYNC_PIXEL(x) (x)
115
116	#define SUN4I_TVE_SLAVE_REG 0x134
117
118	#define SUN4I_TVE_WSS_DATA2_REG 0x244
119
120	struct color_gains {
121	u16 cb;
122	u16 cr;
123	};
124
125	struct burst_levels {
126	u16 cb;
127	u16 cr;
128	};
129
130	struct video_levels {
131	u16 black;
132	u16 blank;
133	};
134
135	struct resync_parameters {
136	bool field;
137	u16 line;
138	u16 pixel;
139	};
140
141	struct tv_mode {
142	char *name;
143
144	u32 mode;
145	u32 chroma_freq;
146	u16 back_porch;
147	u16 front_porch;
148	u16 line_number;
149	u16 vblank_level;
150
151	u32 hdisplay;
152	u16 hfront_porch;
153	u16 hsync_len;
154	u16 hback_porch;
155
156	u32 vdisplay;
157	u16 vfront_porch;
158	u16 vsync_len;
159	u16 vback_porch;
160
161	bool yc_en;
162	bool dac3_en;
163	bool dac_bit25_en;
164
15ae0ea4 VS	165	const struct color_gains *color_gains;
	166	const struct burst_levels *burst_levels;
	167	const struct video_levels *video_levels;
	168	const struct resync_parameters *resync_params;
03c4c71d MR	169	};
	170
	171	struct sun4i_tv {
	172	struct drm_connector connector;
	173	struct drm_encoder encoder;
	174
	175	struct clk *clk;
	176	struct regmap *regs;
	177	struct reset_control *reset;
	178
	179	struct sun4i_drv *drv;
	180	};
	181
15ae0ea4	182	static const struct video_levels ntsc_video_levels = {
2ff77b16 MR	183	.black = 282, .blank = 240,
	184	};
	185
15ae0ea4	186	static const struct video_levels pal_video_levels = {
154f6950 MR	187	.black = 252, .blank = 252,
	188	};
	189
15ae0ea4	190	static const struct burst_levels ntsc_burst_levels = {
2ff77b16 MR	191	.cb = 79, .cr = 0,
	192	};
	193
15ae0ea4	194	static const struct burst_levels pal_burst_levels = {
154f6950 MR	195	.cb = 40, .cr = 40,
	196	};
	197
15ae0ea4	198	static const struct color_gains ntsc_color_gains = {
2ff77b16 MR	199	.cb = 160, .cr = 160,
	200	};
	201
15ae0ea4	202	static const struct color_gains pal_color_gains = {
154f6950 MR	203	.cb = 224, .cr = 224,
	204	};
	205
15ae0ea4	206	static const struct resync_parameters ntsc_resync_parameters = {
2ff77b16 MR	207	.field = false, .line = 14, .pixel = 12,
	208	};
	209
15ae0ea4	210	static const struct resync_parameters pal_resync_parameters = {
154f6950 MR	211	.field = true, .line = 13, .pixel = 12,
	212	};
	213
15ae0ea4	214	static const struct tv_mode tv_modes[] = {
2ff77b16 MR	215	{
	216	.name = "NTSC",
	217	.mode = SUN4I_TVE_CFG0_RES_480i,
	218	.chroma_freq = 0x21f07c1f,
	219	.yc_en = true,
	220	.dac3_en = true,
	221	.dac_bit25_en = true,
	222
	223	.back_porch = 118,
	224	.front_porch = 32,
	225	.line_number = 525,
	226
	227	.hdisplay = 720,
	228	.hfront_porch = 18,
	229	.hsync_len = 2,
	230	.hback_porch = 118,
	231
	232	.vdisplay = 480,
	233	.vfront_porch = 26,
	234	.vsync_len = 2,
	235	.vback_porch = 17,
	236
	237	.vblank_level = 240,
	238
	239	.color_gains = &ntsc_color_gains,
	240	.burst_levels = &ntsc_burst_levels,
	241	.video_levels = &ntsc_video_levels,
	242	.resync_params = &ntsc_resync_parameters,
	243	},
154f6950 MR	244	{
	245	.name = "PAL",
	246	.mode = SUN4I_TVE_CFG0_RES_576i,
	247	.chroma_freq = 0x2a098acb,
	248
	249	.back_porch = 138,
	250	.front_porch = 24,
	251	.line_number = 625,
	252
	253	.hdisplay = 720,
	254	.hfront_porch = 3,
	255	.hsync_len = 2,
	256	.hback_porch = 139,
	257
	258	.vdisplay = 576,
	259	.vfront_porch = 28,
	260	.vsync_len = 2,
	261	.vback_porch = 19,
	262
	263	.vblank_level = 252,
	264
	265	.color_gains = &pal_color_gains,
	266	.burst_levels = &pal_burst_levels,
	267	.video_levels = &pal_video_levels,
	268	.resync_params = &pal_resync_parameters,
	269	},
03c4c71d MR	270	};
	271
	272	static inline struct sun4i_tv *
	273	drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
	274	{
	275	return container_of(encoder, struct sun4i_tv,
	276	encoder);
	277	}
	278
	279	static inline struct sun4i_tv *
	280	drm_connector_to_sun4i_tv(struct drm_connector *connector)
	281	{
	282	return container_of(connector, struct sun4i_tv,
	283	connector);
	284	}
	285
	286	/*
	287	* FIXME: If only the drm_display_mode private field was usable, this
	288	* could go away...
	289	*
	290	* So far, it doesn't seem to be preserved when the mode is passed by
	291	* to mode_set for some reason.
	292	*/
15ae0ea4	293	static const struct tv_mode sun4i_tv_find_tv_by_mode(const struct drm_display_mode mode)
03c4c71d MR	294	{
	295	int i;
	296
	297	/* First try to identify the mode by name */
	298	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
15ae0ea4	299	const struct tv_mode *tv_mode = &tv_modes[i];
03c4c71d MR	300
	301	DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
	302	mode->name, tv_mode->name);
	303
	304	if (!strcmp(mode->name, tv_mode->name))
	305	return tv_mode;
	306	}
	307
	308	/* Then by number of lines */
	309	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
15ae0ea4	310	const struct tv_mode *tv_mode = &tv_modes[i];
03c4c71d MR	311
	312	DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
	313	mode->name, tv_mode->name,
	314	mode->vdisplay, tv_mode->vdisplay);
	315
	316	if (mode->vdisplay == tv_mode->vdisplay)
	317	return tv_mode;
	318	}
	319
	320	return NULL;
	321	}
	322
15ae0ea4	323	static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
03c4c71d MR	324	struct drm_display_mode *mode)
	325	{
	326	DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
	327
	328	mode->type = DRM_MODE_TYPE_DRIVER;
	329	mode->clock = 13500;
	330	mode->flags = DRM_MODE_FLAG_INTERLACE;
	331
	332	mode->hdisplay = tv_mode->hdisplay;
	333	mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
	334	mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
	335	mode->htotal = mode->hsync_end + tv_mode->hback_porch;
	336
	337	mode->vdisplay = tv_mode->vdisplay;
	338	mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
	339	mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
	340	mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
	341	}
	342
03c4c71d MR	343	static void sun4i_tv_disable(struct drm_encoder *encoder)
	344	{
	345	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
279156a3	346	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
03c4c71d MR	347
	348	DRM_DEBUG_DRIVER("Disabling the TV Output\n");
	349
03c4c71d MR	350	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
	351	SUN4I_TVE_EN_ENABLE,
	352	0);
87969338 IZ	353
87969338 IZ	354	sunxi_engine_disable_color_correction(crtc->engine);
03c4c71d MR	355	}
	356
	357	static void sun4i_tv_enable(struct drm_encoder *encoder)
	358	{
	359	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
279156a3	360	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
03c4c71d MR	361
	362	DRM_DEBUG_DRIVER("Enabling the TV Output\n");
	363
87969338	364	sunxi_engine_apply_color_correction(crtc->engine);
03c4c71d MR	365
	366	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
	367	SUN4I_TVE_EN_ENABLE,
	368	SUN4I_TVE_EN_ENABLE);
03c4c71d MR	369	}
	370
	371	static void sun4i_tv_mode_set(struct drm_encoder *encoder,
	372	struct drm_display_mode *mode,
	373	struct drm_display_mode *adjusted_mode)
	374	{
	375	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
15ae0ea4	376	const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
03c4c71d	377
03c4c71d MR	378	/* Enable and map the DAC to the output */
	379	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
	380	SUN4I_TVE_EN_DAC_MAP_MASK,
	381	SUN4I_TVE_EN_DAC_MAP(0, 1) \|
	382	SUN4I_TVE_EN_DAC_MAP(1, 2) \|
	383	SUN4I_TVE_EN_DAC_MAP(2, 3) \|
	384	SUN4I_TVE_EN_DAC_MAP(3, 4));
	385
	386	/* Set PAL settings */
	387	regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
	388	tv_mode->mode \|
	389	(tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) \|
	390	SUN4I_TVE_CFG0_COMP_EN \|
	391	SUN4I_TVE_CFG0_DAC_CONTROL_54M \|
	392	SUN4I_TVE_CFG0_CORE_DATAPATH_54M \|
	393	SUN4I_TVE_CFG0_CORE_CONTROL_54M);
	394
	395	/* Configure the DAC for a composite output */
	396	regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
	397	SUN4I_TVE_DAC0_DAC_EN(0) \|
	398	(tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) \|
	399	SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS \|
	400	SUN4I_TVE_DAC0_CHROMA_0_75 \|
	401	SUN4I_TVE_DAC0_LUMA_0_4 \|
	402	SUN4I_TVE_DAC0_CLOCK_INVERT \|
	403	(tv_mode->dac_bit25_en ? BIT(25) : 0) \|
	404	BIT(30));
	405
	406	/* Configure the sample delay between DAC0 and the other DAC */
	407	regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
	408	SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) \|
	409	SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
	410
	411	regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
	412	tv_mode->chroma_freq);
	413
	414	/* Set the front and back porch */
	415	regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
	416	SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) \|
	417	SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
	418
	419	/* Set the lines setup */
	420	regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
	421	SUN4I_TVE_LINE_FIRST(22) \|
	422	SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
	423
	424	regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
	425	SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) \|
	426	SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
	427
	428	regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
	429	SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) \|
	430	SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) \|
	431	SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) \|
	432	SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
	433
	434	regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
	435	SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) \|
	436	SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
	437
	438	/* Set burst width for a composite output */
	439	regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
	440	SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) \|
	441	SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) \|
442	SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
443
444	regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
445	SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) \|
446	SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
447
448	regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
449	SUN4I_TVE_SYNC_VBI_SYNC(0x10) \|
450	SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
451
452	regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
453	SUN4I_TVE_ACTIVE_LINE(1440));
454
455	/* Set composite chroma gain to 50 % */
456	regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
457	SUN4I_TVE_CHROMA_COMP_GAIN_50);
458
459	regmap_write(tv->regs, SUN4I_TVE_12C_REG,
460	SUN4I_TVE_12C_COMP_YUV_EN \|
461	SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
462
463	regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
464	SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) \|
465	SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) \|
466	(tv_mode->resync_params->field ?
467	SUN4I_TVE_RESYNC_FIELD : 0));
468
469	regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
03c4c71d MR	470	}
	471
	472	static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
03c4c71d MR	473	.disable = sun4i_tv_disable,
	474	.enable = sun4i_tv_enable,
	475	.mode_set = sun4i_tv_mode_set,
	476	};
	477
	478	static void sun4i_tv_destroy(struct drm_encoder *encoder)
	479	{
	480	drm_encoder_cleanup(encoder);
	481	}
	482
	483	static struct drm_encoder_funcs sun4i_tv_funcs = {
	484	.destroy = sun4i_tv_destroy,
	485	};
	486
	487	static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
	488	{
	489	int i;
	490
	491	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
e4192089	492	struct drm_display_mode *mode;
15ae0ea4	493	const struct tv_mode *tv_mode = &tv_modes[i];
03c4c71d	494
e4192089 MR	495	mode = drm_mode_create(connector->dev);
	496	if (!mode) {
	497	DRM_ERROR("Failed to create a new display mode\n");
	498	return 0;
	499	}
	500
03c4c71d MR	501	strcpy(mode->name, tv_mode->name);
	502
	503	sun4i_tv_mode_to_drm_mode(tv_mode, mode);
	504	drm_mode_probed_add(connector, mode);
	505	}
	506
	507	return i;
	508	}
	509
	510	static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
	511	struct drm_display_mode *mode)
	512	{
	513	/* TODO */
	514	return MODE_OK;
	515	}
	516
03c4c71d MR	517	static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
	518	.get_modes = sun4i_tv_comp_get_modes,
	519	.mode_valid = sun4i_tv_comp_mode_valid,
03c4c71d MR	520	};
03c4c71d MR	521
03c4c71d MR	522	static void
	523	sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
	524	{
	525	drm_connector_cleanup(connector);
	526	}
	527
32b4d575	528	static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
03c4c71d MR	529	.fill_modes = drm_helper_probe_single_connector_modes,
	530	.destroy = sun4i_tv_comp_connector_destroy,
	531	.reset = drm_atomic_helper_connector_reset,
	532	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	533	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	534	};
	535
	536	static struct regmap_config sun4i_tv_regmap_config = {
	537	.reg_bits = 32,
	538	.val_bits = 32,
	539	.reg_stride = 4,
	540	.max_register = SUN4I_TVE_WSS_DATA2_REG,
	541	.name = "tv-encoder",
	542	};
	543
	544	static int sun4i_tv_bind(struct device dev, struct device master,
	545	void *data)
	546	{
	547	struct platform_device *pdev = to_platform_device(dev);
	548	struct drm_device *drm = data;
	549	struct sun4i_drv *drv = drm->dev_private;
	550	struct sun4i_tv *tv;
	551	struct resource *res;
	552	void __iomem *regs;
	553	int ret;
	554
	555	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
	556	if (!tv)
	557	return -ENOMEM;
	558	tv->drv = drv;
	559	dev_set_drvdata(dev, tv);
	560
	561	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	562	regs = devm_ioremap_resource(dev, res);
	563	if (IS_ERR(regs)) {
	564	dev_err(dev, "Couldn't map the TV encoder registers\n");
	565	return PTR_ERR(regs);
	566	}
	567
	568	tv->regs = devm_regmap_init_mmio(dev, regs,
	569	&sun4i_tv_regmap_config);
	570	if (IS_ERR(tv->regs)) {
	571	dev_err(dev, "Couldn't create the TV encoder regmap\n");
	572	return PTR_ERR(tv->regs);
	573	}
	574
	575	tv->reset = devm_reset_control_get(dev, NULL);
	576	if (IS_ERR(tv->reset)) {
	577	dev_err(dev, "Couldn't get our reset line\n");
	578	return PTR_ERR(tv->reset);
	579	}
	580
	581	ret = reset_control_deassert(tv->reset);
	582	if (ret) {
	583	dev_err(dev, "Couldn't deassert our reset line\n");
	584	return ret;
	585	}
	586
	587	tv->clk = devm_clk_get(dev, NULL);
	588	if (IS_ERR(tv->clk)) {
	589	dev_err(dev, "Couldn't get the TV encoder clock\n");
	590	ret = PTR_ERR(tv->clk);
	591	goto err_assert_reset;
	592	}
593	clk_prepare_enable(tv->clk);
594
595	drm_encoder_helper_add(&tv->encoder,
596	&sun4i_tv_helper_funcs);
597	ret = drm_encoder_init(drm,
598	&tv->encoder,
599	&sun4i_tv_funcs,
600	DRM_MODE_ENCODER_TVDAC,
601	NULL);
602	if (ret) {
603	dev_err(dev, "Couldn't initialise the TV encoder\n");
604	goto err_disable_clk;
605	}
606
78428d67 CYT	607	tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
	608	dev->of_node);
	609	if (!tv->encoder.possible_crtcs) {
	610	ret = -EPROBE_DEFER;
	611	goto err_disable_clk;
	612	}
03c4c71d MR	613
	614	drm_connector_helper_add(&tv->connector,
	615	&sun4i_tv_comp_connector_helper_funcs);
	616	ret = drm_connector_init(drm, &tv->connector,
	617	&sun4i_tv_comp_connector_funcs,
	618	DRM_MODE_CONNECTOR_Composite);
	619	if (ret) {
	620	dev_err(dev,
	621	"Couldn't initialise the Composite connector\n");
	622	goto err_cleanup_connector;
	623	}
	624	tv->connector.interlace_allowed = true;
	625
cde4c44d	626	drm_connector_attach_encoder(&tv->connector, &tv->encoder);
03c4c71d MR	627
	628	return 0;
	629
	630	err_cleanup_connector:
	631	drm_encoder_cleanup(&tv->encoder);
	632	err_disable_clk:
	633	clk_disable_unprepare(tv->clk);
	634	err_assert_reset:
	635	reset_control_assert(tv->reset);
	636	return ret;
	637	}
	638
	639	static void sun4i_tv_unbind(struct device dev, struct device master,
	640	void *data)
	641	{
	642	struct sun4i_tv *tv = dev_get_drvdata(dev);
	643
	644	drm_connector_cleanup(&tv->connector);
	645	drm_encoder_cleanup(&tv->encoder);
	646	clk_disable_unprepare(tv->clk);
	647	}
	648
dfeb693d	649	static const struct component_ops sun4i_tv_ops = {
03c4c71d MR	650	.bind = sun4i_tv_bind,
	651	.unbind = sun4i_tv_unbind,
	652	};
	653
	654	static int sun4i_tv_probe(struct platform_device *pdev)
	655	{
	656	return component_add(&pdev->dev, &sun4i_tv_ops);
	657	}
	658
	659	static int sun4i_tv_remove(struct platform_device *pdev)
	660	{
	661	component_del(&pdev->dev, &sun4i_tv_ops);
	662
	663	return 0;
	664	}
	665
	666	static const struct of_device_id sun4i_tv_of_table[] = {
	667	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
	668	{ }
	669	};
	670	MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
	671
	672	static struct platform_driver sun4i_tv_platform_driver = {
	673	.probe = sun4i_tv_probe,
	674	.remove = sun4i_tv_remove,
	675	.driver = {
	676	.name = "sun4i-tve",
	677	.of_match_table = sun4i_tv_of_table,
	678	},
	679	};
	680	module_platform_driver(sun4i_tv_platform_driver);
	681
	682	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
	683	MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
	684	MODULE_LICENSE("GPL");