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drm/sun4i: dsi: Restrict DSI tcon clock divider
[thirdparty/linux.git] / drivers / gpu / drm / sun4i / sun6i_mipi_dsi.c
CommitLineData
133add5b
MR		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016 Allwinnertech Co., Ltd.
4 * Copyright (C) 2017-2018 Bootlin
5 *
6 * Maxime Ripard <maxime.ripard@bootlin.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/crc-ccitt.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
c51756d5 16#include <linux/slab.h>
133add5b
MR		 17
18#include <linux/phy/phy.h>
bb3b6fcb 19#include <linux/phy/phy-mipi-dphy.h>
133add5b
MR		 20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
133add5b
MR		 23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_panel.h>
fcd70cd3 25#include <drm/drm_probe_helper.h>
133add5b
MR		 26
27#include "sun4i_drv.h"
28#include "sun6i_mipi_dsi.h"
29
30#include <video/mipi_display.h>
31
32#define SUN6I_DSI_CTL_REG 0x000
33#define SUN6I_DSI_CTL_EN BIT(0)
34
35#define SUN6I_DSI_BASIC_CTL_REG 0x00c
36#define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
37#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
38#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
39
40#define SUN6I_DSI_BASIC_CTL0_REG 0x010
41#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
42#define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
43#define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
44#define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
45
46#define SUN6I_DSI_BASIC_CTL1_REG 0x014
47#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
48#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
49#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
50#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
51
52#define SUN6I_DSI_BASIC_SIZE0_REG 0x018
53#define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
54#define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
55
56#define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
57#define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
58#define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
59
60#define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
61#define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
62#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
63#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
64#define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
65#define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
66
67#define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
68
69#define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
70#define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
71#define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
72
73#define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
74
75#define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
76#define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
77#define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
78#define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
79
80#define SUN6I_DSI_TRANS_START_REG 0x060
81
82#define SUN6I_DSI_TRANS_ZERO_REG 0x078
83
84#define SUN6I_DSI_TCON_DRQ_REG 0x07c
85#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
86#define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
87
88#define SUN6I_DSI_PIXEL_CTL0_REG 0x080
89#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
90#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
91
92#define SUN6I_DSI_PIXEL_CTL1_REG 0x084
93
94#define SUN6I_DSI_PIXEL_PH_REG 0x090
95#define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
96#define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
97#define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
98#define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
99
100#define SUN6I_DSI_PIXEL_PF0_REG 0x098
101#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
102
103#define SUN6I_DSI_PIXEL_PF1_REG 0x09c
104#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
105#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
106
107#define SUN6I_DSI_SYNC_HSS_REG 0x0b0
108
109#define SUN6I_DSI_SYNC_HSE_REG 0x0b4
110
111#define SUN6I_DSI_SYNC_VSS_REG 0x0b8
112
113#define SUN6I_DSI_SYNC_VSE_REG 0x0bc
114
115#define SUN6I_DSI_BLK_HSA0_REG 0x0c0
116
117#define SUN6I_DSI_BLK_HSA1_REG 0x0c4
118#define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
119#define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
120
121#define SUN6I_DSI_BLK_HBP0_REG 0x0c8
122
123#define SUN6I_DSI_BLK_HBP1_REG 0x0cc
124
125#define SUN6I_DSI_BLK_HFP0_REG 0x0d0
126
127#define SUN6I_DSI_BLK_HFP1_REG 0x0d4
128
129#define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
130
131#define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
132
133#define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
134
135#define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
136
137#define SUN6I_DSI_BURST_LINE_REG 0x0f0
138#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
139#define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
140
141#define SUN6I_DSI_BURST_DRQ_REG 0x0f4
142#define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
143#define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
144
145#define SUN6I_DSI_CMD_CTL_REG 0x200
146#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
147#define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
148#define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
149
150#define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
151
152#define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
153
154#define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
155
156enum sun6i_dsi_start_inst {
157 DSI_START_LPRX,
158 DSI_START_LPTX,
159 DSI_START_HSC,
160 DSI_START_HSD,
161};
162
163enum sun6i_dsi_inst_id {
164 DSI_INST_ID_LP11 = 0,
165 DSI_INST_ID_TBA,
166 DSI_INST_ID_HSC,
167 DSI_INST_ID_HSD,
168 DSI_INST_ID_LPDT,
169 DSI_INST_ID_HSCEXIT,
170 DSI_INST_ID_NOP,
171 DSI_INST_ID_DLY,
172 DSI_INST_ID_END = 15,
173};
174
175enum sun6i_dsi_inst_mode {
176 DSI_INST_MODE_STOP = 0,
177 DSI_INST_MODE_TBA,
178 DSI_INST_MODE_HS,
179 DSI_INST_MODE_ESCAPE,
180 DSI_INST_MODE_HSCEXIT,
181 DSI_INST_MODE_NOP,
182};
183
184enum sun6i_dsi_inst_escape {
185 DSI_INST_ESCA_LPDT = 0,
186 DSI_INST_ESCA_ULPS,
187 DSI_INST_ESCA_UN1,
188 DSI_INST_ESCA_UN2,
189 DSI_INST_ESCA_RESET,
190 DSI_INST_ESCA_UN3,
191 DSI_INST_ESCA_UN4,
192 DSI_INST_ESCA_UN5,
193};
194
195enum sun6i_dsi_inst_packet {
196 DSI_INST_PACK_PIXEL = 0,
197 DSI_INST_PACK_COMMAND,
198};
199
200static const u32 sun6i_dsi_ecc_array[] = {
201 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
202 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
203 BIT(23)),
204 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
205 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
206 BIT(23)),
207 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
208 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
209 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
210 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
211 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
212 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
213 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
214 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
215 BIT(23)),
216};
217
218static u32 sun6i_dsi_ecc_compute(unsigned int data)
219{
220 int i;
221 u8 ecc = 0;
222
223 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
224 u32 field = sun6i_dsi_ecc_array[i];
225 bool init = false;
226 u8 val = 0;
227 int j;
228
229 for (j = 0; j < 24; j++) {
230 if (!(BIT(j) & field))
231 continue;
232
233 if (!init) {
234 val = (BIT(j) & data) ? 1 : 0;
235 init = true;
236 } else {
237 val ^= (BIT(j) & data) ? 1 : 0;
238 }
239 }
240
241 ecc |= val << i;
242 }
243
244 return ecc;
245}
246
247static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
248{
249 return crc_ccitt(0xffff, buffer, len);
250}
251
c51756d5 252static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len)
133add5b 253{
133add5b
MR		 254 memset(buffer, pd, len);
255
256 return sun6i_dsi_crc_compute(buffer, len);
257}
258
259static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
260{
261 u32 val = dt & 0x3f;
262
263 val |= (vc & 3) << 6;
264 val |= (d0 & 0xff) << 8;
265 val |= (d1 & 0xff) << 16;
266 val |= sun6i_dsi_ecc_compute(val) << 24;
267
268 return val;
269}
270
271static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
272{
273 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
274 wc & 0xff, wc >> 8);
275}
276
c51756d5 277static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len)
133add5b
MR		 278{
279 u32 val = SUN6I_DSI_BLK_PD(pd);
280
c51756d5 281 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len));
133add5b
MR		 282}
283
284static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
285{
286 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
287 SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
288}
289
290static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
291{
292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
293 SUN6I_DSI_BASIC_CTL0_INST_ST,
294 SUN6I_DSI_BASIC_CTL0_INST_ST);
295}
296
297static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
298{
299 u32 val;
300
301 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
302 val,
303 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
304 100, 5000);
305}
306
307static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
308 enum sun6i_dsi_inst_id id,
309 enum sun6i_dsi_inst_mode mode,
310 bool clock, u8 data,
311 enum sun6i_dsi_inst_packet packet,
312 enum sun6i_dsi_inst_escape escape)
313{
314 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
315 SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
316 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
317 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
318 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
319 SUN6I_DSI_INST_FUNC_LANE_DEN(data));
320}
321
322static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
323 struct mipi_dsi_device *device)
324{
325 u8 lanes_mask = GENMASK(device->lanes - 1, 0);
326
327 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
328 true, lanes_mask, 0, 0);
329
330 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
331 false, 1, 0, 0);
332
333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
334 true, 0, DSI_INST_PACK_PIXEL, 0);
335
336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
337 false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
338
339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
340 false, 1, DSI_INST_PACK_COMMAND,
341 DSI_INST_ESCA_LPDT);
342
343 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
344 true, 0, 0, 0);
345
346 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
347 false, lanes_mask, 0, 0);
348
349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
350 true, lanes_mask, 0, 0);
351
352 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
353 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
354 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
355 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
356};
357
358static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
359 struct drm_display_mode *mode)
360{
361 return mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
362}
363
364static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
365 struct drm_display_mode *mode)
366{
367 struct mipi_dsi_device *device = dsi->device;
368 u32 val = 0;
369
370 if ((mode->hsync_end - mode->hdisplay) > 20) {
371 /* Maaaaaagic */
372 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
373
374 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
375 drq /= 32;
376
377 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
378 SUN6I_DSI_TCON_DRQ_SET(drq));
379 }
380
381 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
382}
383
384static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
385 struct drm_display_mode *mode)
386{
387 u16 delay = 50 - 1;
388
389 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
390 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
391 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
392 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
393 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
394 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
395}
396
397static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
398 struct drm_display_mode *mode)
399{
400 struct mipi_dsi_device *device = dsi->device;
401 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
402 u8 dt, fmt;
403 u16 wc;
404
405 /*
406 * TODO: The format defines are only valid in video mode and
407 * change in command mode.
408 */
409 switch (device->format) {
410 case MIPI_DSI_FMT_RGB888:
411 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
412 fmt = 8;
413 break;
414 case MIPI_DSI_FMT_RGB666:
415 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
416 fmt = 9;
417 break;
418 case MIPI_DSI_FMT_RGB666_PACKED:
419 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
420 fmt = 10;
421 break;
422 case MIPI_DSI_FMT_RGB565:
423 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
424 fmt = 11;
425 break;
426 default:
427 return;
428 }
429 val |= SUN6I_DSI_PIXEL_PH_DT(dt);
430
431 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
432 val |= SUN6I_DSI_PIXEL_PH_WC(wc);
433 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
434
435 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
436
437 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
438 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
439
440 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
441 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
442 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
443
444 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
445 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
446 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
447}
448
449static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
450 struct drm_display_mode *mode)
451{
452 struct mipi_dsi_device *device = dsi->device;
453 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
454 u16 hbp, hfp, hsa, hblk, vblk;
c51756d5
KC		 455 size_t bytes;
456 u8 *buffer;
457
458 /* Do all timing calculations up front to allocate buffer space */
459
460 /*
461 * A sync period is composed of a blanking packet (4 bytes +
462 * payload + 2 bytes) and a sync event packet (4 bytes). Its
463 * minimal size is therefore 10 bytes
464 */
465#define HSA_PACKET_OVERHEAD 10
466 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
467 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
468
469 /*
470 * The backporch is set using a blanking packet (4 bytes +
471 * payload + 2 bytes). Its minimal size is therefore 6 bytes
472 */
473#define HBP_PACKET_OVERHEAD 6
474 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
475 (mode->hsync_start - mode->hdisplay) * Bpp - HBP_PACKET_OVERHEAD);
476
477 /*
478 * The frontporch is set using a blanking packet (4 bytes +
479 * payload + 2 bytes). Its minimal size is therefore 6 bytes
480 */
481#define HFP_PACKET_OVERHEAD 6
482 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
483 (mode->htotal - mode->hsync_end) * Bpp - HFP_PACKET_OVERHEAD);
484
485 /*
486 * hblk seems to be the line + porches length.
487 */
488 hblk = mode->htotal * Bpp - hsa;
489
490 /*
491 * And I'm not entirely sure what vblk is about. The driver in
492 * Allwinner BSP is using a rather convoluted calculation
493 * there only for 4 lanes. However, using 0 (the !4 lanes
494 * case) even with a 4 lanes screen seems to work...
495 */
496 vblk = 0;
497
498 /* How many bytes do we need to send all payloads? */
499 bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
500 buffer = kmalloc(bytes, GFP_KERNEL);
501 if (WARN_ON(!buffer))
502 return;
133add5b
MR		 503
504 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, 0);
505
506 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
507 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
508 device->channel,
509 0, 0));
510
511 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
512 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
513 device->channel,
514 0, 0));
515
516 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
517 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
518 device->channel,
519 0, 0));
520
521 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
522 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
523 device->channel,
524 0, 0));
525
526 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
527 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
528 mode->vsync_start) |
529 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
530 mode->vdisplay));
531
532 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
533 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
534 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
535
c51756d5 536 /* sync */
133add5b
MR		 537 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
538 sun6i_dsi_build_blk0_pkt(device->channel, hsa));
539 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
c51756d5 540 sun6i_dsi_build_blk1_pkt(0, buffer, hsa));
133add5b 541
c51756d5 542 /* backporch */
133add5b
MR		 543 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
544 sun6i_dsi_build_blk0_pkt(device->channel, hbp));
545 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
c51756d5 546 sun6i_dsi_build_blk1_pkt(0, buffer, hbp));
133add5b 547
c51756d5 548 /* frontporch */
133add5b
MR		 549 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
550 sun6i_dsi_build_blk0_pkt(device->channel, hfp));
551 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
c51756d5 552 sun6i_dsi_build_blk1_pkt(0, buffer, hfp));
133add5b 553
c51756d5 554 /* hblk */
133add5b
MR		 555 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
556 sun6i_dsi_build_blk0_pkt(device->channel, hblk));
557 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
c51756d5 558 sun6i_dsi_build_blk1_pkt(0, buffer, hblk));
133add5b 559
c51756d5 560 /* vblk */
133add5b
MR		 561 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
562 sun6i_dsi_build_blk0_pkt(device->channel, vblk));
563 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
c51756d5
KC		 564 sun6i_dsi_build_blk1_pkt(0, buffer, vblk));
565
566 kfree(buffer);
133add5b
MR		 567}
568
569static int sun6i_dsi_start(struct sun6i_dsi *dsi,
570 enum sun6i_dsi_start_inst func)
571{
572 switch (func) {
573 case DSI_START_LPTX:
574 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
575 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
576 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT));
577 break;
578 case DSI_START_LPRX:
579 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
580 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
581 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) |
582 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) |
583 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA));
584 break;
585 case DSI_START_HSC:
586 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
587 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) |
588 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC));
589 break;
590 case DSI_START_HSD:
591 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
592 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) |
593 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) |
594 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) |
595 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) |
596 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT));
597 break;
598 default:
599 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
600 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11));
601 break;
602 }
603
604 sun6i_dsi_inst_abort(dsi);
605 sun6i_dsi_inst_commit(dsi);
606
607 if (func == DSI_START_HSC)
608 regmap_write_bits(dsi->regs,
609 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
610 SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
611
612 return 0;
613}
614
615static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
616{
617 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
618 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
619 struct mipi_dsi_device *device = dsi->device;
bb3b6fcb
MR		 620 union phy_configure_opts opts = { 0 };
621 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
133add5b
MR		 622 u16 delay;
623
624 DRM_DEBUG_DRIVER("Enabling DSI output\n");
625
626 pm_runtime_get_sync(dsi->dev);
627
628 delay = sun6i_dsi_get_video_start_delay(dsi, mode);
629 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
630 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
631 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
632 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
633 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
634
635 sun6i_dsi_setup_burst(dsi, mode);
636 sun6i_dsi_setup_inst_loop(dsi, mode);
637 sun6i_dsi_setup_format(dsi, mode);
638 sun6i_dsi_setup_timings(dsi, mode);
639
bb3b6fcb
MR		 640 phy_init(dsi->dphy);
641
642 phy_mipi_dphy_get_default_config(mode->clock * 1000,
643 mipi_dsi_pixel_format_to_bpp(device->format),
644 device->lanes, cfg);
645
646 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
647 phy_configure(dsi->dphy, &opts);
648 phy_power_on(dsi->dphy);
133add5b
MR		 649
650 if (!IS_ERR(dsi->panel))
651 drm_panel_prepare(dsi->panel);
652
653 /*
654 * FIXME: This should be moved after the switch to HS mode.
655 *
656 * Unfortunately, once in HS mode, it seems like we're not
657 * able to send DCS commands anymore, which would prevent any
658 * panel to send any DCS command as part as their enable
659 * method, which is quite common.
660 *
661 * I haven't seen any artifact due to that sub-optimal
662 * ordering on the panels I've tested it with, so I guess this
663 * will do for now, until that IP is better understood.
664 */
665 if (!IS_ERR(dsi->panel))
666 drm_panel_enable(dsi->panel);
667
668 sun6i_dsi_start(dsi, DSI_START_HSC);
669
670 udelay(1000);
671
672 sun6i_dsi_start(dsi, DSI_START_HSD);
673}
674
675static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
676{
677 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
678
679 DRM_DEBUG_DRIVER("Disabling DSI output\n");
680
681 if (!IS_ERR(dsi->panel)) {
682 drm_panel_disable(dsi->panel);
683 drm_panel_unprepare(dsi->panel);
684 }
685
bb3b6fcb
MR		 686 phy_power_off(dsi->dphy);
687 phy_exit(dsi->dphy);
133add5b
MR		 688
689 pm_runtime_put(dsi->dev);
690}
691
692static int sun6i_dsi_get_modes(struct drm_connector *connector)
693{
694 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
695
696 return drm_panel_get_modes(dsi->panel);
697}
698
699static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
700 .get_modes = sun6i_dsi_get_modes,
701};
702
703static enum drm_connector_status
704sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
705{
706 return connector_status_connected;
707}
708
709static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
710 .detect = sun6i_dsi_connector_detect,
711 .fill_modes = drm_helper_probe_single_connector_modes,
712 .destroy = drm_connector_cleanup,
713 .reset = drm_atomic_helper_connector_reset,
714 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
715 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
716};
717
718static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
719 .disable = sun6i_dsi_encoder_disable,
720 .enable = sun6i_dsi_encoder_enable,
721};
722
723static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
724 .destroy = drm_encoder_cleanup,
725};
726
727static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
728 const struct mipi_dsi_msg *msg)
729{
730 u32 pkt = msg->type;
731
732 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
733 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
734 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
735 } else {
736 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
737 if (msg->tx_len > 1)
738 pkt |= (((u8 *)msg->tx_buf)[1] << 16);
739 }
740
741 pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
742
743 return pkt;
744}
745
746static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
747 const struct mipi_dsi_msg *msg)
748{
749 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
750 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
751 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
752 0xff, (4 - 1));
753
754 sun6i_dsi_start(dsi, DSI_START_LPTX);
755
756 return msg->tx_len;
757}
758
759static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
760 const struct mipi_dsi_msg *msg)
761{
762 int ret, len = 0;
763 u8 *bounce;
764 u16 crc;
765
766 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
767 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
768
769 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
770 if (!bounce)
771 return -ENOMEM;
772
773 memcpy(bounce, msg->tx_buf, msg->tx_len);
774 len += msg->tx_len;
775
776 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
777 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
778 len += sizeof(crc);
779
780 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
781 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
782 kfree(bounce);
783
784 sun6i_dsi_start(dsi, DSI_START_LPTX);
785
786 ret = sun6i_dsi_inst_wait_for_completion(dsi);
787 if (ret < 0) {
788 sun6i_dsi_inst_abort(dsi);
789 return ret;
790 }
791
792 /*
793 * TODO: There's some bits (reg 0x200, bits 8/9) that
794 * apparently can be used to check whether the data have been
795 * sent, but I couldn't get it to work reliably.
796 */
797 return msg->tx_len;
798}
799
800static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
801 const struct mipi_dsi_msg *msg)
802{
803 u32 val;
804 int ret;
805 u8 byte0;
806
807 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
808 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
809 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
810 (4 - 1));
811
812 sun6i_dsi_start(dsi, DSI_START_LPRX);
813
814 ret = sun6i_dsi_inst_wait_for_completion(dsi);
815 if (ret < 0) {
816 sun6i_dsi_inst_abort(dsi);
817 return ret;
818 }
819
820 /*
821 * TODO: There's some bits (reg 0x200, bits 24/25) that
822 * apparently can be used to check whether the data have been
823 * received, but I couldn't get it to work reliably.
824 */
825 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
826 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
827 return -EIO;
828
829 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
830 byte0 = val & 0xff;
831 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
832 return -EIO;
833
834 ((u8 *)msg->rx_buf)[0] = (val >> 8);
835
836 return 1;
837}
838
839static int sun6i_dsi_attach(struct mipi_dsi_host *host,
840 struct mipi_dsi_device *device)
841{
842 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
843
844 dsi->device = device;
845 dsi->panel = of_drm_find_panel(device->dev.of_node);
5fa8e4a2
BB		 846 if (IS_ERR(dsi->panel))
847 return PTR_ERR(dsi->panel);
133add5b
MR		 848
849 dev_info(host->dev, "Attached device %s\n", device->name);
850
851 return 0;
852}
853
854static int sun6i_dsi_detach(struct mipi_dsi_host *host,
855 struct mipi_dsi_device *device)
856{
857 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
858
859 dsi->panel = NULL;
860 dsi->device = NULL;
861
862 return 0;
863}
864
865static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
866 const struct mipi_dsi_msg *msg)
867{
868 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
869 int ret;
870
871 ret = sun6i_dsi_inst_wait_for_completion(dsi);
872 if (ret < 0)
873 sun6i_dsi_inst_abort(dsi);
874
875 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
876 SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
877 SUN6I_DSI_CMD_CTL_RX_FLAG |
878 SUN6I_DSI_CMD_CTL_TX_FLAG);
879
880 switch (msg->type) {
881 case MIPI_DSI_DCS_SHORT_WRITE:
882 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
883 ret = sun6i_dsi_dcs_write_short(dsi, msg);
884 break;
885
886 case MIPI_DSI_DCS_LONG_WRITE:
887 ret = sun6i_dsi_dcs_write_long(dsi, msg);
888 break;
889
890 case MIPI_DSI_DCS_READ:
891 if (msg->rx_len == 1) {
892 ret = sun6i_dsi_dcs_read(dsi, msg);
893 break;
894 }
895
896 default:
897 ret = -EINVAL;
898 }
899
900 return ret;
901}
902
903static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
904 .attach = sun6i_dsi_attach,
905 .detach = sun6i_dsi_detach,
906 .transfer = sun6i_dsi_transfer,
907};
908
909static const struct regmap_config sun6i_dsi_regmap_config = {
910 .reg_bits = 32,
911 .val_bits = 32,
912 .reg_stride = 4,
913 .max_register = SUN6I_DSI_CMD_TX_REG(255),
914 .name = "mipi-dsi",
915};
916
917static int sun6i_dsi_bind(struct device *dev, struct device *master,
918 void *data)
919{
920 struct drm_device *drm = data;
921 struct sun4i_drv *drv = drm->dev_private;
922 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
923 int ret;
924
925 if (!dsi->panel)
926 return -EPROBE_DEFER;
927
928 dsi->drv = drv;
929
930 drm_encoder_helper_add(&dsi->encoder,
931 &sun6i_dsi_enc_helper_funcs);
932 ret = drm_encoder_init(drm,
933 &dsi->encoder,
934 &sun6i_dsi_enc_funcs,
935 DRM_MODE_ENCODER_DSI,
936 NULL);
937 if (ret) {
938 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
939 return ret;
940 }
941 dsi->encoder.possible_crtcs = BIT(0);
942
943 drm_connector_helper_add(&dsi->connector,
944 &sun6i_dsi_connector_helper_funcs);
945 ret = drm_connector_init(drm, &dsi->connector,
946 &sun6i_dsi_connector_funcs,
947 DRM_MODE_CONNECTOR_DSI);
948 if (ret) {
949 dev_err(dsi->dev,
950 "Couldn't initialise the DSI connector\n");
951 goto err_cleanup_connector;
952 }
953
cde4c44d 954 drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
133add5b
MR		 955 drm_panel_attach(dsi->panel, &dsi->connector);
956
957 return 0;
958
959err_cleanup_connector:
960 drm_encoder_cleanup(&dsi->encoder);
961 return ret;
962}
963
964static void sun6i_dsi_unbind(struct device *dev, struct device *master,
965 void *data)
966{
967 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
968
969 drm_panel_detach(dsi->panel);
970}
971
972static const struct component_ops sun6i_dsi_ops = {
973 .bind = sun6i_dsi_bind,
974 .unbind = sun6i_dsi_unbind,
975};
976
977static int sun6i_dsi_probe(struct platform_device *pdev)
978{
979 struct device *dev = &pdev->dev;
133add5b
MR		 980 struct sun6i_dsi *dsi;
981 struct resource *res;
982 void __iomem *base;
983 int ret;
984
985 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
986 if (!dsi)
987 return -ENOMEM;
988 dev_set_drvdata(dev, dsi);
989 dsi->dev = dev;
990 dsi->host.ops = &sun6i_dsi_host_ops;
991 dsi->host.dev = dev;
992
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 base = devm_ioremap_resource(dev, res);
995 if (IS_ERR(base)) {
996 dev_err(dev, "Couldn't map the DSI encoder registers\n");
997 return PTR_ERR(base);
998 }
999
1000 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
1001 &sun6i_dsi_regmap_config);
1002 if (IS_ERR(dsi->regs)) {
1003 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
1004 return PTR_ERR(dsi->regs);
1005 }
1006
1007 dsi->reset = devm_reset_control_get_shared(dev, NULL);
1008 if (IS_ERR(dsi->reset)) {
1009 dev_err(dev, "Couldn't get our reset line\n");
1010 return PTR_ERR(dsi->reset);
1011 }
1012
1013 dsi->mod_clk = devm_clk_get(dev, "mod");
1014 if (IS_ERR(dsi->mod_clk)) {
1015 dev_err(dev, "Couldn't get the DSI mod clock\n");
1016 return PTR_ERR(dsi->mod_clk);
1017 }
1018
1019 /*
1020 * In order to operate properly, that clock seems to be always
1021 * set to 297MHz.
1022 */
1023 clk_set_rate_exclusive(dsi->mod_clk, 297000000);
1024
bb3b6fcb
MR		 1025 dsi->dphy = devm_phy_get(dev, "dphy");
1026 if (IS_ERR(dsi->dphy)) {
133add5b 1027 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1c7c62a3 1028 ret = PTR_ERR(dsi->dphy);
133add5b
MR		 1029 goto err_unprotect_clk;
1030 }
1031
1032 pm_runtime_enable(dev);
1033
1034 ret = mipi_dsi_host_register(&dsi->host);
1035 if (ret) {
1036 dev_err(dev, "Couldn't register MIPI-DSI host\n");
bb3b6fcb 1037 goto err_pm_disable;
133add5b
MR		 1038 }
1039
1040 ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1041 if (ret) {
1042 dev_err(dev, "Couldn't register our component\n");
1043 goto err_remove_dsi_host;
1044 }
1045
1046 return 0;
1047
1048err_remove_dsi_host:
1049 mipi_dsi_host_unregister(&dsi->host);
bb3b6fcb 1050err_pm_disable:
133add5b 1051 pm_runtime_disable(dev);
133add5b
MR		 1052err_unprotect_clk:
1053 clk_rate_exclusive_put(dsi->mod_clk);
1054 return ret;
1055}
1056
1057static int sun6i_dsi_remove(struct platform_device *pdev)
1058{
1059 struct device *dev = &pdev->dev;
1060 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1061
1062 component_del(&pdev->dev, &sun6i_dsi_ops);
1063 mipi_dsi_host_unregister(&dsi->host);
1064 pm_runtime_disable(dev);
133add5b
MR		 1065 clk_rate_exclusive_put(dsi->mod_clk);
1066
1067 return 0;
1068}
1069
6b1c5eaf 1070static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
133add5b
MR		 1071{
1072 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1073
1074 reset_control_deassert(dsi->reset);
1075 clk_prepare_enable(dsi->mod_clk);
1076
1077 /*
1078 * Enable the DSI block.
1079 *
1080 * Some part of it can only be done once we get a number of
1081 * lanes, see sun6i_dsi_inst_init
1082 */
1083 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1084
1085 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1086 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1087
1088 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1089 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1090
1091 if (dsi->device)
1092 sun6i_dsi_inst_init(dsi, dsi->device);
1093
1094 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1095
1096 return 0;
1097}
1098
6b1c5eaf 1099static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
133add5b
MR		 1100{
1101 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1102
1103 clk_disable_unprepare(dsi->mod_clk);
1104 reset_control_assert(dsi->reset);
1105
1106 return 0;
1107}
1108
1109static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1110 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1111 sun6i_dsi_runtime_resume,
1112 NULL)
1113};
1114
1115static const struct of_device_id sun6i_dsi_of_table[] = {
1116 { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1117 { }
1118};
1119MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1120
1121static struct platform_driver sun6i_dsi_platform_driver = {
1122 .probe = sun6i_dsi_probe,
1123 .remove = sun6i_dsi_remove,
1124 .driver = {
1125 .name = "sun6i-mipi-dsi",
1126 .of_match_table = sun6i_dsi_of_table,
1127 .pm = &sun6i_dsi_pm_ops,
1128 },
1129};
1130module_platform_driver(sun6i_dsi_platform_driver);
1131
1132MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1133MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1134MODULE_LICENSE("GPL");
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