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drm/sun4i: dsi: Change the start delay calculation
[thirdparty/linux.git] / drivers / gpu / drm / sun4i / sun6i_mipi_dsi.c
CommitLineData
133add5b
MR		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016 Allwinnertech Co., Ltd.
4 * Copyright (C) 2017-2018 Bootlin
5 *
6 * Maxime Ripard <maxime.ripard@bootlin.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/crc-ccitt.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
c51756d5 16#include <linux/slab.h>
133add5b
MR		 17
18#include <linux/phy/phy.h>
bb3b6fcb 19#include <linux/phy/phy-mipi-dphy.h>
133add5b
MR		 20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
133add5b
MR		 23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_panel.h>
fcd70cd3 25#include <drm/drm_probe_helper.h>
133add5b
MR		 26
27#include "sun4i_drv.h"
28#include "sun6i_mipi_dsi.h"
29
30#include <video/mipi_display.h>
31
32#define SUN6I_DSI_CTL_REG 0x000
33#define SUN6I_DSI_CTL_EN BIT(0)
34
35#define SUN6I_DSI_BASIC_CTL_REG 0x00c
36#define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
37#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
38#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
39
40#define SUN6I_DSI_BASIC_CTL0_REG 0x010
41#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
42#define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
43#define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
44#define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
45
46#define SUN6I_DSI_BASIC_CTL1_REG 0x014
47#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
48#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
49#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
50#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
51
52#define SUN6I_DSI_BASIC_SIZE0_REG 0x018
53#define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
54#define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
55
56#define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
57#define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
58#define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
59
60#define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
61#define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
62#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
63#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
64#define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
65#define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
66
67#define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
68
69#define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
70#define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
71#define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
72
73#define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
74
75#define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
76#define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
77#define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
78#define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
79
80#define SUN6I_DSI_TRANS_START_REG 0x060
81
82#define SUN6I_DSI_TRANS_ZERO_REG 0x078
83
84#define SUN6I_DSI_TCON_DRQ_REG 0x07c
85#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
86#define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
87
88#define SUN6I_DSI_PIXEL_CTL0_REG 0x080
89#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
90#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
91
92#define SUN6I_DSI_PIXEL_CTL1_REG 0x084
93
94#define SUN6I_DSI_PIXEL_PH_REG 0x090
95#define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
96#define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
97#define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
98#define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
99
100#define SUN6I_DSI_PIXEL_PF0_REG 0x098
101#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
102
103#define SUN6I_DSI_PIXEL_PF1_REG 0x09c
104#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
105#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
106
107#define SUN6I_DSI_SYNC_HSS_REG 0x0b0
108
109#define SUN6I_DSI_SYNC_HSE_REG 0x0b4
110
111#define SUN6I_DSI_SYNC_VSS_REG 0x0b8
112
113#define SUN6I_DSI_SYNC_VSE_REG 0x0bc
114
115#define SUN6I_DSI_BLK_HSA0_REG 0x0c0
116
117#define SUN6I_DSI_BLK_HSA1_REG 0x0c4
118#define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
119#define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
120
121#define SUN6I_DSI_BLK_HBP0_REG 0x0c8
122
123#define SUN6I_DSI_BLK_HBP1_REG 0x0cc
124
125#define SUN6I_DSI_BLK_HFP0_REG 0x0d0
126
127#define SUN6I_DSI_BLK_HFP1_REG 0x0d4
128
129#define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
130
131#define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
132
133#define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
134
135#define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
136
137#define SUN6I_DSI_BURST_LINE_REG 0x0f0
138#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
139#define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
140
141#define SUN6I_DSI_BURST_DRQ_REG 0x0f4
142#define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
143#define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
144
145#define SUN6I_DSI_CMD_CTL_REG 0x200
146#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
147#define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
148#define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
149
150#define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
151
152#define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
153
154#define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
155
156enum sun6i_dsi_start_inst {
157 DSI_START_LPRX,
158 DSI_START_LPTX,
159 DSI_START_HSC,
160 DSI_START_HSD,
161};
162
163enum sun6i_dsi_inst_id {
164 DSI_INST_ID_LP11 = 0,
165 DSI_INST_ID_TBA,
166 DSI_INST_ID_HSC,
167 DSI_INST_ID_HSD,
168 DSI_INST_ID_LPDT,
169 DSI_INST_ID_HSCEXIT,
170 DSI_INST_ID_NOP,
171 DSI_INST_ID_DLY,
172 DSI_INST_ID_END = 15,
173};
174
175enum sun6i_dsi_inst_mode {
176 DSI_INST_MODE_STOP = 0,
177 DSI_INST_MODE_TBA,
178 DSI_INST_MODE_HS,
179 DSI_INST_MODE_ESCAPE,
180 DSI_INST_MODE_HSCEXIT,
181 DSI_INST_MODE_NOP,
182};
183
184enum sun6i_dsi_inst_escape {
185 DSI_INST_ESCA_LPDT = 0,
186 DSI_INST_ESCA_ULPS,
187 DSI_INST_ESCA_UN1,
188 DSI_INST_ESCA_UN2,
189 DSI_INST_ESCA_RESET,
190 DSI_INST_ESCA_UN3,
191 DSI_INST_ESCA_UN4,
192 DSI_INST_ESCA_UN5,
193};
194
195enum sun6i_dsi_inst_packet {
196 DSI_INST_PACK_PIXEL = 0,
197 DSI_INST_PACK_COMMAND,
198};
199
200static const u32 sun6i_dsi_ecc_array[] = {
201 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
202 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
203 BIT(23)),
204 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
205 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
206 BIT(23)),
207 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
208 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
209 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
210 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
211 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
212 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
213 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
214 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
215 BIT(23)),
216};
217
218static u32 sun6i_dsi_ecc_compute(unsigned int data)
219{
220 int i;
221 u8 ecc = 0;
222
223 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
224 u32 field = sun6i_dsi_ecc_array[i];
225 bool init = false;
226 u8 val = 0;
227 int j;
228
229 for (j = 0; j < 24; j++) {
230 if (!(BIT(j) & field))
231 continue;
232
233 if (!init) {
234 val = (BIT(j) & data) ? 1 : 0;
235 init = true;
236 } else {
237 val ^= (BIT(j) & data) ? 1 : 0;
238 }
239 }
240
241 ecc |= val << i;
242 }
243
244 return ecc;
245}
246
247static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
248{
249 return crc_ccitt(0xffff, buffer, len);
250}
251
c51756d5 252static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len)
133add5b 253{
133add5b
MR		 254 memset(buffer, pd, len);
255
256 return sun6i_dsi_crc_compute(buffer, len);
257}
258
259static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
260{
261 u32 val = dt & 0x3f;
262
263 val |= (vc & 3) << 6;
264 val |= (d0 & 0xff) << 8;
265 val |= (d1 & 0xff) << 16;
266 val |= sun6i_dsi_ecc_compute(val) << 24;
267
268 return val;
269}
270
271static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
272{
273 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
274 wc & 0xff, wc >> 8);
275}
276
c51756d5 277static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len)
133add5b
MR		 278{
279 u32 val = SUN6I_DSI_BLK_PD(pd);
280
c51756d5 281 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len));
133add5b
MR		 282}
283
284static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
285{
286 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
287 SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
288}
289
290static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
291{
292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
293 SUN6I_DSI_BASIC_CTL0_INST_ST,
294 SUN6I_DSI_BASIC_CTL0_INST_ST);
295}
296
297static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
298{
299 u32 val;
300
301 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
302 val,
303 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
304 100, 5000);
305}
306
307static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
308 enum sun6i_dsi_inst_id id,
309 enum sun6i_dsi_inst_mode mode,
310 bool clock, u8 data,
311 enum sun6i_dsi_inst_packet packet,
312 enum sun6i_dsi_inst_escape escape)
313{
314 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
315 SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
316 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
317 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
318 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
319 SUN6I_DSI_INST_FUNC_LANE_DEN(data));
320}
321
322static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
323 struct mipi_dsi_device *device)
324{
325 u8 lanes_mask = GENMASK(device->lanes - 1, 0);
326
327 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
328 true, lanes_mask, 0, 0);
329
330 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
331 false, 1, 0, 0);
332
333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
334 true, 0, DSI_INST_PACK_PIXEL, 0);
335
336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
337 false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
338
339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
340 false, 1, DSI_INST_PACK_COMMAND,
341 DSI_INST_ESCA_LPDT);
342
343 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
344 true, 0, 0, 0);
345
346 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
347 false, lanes_mask, 0, 0);
348
349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
350 true, lanes_mask, 0, 0);
351
352 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
353 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
354 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
355 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
356};
357
358static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
359 struct drm_display_mode *mode)
360{
da676c6a
MR		 361 u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100);
362
363 return mode->vtotal - (mode->vsync_end - mode->vdisplay) + start;
133add5b
MR		 364}
365
366static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
367 struct drm_display_mode *mode)
368{
369 struct mipi_dsi_device *device = dsi->device;
370 u32 val = 0;
371
372 if ((mode->hsync_end - mode->hdisplay) > 20) {
373 /* Maaaaaagic */
374 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
375
376 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
377 drq /= 32;
378
379 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
380 SUN6I_DSI_TCON_DRQ_SET(drq));
381 }
382
383 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
384}
385
386static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
387 struct drm_display_mode *mode)
388{
389 u16 delay = 50 - 1;
390
391 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
392 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
393 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
394 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
395 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
396 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
397}
398
399static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
400 struct drm_display_mode *mode)
401{
402 struct mipi_dsi_device *device = dsi->device;
403 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
404 u8 dt, fmt;
405 u16 wc;
406
407 /*
408 * TODO: The format defines are only valid in video mode and
409 * change in command mode.
410 */
411 switch (device->format) {
412 case MIPI_DSI_FMT_RGB888:
413 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
414 fmt = 8;
415 break;
416 case MIPI_DSI_FMT_RGB666:
417 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
418 fmt = 9;
419 break;
420 case MIPI_DSI_FMT_RGB666_PACKED:
421 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
422 fmt = 10;
423 break;
424 case MIPI_DSI_FMT_RGB565:
425 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
426 fmt = 11;
427 break;
428 default:
429 return;
430 }
431 val |= SUN6I_DSI_PIXEL_PH_DT(dt);
432
433 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
434 val |= SUN6I_DSI_PIXEL_PH_WC(wc);
435 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
436
437 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
438
439 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
440 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
441
442 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
443 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
444 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
445
446 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
447 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
448 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
449}
450
451static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
452 struct drm_display_mode *mode)
453{
454 struct mipi_dsi_device *device = dsi->device;
455 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
456 u16 hbp, hfp, hsa, hblk, vblk;
c51756d5
KC		 457 size_t bytes;
458 u8 *buffer;
459
460 /* Do all timing calculations up front to allocate buffer space */
461
462 /*
463 * A sync period is composed of a blanking packet (4 bytes +
464 * payload + 2 bytes) and a sync event packet (4 bytes). Its
465 * minimal size is therefore 10 bytes
466 */
467#define HSA_PACKET_OVERHEAD 10
468 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
469 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
470
471 /*
472 * The backporch is set using a blanking packet (4 bytes +
473 * payload + 2 bytes). Its minimal size is therefore 6 bytes
474 */
475#define HBP_PACKET_OVERHEAD 6
476 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
477 (mode->hsync_start - mode->hdisplay) * Bpp - HBP_PACKET_OVERHEAD);
478
479 /*
480 * The frontporch is set using a blanking packet (4 bytes +
481 * payload + 2 bytes). Its minimal size is therefore 6 bytes
482 */
483#define HFP_PACKET_OVERHEAD 6
484 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
485 (mode->htotal - mode->hsync_end) * Bpp - HFP_PACKET_OVERHEAD);
486
487 /*
488 * hblk seems to be the line + porches length.
489 */
490 hblk = mode->htotal * Bpp - hsa;
491
492 /*
493 * And I'm not entirely sure what vblk is about. The driver in
494 * Allwinner BSP is using a rather convoluted calculation
495 * there only for 4 lanes. However, using 0 (the !4 lanes
496 * case) even with a 4 lanes screen seems to work...
497 */
498 vblk = 0;
499
500 /* How many bytes do we need to send all payloads? */
501 bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
502 buffer = kmalloc(bytes, GFP_KERNEL);
503 if (WARN_ON(!buffer))
504 return;
133add5b
MR		 505
506 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, 0);
507
508 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
509 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
510 device->channel,
511 0, 0));
512
513 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
514 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
515 device->channel,
516 0, 0));
517
518 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
519 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
520 device->channel,
521 0, 0));
522
523 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
524 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
525 device->channel,
526 0, 0));
527
528 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
529 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
530 mode->vsync_start) |
531 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
532 mode->vdisplay));
533
534 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
535 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
536 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
537
c51756d5 538 /* sync */
133add5b
MR		 539 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
540 sun6i_dsi_build_blk0_pkt(device->channel, hsa));
541 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
c51756d5 542 sun6i_dsi_build_blk1_pkt(0, buffer, hsa));
133add5b 543
c51756d5 544 /* backporch */
133add5b
MR		 545 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
546 sun6i_dsi_build_blk0_pkt(device->channel, hbp));
547 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
c51756d5 548 sun6i_dsi_build_blk1_pkt(0, buffer, hbp));
133add5b 549
c51756d5 550 /* frontporch */
133add5b
MR		 551 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
552 sun6i_dsi_build_blk0_pkt(device->channel, hfp));
553 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
c51756d5 554 sun6i_dsi_build_blk1_pkt(0, buffer, hfp));
133add5b 555
c51756d5 556 /* hblk */
133add5b
MR		 557 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
558 sun6i_dsi_build_blk0_pkt(device->channel, hblk));
559 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
c51756d5 560 sun6i_dsi_build_blk1_pkt(0, buffer, hblk));
133add5b 561
c51756d5 562 /* vblk */
133add5b
MR		 563 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
564 sun6i_dsi_build_blk0_pkt(device->channel, vblk));
565 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
c51756d5
KC		 566 sun6i_dsi_build_blk1_pkt(0, buffer, vblk));
567
568 kfree(buffer);
133add5b
MR		 569}
570
571static int sun6i_dsi_start(struct sun6i_dsi *dsi,
572 enum sun6i_dsi_start_inst func)
573{
574 switch (func) {
575 case DSI_START_LPTX:
576 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
577 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
578 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT));
579 break;
580 case DSI_START_LPRX:
581 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
582 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
583 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) |
584 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) |
585 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA));
586 break;
587 case DSI_START_HSC:
588 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
589 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) |
590 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC));
591 break;
592 case DSI_START_HSD:
593 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
594 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) |
595 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) |
596 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) |
597 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) |
598 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT));
599 break;
600 default:
601 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
602 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11));
603 break;
604 }
605
606 sun6i_dsi_inst_abort(dsi);
607 sun6i_dsi_inst_commit(dsi);
608
609 if (func == DSI_START_HSC)
610 regmap_write_bits(dsi->regs,
611 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
612 SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
613
614 return 0;
615}
616
617static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
618{
619 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
620 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
621 struct mipi_dsi_device *device = dsi->device;
bb3b6fcb
MR		 622 union phy_configure_opts opts = { 0 };
623 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
133add5b
MR		 624 u16 delay;
625
626 DRM_DEBUG_DRIVER("Enabling DSI output\n");
627
628 pm_runtime_get_sync(dsi->dev);
629
630 delay = sun6i_dsi_get_video_start_delay(dsi, mode);
631 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
632 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
633 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
634 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
635 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
636
637 sun6i_dsi_setup_burst(dsi, mode);
638 sun6i_dsi_setup_inst_loop(dsi, mode);
639 sun6i_dsi_setup_format(dsi, mode);
640 sun6i_dsi_setup_timings(dsi, mode);
641
bb3b6fcb
MR		 642 phy_init(dsi->dphy);
643
644 phy_mipi_dphy_get_default_config(mode->clock * 1000,
645 mipi_dsi_pixel_format_to_bpp(device->format),
646 device->lanes, cfg);
647
648 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
649 phy_configure(dsi->dphy, &opts);
650 phy_power_on(dsi->dphy);
133add5b
MR		 651
652 if (!IS_ERR(dsi->panel))
653 drm_panel_prepare(dsi->panel);
654
655 /*
656 * FIXME: This should be moved after the switch to HS mode.
657 *
658 * Unfortunately, once in HS mode, it seems like we're not
659 * able to send DCS commands anymore, which would prevent any
660 * panel to send any DCS command as part as their enable
661 * method, which is quite common.
662 *
663 * I haven't seen any artifact due to that sub-optimal
664 * ordering on the panels I've tested it with, so I guess this
665 * will do for now, until that IP is better understood.
666 */
667 if (!IS_ERR(dsi->panel))
668 drm_panel_enable(dsi->panel);
669
670 sun6i_dsi_start(dsi, DSI_START_HSC);
671
672 udelay(1000);
673
674 sun6i_dsi_start(dsi, DSI_START_HSD);
675}
676
677static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
678{
679 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
680
681 DRM_DEBUG_DRIVER("Disabling DSI output\n");
682
683 if (!IS_ERR(dsi->panel)) {
684 drm_panel_disable(dsi->panel);
685 drm_panel_unprepare(dsi->panel);
686 }
687
bb3b6fcb
MR		 688 phy_power_off(dsi->dphy);
689 phy_exit(dsi->dphy);
133add5b
MR		 690
691 pm_runtime_put(dsi->dev);
692}
693
694static int sun6i_dsi_get_modes(struct drm_connector *connector)
695{
696 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
697
698 return drm_panel_get_modes(dsi->panel);
699}
700
701static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
702 .get_modes = sun6i_dsi_get_modes,
703};
704
705static enum drm_connector_status
706sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
707{
708 return connector_status_connected;
709}
710
711static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
712 .detect = sun6i_dsi_connector_detect,
713 .fill_modes = drm_helper_probe_single_connector_modes,
714 .destroy = drm_connector_cleanup,
715 .reset = drm_atomic_helper_connector_reset,
716 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
717 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
718};
719
720static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
721 .disable = sun6i_dsi_encoder_disable,
722 .enable = sun6i_dsi_encoder_enable,
723};
724
725static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
726 .destroy = drm_encoder_cleanup,
727};
728
729static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
730 const struct mipi_dsi_msg *msg)
731{
732 u32 pkt = msg->type;
733
734 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
735 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
736 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
737 } else {
738 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
739 if (msg->tx_len > 1)
740 pkt |= (((u8 *)msg->tx_buf)[1] << 16);
741 }
742
743 pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
744
745 return pkt;
746}
747
748static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
749 const struct mipi_dsi_msg *msg)
750{
751 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
752 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
753 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
754 0xff, (4 - 1));
755
756 sun6i_dsi_start(dsi, DSI_START_LPTX);
757
758 return msg->tx_len;
759}
760
761static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
762 const struct mipi_dsi_msg *msg)
763{
764 int ret, len = 0;
765 u8 *bounce;
766 u16 crc;
767
768 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
769 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
770
771 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
772 if (!bounce)
773 return -ENOMEM;
774
775 memcpy(bounce, msg->tx_buf, msg->tx_len);
776 len += msg->tx_len;
777
778 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
779 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
780 len += sizeof(crc);
781
782 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
783 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
784 kfree(bounce);
785
786 sun6i_dsi_start(dsi, DSI_START_LPTX);
787
788 ret = sun6i_dsi_inst_wait_for_completion(dsi);
789 if (ret < 0) {
790 sun6i_dsi_inst_abort(dsi);
791 return ret;
792 }
793
794 /*
795 * TODO: There's some bits (reg 0x200, bits 8/9) that
796 * apparently can be used to check whether the data have been
797 * sent, but I couldn't get it to work reliably.
798 */
799 return msg->tx_len;
800}
801
802static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
803 const struct mipi_dsi_msg *msg)
804{
805 u32 val;
806 int ret;
807 u8 byte0;
808
809 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
810 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
811 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
812 (4 - 1));
813
814 sun6i_dsi_start(dsi, DSI_START_LPRX);
815
816 ret = sun6i_dsi_inst_wait_for_completion(dsi);
817 if (ret < 0) {
818 sun6i_dsi_inst_abort(dsi);
819 return ret;
820 }
821
822 /*
823 * TODO: There's some bits (reg 0x200, bits 24/25) that
824 * apparently can be used to check whether the data have been
825 * received, but I couldn't get it to work reliably.
826 */
827 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
828 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
829 return -EIO;
830
831 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
832 byte0 = val & 0xff;
833 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
834 return -EIO;
835
836 ((u8 *)msg->rx_buf)[0] = (val >> 8);
837
838 return 1;
839}
840
841static int sun6i_dsi_attach(struct mipi_dsi_host *host,
842 struct mipi_dsi_device *device)
843{
844 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
845
846 dsi->device = device;
847 dsi->panel = of_drm_find_panel(device->dev.of_node);
5fa8e4a2
BB		 848 if (IS_ERR(dsi->panel))
849 return PTR_ERR(dsi->panel);
133add5b
MR		 850
851 dev_info(host->dev, "Attached device %s\n", device->name);
852
853 return 0;
854}
855
856static int sun6i_dsi_detach(struct mipi_dsi_host *host,
857 struct mipi_dsi_device *device)
858{
859 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
860
861 dsi->panel = NULL;
862 dsi->device = NULL;
863
864 return 0;
865}
866
867static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
868 const struct mipi_dsi_msg *msg)
869{
870 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
871 int ret;
872
873 ret = sun6i_dsi_inst_wait_for_completion(dsi);
874 if (ret < 0)
875 sun6i_dsi_inst_abort(dsi);
876
877 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
878 SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
879 SUN6I_DSI_CMD_CTL_RX_FLAG |
880 SUN6I_DSI_CMD_CTL_TX_FLAG);
881
882 switch (msg->type) {
883 case MIPI_DSI_DCS_SHORT_WRITE:
884 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
885 ret = sun6i_dsi_dcs_write_short(dsi, msg);
886 break;
887
888 case MIPI_DSI_DCS_LONG_WRITE:
889 ret = sun6i_dsi_dcs_write_long(dsi, msg);
890 break;
891
892 case MIPI_DSI_DCS_READ:
893 if (msg->rx_len == 1) {
894 ret = sun6i_dsi_dcs_read(dsi, msg);
895 break;
896 }
897
898 default:
899 ret = -EINVAL;
900 }
901
902 return ret;
903}
904
905static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
906 .attach = sun6i_dsi_attach,
907 .detach = sun6i_dsi_detach,
908 .transfer = sun6i_dsi_transfer,
909};
910
911static const struct regmap_config sun6i_dsi_regmap_config = {
912 .reg_bits = 32,
913 .val_bits = 32,
914 .reg_stride = 4,
915 .max_register = SUN6I_DSI_CMD_TX_REG(255),
916 .name = "mipi-dsi",
917};
918
919static int sun6i_dsi_bind(struct device *dev, struct device *master,
920 void *data)
921{
922 struct drm_device *drm = data;
923 struct sun4i_drv *drv = drm->dev_private;
924 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
925 int ret;
926
927 if (!dsi->panel)
928 return -EPROBE_DEFER;
929
930 dsi->drv = drv;
931
932 drm_encoder_helper_add(&dsi->encoder,
933 &sun6i_dsi_enc_helper_funcs);
934 ret = drm_encoder_init(drm,
935 &dsi->encoder,
936 &sun6i_dsi_enc_funcs,
937 DRM_MODE_ENCODER_DSI,
938 NULL);
939 if (ret) {
940 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
941 return ret;
942 }
943 dsi->encoder.possible_crtcs = BIT(0);
944
945 drm_connector_helper_add(&dsi->connector,
946 &sun6i_dsi_connector_helper_funcs);
947 ret = drm_connector_init(drm, &dsi->connector,
948 &sun6i_dsi_connector_funcs,
949 DRM_MODE_CONNECTOR_DSI);
950 if (ret) {
951 dev_err(dsi->dev,
952 "Couldn't initialise the DSI connector\n");
953 goto err_cleanup_connector;
954 }
955
cde4c44d 956 drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
133add5b
MR		 957 drm_panel_attach(dsi->panel, &dsi->connector);
958
959 return 0;
960
961err_cleanup_connector:
962 drm_encoder_cleanup(&dsi->encoder);
963 return ret;
964}
965
966static void sun6i_dsi_unbind(struct device *dev, struct device *master,
967 void *data)
968{
969 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
970
971 drm_panel_detach(dsi->panel);
972}
973
974static const struct component_ops sun6i_dsi_ops = {
975 .bind = sun6i_dsi_bind,
976 .unbind = sun6i_dsi_unbind,
977};
978
979static int sun6i_dsi_probe(struct platform_device *pdev)
980{
981 struct device *dev = &pdev->dev;
133add5b
MR		 982 struct sun6i_dsi *dsi;
983 struct resource *res;
984 void __iomem *base;
985 int ret;
986
987 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
988 if (!dsi)
989 return -ENOMEM;
990 dev_set_drvdata(dev, dsi);
991 dsi->dev = dev;
992 dsi->host.ops = &sun6i_dsi_host_ops;
993 dsi->host.dev = dev;
994
995 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
996 base = devm_ioremap_resource(dev, res);
997 if (IS_ERR(base)) {
998 dev_err(dev, "Couldn't map the DSI encoder registers\n");
999 return PTR_ERR(base);
1000 }
1001
1002 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
1003 &sun6i_dsi_regmap_config);
1004 if (IS_ERR(dsi->regs)) {
1005 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
1006 return PTR_ERR(dsi->regs);
1007 }
1008
1009 dsi->reset = devm_reset_control_get_shared(dev, NULL);
1010 if (IS_ERR(dsi->reset)) {
1011 dev_err(dev, "Couldn't get our reset line\n");
1012 return PTR_ERR(dsi->reset);
1013 }
1014
1015 dsi->mod_clk = devm_clk_get(dev, "mod");
1016 if (IS_ERR(dsi->mod_clk)) {
1017 dev_err(dev, "Couldn't get the DSI mod clock\n");
1018 return PTR_ERR(dsi->mod_clk);
1019 }
1020
1021 /*
1022 * In order to operate properly, that clock seems to be always
1023 * set to 297MHz.
1024 */
1025 clk_set_rate_exclusive(dsi->mod_clk, 297000000);
1026
bb3b6fcb
MR		 1027 dsi->dphy = devm_phy_get(dev, "dphy");
1028 if (IS_ERR(dsi->dphy)) {
133add5b 1029 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1c7c62a3 1030 ret = PTR_ERR(dsi->dphy);
133add5b
MR		 1031 goto err_unprotect_clk;
1032 }
1033
1034 pm_runtime_enable(dev);
1035
1036 ret = mipi_dsi_host_register(&dsi->host);
1037 if (ret) {
1038 dev_err(dev, "Couldn't register MIPI-DSI host\n");
bb3b6fcb 1039 goto err_pm_disable;
133add5b
MR		 1040 }
1041
1042 ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1043 if (ret) {
1044 dev_err(dev, "Couldn't register our component\n");
1045 goto err_remove_dsi_host;
1046 }
1047
1048 return 0;
1049
1050err_remove_dsi_host:
1051 mipi_dsi_host_unregister(&dsi->host);
bb3b6fcb 1052err_pm_disable:
133add5b 1053 pm_runtime_disable(dev);
133add5b
MR		 1054err_unprotect_clk:
1055 clk_rate_exclusive_put(dsi->mod_clk);
1056 return ret;
1057}
1058
1059static int sun6i_dsi_remove(struct platform_device *pdev)
1060{
1061 struct device *dev = &pdev->dev;
1062 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1063
1064 component_del(&pdev->dev, &sun6i_dsi_ops);
1065 mipi_dsi_host_unregister(&dsi->host);
1066 pm_runtime_disable(dev);
133add5b
MR		 1067 clk_rate_exclusive_put(dsi->mod_clk);
1068
1069 return 0;
1070}
1071
6b1c5eaf 1072static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
133add5b
MR		 1073{
1074 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1075
1076 reset_control_deassert(dsi->reset);
1077 clk_prepare_enable(dsi->mod_clk);
1078
1079 /*
1080 * Enable the DSI block.
1081 *
1082 * Some part of it can only be done once we get a number of
1083 * lanes, see sun6i_dsi_inst_init
1084 */
1085 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1086
1087 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1088 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1089
1090 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1091 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1092
1093 if (dsi->device)
1094 sun6i_dsi_inst_init(dsi, dsi->device);
1095
1096 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1097
1098 return 0;
1099}
1100
6b1c5eaf 1101static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
133add5b
MR		 1102{
1103 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1104
1105 clk_disable_unprepare(dsi->mod_clk);
1106 reset_control_assert(dsi->reset);
1107
1108 return 0;
1109}
1110
1111static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1112 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1113 sun6i_dsi_runtime_resume,
1114 NULL)
1115};
1116
1117static const struct of_device_id sun6i_dsi_of_table[] = {
1118 { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1119 { }
1120};
1121MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1122
1123static struct platform_driver sun6i_dsi_platform_driver = {
1124 .probe = sun6i_dsi_probe,
1125 .remove = sun6i_dsi_remove,
1126 .driver = {
1127 .name = "sun6i-mipi-dsi",
1128 .of_match_table = sun6i_dsi_of_table,
1129 .pm = &sun6i_dsi_pm_ops,
1130 },
1131};
1132module_platform_driver(sun6i_dsi_platform_driver);
1133
1134MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1135MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1136MODULE_LICENSE("GPL");
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