[thirdparty/kernel/stable.git] / drivers / gpu / drm / tilcdc / tilcdc_drv.c

/*
 * Copyright (C) 2012 Texas Instruments
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/* LCDC DRM driver, based on da8xx-fb */

#include <linux/component.h>
#include <linux/pinctrl/consumer.h>
#include <linux/suspend.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_probe_helper.h>

#include "tilcdc_drv.h"
#include "tilcdc_regs.h"
#include "tilcdc_tfp410.h"
#include "tilcdc_panel.h"
#include "tilcdc_external.h"

static LIST_HEAD(module_list);

static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };

static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
					       DRM_FORMAT_BGR888,
					       DRM_FORMAT_XBGR8888 };

static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
					      DRM_FORMAT_RGB888,
					      DRM_FORMAT_XRGB8888 };

static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
					     DRM_FORMAT_RGB888,
					     DRM_FORMAT_XRGB8888 };

void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
		const struct tilcdc_module_ops *funcs)
{
	mod->name = name;
	mod->funcs = funcs;
	INIT_LIST_HEAD(&mod->list);
	list_add(&mod->list, &module_list);
}

void tilcdc_module_cleanup(struct tilcdc_module *mod)
{
	list_del(&mod->list);
}

static struct of_device_id tilcdc_of_match[];

static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
		struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
{
	return drm_gem_fb_create(dev, file_priv, mode_cmd);
}

static int tilcdc_atomic_check(struct drm_device *dev,
			       struct drm_atomic_state *state)
{
	int ret;

	ret = drm_atomic_helper_check_modeset(dev, state);
	if (ret)
		return ret;

	ret = drm_atomic_helper_check_planes(dev, state);
	if (ret)
		return ret;

	/*
	 * tilcdc ->atomic_check can update ->mode_changed if pixel format
	 * changes, hence will we check modeset changes again.
	 */
	ret = drm_atomic_helper_check_modeset(dev, state);
	if (ret)
		return ret;

	return ret;
}

static int tilcdc_commit(struct drm_device *dev,
		  struct drm_atomic_state *state,
		  bool async)
{
	int ret;

	ret = drm_atomic_helper_prepare_planes(dev, state);
	if (ret)
		return ret;

	ret = drm_atomic_helper_swap_state(state, true);
	if (ret) {
		drm_atomic_helper_cleanup_planes(dev, state);
		return ret;
	}

	/*
	 * Everything below can be run asynchronously without the need to grab
	 * any modeset locks at all under one condition: It must be guaranteed
	 * that the asynchronous work has either been cancelled (if the driver
	 * supports it, which at least requires that the framebuffers get
	 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
	 * before the new state gets committed on the software side with
	 * drm_atomic_helper_swap_state().
	 *
	 * This scheme allows new atomic state updates to be prepared and
	 * checked in parallel to the asynchronous completion of the previous
	 * update. Which is important since compositors need to figure out the
	 * composition of the next frame right after having submitted the
	 * current layout.
	 */

	drm_atomic_helper_commit_modeset_disables(dev, state);

	drm_atomic_helper_commit_planes(dev, state, 0);

	drm_atomic_helper_commit_modeset_enables(dev, state);

	drm_atomic_helper_wait_for_vblanks(dev, state);

	drm_atomic_helper_cleanup_planes(dev, state);

	return 0;
}

static const struct drm_mode_config_funcs mode_config_funcs = {
	.fb_create = tilcdc_fb_create,
	.atomic_check = tilcdc_atomic_check,
	.atomic_commit = tilcdc_commit,
};

static void modeset_init(struct drm_device *dev)
{
	struct tilcdc_drm_private *priv = dev->dev_private;
	struct tilcdc_module *mod;

	list_for_each_entry(mod, &module_list, list) {
		DBG("loading module: %s", mod->name);
		mod->funcs->modeset_init(mod, dev);
	}

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;
	dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
	dev->mode_config.max_height = 2048;
	dev->mode_config.funcs = &mode_config_funcs;
}

#ifdef CONFIG_CPU_FREQ
static int cpufreq_transition(struct notifier_block *nb,
				     unsigned long val, void *data)
{
	struct tilcdc_drm_private *priv = container_of(nb,
			struct tilcdc_drm_private, freq_transition);

	if (val == CPUFREQ_POSTCHANGE)
		tilcdc_crtc_update_clk(priv->crtc);

	return 0;
}
#endif

/*
 * DRM operations:
 */

static void tilcdc_fini(struct drm_device *dev)
{
	struct tilcdc_drm_private *priv = dev->dev_private;

#ifdef CONFIG_CPU_FREQ
	if (priv->freq_transition.notifier_call)
		cpufreq_unregister_notifier(&priv->freq_transition,
					    CPUFREQ_TRANSITION_NOTIFIER);
#endif

	if (priv->crtc)
		tilcdc_crtc_shutdown(priv->crtc);

	if (priv->is_registered)
		drm_dev_unregister(dev);

	drm_kms_helper_poll_fini(dev);
	drm_irq_uninstall(dev);
	drm_mode_config_cleanup(dev);
	tilcdc_remove_external_device(dev);

	if (priv->clk)
		clk_put(priv->clk);

	if (priv->mmio)
		iounmap(priv->mmio);

	if (priv->wq) {
		flush_workqueue(priv->wq);
		destroy_workqueue(priv->wq);
	}

	dev->dev_private = NULL;

	pm_runtime_disable(dev->dev);

	drm_dev_put(dev);
}

static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
{
	struct drm_device *ddev;
	struct platform_device *pdev = to_platform_device(dev);
	struct device_node *node = dev->of_node;
	struct tilcdc_drm_private *priv;
	struct resource *res;
	u32 bpp = 0;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	ddev = drm_dev_alloc(ddrv, dev);
	if (IS_ERR(ddev))
		return PTR_ERR(ddev);

	ddev->dev_private = priv;
	platform_set_drvdata(pdev, ddev);
	drm_mode_config_init(ddev);

	priv->is_componentized =
		tilcdc_get_external_components(dev, NULL) > 0;

	priv->wq = alloc_ordered_workqueue("tilcdc", 0);
	if (!priv->wq) {
		ret = -ENOMEM;
		goto init_failed;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "failed to get memory resource\n");
		ret = -EINVAL;
		goto init_failed;
	}

	priv->mmio = ioremap_nocache(res->start, resource_size(res));
	if (!priv->mmio) {
		dev_err(dev, "failed to ioremap\n");
		ret = -ENOMEM;
		goto init_failed;
	}

	priv->clk = clk_get(dev, "fck");
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "failed to get functional clock\n");
		ret = -ENODEV;
		goto init_failed;
	}

	if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
		priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;

	DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);

	if (of_property_read_u32(node, "max-width", &priv->max_width))
		priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;

	DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);

	if (of_property_read_u32(node, "max-pixelclock",
					&priv->max_pixelclock))
		priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;

	DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);

	pm_runtime_enable(dev);

	/* Determine LCD IP Version */
	pm_runtime_get_sync(dev);
	switch (tilcdc_read(ddev, LCDC_PID_REG)) {
	case 0x4c100102:
		priv->rev = 1;
		break;
	case 0x4f200800:
	case 0x4f201000:
		priv->rev = 2;
		break;
	default:
		dev_warn(dev, "Unknown PID Reg value 0x%08x, "
			"defaulting to LCD revision 1\n",
			tilcdc_read(ddev, LCDC_PID_REG));
		priv->rev = 1;
		break;
	}

	pm_runtime_put_sync(dev);

	if (priv->rev == 1) {
		DBG("Revision 1 LCDC supports only RGB565 format");
		priv->pixelformats = tilcdc_rev1_formats;
		priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
		bpp = 16;
	} else {
		const char *str = "\0";

		of_property_read_string(node, "blue-and-red-wiring", &str);
		if (0 == strcmp(str, "crossed")) {
			DBG("Configured for crossed blue and red wires");
			priv->pixelformats = tilcdc_crossed_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_crossed_formats);
			bpp = 32; /* Choose bpp with RGB support for fbdef */
		} else if (0 == strcmp(str, "straight")) {
			DBG("Configured for straight blue and red wires");
			priv->pixelformats = tilcdc_straight_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_straight_formats);
			bpp = 16; /* Choose bpp with RGB support for fbdef */
		} else {
			DBG("Blue and red wiring '%s' unknown, use legacy mode",
			    str);
			priv->pixelformats = tilcdc_legacy_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_legacy_formats);
			bpp = 16; /* This is just a guess */
		}
	}

	ret = tilcdc_crtc_create(ddev);
	if (ret < 0) {
		dev_err(dev, "failed to create crtc\n");
		goto init_failed;
	}
	modeset_init(ddev);

#ifdef CONFIG_CPU_FREQ
	priv->freq_transition.notifier_call = cpufreq_transition;
	ret = cpufreq_register_notifier(&priv->freq_transition,
			CPUFREQ_TRANSITION_NOTIFIER);
	if (ret) {
		dev_err(dev, "failed to register cpufreq notifier\n");
		priv->freq_transition.notifier_call = NULL;
		goto init_failed;
	}
#endif

	if (priv->is_componentized) {
		ret = component_bind_all(dev, ddev);
		if (ret < 0)
			goto init_failed;

		ret = tilcdc_add_component_encoder(ddev);
		if (ret < 0)
			goto init_failed;
	} else {
		ret = tilcdc_attach_external_device(ddev);
		if (ret)
			goto init_failed;
	}

	if (!priv->external_connector &&
	    ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
		dev_err(dev, "no encoders/connectors found\n");
		ret = -EPROBE_DEFER;
		goto init_failed;
	}

	ret = drm_vblank_init(ddev, 1);
	if (ret < 0) {
		dev_err(dev, "failed to initialize vblank\n");
		goto init_failed;
	}

	ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
	if (ret < 0) {
		dev_err(dev, "failed to install IRQ handler\n");
		goto init_failed;
	}

	drm_mode_config_reset(ddev);

	drm_kms_helper_poll_init(ddev);

	ret = drm_dev_register(ddev, 0);
	if (ret)
		goto init_failed;

	drm_fbdev_generic_setup(ddev, bpp);

	priv->is_registered = true;
	return 0;

init_failed:
	tilcdc_fini(ddev);

	return ret;
}

static irqreturn_t tilcdc_irq(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct tilcdc_drm_private *priv = dev->dev_private;
	return tilcdc_crtc_irq(priv->crtc);
}

#if defined(CONFIG_DEBUG_FS)
static const struct {
	const char *name;
	uint8_t  rev;
	uint8_t  save;
	uint32_t reg;
} registers[] =		{
#define REG(rev, save, reg) { #reg, rev, save, reg }
		/* exists in revision 1: */
		REG(1, false, LCDC_PID_REG),
		REG(1, true,  LCDC_CTRL_REG),
		REG(1, false, LCDC_STAT_REG),
		REG(1, true,  LCDC_RASTER_CTRL_REG),
		REG(1, true,  LCDC_RASTER_TIMING_0_REG),
		REG(1, true,  LCDC_RASTER_TIMING_1_REG),
		REG(1, true,  LCDC_RASTER_TIMING_2_REG),
		REG(1, true,  LCDC_DMA_CTRL_REG),
		REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
		REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
		REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
		REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
		/* new in revision 2: */
		REG(2, false, LCDC_RAW_STAT_REG),
		REG(2, false, LCDC_MASKED_STAT_REG),
		REG(2, true, LCDC_INT_ENABLE_SET_REG),
		REG(2, false, LCDC_INT_ENABLE_CLR_REG),
		REG(2, false, LCDC_END_OF_INT_IND_REG),
		REG(2, true,  LCDC_CLK_ENABLE_REG),
#undef REG
};

#endif

#ifdef CONFIG_DEBUG_FS
static int tilcdc_regs_show(struct seq_file *m, void *arg)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct tilcdc_drm_private *priv = dev->dev_private;
	unsigned i;

	pm_runtime_get_sync(dev->dev);

	seq_printf(m, "revision: %d\n", priv->rev);

	for (i = 0; i < ARRAY_SIZE(registers); i++)
		if (priv->rev >= registers[i].rev)
			seq_printf(m, "%s:\t %08x\n", registers[i].name,
					tilcdc_read(dev, registers[i].reg));

	pm_runtime_put_sync(dev->dev);

	return 0;
}

static int tilcdc_mm_show(struct seq_file *m, void *arg)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_printer p = drm_seq_file_printer(m);
	drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
	return 0;
}

static struct drm_info_list tilcdc_debugfs_list[] = {
		{ "regs", tilcdc_regs_show, 0 },
		{ "mm",   tilcdc_mm_show,   0 },
};

static int tilcdc_debugfs_init(struct drm_minor *minor)
{
	struct drm_device *dev = minor->dev;
	struct tilcdc_module *mod;
	int ret;

	ret = drm_debugfs_create_files(tilcdc_debugfs_list,
			ARRAY_SIZE(tilcdc_debugfs_list),
			minor->debugfs_root, minor);

	list_for_each_entry(mod, &module_list, list)
		if (mod->funcs->debugfs_init)
			mod->funcs->debugfs_init(mod, minor);

	if (ret) {
		dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
		return ret;
	}

	return ret;
}
#endif

DEFINE_DRM_GEM_CMA_FOPS(fops);

static struct drm_driver tilcdc_driver = {
	.driver_features    = (DRIVER_GEM | DRIVER_MODESET |
			       DRIVER_PRIME | DRIVER_ATOMIC),
	.irq_handler        = tilcdc_irq,
	.gem_free_object_unlocked = drm_gem_cma_free_object,
	.gem_print_info     = drm_gem_cma_print_info,
	.gem_vm_ops         = &drm_gem_cma_vm_ops,
	.dumb_create        = drm_gem_cma_dumb_create,

	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
	.gem_prime_import	= drm_gem_prime_import,
	.gem_prime_export	= drm_gem_prime_export,
	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
#ifdef CONFIG_DEBUG_FS
	.debugfs_init       = tilcdc_debugfs_init,
#endif
	.fops               = &fops,
	.name               = "tilcdc",
	.desc               = "TI LCD Controller DRM",
	.date               = "20121205",
	.major              = 1,
	.minor              = 0,
};

/*
 * Power management:
 */

#ifdef CONFIG_PM_SLEEP
static int tilcdc_pm_suspend(struct device *dev)
{
	struct drm_device *ddev = dev_get_drvdata(dev);
	int ret = 0;

	ret = drm_mode_config_helper_suspend(ddev);

	/* Select sleep pin state */
	pinctrl_pm_select_sleep_state(dev);

	return ret;
}

static int tilcdc_pm_resume(struct device *dev)
{
	struct drm_device *ddev = dev_get_drvdata(dev);

	/* Select default pin state */
	pinctrl_pm_select_default_state(dev);
	return  drm_mode_config_helper_resume(ddev);
}
#endif

static const struct dev_pm_ops tilcdc_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
};

/*
 * Platform driver:
 */
static int tilcdc_bind(struct device *dev)
{
	return tilcdc_init(&tilcdc_driver, dev);
}

static void tilcdc_unbind(struct device *dev)
{
	struct drm_device *ddev = dev_get_drvdata(dev);

	/* Check if a subcomponent has already triggered the unloading. */
	if (!ddev->dev_private)
		return;

	tilcdc_fini(dev_get_drvdata(dev));
}

static const struct component_master_ops tilcdc_comp_ops = {
	.bind = tilcdc_bind,
	.unbind = tilcdc_unbind,
};

static int tilcdc_pdev_probe(struct platform_device *pdev)
{
	struct component_match *match = NULL;
	int ret;

	/* bail out early if no DT data: */
	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "device-tree data is missing\n");
		return -ENXIO;
	}

	ret = tilcdc_get_external_components(&pdev->dev, &match);
	if (ret < 0)
		return ret;
	else if (ret == 0)
		return tilcdc_init(&tilcdc_driver, &pdev->dev);
	else
		return component_master_add_with_match(&pdev->dev,
						       &tilcdc_comp_ops,
						       match);
}

static int tilcdc_pdev_remove(struct platform_device *pdev)
{
	int ret;

	ret = tilcdc_get_external_components(&pdev->dev, NULL);
	if (ret < 0)
		return ret;
	else if (ret == 0)
		tilcdc_fini(platform_get_drvdata(pdev));
	else
		component_master_del(&pdev->dev, &tilcdc_comp_ops);

	return 0;
}

static struct of_device_id tilcdc_of_match[] = {
		{ .compatible = "ti,am33xx-tilcdc", },
		{ .compatible = "ti,da850-tilcdc", },
		{ },
};
MODULE_DEVICE_TABLE(of, tilcdc_of_match);

static struct platform_driver tilcdc_platform_driver = {
	.probe      = tilcdc_pdev_probe,
	.remove     = tilcdc_pdev_remove,
	.driver     = {
		.name   = "tilcdc",
		.pm     = &tilcdc_pm_ops,
		.of_match_table = tilcdc_of_match,
	},
};

static int __init tilcdc_drm_init(void)
{
	DBG("init");
	tilcdc_tfp410_init();
	tilcdc_panel_init();
	return platform_driver_register(&tilcdc_platform_driver);
}

static void __exit tilcdc_drm_fini(void)
{
	DBG("fini");
	platform_driver_unregister(&tilcdc_platform_driver);
	tilcdc_panel_fini();
	tilcdc_tfp410_fini();
}

module_init(tilcdc_drm_init);
module_exit(tilcdc_drm_fini);

MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
16ea975e RC	1	/*
	2	* Copyright (C) 2012 Texas Instruments
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	/* LCDC DRM driver, based on da8xx-fb */
	19
103cd8bc	20	#include <linux/component.h>
416a07fb DG	21	#include <linux/pinctrl/consumer.h>
416a07fb DG	22	#include <linux/suspend.h>
edc43303 JS	23	#include <drm/drm_atomic.h>
edc43303 JS	24	#include <drm/drm_atomic_helper.h>
bb2af9bd	25	#include <drm/drm_fb_helper.h>
6025a157	26	#include <drm/drm_gem_framebuffer_helper.h>
fcd70cd3	27	#include <drm/drm_probe_helper.h>
103cd8bc	28
16ea975e RC	29	#include "tilcdc_drv.h"
	30	#include "tilcdc_regs.h"
	31	#include "tilcdc_tfp410.h"
0d4bbaf9	32	#include "tilcdc_panel.h"
103cd8bc	33	#include "tilcdc_external.h"
16ea975e	34
16ea975e RC	35	static LIST_HEAD(module_list);
16ea975e RC	36
bcc5a6f5 JS	37	static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
	38
	39	static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
	40	DRM_FORMAT_BGR888,
	41	DRM_FORMAT_XBGR8888 };
	42
	43	static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
	44	DRM_FORMAT_RGB888,
	45	DRM_FORMAT_XRGB8888 };
	46
	47	static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
	48	DRM_FORMAT_RGB888,
	49	DRM_FORMAT_XRGB8888 };
	50
16ea975e RC	51	void tilcdc_module_init(struct tilcdc_module mod, const char name,
	52	const struct tilcdc_module_ops *funcs)
	53	{
	54	mod->name = name;
	55	mod->funcs = funcs;
	56	INIT_LIST_HEAD(&mod->list);
	57	list_add(&mod->list, &module_list);
	58	}
	59
	60	void tilcdc_module_cleanup(struct tilcdc_module *mod)
	61	{
	62	list_del(&mod->list);
	63	}
	64
	65	static struct of_device_id tilcdc_of_match[];
	66
	67	static struct drm_framebuffer tilcdc_fb_create(struct drm_device dev,
1eb83451	68	struct drm_file file_priv, const struct drm_mode_fb_cmd2 mode_cmd)
16ea975e	69	{
6025a157	70	return drm_gem_fb_create(dev, file_priv, mode_cmd);
16ea975e RC	71	}
16ea975e RC	72
30457676 WY	73	static int tilcdc_atomic_check(struct drm_device *dev,
30457676 WY	74	struct drm_atomic_state *state)
edc43303 JS	75	{
	76	int ret;
	77
	78	ret = drm_atomic_helper_check_modeset(dev, state);
	79	if (ret)
	80	return ret;
	81
	82	ret = drm_atomic_helper_check_planes(dev, state);
	83	if (ret)
	84	return ret;
	85
	86	/*
	87	* tilcdc ->atomic_check can update ->mode_changed if pixel format
	88	* changes, hence will we check modeset changes again.
	89	*/
	90	ret = drm_atomic_helper_check_modeset(dev, state);
	91	if (ret)
	92	return ret;
	93
	94	return ret;
	95	}
	96
	97	static int tilcdc_commit(struct drm_device *dev,
	98	struct drm_atomic_state *state,
	99	bool async)
	100	{
	101	int ret;
	102
	103	ret = drm_atomic_helper_prepare_planes(dev, state);
	104	if (ret)
	105	return ret;
	106
fad9e43a ML	107	ret = drm_atomic_helper_swap_state(state, true);
	108	if (ret) {
	109	drm_atomic_helper_cleanup_planes(dev, state);
	110	return ret;
	111	}
edc43303 JS	112
	113	/*
	114	* Everything below can be run asynchronously without the need to grab
	115	* any modeset locks at all under one condition: It must be guaranteed
	116	* that the asynchronous work has either been cancelled (if the driver
	117	* supports it, which at least requires that the framebuffers get
	118	* cleaned up with drm_atomic_helper_cleanup_planes()) or completed
	119	* before the new state gets committed on the software side with
	120	* drm_atomic_helper_swap_state().
	121	*
	122	* This scheme allows new atomic state updates to be prepared and
	123	* checked in parallel to the asynchronous completion of the previous
	124	* update. Which is important since compositors need to figure out the
	125	* composition of the next frame right after having submitted the
	126	* current layout.
	127	*/
	128
	129	drm_atomic_helper_commit_modeset_disables(dev, state);
	130
2b58e98d	131	drm_atomic_helper_commit_planes(dev, state, 0);
edc43303 JS	132
	133	drm_atomic_helper_commit_modeset_enables(dev, state);
	134
	135	drm_atomic_helper_wait_for_vblanks(dev, state);
	136
	137	drm_atomic_helper_cleanup_planes(dev, state);
	138
edc43303 JS	139	return 0;
	140	}
	141
16ea975e RC	142	static const struct drm_mode_config_funcs mode_config_funcs = {
16ea975e RC	143	.fb_create = tilcdc_fb_create,
edc43303 JS	144	.atomic_check = tilcdc_atomic_check,
edc43303 JS	145	.atomic_commit = tilcdc_commit,
16ea975e RC	146	};
16ea975e RC	147
9963d36d	148	static void modeset_init(struct drm_device *dev)
16ea975e RC	149	{
	150	struct tilcdc_drm_private *priv = dev->dev_private;
	151	struct tilcdc_module *mod;
	152
16ea975e RC	153	list_for_each_entry(mod, &module_list, list) {
	154	DBG("loading module: %s", mod->name);
	155	mod->funcs->modeset_init(mod, dev);
	156	}
	157
16ea975e RC	158	dev->mode_config.min_width = 0;
	159	dev->mode_config.min_height = 0;
	160	dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
	161	dev->mode_config.max_height = 2048;
	162	dev->mode_config.funcs = &mode_config_funcs;
16ea975e RC	163	}
	164
	165	#ifdef CONFIG_CPU_FREQ
	166	static int cpufreq_transition(struct notifier_block *nb,
	167	unsigned long val, void *data)
	168	{
	169	struct tilcdc_drm_private *priv = container_of(nb,
	170	struct tilcdc_drm_private, freq_transition);
a6b7ebaa	171
642e5167 JS	172	if (val == CPUFREQ_POSTCHANGE)
642e5167 JS	173	tilcdc_crtc_update_clk(priv->crtc);
16ea975e RC	174
	175	return 0;
	176	}
	177	#endif
	178
	179	/*
	180	* DRM operations:
	181	*/
	182
923310ba	183	static void tilcdc_fini(struct drm_device *dev)
16ea975e RC	184	{
16ea975e RC	185	struct tilcdc_drm_private *priv = dev->dev_private;
16ea975e	186
432973fd JS	187	#ifdef CONFIG_CPU_FREQ
	188	if (priv->freq_transition.notifier_call)
	189	cpufreq_unregister_notifier(&priv->freq_transition,
	190	CPUFREQ_TRANSITION_NOTIFIER);
	191	#endif
	192
9e79e062	193	if (priv->crtc)
2d53a180	194	tilcdc_crtc_shutdown(priv->crtc);
923310ba	195
9e79e062 JS	196	if (priv->is_registered)
9e79e062 JS	197	drm_dev_unregister(dev);
103cd8bc	198
16ea975e	199	drm_kms_helper_poll_fini(dev);
923310ba	200	drm_irq_uninstall(dev);
16ea975e	201	drm_mode_config_cleanup(dev);
ec9eab09	202	tilcdc_remove_external_device(dev);
16ea975e	203
16ea975e RC	204	if (priv->clk)
	205	clk_put(priv->clk);
	206
	207	if (priv->mmio)
	208	iounmap(priv->mmio);
	209
9e79e062 JS	210	if (priv->wq) {
	211	flush_workqueue(priv->wq);
	212	destroy_workqueue(priv->wq);
	213	}
16ea975e RC	214
	215	dev->dev_private = NULL;
	216
	217	pm_runtime_disable(dev->dev);
	218
ce7b700d	219	drm_dev_put(dev);
16ea975e RC	220	}
16ea975e RC	221
923310ba	222	static int tilcdc_init(struct drm_driver ddrv, struct device dev)
16ea975e	223	{
923310ba JS	224	struct drm_device *ddev;
	225	struct platform_device *pdev = to_platform_device(dev);
	226	struct device_node *node = dev->of_node;
16ea975e RC	227	struct tilcdc_drm_private *priv;
16ea975e RC	228	struct resource *res;
dc28aa07	229	u32 bpp = 0;
16ea975e RC	230	int ret;
16ea975e RC	231
923310ba	232	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3366ba38	233	if (!priv)
16ea975e	234	return -ENOMEM;
16ea975e	235
923310ba JS	236	ddev = drm_dev_alloc(ddrv, dev);
	237	if (IS_ERR(ddev))
	238	return PTR_ERR(ddev);
	239
923310ba	240	ddev->dev_private = priv;
9e79e062 JS	241	platform_set_drvdata(pdev, ddev);
9e79e062 JS	242	drm_mode_config_init(ddev);
16ea975e	243
103cd8bc	244	priv->is_componentized =
923310ba	245	tilcdc_get_external_components(dev, NULL) > 0;
103cd8bc	246
16ea975e	247	priv->wq = alloc_ordered_workqueue("tilcdc", 0);
b478e336 EG	248	if (!priv->wq) {
b478e336 EG	249	ret = -ENOMEM;
9e79e062	250	goto init_failed;
b478e336	251	}
16ea975e RC	252
	253	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	254	if (!res) {
923310ba	255	dev_err(dev, "failed to get memory resource\n");
16ea975e	256	ret = -EINVAL;
9e79e062	257	goto init_failed;
16ea975e RC	258	}
	259
	260	priv->mmio = ioremap_nocache(res->start, resource_size(res));
	261	if (!priv->mmio) {
923310ba	262	dev_err(dev, "failed to ioremap\n");
16ea975e	263	ret = -ENOMEM;
9e79e062	264	goto init_failed;
16ea975e RC	265	}
16ea975e RC	266
923310ba	267	priv->clk = clk_get(dev, "fck");
16ea975e	268	if (IS_ERR(priv->clk)) {
923310ba	269	dev_err(dev, "failed to get functional clock\n");
16ea975e	270	ret = -ENODEV;
9e79e062	271	goto init_failed;
16ea975e RC	272	}
16ea975e RC	273
16ea975e	274	if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
4e564346 DE	275	priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
	276
	277	DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
	278
0186fcce	279	if (of_property_read_u32(node, "max-width", &priv->max_width))
4e564346 DE	280	priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
	281
	282	DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
	283
0186fcce	284	if (of_property_read_u32(node, "max-pixelclock",
4e564346 DE	285	&priv->max_pixelclock))
	286	priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
	287
	288	DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
16ea975e	289
923310ba	290	pm_runtime_enable(dev);
16ea975e RC	291
16ea975e RC	292	/* Determine LCD IP Version */
923310ba JS	293	pm_runtime_get_sync(dev);
923310ba JS	294	switch (tilcdc_read(ddev, LCDC_PID_REG)) {
16ea975e RC	295	case 0x4c100102:
	296	priv->rev = 1;
	297	break;
	298	case 0x4f200800:
	299	case 0x4f201000:
	300	priv->rev = 2;
	301	break;
	302	default:
923310ba JS	303	dev_warn(dev, "Unknown PID Reg value 0x%08x, "
	304	"defaulting to LCD revision 1\n",
	305	tilcdc_read(ddev, LCDC_PID_REG));
16ea975e RC	306	priv->rev = 1;
	307	break;
	308	}
	309
923310ba	310	pm_runtime_put_sync(dev);
16ea975e	311
bcc5a6f5 JS	312	if (priv->rev == 1) {
	313	DBG("Revision 1 LCDC supports only RGB565 format");
	314	priv->pixelformats = tilcdc_rev1_formats;
	315	priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
c5665385	316	bpp = 16;
bcc5a6f5 JS	317	} else {
	318	const char *str = "\0";
	319
	320	of_property_read_string(node, "blue-and-red-wiring", &str);
	321	if (0 == strcmp(str, "crossed")) {
	322	DBG("Configured for crossed blue and red wires");
	323	priv->pixelformats = tilcdc_crossed_formats;
	324	priv->num_pixelformats =
	325	ARRAY_SIZE(tilcdc_crossed_formats);
c5665385	326	bpp = 32; /* Choose bpp with RGB support for fbdef */
bcc5a6f5 JS	327	} else if (0 == strcmp(str, "straight")) {
	328	DBG("Configured for straight blue and red wires");
	329	priv->pixelformats = tilcdc_straight_formats;
	330	priv->num_pixelformats =
	331	ARRAY_SIZE(tilcdc_straight_formats);
c5665385	332	bpp = 16; /* Choose bpp with RGB support for fbdef */
bcc5a6f5 JS	333	} else {
	334	DBG("Blue and red wiring '%s' unknown, use legacy mode",
	335	str);
	336	priv->pixelformats = tilcdc_legacy_formats;
	337	priv->num_pixelformats =
	338	ARRAY_SIZE(tilcdc_legacy_formats);
c5665385	339	bpp = 16; /* This is just a guess */
bcc5a6f5 JS	340	}
	341	}
	342
9963d36d	343	ret = tilcdc_crtc_create(ddev);
16ea975e	344	if (ret < 0) {
9963d36d	345	dev_err(dev, "failed to create crtc\n");
9e79e062	346	goto init_failed;
16ea975e	347	}
9963d36d	348	modeset_init(ddev);
16ea975e	349
432973fd JS	350	#ifdef CONFIG_CPU_FREQ
	351	priv->freq_transition.notifier_call = cpufreq_transition;
	352	ret = cpufreq_register_notifier(&priv->freq_transition,
	353	CPUFREQ_TRANSITION_NOTIFIER);
	354	if (ret) {
	355	dev_err(dev, "failed to register cpufreq notifier\n");
	356	priv->freq_transition.notifier_call = NULL;
	357	goto init_failed;
	358	}
	359	#endif
	360
103cd8bc	361	if (priv->is_componentized) {
923310ba	362	ret = component_bind_all(dev, ddev);
103cd8bc	363	if (ret < 0)
9e79e062	364	goto init_failed;
103cd8bc	365
ec9eab09	366	ret = tilcdc_add_component_encoder(ddev);
103cd8bc	367	if (ret < 0)
9e79e062	368	goto init_failed;
ec9eab09 JS	369	} else {
	370	ret = tilcdc_attach_external_device(ddev);
	371	if (ret)
	372	goto init_failed;
103cd8bc JS	373	}
103cd8bc JS	374
ec9eab09 JS	375	if (!priv->external_connector &&
ec9eab09 JS	376	((priv->num_encoders == 0) \|\| (priv->num_connectors == 0))) {
923310ba	377	dev_err(dev, "no encoders/connectors found\n");
a132b5a5	378	ret = -EPROBE_DEFER;
9e79e062	379	goto init_failed;
103cd8bc JS	380	}
103cd8bc JS	381
923310ba	382	ret = drm_vblank_init(ddev, 1);
16ea975e	383	if (ret < 0) {
923310ba	384	dev_err(dev, "failed to initialize vblank\n");
9e79e062	385	goto init_failed;
16ea975e RC	386	}
16ea975e RC	387
923310ba	388	ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
16ea975e	389	if (ret < 0) {
923310ba	390	dev_err(dev, "failed to install IRQ handler\n");
9e79e062	391	goto init_failed;
16ea975e RC	392	}
16ea975e RC	393
923310ba	394	drm_mode_config_reset(ddev);
522a76f8	395
923310ba JS	396	drm_kms_helper_poll_init(ddev);
	397
	398	ret = drm_dev_register(ddev, 0);
	399	if (ret)
9e79e062	400	goto init_failed;
16ea975e	401
45cf8756 NT	402	drm_fbdev_generic_setup(ddev, bpp);
45cf8756 NT	403
9e79e062	404	priv->is_registered = true;
16ea975e RC	405	return 0;
16ea975e RC	406
9e79e062 JS	407	init_failed:
9e79e062 JS	408	tilcdc_fini(ddev);
d0ec32ca	409
16ea975e RC	410	return ret;
	411	}
	412
e9f0d76f	413	static irqreturn_t tilcdc_irq(int irq, void *arg)
16ea975e RC	414	{
	415	struct drm_device *dev = arg;
	416	struct tilcdc_drm_private *priv = dev->dev_private;
	417	return tilcdc_crtc_irq(priv->crtc);
	418	}
	419
514d1a1f	420	#if defined(CONFIG_DEBUG_FS)
16ea975e RC	421	static const struct {
	422	const char *name;
	423	uint8_t rev;
	424	uint8_t save;
	425	uint32_t reg;
32501459	426	} registers[] = {
16ea975e RC	427	#define REG(rev, save, reg) { #reg, rev, save, reg }
	428	/* exists in revision 1: */
	429	REG(1, false, LCDC_PID_REG),
	430	REG(1, true, LCDC_CTRL_REG),
	431	REG(1, false, LCDC_STAT_REG),
	432	REG(1, true, LCDC_RASTER_CTRL_REG),
	433	REG(1, true, LCDC_RASTER_TIMING_0_REG),
	434	REG(1, true, LCDC_RASTER_TIMING_1_REG),
	435	REG(1, true, LCDC_RASTER_TIMING_2_REG),
	436	REG(1, true, LCDC_DMA_CTRL_REG),
	437	REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
	438	REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
	439	REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
	440	REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
	441	/* new in revision 2: */
	442	REG(2, false, LCDC_RAW_STAT_REG),
	443	REG(2, false, LCDC_MASKED_STAT_REG),
f3a99946	444	REG(2, true, LCDC_INT_ENABLE_SET_REG),
16ea975e RC	445	REG(2, false, LCDC_INT_ENABLE_CLR_REG),
	446	REG(2, false, LCDC_END_OF_INT_IND_REG),
	447	REG(2, true, LCDC_CLK_ENABLE_REG),
16ea975e RC	448	#undef REG
16ea975e RC	449	};
29ddd6e1	450
16ea975e RC	451	#endif
	452
	453	#ifdef CONFIG_DEBUG_FS
	454	static int tilcdc_regs_show(struct seq_file m, void arg)
	455	{
	456	struct drm_info_node node = (struct drm_info_node ) m->private;
	457	struct drm_device *dev = node->minor->dev;
	458	struct tilcdc_drm_private *priv = dev->dev_private;
	459	unsigned i;
	460
	461	pm_runtime_get_sync(dev->dev);
	462
	463	seq_printf(m, "revision: %d\n", priv->rev);
	464
	465	for (i = 0; i < ARRAY_SIZE(registers); i++)
	466	if (priv->rev >= registers[i].rev)
	467	seq_printf(m, "%s:\t %08x\n", registers[i].name,
	468	tilcdc_read(dev, registers[i].reg));
	469
	470	pm_runtime_put_sync(dev->dev);
	471
	472	return 0;
	473	}
	474
	475	static int tilcdc_mm_show(struct seq_file m, void arg)
	476	{
	477	struct drm_info_node node = (struct drm_info_node ) m->private;
	478	struct drm_device *dev = node->minor->dev;
b5c3714f SV	479	struct drm_printer p = drm_seq_file_printer(m);
	480	drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
	481	return 0;
16ea975e RC	482	}
	483
	484	static struct drm_info_list tilcdc_debugfs_list[] = {
	485	{ "regs", tilcdc_regs_show, 0 },
	486	{ "mm", tilcdc_mm_show, 0 },
16ea975e RC	487	};
	488
	489	static int tilcdc_debugfs_init(struct drm_minor *minor)
	490	{
	491	struct drm_device *dev = minor->dev;
	492	struct tilcdc_module *mod;
	493	int ret;
	494
	495	ret = drm_debugfs_create_files(tilcdc_debugfs_list,
	496	ARRAY_SIZE(tilcdc_debugfs_list),
	497	minor->debugfs_root, minor);
	498
	499	list_for_each_entry(mod, &module_list, list)
	500	if (mod->funcs->debugfs_init)
	501	mod->funcs->debugfs_init(mod, minor);
	502
	503	if (ret) {
	504	dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
	505	return ret;
	506	}
	507
	508	return ret;
	509	}
16ea975e RC	510	#endif
16ea975e RC	511
d55f7e5d	512	DEFINE_DRM_GEM_CMA_FOPS(fops);
16ea975e RC	513
16ea975e RC	514	static struct drm_driver tilcdc_driver = {
5b38e747	515	.driver_features = (DRIVER_GEM \| DRIVER_MODESET \|
305198de	516	DRIVER_PRIME \| DRIVER_ATOMIC),
16ea975e	517	.irq_handler = tilcdc_irq,
aa0438ce	518	.gem_free_object_unlocked = drm_gem_cma_free_object,
fbf65b7e	519	.gem_print_info = drm_gem_cma_print_info,
16ea975e RC	520	.gem_vm_ops = &drm_gem_cma_vm_ops,
16ea975e RC	521	.dumb_create = drm_gem_cma_dumb_create,
9c153905 JS	522
	523	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	524	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	525	.gem_prime_import = drm_gem_prime_import,
	526	.gem_prime_export = drm_gem_prime_export,
	527	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
	528	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	529	.gem_prime_vmap = drm_gem_cma_prime_vmap,
	530	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
	531	.gem_prime_mmap = drm_gem_cma_prime_mmap,
16ea975e RC	532	#ifdef CONFIG_DEBUG_FS
16ea975e RC	533	.debugfs_init = tilcdc_debugfs_init,
16ea975e RC	534	#endif
	535	.fops = &fops,
	536	.name = "tilcdc",
	537	.desc = "TI LCD Controller DRM",
	538	.date = "20121205",
	539	.major = 1,
	540	.minor = 0,
	541	};
	542
	543	/*
	544	* Power management:
	545	*/
	546
	547	#ifdef CONFIG_PM_SLEEP
	548	static int tilcdc_pm_suspend(struct device *dev)
	549	{
	550	struct drm_device *ddev = dev_get_drvdata(dev);
4fdce78a	551	int ret = 0;
16ea975e	552
4fdce78a	553	ret = drm_mode_config_helper_suspend(ddev);
16ea975e	554
85fd27f8 DE	555	/* Select sleep pin state */
	556	pinctrl_pm_select_sleep_state(dev);
	557
4fdce78a	558	return ret;
16ea975e RC	559	}
	560
	561	static int tilcdc_pm_resume(struct device *dev)
	562	{
	563	struct drm_device *ddev = dev_get_drvdata(dev);
16ea975e	564
416a07fb DG	565	/* Select default pin state */
416a07fb DG	566	pinctrl_pm_select_default_state(dev);
4fdce78a	567	return drm_mode_config_helper_resume(ddev);
16ea975e RC	568	}
	569	#endif
	570
	571	static const struct dev_pm_ops tilcdc_pm_ops = {
	572	SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
	573	};
	574
	575	/*
	576	* Platform driver:
	577	*/
103cd8bc JS	578	static int tilcdc_bind(struct device *dev)
103cd8bc JS	579	{
923310ba	580	return tilcdc_init(&tilcdc_driver, dev);
103cd8bc JS	581	}
	582
	583	static void tilcdc_unbind(struct device *dev)
	584	{
20a98acb JS	585	struct drm_device *ddev = dev_get_drvdata(dev);
	586
	587	/* Check if a subcomponent has already triggered the unloading. */
	588	if (!ddev->dev_private)
	589	return;
	590
923310ba	591	tilcdc_fini(dev_get_drvdata(dev));
103cd8bc JS	592	}
	593
	594	static const struct component_master_ops tilcdc_comp_ops = {
	595	.bind = tilcdc_bind,
	596	.unbind = tilcdc_unbind,
	597	};
	598
16ea975e RC	599	static int tilcdc_pdev_probe(struct platform_device *pdev)
16ea975e RC	600	{
103cd8bc JS	601	struct component_match *match = NULL;
	602	int ret;
	603
16ea975e RC	604	/* bail out early if no DT data: */
	605	if (!pdev->dev.of_node) {
	606	dev_err(&pdev->dev, "device-tree data is missing\n");
	607	return -ENXIO;
	608	}
	609
103cd8bc JS	610	ret = tilcdc_get_external_components(&pdev->dev, &match);
	611	if (ret < 0)
	612	return ret;
	613	else if (ret == 0)
923310ba	614	return tilcdc_init(&tilcdc_driver, &pdev->dev);
103cd8bc JS	615	else
	616	return component_master_add_with_match(&pdev->dev,
	617	&tilcdc_comp_ops,
	618	match);
16ea975e RC	619	}
	620
	621	static int tilcdc_pdev_remove(struct platform_device *pdev)
	622	{
20a98acb	623	int ret;
103cd8bc	624
20a98acb JS	625	ret = tilcdc_get_external_components(&pdev->dev, NULL);
	626	if (ret < 0)
	627	return ret;
	628	else if (ret == 0)
923310ba	629	tilcdc_fini(platform_get_drvdata(pdev));
20a98acb JS	630	else
20a98acb JS	631	component_master_del(&pdev->dev, &tilcdc_comp_ops);
16ea975e RC	632
	633	return 0;
	634	}
	635
	636	static struct of_device_id tilcdc_of_match[] = {
	637	{ .compatible = "ti,am33xx-tilcdc", },
507b72b2	638	{ .compatible = "ti,da850-tilcdc", },
16ea975e RC	639	{ },
	640	};
	641	MODULE_DEVICE_TABLE(of, tilcdc_of_match);
	642
	643	static struct platform_driver tilcdc_platform_driver = {
	644	.probe = tilcdc_pdev_probe,
	645	.remove = tilcdc_pdev_remove,
	646	.driver = {
16ea975e RC	647	.name = "tilcdc",
	648	.pm = &tilcdc_pm_ops,
	649	.of_match_table = tilcdc_of_match,
	650	},
	651	};
	652
	653	static int __init tilcdc_drm_init(void)
	654	{
	655	DBG("init");
	656	tilcdc_tfp410_init();
0d4bbaf9	657	tilcdc_panel_init();
16ea975e RC	658	return platform_driver_register(&tilcdc_platform_driver);
	659	}
	660
	661	static void __exit tilcdc_drm_fini(void)
	662	{
	663	DBG("fini");
16ea975e	664	platform_driver_unregister(&tilcdc_platform_driver);
eb565a2b	665	tilcdc_panel_fini();
eb565a2b	666	tilcdc_tfp410_fini();
16ea975e RC	667	}
16ea975e RC	668
2023d84d	669	module_init(tilcdc_drm_init);
16ea975e RC	670	module_exit(tilcdc_drm_fini);
	671
	672	MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
	673	MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
	674	MODULE_LICENSE("GPL");