]>
Commit | Line | Data |
---|---|---|
dc5698e8 DA |
1 | /* |
2 | * Copyright (C) 2015 Red Hat, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
a3d63977 SR |
26 | #include <drm/drm_file.h> |
27 | #include <drm/drm_fourcc.h> | |
28 | ||
dc5698e8 DA |
29 | #include "virtgpu_drv.h" |
30 | ||
dc5698e8 DA |
31 | int virtio_gpu_gem_create(struct drm_file *file, |
32 | struct drm_device *dev, | |
4441235f | 33 | struct virtio_gpu_object_params *params, |
dc5698e8 DA |
34 | struct drm_gem_object **obj_p, |
35 | uint32_t *handle_p) | |
36 | { | |
2e0d9ee4 | 37 | struct virtio_gpu_device *vgdev = dev->dev_private; |
dc5698e8 DA |
38 | struct virtio_gpu_object *obj; |
39 | int ret; | |
40 | u32 handle; | |
41 | ||
c3e2850a GS |
42 | if (vgdev->has_virgl_3d) |
43 | virtio_gpu_create_context(dev, file); | |
44 | ||
2e0d9ee4 GH |
45 | ret = virtio_gpu_object_create(vgdev, params, &obj, NULL); |
46 | if (ret < 0) | |
47 | return ret; | |
dc5698e8 | 48 | |
c66df701 | 49 | ret = drm_gem_handle_create(file, &obj->base.base, &handle); |
dc5698e8 | 50 | if (ret) { |
c66df701 | 51 | drm_gem_object_release(&obj->base.base); |
dc5698e8 DA |
52 | return ret; |
53 | } | |
54 | ||
c66df701 | 55 | *obj_p = &obj->base.base; |
dc5698e8 DA |
56 | |
57 | /* drop reference from allocate - handle holds it now */ | |
c66df701 | 58 | drm_gem_object_put_unlocked(&obj->base.base); |
dc5698e8 DA |
59 | |
60 | *handle_p = handle; | |
61 | return 0; | |
62 | } | |
63 | ||
64 | int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, | |
65 | struct drm_device *dev, | |
66 | struct drm_mode_create_dumb *args) | |
67 | { | |
dc5698e8 | 68 | struct drm_gem_object *gobj; |
4441235f | 69 | struct virtio_gpu_object_params params = { 0 }; |
dc5698e8 DA |
70 | int ret; |
71 | uint32_t pitch; | |
dc5698e8 | 72 | |
42fd9e6c GH |
73 | if (args->bpp != 32) |
74 | return -EINVAL; | |
75 | ||
76 | pitch = args->width * 4; | |
dc5698e8 DA |
77 | args->size = pitch * args->height; |
78 | args->size = ALIGN(args->size, PAGE_SIZE); | |
79 | ||
f9659329 GH |
80 | params.format = virtio_gpu_translate_format(DRM_FORMAT_HOST_XRGB8888); |
81 | params.width = args->width; | |
82 | params.height = args->height; | |
4441235f | 83 | params.size = args->size; |
530b2842 | 84 | params.dumb = true; |
4441235f | 85 | ret = virtio_gpu_gem_create(file_priv, dev, ¶ms, &gobj, |
dc5698e8 DA |
86 | &args->handle); |
87 | if (ret) | |
88 | goto fail; | |
89 | ||
dc5698e8 DA |
90 | args->pitch = pitch; |
91 | return ret; | |
92 | ||
93 | fail: | |
94 | return ret; | |
95 | } | |
96 | ||
dc5698e8 DA |
97 | int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, |
98 | struct drm_device *dev, | |
99 | uint32_t handle, uint64_t *offset_p) | |
100 | { | |
101 | struct drm_gem_object *gobj; | |
9d492b6b | 102 | |
dc5698e8 | 103 | BUG_ON(!offset_p); |
a8ad0bd8 | 104 | gobj = drm_gem_object_lookup(file_priv, handle); |
dc5698e8 DA |
105 | if (gobj == NULL) |
106 | return -ENOENT; | |
093bd9cf | 107 | *offset_p = drm_vma_node_offset_addr(&gobj->vma_node); |
1af0838d | 108 | drm_gem_object_put_unlocked(gobj); |
dc5698e8 DA |
109 | return 0; |
110 | } | |
62fb7a5e GH |
111 | |
112 | int virtio_gpu_gem_object_open(struct drm_gem_object *obj, | |
113 | struct drm_file *file) | |
114 | { | |
115 | struct virtio_gpu_device *vgdev = obj->dev->dev_private; | |
116 | struct virtio_gpu_fpriv *vfpriv = file->driver_priv; | |
93c38d15 | 117 | struct virtio_gpu_object_array *objs; |
62fb7a5e GH |
118 | |
119 | if (!vgdev->has_virgl_3d) | |
120 | return 0; | |
121 | ||
93c38d15 GH |
122 | objs = virtio_gpu_array_alloc(1); |
123 | if (!objs) | |
124 | return -ENOMEM; | |
125 | virtio_gpu_array_add_obj(objs, obj); | |
62fb7a5e GH |
126 | |
127 | virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id, | |
93c38d15 | 128 | objs); |
97452907 | 129 | virtio_gpu_notify(vgdev); |
62fb7a5e GH |
130 | return 0; |
131 | } | |
132 | ||
133 | void virtio_gpu_gem_object_close(struct drm_gem_object *obj, | |
134 | struct drm_file *file) | |
135 | { | |
136 | struct virtio_gpu_device *vgdev = obj->dev->dev_private; | |
137 | struct virtio_gpu_fpriv *vfpriv = file->driver_priv; | |
93c38d15 | 138 | struct virtio_gpu_object_array *objs; |
62fb7a5e GH |
139 | |
140 | if (!vgdev->has_virgl_3d) | |
141 | return; | |
142 | ||
93c38d15 GH |
143 | objs = virtio_gpu_array_alloc(1); |
144 | if (!objs) | |
62fb7a5e | 145 | return; |
93c38d15 | 146 | virtio_gpu_array_add_obj(objs, obj); |
62fb7a5e GH |
147 | |
148 | virtio_gpu_cmd_context_detach_resource(vgdev, vfpriv->ctx_id, | |
93c38d15 | 149 | objs); |
97452907 | 150 | virtio_gpu_notify(vgdev); |
62fb7a5e | 151 | } |
98abe21d GH |
152 | |
153 | struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents) | |
154 | { | |
155 | struct virtio_gpu_object_array *objs; | |
156 | size_t size = sizeof(*objs) + sizeof(objs->objs[0]) * nents; | |
157 | ||
158 | objs = kmalloc(size, GFP_KERNEL); | |
159 | if (!objs) | |
160 | return NULL; | |
161 | ||
162 | objs->nents = 0; | |
163 | objs->total = nents; | |
164 | return objs; | |
165 | } | |
166 | ||
167 | static void virtio_gpu_array_free(struct virtio_gpu_object_array *objs) | |
168 | { | |
169 | kfree(objs); | |
170 | } | |
171 | ||
172 | struct virtio_gpu_object_array* | |
173 | virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents) | |
174 | { | |
175 | struct virtio_gpu_object_array *objs; | |
176 | u32 i; | |
177 | ||
178 | objs = virtio_gpu_array_alloc(nents); | |
179 | if (!objs) | |
180 | return NULL; | |
181 | ||
182 | for (i = 0; i < nents; i++) { | |
183 | objs->objs[i] = drm_gem_object_lookup(drm_file, handles[i]); | |
184 | if (!objs->objs[i]) { | |
185 | objs->nents = i; | |
186 | virtio_gpu_array_put_free(objs); | |
187 | return NULL; | |
188 | } | |
189 | } | |
190 | objs->nents = i; | |
191 | return objs; | |
192 | } | |
193 | ||
194 | void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs, | |
195 | struct drm_gem_object *obj) | |
196 | { | |
197 | if (WARN_ON_ONCE(objs->nents == objs->total)) | |
198 | return; | |
199 | ||
200 | drm_gem_object_get(obj); | |
201 | objs->objs[objs->nents] = obj; | |
202 | objs->nents++; | |
203 | } | |
204 | ||
205 | int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs) | |
206 | { | |
207 | int ret; | |
208 | ||
209 | if (objs->nents == 1) { | |
210 | ret = dma_resv_lock_interruptible(objs->objs[0]->resv, NULL); | |
211 | } else { | |
212 | ret = drm_gem_lock_reservations(objs->objs, objs->nents, | |
213 | &objs->ticket); | |
214 | } | |
215 | return ret; | |
216 | } | |
217 | ||
218 | void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs) | |
219 | { | |
220 | if (objs->nents == 1) { | |
221 | dma_resv_unlock(objs->objs[0]->resv); | |
222 | } else { | |
223 | drm_gem_unlock_reservations(objs->objs, objs->nents, | |
224 | &objs->ticket); | |
225 | } | |
226 | } | |
227 | ||
228 | void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs, | |
229 | struct dma_fence *fence) | |
230 | { | |
231 | int i; | |
232 | ||
233 | for (i = 0; i < objs->nents; i++) | |
234 | dma_resv_add_excl_fence(objs->objs[i]->resv, fence); | |
235 | } | |
236 | ||
237 | void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs) | |
238 | { | |
239 | u32 i; | |
240 | ||
241 | for (i = 0; i < objs->nents; i++) | |
242 | drm_gem_object_put_unlocked(objs->objs[i]); | |
243 | virtio_gpu_array_free(objs); | |
244 | } | |
f0c6cef7 GH |
245 | |
246 | void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev, | |
247 | struct virtio_gpu_object_array *objs) | |
248 | { | |
249 | spin_lock(&vgdev->obj_free_lock); | |
250 | list_add_tail(&objs->next, &vgdev->obj_free_list); | |
251 | spin_unlock(&vgdev->obj_free_lock); | |
252 | schedule_work(&vgdev->obj_free_work); | |
253 | } | |
254 | ||
255 | void virtio_gpu_array_put_free_work(struct work_struct *work) | |
256 | { | |
257 | struct virtio_gpu_device *vgdev = | |
258 | container_of(work, struct virtio_gpu_device, obj_free_work); | |
259 | struct virtio_gpu_object_array *objs; | |
260 | ||
261 | spin_lock(&vgdev->obj_free_lock); | |
262 | while (!list_empty(&vgdev->obj_free_list)) { | |
263 | objs = list_first_entry(&vgdev->obj_free_list, | |
264 | struct virtio_gpu_object_array, next); | |
265 | list_del(&objs->next); | |
266 | spin_unlock(&vgdev->obj_free_lock); | |
267 | virtio_gpu_array_put_free(objs); | |
268 | spin_lock(&vgdev->obj_free_lock); | |
269 | } | |
270 | spin_unlock(&vgdev->obj_free_lock); | |
271 | } |