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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # I2C subsystem configuration | |
3 | # | |
4 | ||
5 | menu "I2C support" | |
6 | ||
b6036bcd MY |
7 | config DM_I2C |
8 | bool "Enable Driver Model for I2C drivers" | |
9 | depends on DM | |
10 | help | |
705fcf4d PM |
11 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
12 | write and speed, is implemented with the bus drivers operations, | |
13 | which provide methods for bus setting and data transfer. Each chip | |
14 | device (bus child) info is kept as parent platdata. The interface | |
15 | is defined in include/i2c.h. When i2c bus driver supports the i2c | |
16 | uclass, but the device drivers not, then DM_I2C_COMPAT config can | |
17 | be used as compatibility layer. | |
26f820f3 | 18 | |
4bba9d3f SG |
19 | config DM_I2C_COMPAT |
20 | bool "Enable I2C compatibility layer" | |
21 | depends on DM | |
22 | help | |
23 | Enable old-style I2C functions for compatibility with existing code. | |
24 | This option can be enabled as a temporary measure to avoid needing | |
25 | to convert all code for a board in a single commit. It should not | |
26 | be enabled for any board in an official release. | |
27 | ||
cc456bd7 SG |
28 | config I2C_CROS_EC_TUNNEL |
29 | tristate "Chrome OS EC tunnel I2C bus" | |
30 | depends on CROS_EC | |
31 | help | |
32 | This provides an I2C bus that will tunnel i2c commands through to | |
33 | the other side of the Chrome OS EC to the I2C bus connected there. | |
34 | This will work whatever the interface used to talk to the EC (SPI, | |
35 | I2C or LPC). Some Chromebooks use this when the hardware design | |
36 | does not allow direct access to the main PMIC from the AP. | |
37 | ||
f48eaf01 SG |
38 | config I2C_CROS_EC_LDO |
39 | bool "Provide access to LDOs on the Chrome OS EC" | |
40 | depends on CROS_EC | |
41 | ---help--- | |
42 | On many Chromebooks the main PMIC is inaccessible to the AP. This is | |
43 | often dealt with by using an I2C pass-through interface provided by | |
44 | the EC. On some unfortunate models (e.g. Spring) the pass-through | |
45 | is not available, and an LDO message is available instead. This | |
46 | option enables a driver which provides very basic access to those | |
47 | regulators, via the EC. We implement this as an I2C bus which | |
48 | emulates just the TPS65090 messages we know about. This is done to | |
49 | avoid duplicating the logic in the TPS65090 regulator driver for | |
50 | enabling/disabling an LDO. | |
cc456bd7 | 51 | |
e46f8a33 LM |
52 | config I2C_SET_DEFAULT_BUS_NUM |
53 | bool "Set default I2C bus number" | |
54 | depends on DM_I2C | |
55 | help | |
56 | Set default number of I2C bus to be accessed. This option provides | |
57 | behaviour similar to old (i.e. pre DM) I2C bus driver. | |
58 | ||
59 | config I2C_DEFAULT_BUS_NUMBER | |
60 | hex "I2C default bus number" | |
61 | depends on I2C_SET_DEFAULT_BUS_NUM | |
62 | default 0x0 | |
63 | help | |
64 | Number of default I2C bus to use | |
65 | ||
c54473cb PM |
66 | config DM_I2C_GPIO |
67 | bool "Enable Driver Model for software emulated I2C bus driver" | |
68 | depends on DM_I2C && DM_GPIO | |
69 | help | |
70 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
71 | configuration is given by the device tree. Kernel-style device tree | |
72 | bindings are supported. | |
73 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
74 | ||
8800e0fa SW |
75 | config SYS_I2C_AT91 |
76 | bool "Atmel I2C driver" | |
77 | depends on DM_I2C && ARCH_AT91 | |
78 | help | |
79 | Add support for the Atmel I2C driver. A serious problem is that there | |
80 | is no documented way to issue repeated START conditions for more than | |
81 | two messages, as needed to support combined I2C messages. Use the | |
82 | i2c-gpio driver unless your system can cope with this limitation. | |
83 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt | |
84 | ||
dbc82ce3 | 85 | config SYS_I2C_FSL |
86 | bool "Freescale I2C bus driver" | |
87 | depends on DM_I2C | |
88 | help | |
89 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and | |
90 | MPC85xx processors. | |
91 | ||
fdec2d21 MF |
92 | config SYS_I2C_CADENCE |
93 | tristate "Cadence I2C Controller" | |
94 | depends on DM_I2C && (ARCH_ZYNQ || ARM64) | |
95 | help | |
96 | Say yes here to select Cadence I2C Host Controller. This controller is | |
97 | e.g. used by Xilinx Zynq. | |
98 | ||
e32d0db7 SR |
99 | config SYS_I2C_DW |
100 | bool "Designware I2C Controller" | |
101 | default n | |
102 | help | |
103 | Say yes here to select the Designware I2C Host Controller. This | |
104 | controller is used in various SoCs, e.g. the ST SPEAr, Altera | |
105 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. | |
106 | ||
3a370528 SR |
107 | config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED |
108 | bool "DW I2C Enable Status Register not supported" | |
109 | depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ | |
110 | TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) | |
111 | default y | |
112 | help | |
113 | Some versions of the Designware I2C controller do not support the | |
114 | enable status register. This config option can be enabled in such | |
115 | cases. | |
116 | ||
4dc038f3 | 117 | config SYS_I2C_ASPEED |
118 | bool "Aspeed I2C Controller" | |
119 | depends on DM_I2C && ARCH_ASPEED | |
120 | help | |
121 | Say yes here to select Aspeed I2C Host Controller. The driver | |
122 | supports AST2500 and AST2400 controllers, but is very limited. | |
123 | Only single master mode is supported and only byte-by-byte | |
124 | synchronous reads and writes are supported, no Pool Buffers or DMA. | |
125 | ||
abb0b01e SG |
126 | config SYS_I2C_INTEL |
127 | bool "Intel I2C/SMBUS driver" | |
128 | depends on DM_I2C | |
129 | help | |
130 | Add support for the Intel SMBUS driver. So far this driver is just | |
131 | a stub which perhaps some basic init. There is no implementation of | |
132 | the I2C API meaning that any I2C operations will immediately fail | |
133 | for now. | |
134 | ||
7ee3f149 PF |
135 | config SYS_I2C_IMX_LPI2C |
136 | bool "NXP i.MX LPI2C driver" | |
7ee3f149 PF |
137 | help |
138 | Add support for the NXP i.MX LPI2C driver. | |
139 | ||
f8d9ca18 BG |
140 | config SYS_I2C_MESON |
141 | bool "Amlogic Meson I2C driver" | |
142 | depends on DM_I2C && ARCH_MESON | |
143 | help | |
4ecbb8b6 BG |
144 | Add support for the I2C controller available in Amlogic Meson |
145 | SoCs. The controller supports programmable bus speed including | |
146 | standard (100kbits/s) and fast (400kbit/s) speed and allows the | |
147 | software to define a flexible format of the bit streams. It has an | |
148 | internal buffer holding up to 8 bytes for transfers and supports | |
149 | both 7-bit and 10-bit addresses. | |
f8d9ca18 | 150 | |
72c8c10b JT |
151 | config SYS_I2C_MXC |
152 | bool "NXP i.MX I2C driver" | |
153 | depends on MX6 | |
154 | help | |
155 | Add support for the NXP i.MX I2C driver. This supports upto for bus | |
156 | channels and operating on standard mode upto 100 kbits/s and fast | |
157 | mode upto 400 kbits/s. | |
158 | ||
daa0f050 AF |
159 | config SYS_I2C_OMAP24XX |
160 | bool "TI OMAP2+ I2C driver" | |
161 | depends on ARCH_OMAP2PLUS | |
162 | help | |
163 | Add support for the OMAP2+ I2C driver. | |
164 | ||
11d2e98d AF |
165 | if SYS_I2C_OMAP24XX |
166 | config SYS_OMAP24_I2C_SLAVE | |
167 | int "I2C Slave addr channel 0" | |
168 | default 1 | |
169 | help | |
170 | OMAP24xx I2C Slave address channel 0 | |
171 | ||
172 | config SYS_OMAP24_I2C_SPEED | |
173 | int "I2C Slave channel 0 speed" | |
174 | default 100000 | |
175 | help | |
176 | OMAP24xx Slave speed channel 0 | |
177 | endif | |
178 | ||
9e75ea46 MV |
179 | config SYS_I2C_RCAR_IIC |
180 | bool "Renesas RCar Gen3 IIC driver" | |
181 | depends on RCAR_GEN3 && DM_I2C | |
182 | help | |
183 | Support for Renesas RCar Gen3 IIC controller. | |
184 | ||
34374699 SG |
185 | config SYS_I2C_ROCKCHIP |
186 | bool "Rockchip I2C driver" | |
187 | depends on DM_I2C | |
188 | help | |
189 | Add support for the Rockchip I2C driver. This is used with various | |
190 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips | |
191 | have several I2C ports and all are provided, controled by the | |
192 | device tree. | |
193 | ||
1174aada SG |
194 | config SYS_I2C_SANDBOX |
195 | bool "Sandbox I2C driver" | |
196 | depends on SANDBOX && DM_I2C | |
197 | help | |
198 | Enable I2C support for sandbox. This is an emulation of a real I2C | |
199 | bus. Devices can be attached to the bus using the device tree | |
c77c7db5 | 200 | which specifies the driver to use. See sandbox.dts as an example. |
1174aada | 201 | |
1d61ad95 JC |
202 | config SYS_I2C_S3C24X0 |
203 | bool "Samsung I2C driver" | |
204 | depends on ARCH_EXYNOS4 && DM_I2C | |
205 | help | |
206 | Support for Samsung I2C controller as Samsung SoCs. | |
1174aada | 207 | |
4fadcaf0 PC |
208 | config SYS_I2C_STM32F7 |
209 | bool "STMicroelectronics STM32F7 I2C support" | |
210 | depends on (STM32F7 || STM32H7) && DM_I2C | |
211 | help | |
212 | Enable this option to add support for STM32 I2C controller | |
213 | introduced with STM32F7/H7 SoCs. This I2C controller supports : | |
214 | _ Slave and master modes | |
215 | _ Multimaster capability | |
216 | _ Standard-mode (up to 100 kHz) | |
217 | _ Fast-mode (up to 400 kHz) | |
218 | _ Fast-mode Plus (up to 1 MHz) | |
219 | _ 7-bit and 10-bit addressing mode | |
220 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) | |
221 | _ All 7-bit addresses acknowledge mode | |
222 | _ General call | |
223 | _ Programmable setup and hold times | |
224 | _ Easy to use event management | |
225 | _ Optional clock stretching | |
226 | _ Software reset | |
227 | ||
26f820f3 MY |
228 | config SYS_I2C_UNIPHIER |
229 | bool "UniPhier I2C driver" | |
230 | depends on ARCH_UNIPHIER && DM_I2C | |
231 | default y | |
232 | help | |
b6ef3a3f MY |
233 | Support for UniPhier I2C controller driver. This I2C controller |
234 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. | |
238bd0b8 MY |
235 | |
236 | config SYS_I2C_UNIPHIER_F | |
237 | bool "UniPhier FIFO-builtin I2C driver" | |
238 | depends on ARCH_UNIPHIER && DM_I2C | |
239 | default y | |
240 | help | |
b6ef3a3f | 241 | Support for UniPhier FIFO-builtin I2C controller driver. |
238bd0b8 | 242 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
3d1957f0 | 243 | |
14a6ff2c | 244 | config SYS_I2C_MVTWSI |
245 | bool "Marvell I2C driver" | |
246 | depends on DM_I2C | |
247 | help | |
248 | Support for Marvell I2C controllers as used on the orion5x and | |
249 | kirkwood SoC families. | |
250 | ||
34f1c9fe SW |
251 | config TEGRA186_BPMP_I2C |
252 | bool "Enable Tegra186 BPMP-based I2C driver" | |
253 | depends on TEGRA186_BPMP | |
254 | help | |
255 | Support for Tegra I2C controllers managed by the BPMP (Boot and | |
256 | Power Management Processor). On Tegra186, some I2C controllers are | |
257 | directly controlled by the main CPU, whereas others are controlled | |
258 | by the BPMP, and can only be accessed by the main CPU via IPC | |
259 | requests to the BPMP. This driver covers the latter case. | |
260 | ||
fc760cc6 AF |
261 | config SYS_I2C_BUS_MAX |
262 | int "Max I2C busses" | |
263 | depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA | |
264 | default 2 if TI816X | |
265 | default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE | |
266 | default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X | |
267 | default 5 if OMAP54XX | |
268 | help | |
269 | Define the maximum number of available I2C buses. | |
270 | ||
92164216 MS |
271 | config SYS_I2C_IHS |
272 | bool "gdsys IHS I2C driver" | |
273 | depends on DM_I2C | |
274 | help | |
275 | Support for gdsys IHS I2C driver on FPGA bus. | |
276 | ||
3d1957f0 | 277 | source "drivers/i2c/muxes/Kconfig" |
0b11dbf7 MY |
278 | |
279 | endmenu |