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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # I2C subsystem configuration | |
3 | # | |
4 | ||
5 | menu "I2C support" | |
6 | ||
b6036bcd MY |
7 | config DM_I2C |
8 | bool "Enable Driver Model for I2C drivers" | |
9 | depends on DM | |
10 | help | |
705fcf4d PM |
11 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
12 | write and speed, is implemented with the bus drivers operations, | |
13 | which provide methods for bus setting and data transfer. Each chip | |
14 | device (bus child) info is kept as parent platdata. The interface | |
e3114824 | 15 | is defined in include/i2c.h. |
4bba9d3f | 16 | |
cc456bd7 SG |
17 | config I2C_CROS_EC_TUNNEL |
18 | tristate "Chrome OS EC tunnel I2C bus" | |
19 | depends on CROS_EC | |
20 | help | |
21 | This provides an I2C bus that will tunnel i2c commands through to | |
22 | the other side of the Chrome OS EC to the I2C bus connected there. | |
23 | This will work whatever the interface used to talk to the EC (SPI, | |
24 | I2C or LPC). Some Chromebooks use this when the hardware design | |
25 | does not allow direct access to the main PMIC from the AP. | |
26 | ||
f48eaf01 SG |
27 | config I2C_CROS_EC_LDO |
28 | bool "Provide access to LDOs on the Chrome OS EC" | |
29 | depends on CROS_EC | |
30 | ---help--- | |
31 | On many Chromebooks the main PMIC is inaccessible to the AP. This is | |
32 | often dealt with by using an I2C pass-through interface provided by | |
33 | the EC. On some unfortunate models (e.g. Spring) the pass-through | |
34 | is not available, and an LDO message is available instead. This | |
35 | option enables a driver which provides very basic access to those | |
36 | regulators, via the EC. We implement this as an I2C bus which | |
37 | emulates just the TPS65090 messages we know about. This is done to | |
38 | avoid duplicating the logic in the TPS65090 regulator driver for | |
39 | enabling/disabling an LDO. | |
cc456bd7 | 40 | |
e46f8a33 LM |
41 | config I2C_SET_DEFAULT_BUS_NUM |
42 | bool "Set default I2C bus number" | |
43 | depends on DM_I2C | |
44 | help | |
45 | Set default number of I2C bus to be accessed. This option provides | |
46 | behaviour similar to old (i.e. pre DM) I2C bus driver. | |
47 | ||
48 | config I2C_DEFAULT_BUS_NUMBER | |
49 | hex "I2C default bus number" | |
50 | depends on I2C_SET_DEFAULT_BUS_NUM | |
51 | default 0x0 | |
52 | help | |
53 | Number of default I2C bus to use | |
54 | ||
c54473cb PM |
55 | config DM_I2C_GPIO |
56 | bool "Enable Driver Model for software emulated I2C bus driver" | |
57 | depends on DM_I2C && DM_GPIO | |
58 | help | |
59 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
60 | configuration is given by the device tree. Kernel-style device tree | |
61 | bindings are supported. | |
62 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
63 | ||
8800e0fa SW |
64 | config SYS_I2C_AT91 |
65 | bool "Atmel I2C driver" | |
66 | depends on DM_I2C && ARCH_AT91 | |
67 | help | |
68 | Add support for the Atmel I2C driver. A serious problem is that there | |
69 | is no documented way to issue repeated START conditions for more than | |
70 | two messages, as needed to support combined I2C messages. Use the | |
71 | i2c-gpio driver unless your system can cope with this limitation. | |
72 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt | |
73 | ||
956d57a8 RK |
74 | config SYS_I2C_IPROC |
75 | bool "Broadcom I2C driver" | |
76 | depends on DM_I2C | |
77 | help | |
78 | Broadcom I2C driver. | |
79 | Add support for Broadcom I2C driver. | |
80 | Say yes here to to enable the Broadco I2C driver. | |
81 | ||
dbc82ce3 | 82 | config SYS_I2C_FSL |
83 | bool "Freescale I2C bus driver" | |
84 | depends on DM_I2C | |
85 | help | |
86 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and | |
87 | MPC85xx processors. | |
88 | ||
fdec2d21 MF |
89 | config SYS_I2C_CADENCE |
90 | tristate "Cadence I2C Controller" | |
91 | depends on DM_I2C && (ARCH_ZYNQ || ARM64) | |
92 | help | |
93 | Say yes here to select Cadence I2C Host Controller. This controller is | |
94 | e.g. used by Xilinx Zynq. | |
95 | ||
9f8cf76b AF |
96 | config SYS_I2C_DAVINCI |
97 | bool "Davinci I2C Controller" | |
98 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) | |
99 | help | |
100 | Say yes here to add support for Davinci and Keystone I2C controller | |
101 | ||
e32d0db7 SR |
102 | config SYS_I2C_DW |
103 | bool "Designware I2C Controller" | |
104 | default n | |
105 | help | |
106 | Say yes here to select the Designware I2C Host Controller. This | |
107 | controller is used in various SoCs, e.g. the ST SPEAr, Altera | |
108 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. | |
109 | ||
3a370528 SR |
110 | config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED |
111 | bool "DW I2C Enable Status Register not supported" | |
112 | depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ | |
113 | TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) | |
114 | default y | |
115 | help | |
116 | Some versions of the Designware I2C controller do not support the | |
117 | enable status register. This config option can be enabled in such | |
118 | cases. | |
119 | ||
4dc038f3 | 120 | config SYS_I2C_ASPEED |
121 | bool "Aspeed I2C Controller" | |
122 | depends on DM_I2C && ARCH_ASPEED | |
123 | help | |
124 | Say yes here to select Aspeed I2C Host Controller. The driver | |
125 | supports AST2500 and AST2400 controllers, but is very limited. | |
126 | Only single master mode is supported and only byte-by-byte | |
127 | synchronous reads and writes are supported, no Pool Buffers or DMA. | |
128 | ||
abb0b01e SG |
129 | config SYS_I2C_INTEL |
130 | bool "Intel I2C/SMBUS driver" | |
131 | depends on DM_I2C | |
132 | help | |
133 | Add support for the Intel SMBUS driver. So far this driver is just | |
134 | a stub which perhaps some basic init. There is no implementation of | |
135 | the I2C API meaning that any I2C operations will immediately fail | |
136 | for now. | |
137 | ||
7ee3f149 PF |
138 | config SYS_I2C_IMX_LPI2C |
139 | bool "NXP i.MX LPI2C driver" | |
7ee3f149 PF |
140 | help |
141 | Add support for the NXP i.MX LPI2C driver. | |
142 | ||
f8d9ca18 BG |
143 | config SYS_I2C_MESON |
144 | bool "Amlogic Meson I2C driver" | |
145 | depends on DM_I2C && ARCH_MESON | |
146 | help | |
4ecbb8b6 BG |
147 | Add support for the I2C controller available in Amlogic Meson |
148 | SoCs. The controller supports programmable bus speed including | |
149 | standard (100kbits/s) and fast (400kbit/s) speed and allows the | |
150 | software to define a flexible format of the bit streams. It has an | |
151 | internal buffer holding up to 8 bytes for transfers and supports | |
152 | both 7-bit and 10-bit addresses. | |
f8d9ca18 | 153 | |
72c8c10b | 154 | config SYS_I2C_MXC |
942ecc8b | 155 | bool "NXP MXC I2C driver" |
72c8c10b | 156 | help |
74751454 CP |
157 | Add support for the NXP I2C driver. This supports up to four bus |
158 | channels and operating on standard mode up to 100 kbits/s and fast | |
159 | mode up to 400 kbits/s. | |
72c8c10b | 160 | |
ca0a8f3e TP |
161 | # These settings are not used with DM_I2C, however SPL doesn't use |
162 | # DM_I2C even if DM_I2C is enabled, and so might use these settings even | |
163 | # when main u-boot does not! | |
164 | if SYS_I2C_MXC && (!DM_I2C || SPL) | |
942ecc8b SD |
165 | config SYS_I2C_MXC_I2C1 |
166 | bool "NXP MXC I2C1" | |
167 | help | |
168 | Add support for NXP MXC I2C Controller 1. | |
169 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A | |
170 | ||
171 | config SYS_I2C_MXC_I2C2 | |
172 | bool "NXP MXC I2C2" | |
173 | help | |
174 | Add support for NXP MXC I2C Controller 2. | |
175 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A | |
176 | ||
177 | config SYS_I2C_MXC_I2C3 | |
178 | bool "NXP MXC I2C3" | |
179 | help | |
180 | Add support for NXP MXC I2C Controller 3. | |
181 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A | |
182 | ||
183 | config SYS_I2C_MXC_I2C4 | |
184 | bool "NXP MXC I2C4" | |
185 | help | |
186 | Add support for NXP MXC I2C Controller 4. | |
187 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A | |
fa452192 SD |
188 | |
189 | config SYS_I2C_MXC_I2C5 | |
190 | bool "NXP MXC I2C5" | |
191 | help | |
192 | Add support for NXP MXC I2C Controller 5. | |
193 | Required for SoCs which have I2C MXC controller 5 eg LX2160A | |
194 | ||
195 | config SYS_I2C_MXC_I2C6 | |
196 | bool "NXP MXC I2C6" | |
197 | help | |
198 | Add support for NXP MXC I2C Controller 6. | |
199 | Required for SoCs which have I2C MXC controller 6 eg LX2160A | |
200 | ||
201 | config SYS_I2C_MXC_I2C7 | |
202 | bool "NXP MXC I2C7" | |
203 | help | |
204 | Add support for NXP MXC I2C Controller 7. | |
205 | Required for SoCs which have I2C MXC controller 7 eg LX2160A | |
206 | ||
207 | config SYS_I2C_MXC_I2C8 | |
208 | bool "NXP MXC I2C8" | |
209 | help | |
210 | Add support for NXP MXC I2C Controller 8. | |
211 | Required for SoCs which have I2C MXC controller 8 eg LX2160A | |
942ecc8b SD |
212 | endif |
213 | ||
214 | if SYS_I2C_MXC_I2C1 | |
215 | config SYS_MXC_I2C1_SPEED | |
216 | int "I2C Channel 1 speed" | |
217 | default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU | |
218 | default 100000 | |
219 | help | |
220 | MXC I2C Channel 1 speed | |
221 | ||
222 | config SYS_MXC_I2C1_SLAVE | |
223 | int "I2C1 Slave" | |
224 | default 0 | |
225 | help | |
226 | MXC I2C1 Slave | |
227 | endif | |
228 | ||
229 | if SYS_I2C_MXC_I2C2 | |
230 | config SYS_MXC_I2C2_SPEED | |
231 | int "I2C Channel 2 speed" | |
232 | default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU | |
233 | default 100000 | |
234 | help | |
235 | MXC I2C Channel 2 speed | |
236 | ||
237 | config SYS_MXC_I2C2_SLAVE | |
238 | int "I2C2 Slave" | |
239 | default 0 | |
240 | help | |
241 | MXC I2C2 Slave | |
242 | endif | |
243 | ||
244 | if SYS_I2C_MXC_I2C3 | |
245 | config SYS_MXC_I2C3_SPEED | |
246 | int "I2C Channel 3 speed" | |
247 | default 100000 | |
248 | help | |
249 | MXC I2C Channel 3 speed | |
250 | ||
251 | config SYS_MXC_I2C3_SLAVE | |
252 | int "I2C3 Slave" | |
253 | default 0 | |
254 | help | |
255 | MXC I2C3 Slave | |
256 | endif | |
257 | ||
258 | if SYS_I2C_MXC_I2C4 | |
259 | config SYS_MXC_I2C4_SPEED | |
260 | int "I2C Channel 4 speed" | |
261 | default 100000 | |
262 | help | |
263 | MXC I2C Channel 4 speed | |
264 | ||
265 | config SYS_MXC_I2C4_SLAVE | |
266 | int "I2C4 Slave" | |
267 | default 0 | |
268 | help | |
269 | MXC I2C4 Slave | |
270 | endif | |
271 | ||
fa452192 SD |
272 | if SYS_I2C_MXC_I2C5 |
273 | config SYS_MXC_I2C5_SPEED | |
274 | int "I2C Channel 5 speed" | |
275 | default 100000 | |
276 | help | |
277 | MXC I2C Channel 5 speed | |
278 | ||
279 | config SYS_MXC_I2C5_SLAVE | |
280 | int "I2C5 Slave" | |
281 | default 0 | |
282 | help | |
283 | MXC I2C5 Slave | |
284 | endif | |
285 | ||
286 | if SYS_I2C_MXC_I2C6 | |
287 | config SYS_MXC_I2C6_SPEED | |
288 | int "I2C Channel 6 speed" | |
289 | default 100000 | |
290 | help | |
291 | MXC I2C Channel 6 speed | |
292 | ||
293 | config SYS_MXC_I2C6_SLAVE | |
294 | int "I2C6 Slave" | |
295 | default 0 | |
296 | help | |
297 | MXC I2C6 Slave | |
298 | endif | |
299 | ||
300 | if SYS_I2C_MXC_I2C7 | |
301 | config SYS_MXC_I2C7_SPEED | |
302 | int "I2C Channel 7 speed" | |
303 | default 100000 | |
304 | help | |
305 | MXC I2C Channel 7 speed | |
306 | ||
307 | config SYS_MXC_I2C7_SLAVE | |
308 | int "I2C7 Slave" | |
309 | default 0 | |
310 | help | |
311 | MXC I2C7 Slave | |
312 | endif | |
313 | ||
314 | if SYS_I2C_MXC_I2C8 | |
315 | config SYS_MXC_I2C8_SPEED | |
316 | int "I2C Channel 8 speed" | |
317 | default 100000 | |
318 | help | |
319 | MXC I2C Channel 8 speed | |
320 | ||
321 | config SYS_MXC_I2C8_SLAVE | |
322 | int "I2C8 Slave" | |
323 | default 0 | |
324 | help | |
325 | MXC I2C8 Slave | |
326 | endif | |
327 | ||
daa0f050 AF |
328 | config SYS_I2C_OMAP24XX |
329 | bool "TI OMAP2+ I2C driver" | |
14106bca | 330 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
daa0f050 AF |
331 | help |
332 | Add support for the OMAP2+ I2C driver. | |
333 | ||
11d2e98d AF |
334 | if SYS_I2C_OMAP24XX |
335 | config SYS_OMAP24_I2C_SLAVE | |
336 | int "I2C Slave addr channel 0" | |
337 | default 1 | |
338 | help | |
339 | OMAP24xx I2C Slave address channel 0 | |
340 | ||
341 | config SYS_OMAP24_I2C_SPEED | |
342 | int "I2C Slave channel 0 speed" | |
343 | default 100000 | |
344 | help | |
345 | OMAP24xx Slave speed channel 0 | |
346 | endif | |
347 | ||
a06a0ac3 MV |
348 | config SYS_I2C_RCAR_I2C |
349 | bool "Renesas RCar I2C driver" | |
350 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C | |
351 | help | |
352 | Support for Renesas RCar I2C controller. | |
353 | ||
9e75ea46 MV |
354 | config SYS_I2C_RCAR_IIC |
355 | bool "Renesas RCar Gen3 IIC driver" | |
f51155ec | 356 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
9e75ea46 MV |
357 | help |
358 | Support for Renesas RCar Gen3 IIC controller. | |
359 | ||
34374699 SG |
360 | config SYS_I2C_ROCKCHIP |
361 | bool "Rockchip I2C driver" | |
362 | depends on DM_I2C | |
363 | help | |
364 | Add support for the Rockchip I2C driver. This is used with various | |
365 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips | |
74751454 | 366 | have several I2C ports and all are provided, controlled by the |
34374699 SG |
367 | device tree. |
368 | ||
1174aada SG |
369 | config SYS_I2C_SANDBOX |
370 | bool "Sandbox I2C driver" | |
371 | depends on SANDBOX && DM_I2C | |
372 | help | |
373 | Enable I2C support for sandbox. This is an emulation of a real I2C | |
374 | bus. Devices can be attached to the bus using the device tree | |
c77c7db5 | 375 | which specifies the driver to use. See sandbox.dts as an example. |
1174aada | 376 | |
1d61ad95 JC |
377 | config SYS_I2C_S3C24X0 |
378 | bool "Samsung I2C driver" | |
379 | depends on ARCH_EXYNOS4 && DM_I2C | |
380 | help | |
381 | Support for Samsung I2C controller as Samsung SoCs. | |
1174aada | 382 | |
4fadcaf0 PC |
383 | config SYS_I2C_STM32F7 |
384 | bool "STMicroelectronics STM32F7 I2C support" | |
2514c2d0 | 385 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
4fadcaf0 PC |
386 | help |
387 | Enable this option to add support for STM32 I2C controller | |
388 | introduced with STM32F7/H7 SoCs. This I2C controller supports : | |
389 | _ Slave and master modes | |
390 | _ Multimaster capability | |
391 | _ Standard-mode (up to 100 kHz) | |
392 | _ Fast-mode (up to 400 kHz) | |
393 | _ Fast-mode Plus (up to 1 MHz) | |
394 | _ 7-bit and 10-bit addressing mode | |
395 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) | |
396 | _ All 7-bit addresses acknowledge mode | |
397 | _ General call | |
398 | _ Programmable setup and hold times | |
399 | _ Easy to use event management | |
400 | _ Optional clock stretching | |
401 | _ Software reset | |
402 | ||
02253d4d PR |
403 | config SYS_I2C_TEGRA |
404 | bool "NVIDIA Tegra internal I2C controller" | |
18138ab2 | 405 | depends on ARCH_TEGRA |
02253d4d PR |
406 | help |
407 | Support for NVIDIA I2C controller available in Tegra SoCs. | |
408 | ||
26f820f3 MY |
409 | config SYS_I2C_UNIPHIER |
410 | bool "UniPhier I2C driver" | |
411 | depends on ARCH_UNIPHIER && DM_I2C | |
412 | default y | |
413 | help | |
b6ef3a3f MY |
414 | Support for UniPhier I2C controller driver. This I2C controller |
415 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. | |
238bd0b8 MY |
416 | |
417 | config SYS_I2C_UNIPHIER_F | |
418 | bool "UniPhier FIFO-builtin I2C driver" | |
419 | depends on ARCH_UNIPHIER && DM_I2C | |
420 | default y | |
421 | help | |
b6ef3a3f | 422 | Support for UniPhier FIFO-builtin I2C controller driver. |
238bd0b8 | 423 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
3d1957f0 | 424 | |
e3bc4bb8 HS |
425 | config SYS_I2C_VERSATILE |
426 | bool "Arm Ltd Versatile I2C bus driver" | |
427 | depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) | |
428 | help | |
429 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host | |
430 | controller is present in the development boards manufactured by Arm Ltd. | |
431 | ||
14a6ff2c | 432 | config SYS_I2C_MVTWSI |
433 | bool "Marvell I2C driver" | |
434 | depends on DM_I2C | |
435 | help | |
436 | Support for Marvell I2C controllers as used on the orion5x and | |
437 | kirkwood SoC families. | |
438 | ||
34f1c9fe SW |
439 | config TEGRA186_BPMP_I2C |
440 | bool "Enable Tegra186 BPMP-based I2C driver" | |
441 | depends on TEGRA186_BPMP | |
442 | help | |
443 | Support for Tegra I2C controllers managed by the BPMP (Boot and | |
444 | Power Management Processor). On Tegra186, some I2C controllers are | |
445 | directly controlled by the main CPU, whereas others are controlled | |
446 | by the BPMP, and can only be accessed by the main CPU via IPC | |
447 | requests to the BPMP. This driver covers the latter case. | |
448 | ||
fc760cc6 AF |
449 | config SYS_I2C_BUS_MAX |
450 | int "Max I2C busses" | |
451 | depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA | |
452 | default 2 if TI816X | |
453 | default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE | |
454 | default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X | |
455 | default 5 if OMAP54XX | |
456 | help | |
457 | Define the maximum number of available I2C buses. | |
458 | ||
ad827a50 MV |
459 | config SYS_I2C_XILINX_XIIC |
460 | bool "Xilinx AXI I2C driver" | |
461 | depends on DM_I2C | |
462 | help | |
463 | Support for Xilinx AXI I2C controller. | |
464 | ||
92164216 MS |
465 | config SYS_I2C_IHS |
466 | bool "gdsys IHS I2C driver" | |
467 | depends on DM_I2C | |
468 | help | |
469 | Support for gdsys IHS I2C driver on FPGA bus. | |
470 | ||
3d1957f0 | 471 | source "drivers/i2c/muxes/Kconfig" |
0b11dbf7 MY |
472 | |
473 | endmenu |